src/intel/vulkan/gen7_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #if GEN_GEN == 7 && !GEN_IS_HASWELL
  36 void
  37 gen7_cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer *cmd_buffer,
  38                                          uint32_t stages)
  39 {
  40    static const uint32_t sampler_state_opcodes[] = {
  41       [MESA_SHADER_VERTEX]                      = 43,
  42       [MESA_SHADER_TESS_CTRL]                   = 44, /* HS */
  43       [MESA_SHADER_TESS_EVAL]                   = 45, /* DS */
  44       [MESA_SHADER_GEOMETRY]                    = 46,
  45       [MESA_SHADER_FRAGMENT]                    = 47,
  46       [MESA_SHADER_COMPUTE]                     = 0,
  47    };
  48
  49    static const uint32_t binding_table_opcodes[] = {
  50       [MESA_SHADER_VERTEX]                      = 38,
  51       [MESA_SHADER_TESS_CTRL]                   = 39,
  52       [MESA_SHADER_TESS_EVAL]                   = 40,
  53       [MESA_SHADER_GEOMETRY]                    = 41,
  54       [MESA_SHADER_FRAGMENT]                    = 42,
  55       [MESA_SHADER_COMPUTE]                     = 0,
  56    };
  57
  58    anv_foreach_stage(s, stages) {
  59       if (cmd_buffer->state.samplers[s].alloc_size > 0) {
  60          anv_batch_emit(&cmd_buffer->batch,
  61                         GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS), ssp) {
  62             ssp._3DCommandSubOpcode = sampler_state_opcodes[s];
  63             ssp.PointertoVSSamplerState = cmd_buffer->state.samplers[s].offset;
  64          }
  65       }
  66
  67       /* Always emit binding table pointers if we're asked to, since on SKL
  68        * this is what flushes push constants. */
  69       anv_batch_emit(&cmd_buffer->batch,
  70                      GENX(3DSTATE_BINDING_TABLE_POINTERS_VS), btp) {
  71          btp._3DCommandSubOpcode = binding_table_opcodes[s];
  72          btp.PointertoVSBindingTable = cmd_buffer->state.binding_tables[s].offset;
  73       }
  74    }
  75 }
  76
  77 uint32_t
  78 gen7_cmd_buffer_flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer)
  79 {
  80    VkShaderStageFlags dirty = cmd_buffer->state.descriptors_dirty &
  81                               cmd_buffer->state.pipeline->active_stages;
  82
  83    VkResult result = VK_SUCCESS;
  84    anv_foreach_stage(s, dirty) {
  85       result = anv_cmd_buffer_emit_samplers(cmd_buffer, s,
  86                                             &cmd_buffer->state.samplers[s]);
  87       if (result != VK_SUCCESS)
  88          break;
  89       result = anv_cmd_buffer_emit_binding_table(cmd_buffer, s,
  90                                                  &cmd_buffer->state.binding_tables[s]);
  91       if (result != VK_SUCCESS)
  92          break;
  93    }
  94
  95    if (result != VK_SUCCESS) {
  96       assert(result == VK_ERROR_OUT_OF_DEVICE_MEMORY);
  97
  98       result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
  99       assert(result == VK_SUCCESS);
 100
 101       /* Re-emit state base addresses so we get the new surface state base
 102        * address before we start emitting binding tables etc.
 103        */
 104       anv_cmd_buffer_emit_state_base_address(cmd_buffer);
 105
 106       /* Re-emit all active binding tables */
 107       dirty |= cmd_buffer->state.pipeline->active_stages;
 108       anv_foreach_stage(s, dirty) {
 109          result = anv_cmd_buffer_emit_samplers(cmd_buffer, s,
 110                                                &cmd_buffer->state.samplers[s]);
 111          if (result != VK_SUCCESS)
 112             return result;
 113          result = anv_cmd_buffer_emit_binding_table(cmd_buffer, s,
 114                                                     &cmd_buffer->state.binding_tables[s]);
 115          if (result != VK_SUCCESS)
 116             return result;
 117       }
 118    }
 119
 120    cmd_buffer->state.descriptors_dirty &= ~dirty;
 121
 122    return dirty;
 123 }
 124 #endif /* GEN_GEN == 7 && !GEN_IS_HASWELL */
 125
 126 static inline int64_t
 127 clamp_int64(int64_t x, int64_t min, int64_t max)
 128 {
 129    if (x < min)
 130       return min;
 131    else if (x < max)
 132       return x;
 133    else
 134       return max;
 135 }
 136
 137 #if GEN_GEN == 7 && !GEN_IS_HASWELL
 138 void
 139 gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
 140 {
 141    uint32_t count = cmd_buffer->state.dynamic.scissor.count;
 142    const VkRect2D *scissors =  cmd_buffer->state.dynamic.scissor.scissors;
 143    struct anv_state scissor_state =
 144       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
 145
 146    for (uint32_t i = 0; i < count; i++) {
 147       const VkRect2D *s = &scissors[i];
 148
 149       /* Since xmax and ymax are inclusive, we have to have xmax < xmin or
 150        * ymax < ymin for empty clips.  In case clip x, y, width height are all
 151        * 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
 152        * what we want. Just special case empty clips and produce a canonical
 153        * empty clip. */
 154       static const struct GEN7_SCISSOR_RECT empty_scissor = {
 155          .ScissorRectangleYMin = 1,
 156          .ScissorRectangleXMin = 1,
 157          .ScissorRectangleYMax = 0,
 158          .ScissorRectangleXMax = 0
 159       };
 160
 161       const int max = 0xffff;
 162       struct GEN7_SCISSOR_RECT scissor = {
 163          /* Do this math using int64_t so overflow gets clamped correctly. */
 164          .ScissorRectangleYMin = clamp_int64(s->offset.y, 0, max),
 165          .ScissorRectangleXMin = clamp_int64(s->offset.x, 0, max),
 166          .ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, max),
 167          .ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, max)
 168       };
 169
 170       if (s->extent.width <= 0 || s->extent.height <= 0) {
 171          GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8,
 172                                 &empty_scissor);
 173       } else {
 174          GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8, &scissor);
 175       }
 176    }
 177
 178    anv_batch_emit(&cmd_buffer->batch,
 179                   GEN7_3DSTATE_SCISSOR_STATE_POINTERS, ssp) {
 180       ssp.ScissorRectPointer = scissor_state.offset;
 181    }
 182
 183    if (!cmd_buffer->device->info.has_llc)
 184       anv_state_clflush(scissor_state);
 185 }
 186 #endif
 187
 188 static const uint32_t vk_to_gen_index_type[] = {
 189    [VK_INDEX_TYPE_UINT16]                       = INDEX_WORD,
 190    [VK_INDEX_TYPE_UINT32]                       = INDEX_DWORD,
 191 };
 192
 193 static const uint32_t restart_index_for_type[] = {
 194    [VK_INDEX_TYPE_UINT16]                    = UINT16_MAX,
 195    [VK_INDEX_TYPE_UINT32]                    = UINT32_MAX,
 196 };
 197
 198 void genX(CmdBindIndexBuffer)(
 199     VkCommandBuffer                             commandBuffer,
 200     VkBuffer                                    _buffer,
 201     VkDeviceSize                                offset,
 202     VkIndexType                                 indexType)
 203 {
 204    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 205    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 206
 207    cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 208    if (GEN_IS_HASWELL)
 209       cmd_buffer->state.restart_index = restart_index_for_type[indexType];
 210    cmd_buffer->state.gen7.index_buffer = buffer;
 211    cmd_buffer->state.gen7.index_type = vk_to_gen_index_type[indexType];
 212    cmd_buffer->state.gen7.index_offset = offset;
 213 }
 214
 215 static VkResult
 216 flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
 217 {
 218    struct anv_device *device = cmd_buffer->device;
 219    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 220    struct anv_state surfaces = { 0, }, samplers = { 0, };
 221    VkResult result;
 222
 223    result = anv_cmd_buffer_emit_samplers(cmd_buffer,
 224                                          MESA_SHADER_COMPUTE, &samplers);
 225    if (result != VK_SUCCESS)
 226       return result;
 227    result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
 228                                               MESA_SHADER_COMPUTE, &surfaces);
 229    if (result != VK_SUCCESS)
 230       return result;
 231
 232    struct anv_state push_state = anv_cmd_buffer_cs_push_constants(cmd_buffer);
 233
 234    const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
 235    const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
 236
 237    if (push_state.alloc_size) {
 238       anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD), curbe) {
 239          curbe.CURBETotalDataLength    = push_state.alloc_size;
 240          curbe.CURBEDataStartAddress   = push_state.offset;
 241       }
 242    }
 243
 244    const uint32_t slm_size = encode_slm_size(GEN_GEN, prog_data->total_shared);
 245
 246    struct anv_state state =
 247       anv_state_pool_emit(&device->dynamic_state_pool,
 248                           GENX(INTERFACE_DESCRIPTOR_DATA), 64,
 249                           .KernelStartPointer = pipeline->cs_simd,
 250                           .BindingTablePointer = surfaces.offset,
 251                           .SamplerStatePointer = samplers.offset,
 252                           .ConstantURBEntryReadLength =
 253                              cs_prog_data->push.per_thread.regs,
 254 #if GEN_IS_HASWELL
 255                           .CrossThreadConstantDataReadLength =
 256                              cs_prog_data->push.cross_thread.regs,
 257 #else
 258                           .ConstantURBEntryReadOffset = 0,
 259 #endif
 260                           .BarrierEnable = cs_prog_data->uses_barrier,
 261                           .SharedLocalMemorySize = slm_size,
 262                           .NumberofThreadsinGPGPUThreadGroup =
 263                              cs_prog_data->threads);
 264
 265    const uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
 266    anv_batch_emit(&cmd_buffer->batch,
 267                   GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), idl) {
 268       idl.InterfaceDescriptorTotalLength        = size;
 269       idl.InterfaceDescriptorDataStartAddress = state.offset;
 270    }
 271
 272    return VK_SUCCESS;
 273 }
 274
 275 void
 276 genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
 277 {
 278    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 279    MAYBE_UNUSED VkResult result;
 280
 281    assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
 282
 283    genX(cmd_buffer_config_l3)(cmd_buffer, pipeline);
 284
 285    genX(flush_pipeline_select_gpgpu)(cmd_buffer);
 286
 287    if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
 288       anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
 289
 290    if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
 291        (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
 292       /* FIXME: figure out descriptors for gen7 */
 293       result = flush_compute_descriptor_set(cmd_buffer);
 294       assert(result == VK_SUCCESS);
 295       cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
 296    }
 297
 298    cmd_buffer->state.compute_dirty = 0;
 299
 300    genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
 301 }
 302
 303 void
 304 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 305 {
 306    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 307
 308    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 309                                   ANV_CMD_DIRTY_RENDER_TARGETS |
 310                                   ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
 311                                   ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
 312
 313       const struct anv_image_view *iview =
 314          anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
 315       const struct anv_image *image = iview ? iview->image : NULL;
 316       const bool has_depth =
 317          image && (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT);
 318       const uint32_t depth_format = has_depth ?
 319          isl_surf_get_depth_format(&cmd_buffer->device->isl_dev,
 320                                    &image->depth_surface.isl) : D16_UNORM;
 321
 322       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 323       struct GENX(3DSTATE_SF) sf = {
 324          GENX(3DSTATE_SF_header),
 325          .DepthBufferSurfaceFormat = depth_format,
 326          .LineWidth = cmd_buffer->state.dynamic.line_width,
 327          .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
 328          .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
 329          .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
 330       };
 331       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 332
 333       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf);
 334    }
 335
 336    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 337                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 338       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 339       struct anv_state cc_state =
 340          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 341                                             GENX(COLOR_CALC_STATE_length) * 4,
 342                                             64);
 343       struct GENX(COLOR_CALC_STATE) cc = {
 344          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 345          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 346          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 347          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 348          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 349          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 350       };
 351       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 352       if (!cmd_buffer->device->info.has_llc)
 353          anv_state_clflush(cc_state);
 354
 355       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
 356          ccp.ColorCalcStatePointer = cc_state.offset;
 357       }
 358    }
 359
 360    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 361                                   ANV_CMD_DIRTY_RENDER_TARGETS |
 362                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 363                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 364       uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
 365       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 366
 367       struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
 368          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 369          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 370
 371          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 372          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 373       };
 374       GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil);
 375
 376       struct anv_state ds_state =
 377          anv_cmd_buffer_merge_dynamic(cmd_buffer, depth_stencil_dw,
 378                                       pipeline->gen7.depth_stencil_state,
 379                                       GENX(DEPTH_STENCIL_STATE_length), 64);
 380
 381       anv_batch_emit(&cmd_buffer->batch,
 382                      GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS), dsp) {
 383          dsp.PointertoDEPTH_STENCIL_STATE = ds_state.offset;
 384       }
 385    }
 386
 387    if (cmd_buffer->state.gen7.index_buffer &&
 388        cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 389                                   ANV_CMD_DIRTY_INDEX_BUFFER)) {
 390       struct anv_buffer *buffer = cmd_buffer->state.gen7.index_buffer;
 391       uint32_t offset = cmd_buffer->state.gen7.index_offset;
 392
 393 #if GEN_IS_HASWELL
 394       anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF, vf) {
 395          vf.IndexedDrawCutIndexEnable  = pipeline->primitive_restart;
 396          vf.CutIndex                   = cmd_buffer->state.restart_index;
 397       }
 398 #endif
 399
 400       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
 401 #if !GEN_IS_HASWELL
 402          ib.CutIndexEnable             = pipeline->primitive_restart;
 403 #endif
 404          ib.IndexFormat                = cmd_buffer->state.gen7.index_type;
 405          ib.MemoryObjectControlState   = GENX(MOCS);
 406
 407          ib.BufferStartingAddress =
 408             (struct anv_address) { buffer->bo, buffer->offset + offset };
 409          ib.BufferEndingAddress =
 410             (struct anv_address) { buffer->bo, buffer->offset + buffer->size };
 411       }
 412    }
 413
 414    cmd_buffer->state.dirty = 0;
 415 }
 416
 417 void genX(CmdSetEvent)(
 418     VkCommandBuffer                             commandBuffer,
 419     VkEvent                                     event,
 420     VkPipelineStageFlags                        stageMask)
 421 {
 422    stub();
 423 }
 424
 425 void genX(CmdResetEvent)(
 426     VkCommandBuffer                             commandBuffer,
 427     VkEvent                                     event,
 428     VkPipelineStageFlags                        stageMask)
 429 {
 430    stub();
 431 }
 432
 433 void genX(CmdWaitEvents)(
 434     VkCommandBuffer                             commandBuffer,
 435     uint32_t                                    eventCount,
 436     const VkEvent*                              pEvents,
 437     VkPipelineStageFlags                        srcStageMask,
 438     VkPipelineStageFlags                        destStageMask,
 439     uint32_t                                    memoryBarrierCount,
 440     const VkMemoryBarrier*                      pMemoryBarriers,
 441     uint32_t                                    bufferMemoryBarrierCount,
 442     const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
 443     uint32_t                                    imageMemoryBarrierCount,
 444     const VkImageMemoryBarrier*                 pImageMemoryBarriers)
 445 {
 446    stub();
 447
 448    genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
 449                             false, /* byRegion */
 450                             memoryBarrierCount, pMemoryBarriers,
 451                             bufferMemoryBarrierCount, pBufferMemoryBarriers,
 452                             imageMemoryBarrierCount, pImageMemoryBarriers);
 453 }