src/intel/vulkan/gen7_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #include "genX_pipeline_util.h"
  36
  37 VkResult
  38 genX(graphics_pipeline_create)(
  39     VkDevice                                    _device,
  40     struct anv_pipeline_cache *                 cache,
  41     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
  42     const struct anv_graphics_pipeline_create_info *extra,
  43     const VkAllocationCallbacks*                pAllocator,
  44     VkPipeline*                                 pPipeline)
  45 {
  46    ANV_FROM_HANDLE(anv_device, device, _device);
  47    ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
  48    struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
  49    struct anv_pipeline *pipeline;
  50    VkResult result;
  51
  52    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
  53
  54    pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
  55                          VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  56    if (pipeline == NULL)
  57       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
  58
  59    result = anv_pipeline_init(pipeline, device, cache,
  60                               pCreateInfo, extra, pAllocator);
  61    if (result != VK_SUCCESS) {
  62       anv_free2(&device->alloc, pAllocator, pipeline);
  63       return result;
  64    }
  65
  66    assert(pCreateInfo->pVertexInputState);
  67    emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
  68
  69    assert(pCreateInfo->pRasterizationState);
  70    emit_rs_state(pipeline, pCreateInfo->pRasterizationState,
  71                  pCreateInfo->pMultisampleState, pass, subpass, extra);
  72
  73    emit_ds_state(pipeline, pCreateInfo->pDepthStencilState, pass, subpass);
  74
  75    emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
  76                            pCreateInfo->pMultisampleState);
  77
  78    emit_urb_setup(pipeline);
  79
  80    emit_3dstate_clip(pipeline, pCreateInfo->pViewportState,
  81                      pCreateInfo->pRasterizationState, extra);
  82    emit_3dstate_streamout(pipeline, pCreateInfo->pRasterizationState);
  83
  84    emit_ms_state(pipeline, pCreateInfo->pMultisampleState);
  85
  86    const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
  87
  88 #if 0
  89    /* From gen7_vs_state.c */
  90
  91    /**
  92     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
  93     * Geometry > Geometry Shader > State:
  94     *
  95     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
  96     *     whole fixed function pipeline when the GS enable changes value in
  97     *     the 3DSTATE_GS."
  98     *
  99     * The hardware architects have clarified that in this context "flush the
 100     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
 101     * Stall" bit set.
 102     */
 103    if (!brw->is_haswell && !brw->is_baytrail)
 104       gen7_emit_vs_workaround_flush(brw);
 105 #endif
 106
 107    if (pipeline->vs_vec4 == NO_KERNEL || (extra && extra->disable_vs))
 108       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs);
 109    else
 110       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
 111          vs.KernelStartPointer         = pipeline->vs_vec4;
 112
 113          vs.ScratchSpaceBasePointer = (struct anv_address) {
 114             .bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
 115                                          MESA_SHADER_VERTEX,
 116                                          vs_prog_data->base.base.total_scratch),
 117             .offset = 0,
 118          };
 119          vs.PerThreadScratchSpace      = scratch_space(&vs_prog_data->base.base);
 120
 121          vs.DispatchGRFStartRegisterforURBData    =
 122             vs_prog_data->base.base.dispatch_grf_start_reg;
 123
 124          vs.VertexURBEntryReadLength   = vs_prog_data->base.urb_read_length;
 125          vs.VertexURBEntryReadOffset   = 0;
 126          vs.MaximumNumberofThreads     = device->info.max_vs_threads - 1;
 127          vs.StatisticsEnable           = true;
 128          vs.VSFunctionEnable           = true;
 129       }
 130
 131    const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
 132
 133    if (pipeline->gs_kernel == NO_KERNEL || (extra && extra->disable_vs)) {
 134       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs);
 135    } else {
 136       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs) {
 137          gs.KernelStartPointer         = pipeline->gs_kernel;
 138
 139          gs.ScratchSpaceBasePointer = (struct anv_address) {
 140             .bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
 141                                          MESA_SHADER_GEOMETRY,
 142                                          gs_prog_data->base.base.total_scratch),
 143             .offset = 0,
 144          };
 145          gs.PerThreadScratchSpace      = scratch_space(&gs_prog_data->base.base);
 146
 147          gs.OutputVertexSize           = gs_prog_data->output_vertex_size_hwords * 2 - 1;
 148          gs.OutputTopology             = gs_prog_data->output_topology;
 149          gs.VertexURBEntryReadLength   = gs_prog_data->base.urb_read_length;
 150          gs.IncludeVertexHandles       = gs_prog_data->base.include_vue_handles;
 151
 152          gs.DispatchGRFStartRegisterforURBData =
 153             gs_prog_data->base.base.dispatch_grf_start_reg;
 154
 155          gs.MaximumNumberofThreads     = device->info.max_gs_threads - 1;
 156          /* This in the next dword on HSW. */
 157          gs.ControlDataFormat          = gs_prog_data->control_data_format;
 158          gs.ControlDataHeaderSize      = gs_prog_data->control_data_header_size_hwords;
 159          gs.InstanceControl            = MAX2(gs_prog_data->invocations, 1) - 1;
 160          gs.DispatchMode               = gs_prog_data->base.dispatch_mode;
 161          gs.GSStatisticsEnable         = true;
 162          gs.IncludePrimitiveID         = gs_prog_data->include_primitive_id;
 163 #     if (GEN_IS_HASWELL)
 164          gs.ReorderMode                = REORDER_TRAILING;
 165 #     else
 166          gs.ReorderEnable              = true;
 167 #     endif
 168          gs.GSEnable                   = true;
 169       }
 170    }
 171
 172    if (pipeline->ps_ksp0 == NO_KERNEL) {
 173       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE), sbe);
 174
 175       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM), wm) {
 176          wm.StatisticsEnable                    = true;
 177          wm.ThreadDispatchEnable                = false;
 178          wm.LineEndCapAntialiasingRegionWidth   = 0; /* 0.5 pixels */
 179          wm.LineAntialiasingRegionWidth         = 1; /* 1.0 pixels */
 180          wm.EarlyDepthStencilControl            = EDSC_NORMAL;
 181          wm.PointRasterizationRule              = RASTRULE_UPPER_RIGHT;
 182       }
 183
 184       /* Even if no fragments are ever dispatched, the hardware hangs if we
 185        * don't at least set the maximum number of threads.
 186        */
 187       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) {
 188          ps.MaximumNumberofThreads = device->info.max_wm_threads - 1;
 189       }
 190    } else {
 191       const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
 192       if (wm_prog_data->urb_setup[VARYING_SLOT_BFC0] != -1 ||
 193           wm_prog_data->urb_setup[VARYING_SLOT_BFC1] != -1)
 194          anv_finishme("two-sided color needs sbe swizzling setup");
 195       if (wm_prog_data->urb_setup[VARYING_SLOT_PRIMITIVE_ID] != -1)
 196          anv_finishme("primitive_id needs sbe swizzling setup");
 197
 198       emit_3dstate_sbe(pipeline);
 199
 200       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) {
 201          ps.KernelStartPointer0           = pipeline->ps_ksp0;
 202
 203          ps.ScratchSpaceBasePointer = (struct anv_address) {
 204             .bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
 205                                          MESA_SHADER_FRAGMENT,
 206                                          wm_prog_data->base.total_scratch),
 207             .offset = 0,
 208          };
 209          ps.PerThreadScratchSpace         = scratch_space(&wm_prog_data->base);
 210          ps.MaximumNumberofThreads        = device->info.max_wm_threads - 1;
 211          ps.PushConstantEnable            = wm_prog_data->base.nr_params > 0;
 212          ps.AttributeEnable               = wm_prog_data->num_varying_inputs > 0;
 213          ps.oMaskPresenttoRenderTarget    = wm_prog_data->uses_omask;
 214
 215          ps.RenderTargetFastClearEnable   = false;
 216          ps.DualSourceBlendEnable         = false;
 217          ps.RenderTargetResolveEnable     = false;
 218
 219          ps.PositionXYOffsetSelect        = wm_prog_data->uses_pos_offset ?
 220                                             POSOFFSET_SAMPLE : POSOFFSET_NONE;
 221
 222          ps._32PixelDispatchEnable        = false;
 223          ps._16PixelDispatchEnable        = wm_prog_data->dispatch_16;
 224          ps._8PixelDispatchEnable         = wm_prog_data->dispatch_8;
 225
 226          ps.DispatchGRFStartRegisterforConstantSetupData0 =
 227             wm_prog_data->base.dispatch_grf_start_reg,
 228          ps.DispatchGRFStartRegisterforConstantSetupData1 = 0,
 229          ps.DispatchGRFStartRegisterforConstantSetupData2 =
 230             wm_prog_data->dispatch_grf_start_reg_2,
 231
 232          /* Haswell requires the sample mask to be set in this packet as well as
 233           * in 3DSTATE_SAMPLE_MASK; the values should match. */
 234          /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 235
 236          ps.KernelStartPointer1           = 0;
 237          ps.KernelStartPointer2           = pipeline->ps_ksp0 + wm_prog_data->prog_offset_2;
 238       }
 239
 240       uint32_t samples = pCreateInfo->pMultisampleState ?
 241                          pCreateInfo->pMultisampleState->rasterizationSamples : 1;
 242
 243       /* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
 244       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM), wm) {
 245          wm.StatisticsEnable                    = true;
 246          wm.ThreadDispatchEnable                = true;
 247          wm.LineEndCapAntialiasingRegionWidth   = 0; /* 0.5 pixels */
 248          wm.LineAntialiasingRegionWidth         = 1; /* 1.0 pixels */
 249          wm.PointRasterizationRule              = RASTRULE_UPPER_RIGHT;
 250          wm.PixelShaderKillPixel                = wm_prog_data->uses_kill;
 251          wm.PixelShaderComputedDepthMode        = wm_prog_data->computed_depth_mode;
 252          wm.PixelShaderUsesSourceDepth          = wm_prog_data->uses_src_depth;
 253          wm.PixelShaderUsesSourceW              = wm_prog_data->uses_src_w;
 254          wm.PixelShaderUsesInputCoverageMask    = wm_prog_data->uses_sample_mask;
 255
 256          if (wm_prog_data->early_fragment_tests) {
 257             wm.EarlyDepthStencilControl         = EDSC_PREPS;
 258          } else if (wm_prog_data->has_side_effects) {
 259             wm.EarlyDepthStencilControl         = EDSC_PSEXEC;
 260          } else {
 261             wm.EarlyDepthStencilControl         = EDSC_NORMAL;
 262          }
 263
 264          wm.BarycentricInterpolationMode        = wm_prog_data->barycentric_interp_modes;
 265
 266          wm.MultisampleRasterizationMode        = samples > 1 ?
 267                                                   MSRASTMODE_ON_PATTERN : MSRASTMODE_OFF_PIXEL;
 268          wm.MultisampleDispatchMode             = wm_prog_data->persample_dispatch ?
 269                                                   MSDISPMODE_PERSAMPLE : MSDISPMODE_PERPIXEL;
 270       }
 271    }
 272
 273    *pPipeline = anv_pipeline_to_handle(pipeline);
 274
 275    return VK_SUCCESS;
 276 }