src/intel/vulkan/gen7_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #include "genX_pipeline_util.h"
  36
  37 VkResult
  38 genX(graphics_pipeline_create)(
  39     VkDevice                                    _device,
  40     struct anv_pipeline_cache *                 cache,
  41     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
  42     const struct anv_graphics_pipeline_create_info *extra,
  43     const VkAllocationCallbacks*                pAllocator,
  44     VkPipeline*                                 pPipeline)
  45 {
  46    ANV_FROM_HANDLE(anv_device, device, _device);
  47    ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
  48    const struct anv_physical_device *physical_device =
  49       &device->instance->physicalDevice;
  50    const struct gen_device_info *devinfo = &physical_device->info;
  51    struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
  52    struct anv_pipeline *pipeline;
  53    VkResult result;
  54
  55    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
  56
  57    pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
  58                          VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  59    if (pipeline == NULL)
  60       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
  61
  62    result = anv_pipeline_init(pipeline, device, cache,
  63                               pCreateInfo, extra, pAllocator);
  64    if (result != VK_SUCCESS) {
  65       anv_free2(&device->alloc, pAllocator, pipeline);
  66       return result;
  67    }
  68
  69    assert(pCreateInfo->pVertexInputState);
  70    emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
  71
  72    assert(pCreateInfo->pRasterizationState);
  73    emit_rs_state(pipeline, pCreateInfo->pRasterizationState,
  74                  pCreateInfo->pMultisampleState, pass, subpass, extra);
  75
  76    emit_ds_state(pipeline, pCreateInfo->pDepthStencilState, pass, subpass);
  77
  78    emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
  79                            pCreateInfo->pMultisampleState);
  80
  81    emit_urb_setup(pipeline);
  82
  83    emit_3dstate_clip(pipeline, pCreateInfo->pViewportState,
  84                      pCreateInfo->pRasterizationState, extra);
  85    emit_3dstate_streamout(pipeline, pCreateInfo->pRasterizationState);
  86
  87    emit_ms_state(pipeline, pCreateInfo->pMultisampleState);
  88
  89    const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
  90
  91 #if 0
  92    /* From gen7_vs_state.c */
  93
  94    /**
  95     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
  96     * Geometry > Geometry Shader > State:
  97     *
  98     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
  99     *     whole fixed function pipeline when the GS enable changes value in
 100     *     the 3DSTATE_GS."
 101     *
 102     * The hardware architects have clarified that in this context "flush the
 103     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
 104     * Stall" bit set.
 105     */
 106    if (!brw->is_haswell && !brw->is_baytrail)
 107       gen7_emit_vs_workaround_flush(brw);
 108 #endif
 109
 110    if (pipeline->vs_vec4 == NO_KERNEL || (extra && extra->disable_vs))
 111       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs);
 112    else
 113       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
 114          vs.KernelStartPointer         = pipeline->vs_vec4;
 115
 116          vs.ScratchSpaceBasePointer = (struct anv_address) {
 117             .bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
 118                                          MESA_SHADER_VERTEX,
 119                                          vs_prog_data->base.base.total_scratch),
 120             .offset = 0,
 121          };
 122          vs.PerThreadScratchSpace      = scratch_space(&vs_prog_data->base.base);
 123
 124          vs.DispatchGRFStartRegisterforURBData    =
 125             vs_prog_data->base.base.dispatch_grf_start_reg;
 126
 127          vs.VertexURBEntryReadLength   = vs_prog_data->base.urb_read_length;
 128          vs.VertexURBEntryReadOffset   = 0;
 129          vs.MaximumNumberofThreads     = devinfo->max_vs_threads - 1;
 130          vs.StatisticsEnable           = true;
 131          vs.VSFunctionEnable           = true;
 132       }
 133
 134    const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
 135
 136    if (pipeline->gs_kernel == NO_KERNEL || (extra && extra->disable_vs)) {
 137       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs);
 138    } else {
 139       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs) {
 140          gs.KernelStartPointer         = pipeline->gs_kernel;
 141
 142          gs.ScratchSpaceBasePointer = (struct anv_address) {
 143             .bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
 144                                          MESA_SHADER_GEOMETRY,
 145                                          gs_prog_data->base.base.total_scratch),
 146             .offset = 0,
 147          };
 148          gs.PerThreadScratchSpace      = scratch_space(&gs_prog_data->base.base);
 149
 150          gs.OutputVertexSize           = gs_prog_data->output_vertex_size_hwords * 2 - 1;
 151          gs.OutputTopology             = gs_prog_data->output_topology;
 152          gs.VertexURBEntryReadLength   = gs_prog_data->base.urb_read_length;
 153          gs.IncludeVertexHandles       = gs_prog_data->base.include_vue_handles;
 154
 155          gs.DispatchGRFStartRegisterforURBData =
 156             gs_prog_data->base.base.dispatch_grf_start_reg;
 157
 158          gs.MaximumNumberofThreads     = devinfo->max_gs_threads - 1;
 159          /* This in the next dword on HSW. */
 160          gs.ControlDataFormat          = gs_prog_data->control_data_format;
 161          gs.ControlDataHeaderSize      = gs_prog_data->control_data_header_size_hwords;
 162          gs.InstanceControl            = MAX2(gs_prog_data->invocations, 1) - 1;
 163          gs.DispatchMode               = gs_prog_data->base.dispatch_mode;
 164          gs.GSStatisticsEnable         = true;
 165          gs.IncludePrimitiveID         = gs_prog_data->include_primitive_id;
 166 #     if (GEN_IS_HASWELL)
 167          gs.ReorderMode                = REORDER_TRAILING;
 168 #     else
 169          gs.ReorderEnable              = true;
 170 #     endif
 171          gs.GSEnable                   = true;
 172       }
 173    }
 174
 175    if (pipeline->ps_ksp0 == NO_KERNEL) {
 176       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE), sbe);
 177
 178       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM), wm) {
 179          wm.StatisticsEnable                    = true;
 180          wm.ThreadDispatchEnable                = false;
 181          wm.LineEndCapAntialiasingRegionWidth   = 0; /* 0.5 pixels */
 182          wm.LineAntialiasingRegionWidth         = 1; /* 1.0 pixels */
 183          wm.EarlyDepthStencilControl            = EDSC_NORMAL;
 184          wm.PointRasterizationRule              = RASTRULE_UPPER_RIGHT;
 185       }
 186
 187       /* Even if no fragments are ever dispatched, the hardware hangs if we
 188        * don't at least set the maximum number of threads.
 189        */
 190       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) {
 191          ps.MaximumNumberofThreads = devinfo->max_wm_threads - 1;
 192       }
 193    } else {
 194       const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
 195       if (wm_prog_data->urb_setup[VARYING_SLOT_BFC0] != -1 ||
 196           wm_prog_data->urb_setup[VARYING_SLOT_BFC1] != -1)
 197          anv_finishme("two-sided color needs sbe swizzling setup");
 198       if (wm_prog_data->urb_setup[VARYING_SLOT_PRIMITIVE_ID] != -1)
 199          anv_finishme("primitive_id needs sbe swizzling setup");
 200
 201       emit_3dstate_sbe(pipeline);
 202
 203       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) {
 204          ps.KernelStartPointer0           = pipeline->ps_ksp0;
 205
 206          ps.ScratchSpaceBasePointer = (struct anv_address) {
 207             .bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
 208                                          MESA_SHADER_FRAGMENT,
 209                                          wm_prog_data->base.total_scratch),
 210             .offset = 0,
 211          };
 212          ps.PerThreadScratchSpace         = scratch_space(&wm_prog_data->base);
 213          ps.MaximumNumberofThreads        = devinfo->max_wm_threads - 1;
 214          ps.PushConstantEnable            = wm_prog_data->base.nr_params > 0;
 215          ps.AttributeEnable               = wm_prog_data->num_varying_inputs > 0;
 216          ps.oMaskPresenttoRenderTarget    = wm_prog_data->uses_omask;
 217
 218          ps.RenderTargetFastClearEnable   = false;
 219          ps.DualSourceBlendEnable         = false;
 220          ps.RenderTargetResolveEnable     = false;
 221
 222          ps.PositionXYOffsetSelect        = wm_prog_data->uses_pos_offset ?
 223                                             POSOFFSET_SAMPLE : POSOFFSET_NONE;
 224
 225          ps._32PixelDispatchEnable        = false;
 226          ps._16PixelDispatchEnable        = wm_prog_data->dispatch_16;
 227          ps._8PixelDispatchEnable         = wm_prog_data->dispatch_8;
 228
 229          ps.DispatchGRFStartRegisterforConstantSetupData0 =
 230             wm_prog_data->base.dispatch_grf_start_reg,
 231          ps.DispatchGRFStartRegisterforConstantSetupData1 = 0,
 232          ps.DispatchGRFStartRegisterforConstantSetupData2 =
 233             wm_prog_data->dispatch_grf_start_reg_2,
 234
 235          /* Haswell requires the sample mask to be set in this packet as well as
 236           * in 3DSTATE_SAMPLE_MASK; the values should match. */
 237          /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 238
 239          ps.KernelStartPointer1           = 0;
 240          ps.KernelStartPointer2           = pipeline->ps_ksp0 + wm_prog_data->prog_offset_2;
 241       }
 242
 243       uint32_t samples = pCreateInfo->pMultisampleState ?
 244                          pCreateInfo->pMultisampleState->rasterizationSamples : 1;
 245
 246       /* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
 247       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM), wm) {
 248          wm.StatisticsEnable                    = true;
 249          wm.ThreadDispatchEnable                = true;
 250          wm.LineEndCapAntialiasingRegionWidth   = 0; /* 0.5 pixels */
 251          wm.LineAntialiasingRegionWidth         = 1; /* 1.0 pixels */
 252          wm.PointRasterizationRule              = RASTRULE_UPPER_RIGHT;
 253          wm.PixelShaderKillPixel                = wm_prog_data->uses_kill;
 254          wm.PixelShaderComputedDepthMode        = wm_prog_data->computed_depth_mode;
 255          wm.PixelShaderUsesSourceDepth          = wm_prog_data->uses_src_depth;
 256          wm.PixelShaderUsesSourceW              = wm_prog_data->uses_src_w;
 257          wm.PixelShaderUsesInputCoverageMask    = wm_prog_data->uses_sample_mask;
 258
 259          if (wm_prog_data->early_fragment_tests) {
 260             wm.EarlyDepthStencilControl         = EDSC_PREPS;
 261          } else if (wm_prog_data->has_side_effects) {
 262             wm.EarlyDepthStencilControl         = EDSC_PSEXEC;
 263          } else {
 264             wm.EarlyDepthStencilControl         = EDSC_NORMAL;
 265          }
 266
 267          wm.BarycentricInterpolationMode        = wm_prog_data->barycentric_interp_modes;
 268
 269          wm.MultisampleRasterizationMode        = samples > 1 ?
 270                                                   MSRASTMODE_ON_PATTERN : MSRASTMODE_OFF_PIXEL;
 271          wm.MultisampleDispatchMode             = wm_prog_data->persample_dispatch ?
 272                                                   MSDISPMODE_PERSAMPLE : MSDISPMODE_PERPIXEL;
 273       }
 274    }
 275
 276    *pPipeline = anv_pipeline_to_handle(pipeline);
 277
 278    return VK_SUCCESS;
 279 }