src/intel/vulkan/gen7_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #include "genX_pipeline_util.h"
  36
  37 static void
  38 gen7_emit_rs_state(struct anv_pipeline *pipeline,
  39                    const VkPipelineRasterizationStateCreateInfo *info,
  40                    const struct anv_graphics_pipeline_create_info *extra)
  41 {
  42    struct GENX(3DSTATE_SF) sf = {
  43       GENX(3DSTATE_SF_header),
  44
  45       /* LegacyGlobalDepthBiasEnable */
  46
  47       .StatisticsEnable                         = true,
  48       .FrontFaceFillMode                        = vk_to_gen_fillmode[info->polygonMode],
  49       .BackFaceFillMode                         = vk_to_gen_fillmode[info->polygonMode],
  50       .ViewTransformEnable                      = !(extra && extra->use_rectlist),
  51       .FrontWinding                             = vk_to_gen_front_face[info->frontFace],
  52       /* bool                                         AntiAliasingEnable; */
  53
  54       .CullMode                                 = vk_to_gen_cullmode[info->cullMode],
  55
  56       /* uint32_t                                     LineEndCapAntialiasingRegionWidth; */
  57       .ScissorRectangleEnable                   =  !(extra && extra->use_rectlist),
  58
  59       /* uint32_t                                     MultisampleRasterizationMode; */
  60       /* bool                                         LastPixelEnable; */
  61
  62       .TriangleStripListProvokingVertexSelect   = 0,
  63       .LineStripListProvokingVertexSelect       = 0,
  64       .TriangleFanProvokingVertexSelect         = 1,
  65
  66       /* uint32_t                                     AALineDistanceMode; */
  67       /* uint32_t                                     VertexSubPixelPrecisionSelect; */
  68       .UsePointWidthState                       = false,
  69       .PointWidth                               = 1.0,
  70       .GlobalDepthOffsetEnableSolid             = info->depthBiasEnable,
  71       .GlobalDepthOffsetEnableWireframe         = info->depthBiasEnable,
  72       .GlobalDepthOffsetEnablePoint             = info->depthBiasEnable,
  73    };
  74
  75    GENX(3DSTATE_SF_pack)(NULL, &pipeline->gen7.sf, &sf);
  76 }
  77
  78 static void
  79 gen7_emit_ds_state(struct anv_pipeline *pipeline,
  80                    const VkPipelineDepthStencilStateCreateInfo *info)
  81 {
  82    if (info == NULL) {
  83       /* We're going to OR this together with the dynamic state.  We need
  84        * to make sure it's initialized to something useful.
  85        */
  86       memset(pipeline->gen7.depth_stencil_state, 0,
  87              sizeof(pipeline->gen7.depth_stencil_state));
  88       return;
  89    }
  90
  91    struct GENX(DEPTH_STENCIL_STATE) state = {
  92       .DepthTestEnable = info->depthTestEnable,
  93       .DepthBufferWriteEnable = info->depthWriteEnable,
  94       .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
  95       .DoubleSidedStencilEnable = true,
  96
  97       .StencilTestEnable = info->stencilTestEnable,
  98       .StencilBufferWriteEnable = info->stencilTestEnable,
  99       .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
 100       .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
 101       .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
 102       .StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp],
 103
 104       .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp],
 105       .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp],
 106       .BackfaceStencilPassDepthFailOp = vk_to_gen_stencil_op[info->back.depthFailOp],
 107       .BackFaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
 108    };
 109
 110    GENX(DEPTH_STENCIL_STATE_pack)(NULL, &pipeline->gen7.depth_stencil_state, &state);
 111 }
 112
 113 static void
 114 gen7_emit_cb_state(struct anv_pipeline *pipeline,
 115                    const VkPipelineColorBlendStateCreateInfo *info,
 116                    const VkPipelineMultisampleStateCreateInfo *ms_info)
 117 {
 118    struct anv_device *device = pipeline->device;
 119
 120    if (info == NULL || info->attachmentCount == 0) {
 121       pipeline->blend_state =
 122          anv_state_pool_emit(&device->dynamic_state_pool,
 123             GENX(BLEND_STATE), 64,
 124             .ColorBufferBlendEnable = false,
 125             .WriteDisableAlpha = true,
 126             .WriteDisableRed = true,
 127             .WriteDisableGreen = true,
 128             .WriteDisableBlue = true);
 129    } else {
 130       const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[0];
 131       struct GENX(BLEND_STATE) blend = {
 132          .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
 133          .AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable,
 134
 135          .LogicOpEnable = info->logicOpEnable,
 136          .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
 137          .ColorBufferBlendEnable = a->blendEnable,
 138          .ColorClampRange = COLORCLAMP_RTFORMAT,
 139          .PreBlendColorClampEnable = true,
 140          .PostBlendColorClampEnable = true,
 141          .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
 142          .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
 143          .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
 144          .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
 145          .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
 146          .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
 147          .WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
 148          .WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
 149          .WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
 150          .WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
 151       };
 152
 153       /* Our hardware applies the blend factor prior to the blend function
 154        * regardless of what function is used.  Technically, this means the
 155        * hardware can do MORE than GL or Vulkan specify.  However, it also
 156        * means that, for MIN and MAX, we have to stomp the blend factor to
 157        * ONE to make it a no-op.
 158        */
 159       if (a->colorBlendOp == VK_BLEND_OP_MIN ||
 160           a->colorBlendOp == VK_BLEND_OP_MAX) {
 161          blend.SourceBlendFactor = BLENDFACTOR_ONE;
 162          blend.DestinationBlendFactor = BLENDFACTOR_ONE;
 163       }
 164       if (a->alphaBlendOp == VK_BLEND_OP_MIN ||
 165           a->alphaBlendOp == VK_BLEND_OP_MAX) {
 166          blend.SourceAlphaBlendFactor = BLENDFACTOR_ONE;
 167          blend.DestinationAlphaBlendFactor = BLENDFACTOR_ONE;
 168       }
 169
 170       pipeline->blend_state = anv_state_pool_alloc(&device->dynamic_state_pool,
 171                                                    GENX(BLEND_STATE_length) * 4,
 172                                                    64);
 173       GENX(BLEND_STATE_pack)(NULL, pipeline->blend_state.map, &blend);
 174       if (pipeline->device->info.has_llc)
 175          anv_state_clflush(pipeline->blend_state);
 176     }
 177
 178    anv_batch_emit_blk(&pipeline->batch,
 179                       GENX(3DSTATE_BLEND_STATE_POINTERS), bsp) {
 180       bsp.BlendStatePointer = pipeline->blend_state.offset;
 181    }
 182 }
 183
 184 VkResult
 185 genX(graphics_pipeline_create)(
 186     VkDevice                                    _device,
 187     struct anv_pipeline_cache *                 cache,
 188     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
 189     const struct anv_graphics_pipeline_create_info *extra,
 190     const VkAllocationCallbacks*                pAllocator,
 191     VkPipeline*                                 pPipeline)
 192 {
 193    ANV_FROM_HANDLE(anv_device, device, _device);
 194    struct anv_pipeline *pipeline;
 195    VkResult result;
 196
 197    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
 198
 199    pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
 200                          VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 201    if (pipeline == NULL)
 202       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 203
 204    result = anv_pipeline_init(pipeline, device, cache,
 205                               pCreateInfo, extra, pAllocator);
 206    if (result != VK_SUCCESS) {
 207       anv_free2(&device->alloc, pAllocator, pipeline);
 208       return result;
 209    }
 210
 211    assert(pCreateInfo->pVertexInputState);
 212    emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
 213
 214    assert(pCreateInfo->pRasterizationState);
 215    gen7_emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
 216
 217    gen7_emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
 218
 219    gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
 220                                 pCreateInfo->pMultisampleState);
 221
 222    emit_urb_setup(pipeline);
 223
 224    const VkPipelineRasterizationStateCreateInfo *rs_info =
 225       pCreateInfo->pRasterizationState;
 226
 227    anv_batch_emit_blk(&pipeline->batch, GENX(3DSTATE_CLIP), clip) {
 228       clip.FrontWinding             = vk_to_gen_front_face[rs_info->frontFace],
 229       clip.CullMode                 = vk_to_gen_cullmode[rs_info->cullMode],
 230       clip.ClipEnable               = !(extra && extra->use_rectlist),
 231       clip.APIMode                  = APIMODE_OGL,
 232       clip.ViewportXYClipTestEnable = true,
 233       clip.ClipMode                 = CLIPMODE_NORMAL,
 234
 235       clip.TriangleStripListProvokingVertexSelect   = 0,
 236       clip.LineStripListProvokingVertexSelect       = 0,
 237       clip.TriangleFanProvokingVertexSelect         = 1,
 238
 239       clip.MinimumPointWidth        = 0.125,
 240       clip.MaximumPointWidth        = 255.875,
 241       clip.MaximumVPIndex = pCreateInfo->pViewportState->viewportCount - 1;
 242    }
 243
 244    if (pCreateInfo->pMultisampleState &&
 245        pCreateInfo->pMultisampleState->rasterizationSamples > 1)
 246       anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO");
 247
 248    uint32_t samples = 1;
 249    uint32_t log2_samples = __builtin_ffs(samples) - 1;
 250
 251    anv_batch_emit_blk(&pipeline->batch, GENX(3DSTATE_MULTISAMPLE), ms) {
 252       ms.PixelLocation        = PIXLOC_CENTER;
 253       ms.NumberofMultisamples = log2_samples;
 254    }
 255
 256    anv_batch_emit_blk(&pipeline->batch, GENX(3DSTATE_SAMPLE_MASK), sm) {
 257       sm.SampleMask = 0xff;
 258    }
 259
 260    const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
 261
 262 #if 0
 263    /* From gen7_vs_state.c */
 264
 265    /**
 266     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
 267     * Geometry > Geometry Shader > State:
 268     *
 269     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
 270     *     whole fixed function pipeline when the GS enable changes value in
 271     *     the 3DSTATE_GS."
 272     *
 273     * The hardware architects have clarified that in this context "flush the
 274     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
 275     * Stall" bit set.
 276     */
 277    if (!brw->is_haswell && !brw->is_baytrail)
 278       gen7_emit_vs_workaround_flush(brw);
 279 #endif
 280
 281    if (pipeline->vs_vec4 == NO_KERNEL || (extra && extra->disable_vs))
 282       anv_batch_emit_blk(&pipeline->batch, GENX(3DSTATE_VS), vs);
 283    else
 284       anv_batch_emit_blk(&pipeline->batch, GENX(3DSTATE_VS), vs) {
 285          vs.KernelStartPointer         = pipeline->vs_vec4;
 286          vs.ScratchSpaceBaseOffset     = pipeline->scratch_start[MESA_SHADER_VERTEX];
 287          vs.PerThreadScratchSpace      = scratch_space(&vs_prog_data->base.base);
 288
 289          vs.DispatchGRFStartRegisterforURBData    =
 290             vs_prog_data->base.base.dispatch_grf_start_reg;
 291
 292          vs.VertexURBEntryReadLength   = vs_prog_data->base.urb_read_length;
 293          vs.VertexURBEntryReadOffset   = 0;
 294          vs.MaximumNumberofThreads     = device->info.max_vs_threads - 1;
 295          vs.StatisticsEnable           = true;
 296          vs.VSFunctionEnable           = true;
 297       }
 298
 299    const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
 300
 301    if (pipeline->gs_kernel == NO_KERNEL || (extra && extra->disable_vs)) {
 302       anv_batch_emit_blk(&pipeline->batch, GENX(3DSTATE_GS), gs);
 303    } else {
 304       anv_batch_emit_blk(&pipeline->batch, GENX(3DSTATE_GS), gs) {
 305          gs.KernelStartPointer         = pipeline->gs_kernel;
 306          gs.ScratchSpaceBasePointer    = pipeline->scratch_start[MESA_SHADER_GEOMETRY];
 307          gs.PerThreadScratchSpace      = scratch_space(&gs_prog_data->base.base);
 308
 309          gs.OutputVertexSize           = gs_prog_data->output_vertex_size_hwords * 2 - 1;
 310          gs.OutputTopology             = gs_prog_data->output_topology;
 311          gs.VertexURBEntryReadLength   = gs_prog_data->base.urb_read_length;
 312          gs.IncludeVertexHandles       = gs_prog_data->base.include_vue_handles;
 313
 314          gs.DispatchGRFStartRegisterforURBData =
 315             gs_prog_data->base.base.dispatch_grf_start_reg;
 316
 317          gs.MaximumNumberofThreads     = device->info.max_gs_threads - 1;
 318          /* This in the next dword on HSW. */
 319          gs.ControlDataFormat          = gs_prog_data->control_data_format;
 320          gs.ControlDataHeaderSize      = gs_prog_data->control_data_header_size_hwords;
 321          gs.InstanceControl            = MAX2(gs_prog_data->invocations, 1) - 1;
 322          gs.DispatchMode               = gs_prog_data->base.dispatch_mode;
 323          gs.GSStatisticsEnable         = true;
 324          gs.IncludePrimitiveID         = gs_prog_data->include_primitive_id;
 325 #     if (GEN_IS_HASWELL)
 326          gs.ReorderMode                = REORDER_TRAILING;
 327 #     else
 328          gs.ReorderEnable              = true;
 329 #     endif
 330          gs.GSEnable                   = true;
 331       }
 332    }
 333
 334    if (pipeline->ps_ksp0 == NO_KERNEL) {
 335       anv_batch_emit_blk(&pipeline->batch, GENX(3DSTATE_SBE), sbe);
 336
 337       anv_batch_emit_blk(&pipeline->batch, GENX(3DSTATE_WM), wm) {
 338          wm.StatisticsEnable                    = true;
 339          wm.ThreadDispatchEnable                = false;
 340          wm.LineEndCapAntialiasingRegionWidth   = 0; /* 0.5 pixels */
 341          wm.LineAntialiasingRegionWidth         = 1; /* 1.0 pixels */
 342          wm.EarlyDepthStencilControl            = EDSC_NORMAL;
 343          wm.PointRasterizationRule              = RASTRULE_UPPER_RIGHT;
 344       }
 345
 346       /* Even if no fragments are ever dispatched, the hardware hangs if we
 347        * don't at least set the maximum number of threads.
 348        */
 349       anv_batch_emit_blk(&pipeline->batch, GENX(3DSTATE_PS), ps) {
 350          ps.MaximumNumberofThreads = device->info.max_wm_threads - 1;
 351       }
 352    } else {
 353       const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
 354       if (wm_prog_data->urb_setup[VARYING_SLOT_BFC0] != -1 ||
 355           wm_prog_data->urb_setup[VARYING_SLOT_BFC1] != -1)
 356          anv_finishme("two-sided color needs sbe swizzling setup");
 357       if (wm_prog_data->urb_setup[VARYING_SLOT_PRIMITIVE_ID] != -1)
 358          anv_finishme("primitive_id needs sbe swizzling setup");
 359
 360       emit_3dstate_sbe(pipeline);
 361
 362       anv_batch_emit_blk(&pipeline->batch, GENX(3DSTATE_PS), ps) {
 363          ps.KernelStartPointer0           = pipeline->ps_ksp0;
 364          ps.ScratchSpaceBasePointer       = pipeline->scratch_start[MESA_SHADER_FRAGMENT];
 365          ps.PerThreadScratchSpace         = scratch_space(&wm_prog_data->base);
 366          ps.MaximumNumberofThreads        = device->info.max_wm_threads - 1;
 367          ps.PushConstantEnable            = wm_prog_data->base.nr_params > 0;
 368          ps.AttributeEnable               = wm_prog_data->num_varying_inputs > 0;
 369          ps.oMaskPresenttoRenderTarget    = wm_prog_data->uses_omask;
 370
 371          ps.RenderTargetFastClearEnable   = false;
 372          ps.DualSourceBlendEnable         = false;
 373          ps.RenderTargetResolveEnable     = false;
 374
 375          ps.PositionXYOffsetSelect        = wm_prog_data->uses_pos_offset ?
 376                                             POSOFFSET_SAMPLE : POSOFFSET_NONE;
 377
 378          ps._32PixelDispatchEnable        = false;
 379          ps._16PixelDispatchEnable        = pipeline->ps_simd16 != NO_KERNEL;
 380          ps._8PixelDispatchEnable         = pipeline->ps_simd8 != NO_KERNEL;
 381
 382          ps.DispatchGRFStartRegisterforConstantSetupData0 = pipeline->ps_grf_start0,
 383          ps.DispatchGRFStartRegisterforConstantSetupData1 = 0,
 384          ps.DispatchGRFStartRegisterforConstantSetupData2 = pipeline->ps_grf_start2,
 385
 386          /* Haswell requires the sample mask to be set in this packet as well as
 387           * in 3DSTATE_SAMPLE_MASK; the values should match. */
 388          /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 389
 390          ps.KernelStartPointer1           = 0;
 391          ps.KernelStartPointer2           = pipeline->ps_ksp2;
 392       }
 393
 394       /* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
 395       anv_batch_emit_blk(&pipeline->batch, GENX(3DSTATE_WM), wm) {
 396          wm.StatisticsEnable                    = true;
 397          wm.ThreadDispatchEnable                = true;
 398          wm.LineEndCapAntialiasingRegionWidth   = 0; /* 0.5 pixels */
 399          wm.LineAntialiasingRegionWidth         = 1; /* 1.0 pixels */
 400          wm.EarlyDepthStencilControl            = EDSC_NORMAL;
 401          wm.PointRasterizationRule              = RASTRULE_UPPER_RIGHT;
 402          wm.PixelShaderComputedDepthMode        = wm_prog_data->computed_depth_mode;
 403          wm.PixelShaderUsesSourceDepth          = wm_prog_data->uses_src_depth;
 404          wm.PixelShaderUsesSourceW              = wm_prog_data->uses_src_w;
 405          wm.PixelShaderUsesInputCoverageMask    = wm_prog_data->uses_sample_mask;
 406          wm.BarycentricInterpolationMode        = wm_prog_data->barycentric_interp_modes;
 407       }
 408    }
 409
 410    *pPipeline = anv_pipeline_to_handle(pipeline);
 411
 412    return VK_SUCCESS;
 413 }