src/intel/vulkan/gen7_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #include "genX_pipeline_util.h"
  36
  37 static void
  38 gen7_emit_rs_state(struct anv_pipeline *pipeline,
  39                    const VkPipelineRasterizationStateCreateInfo *info,
  40                    const struct anv_graphics_pipeline_create_info *extra)
  41 {
  42    struct GENX(3DSTATE_SF) sf = {
  43       GENX(3DSTATE_SF_header),
  44
  45       /* LegacyGlobalDepthBiasEnable */
  46
  47       .StatisticsEnable                         = true,
  48       .FrontFaceFillMode                        = vk_to_gen_fillmode[info->polygonMode],
  49       .BackFaceFillMode                         = vk_to_gen_fillmode[info->polygonMode],
  50       .ViewTransformEnable                      = !(extra && extra->disable_viewport),
  51       .FrontWinding                             = vk_to_gen_front_face[info->frontFace],
  52       /* bool                                         AntiAliasingEnable; */
  53
  54       .CullMode                                 = vk_to_gen_cullmode[info->cullMode],
  55
  56       /* uint32_t                                     LineEndCapAntialiasingRegionWidth; */
  57       .ScissorRectangleEnable                   =  !(extra && extra->disable_scissor),
  58
  59       /* uint32_t                                     MultisampleRasterizationMode; */
  60       /* bool                                         LastPixelEnable; */
  61
  62       .TriangleStripListProvokingVertexSelect   = 0,
  63       .LineStripListProvokingVertexSelect       = 0,
  64       .TriangleFanProvokingVertexSelect         = 0,
  65
  66       /* uint32_t                                     AALineDistanceMode; */
  67       /* uint32_t                                     VertexSubPixelPrecisionSelect; */
  68       .UsePointWidthState                       = !pipeline->writes_point_size,
  69       .PointWidth                               = 1.0,
  70    };
  71
  72    GENX(3DSTATE_SF_pack)(NULL, &pipeline->gen7.sf, &sf);
  73 }
  74
  75 static void
  76 gen7_emit_ds_state(struct anv_pipeline *pipeline,
  77                    const VkPipelineDepthStencilStateCreateInfo *info)
  78 {
  79    if (info == NULL) {
  80       /* We're going to OR this together with the dynamic state.  We need
  81        * to make sure it's initialized to something useful.
  82        */
  83       memset(pipeline->gen7.depth_stencil_state, 0,
  84              sizeof(pipeline->gen7.depth_stencil_state));
  85       return;
  86    }
  87
  88    struct GENX(DEPTH_STENCIL_STATE) state = {
  89       .DepthTestEnable = info->depthTestEnable,
  90       .DepthBufferWriteEnable = info->depthWriteEnable,
  91       .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
  92       .DoubleSidedStencilEnable = true,
  93
  94       .StencilTestEnable = info->stencilTestEnable,
  95       .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
  96       .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
  97       .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
  98       .StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp],
  99
 100       .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp],
 101       .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp],
 102       .BackfaceStencilPassDepthFailOp = vk_to_gen_stencil_op[info->back.depthFailOp],
 103       .BackFaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
 104    };
 105
 106    GENX(DEPTH_STENCIL_STATE_pack)(NULL, &pipeline->gen7.depth_stencil_state, &state);
 107 }
 108
 109 static void
 110 gen7_emit_cb_state(struct anv_pipeline *pipeline,
 111                    const VkPipelineColorBlendStateCreateInfo *info,
 112                    const VkPipelineMultisampleStateCreateInfo *ms_info)
 113 {
 114    struct anv_device *device = pipeline->device;
 115
 116    if (info == NULL || info->attachmentCount == 0) {
 117       pipeline->blend_state =
 118          anv_state_pool_emit(&device->dynamic_state_pool,
 119             GENX(BLEND_STATE), 64,
 120             .ColorBufferBlendEnable = false,
 121             .WriteDisableAlpha = true,
 122             .WriteDisableRed = true,
 123             .WriteDisableGreen = true,
 124             .WriteDisableBlue = true);
 125    } else {
 126       const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[0];
 127       struct GENX(BLEND_STATE) blend = {
 128          .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
 129          .AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable,
 130
 131          .LogicOpEnable = info->logicOpEnable,
 132          .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
 133          .ColorBufferBlendEnable = a->blendEnable,
 134          .ColorClampRange = COLORCLAMP_RTFORMAT,
 135          .PreBlendColorClampEnable = true,
 136          .PostBlendColorClampEnable = true,
 137          .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
 138          .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
 139          .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
 140          .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
 141          .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
 142          .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
 143          .WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
 144          .WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
 145          .WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
 146          .WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
 147       };
 148
 149       /* Our hardware applies the blend factor prior to the blend function
 150        * regardless of what function is used.  Technically, this means the
 151        * hardware can do MORE than GL or Vulkan specify.  However, it also
 152        * means that, for MIN and MAX, we have to stomp the blend factor to
 153        * ONE to make it a no-op.
 154        */
 155       if (a->colorBlendOp == VK_BLEND_OP_MIN ||
 156           a->colorBlendOp == VK_BLEND_OP_MAX) {
 157          blend.SourceBlendFactor = BLENDFACTOR_ONE;
 158          blend.DestinationBlendFactor = BLENDFACTOR_ONE;
 159       }
 160       if (a->alphaBlendOp == VK_BLEND_OP_MIN ||
 161           a->alphaBlendOp == VK_BLEND_OP_MAX) {
 162          blend.SourceAlphaBlendFactor = BLENDFACTOR_ONE;
 163          blend.DestinationAlphaBlendFactor = BLENDFACTOR_ONE;
 164       }
 165
 166       pipeline->blend_state = anv_state_pool_alloc(&device->dynamic_state_pool,
 167                                                    GENX(BLEND_STATE_length) * 4,
 168                                                    64);
 169       GENX(BLEND_STATE_pack)(NULL, pipeline->blend_state.map, &blend);
 170       if (pipeline->device->info.has_llc)
 171          anv_state_clflush(pipeline->blend_state);
 172     }
 173
 174    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_BLEND_STATE_POINTERS),
 175                   .BlendStatePointer = pipeline->blend_state.offset);
 176 }
 177
 178 VkResult
 179 genX(graphics_pipeline_create)(
 180     VkDevice                                    _device,
 181     struct anv_pipeline_cache *                 cache,
 182     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
 183     const struct anv_graphics_pipeline_create_info *extra,
 184     const VkAllocationCallbacks*                pAllocator,
 185     VkPipeline*                                 pPipeline)
 186 {
 187    ANV_FROM_HANDLE(anv_device, device, _device);
 188    struct anv_pipeline *pipeline;
 189    VkResult result;
 190
 191    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
 192
 193    pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
 194                          VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 195    if (pipeline == NULL)
 196       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 197
 198    result = anv_pipeline_init(pipeline, device, cache,
 199                               pCreateInfo, extra, pAllocator);
 200    if (result != VK_SUCCESS) {
 201       anv_free2(&device->alloc, pAllocator, pipeline);
 202       return result;
 203    }
 204
 205    assert(pCreateInfo->pVertexInputState);
 206    emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
 207
 208    assert(pCreateInfo->pRasterizationState);
 209    gen7_emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
 210
 211    gen7_emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
 212
 213    gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
 214                                 pCreateInfo->pMultisampleState);
 215
 216    emit_urb_setup(pipeline);
 217
 218    const VkPipelineRasterizationStateCreateInfo *rs_info =
 219       pCreateInfo->pRasterizationState;
 220
 221    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_CLIP),
 222       .FrontWinding                             = vk_to_gen_front_face[rs_info->frontFace],
 223       .CullMode                                 = vk_to_gen_cullmode[rs_info->cullMode],
 224       .ClipEnable                               = true,
 225       .APIMode                                  = APIMODE_OGL,
 226       .ViewportXYClipTestEnable                 = !(extra && extra->disable_viewport),
 227       .ClipMode                                 = CLIPMODE_NORMAL,
 228       .TriangleStripListProvokingVertexSelect   = 0,
 229       .LineStripListProvokingVertexSelect       = 0,
 230       .TriangleFanProvokingVertexSelect         = 0,
 231       .MinimumPointWidth                        = 0.125,
 232       .MaximumPointWidth                        = 255.875,
 233       .MaximumVPIndex = pCreateInfo->pViewportState->viewportCount - 1);
 234
 235    if (pCreateInfo->pMultisampleState &&
 236        pCreateInfo->pMultisampleState->rasterizationSamples > 1)
 237       anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO");
 238
 239    uint32_t samples = 1;
 240    uint32_t log2_samples = __builtin_ffs(samples) - 1;
 241
 242    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_MULTISAMPLE),
 243       .PixelLocation                            = PIXLOC_CENTER,
 244       .NumberofMultisamples                     = log2_samples);
 245
 246    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SAMPLE_MASK),
 247       .SampleMask                               = 0xff);
 248
 249    const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
 250
 251 #if 0
 252    /* From gen7_vs_state.c */
 253
 254    /**
 255     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
 256     * Geometry > Geometry Shader > State:
 257     *
 258     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
 259     *     whole fixed function pipeline when the GS enable changes value in
 260     *     the 3DSTATE_GS."
 261     *
 262     * The hardware architects have clarified that in this context "flush the
 263     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
 264     * Stall" bit set.
 265     */
 266    if (!brw->is_haswell && !brw->is_baytrail)
 267       gen7_emit_vs_workaround_flush(brw);
 268 #endif
 269
 270    if (pipeline->vs_vec4 == NO_KERNEL || (extra && extra->disable_vs))
 271       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), .VSFunctionEnable = false);
 272    else
 273       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
 274          .KernelStartPointer                    = pipeline->vs_vec4,
 275          .ScratchSpaceBaseOffset                = pipeline->scratch_start[MESA_SHADER_VERTEX],
 276          .PerThreadScratchSpace                 = scratch_space(&vue_prog_data->base),
 277
 278          .DispatchGRFStartRegisterforURBData    =
 279             vue_prog_data->base.dispatch_grf_start_reg,
 280          .VertexURBEntryReadLength              = vue_prog_data->urb_read_length,
 281          .VertexURBEntryReadOffset              = 0,
 282
 283          .MaximumNumberofThreads                = device->info.max_vs_threads - 1,
 284          .StatisticsEnable                      = true,
 285          .VSFunctionEnable                      = true);
 286
 287    const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
 288
 289    if (pipeline->gs_kernel == NO_KERNEL || (extra && extra->disable_vs)) {
 290       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .GSEnable = false);
 291    } else {
 292       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS),
 293          .KernelStartPointer                    = pipeline->gs_kernel,
 294          .ScratchSpaceBasePointer               = pipeline->scratch_start[MESA_SHADER_GEOMETRY],
 295          .PerThreadScratchSpace                 = scratch_space(&gs_prog_data->base.base),
 296
 297          .OutputVertexSize                      = gs_prog_data->output_vertex_size_hwords * 2 - 1,
 298          .OutputTopology                        = gs_prog_data->output_topology,
 299          .VertexURBEntryReadLength              = gs_prog_data->base.urb_read_length,
 300          .IncludeVertexHandles                  = gs_prog_data->base.include_vue_handles,
 301          .DispatchGRFStartRegisterforURBData    =
 302             gs_prog_data->base.base.dispatch_grf_start_reg,
 303
 304          .MaximumNumberofThreads                = device->info.max_gs_threads - 1,
 305          /* This in the next dword on HSW. */
 306          .ControlDataFormat                     = gs_prog_data->control_data_format,
 307          .ControlDataHeaderSize                 = gs_prog_data->control_data_header_size_hwords,
 308          .InstanceControl                       = MAX2(gs_prog_data->invocations, 1) - 1,
 309          .DispatchMode                          = gs_prog_data->base.dispatch_mode,
 310          .GSStatisticsEnable                    = true,
 311          .IncludePrimitiveID                    = gs_prog_data->include_primitive_id,
 312 #     if (GEN_IS_HASWELL)
 313          .ReorderMode                           = REORDER_TRAILING,
 314 #     else
 315          .ReorderEnable                         = true,
 316 #     endif
 317          .GSEnable                              = true);
 318    }
 319
 320    if (pipeline->ps_ksp0 == NO_KERNEL) {
 321       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE));
 322
 323       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM),
 324                      .StatisticsEnable                         = true,
 325                      .ThreadDispatchEnable                     = false,
 326                      .LineEndCapAntialiasingRegionWidth        = 0, /* 0.5 pixels */
 327                      .LineAntialiasingRegionWidth              = 1, /* 1.0 pixels */
 328                      .EarlyDepthStencilControl                 = EDSC_NORMAL,
 329                      .PointRasterizationRule                   = RASTRULE_UPPER_RIGHT);
 330
 331       /* Even if no fragments are ever dispatched, the hardware hangs if we
 332        * don't at least set the maximum number of threads.
 333        */
 334       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
 335                      .MaximumNumberofThreads                   = device->info.max_wm_threads - 1);
 336    } else {
 337       const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
 338       if (wm_prog_data->urb_setup[VARYING_SLOT_BFC0] != -1 ||
 339           wm_prog_data->urb_setup[VARYING_SLOT_BFC1] != -1)
 340          anv_finishme("two-sided color needs sbe swizzling setup");
 341       if (wm_prog_data->urb_setup[VARYING_SLOT_PRIMITIVE_ID] != -1)
 342          anv_finishme("primitive_id needs sbe swizzling setup");
 343
 344       emit_3dstate_sbe(pipeline);
 345
 346       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
 347                      .KernelStartPointer0                      = pipeline->ps_ksp0,
 348                      .ScratchSpaceBasePointer                  = pipeline->scratch_start[MESA_SHADER_FRAGMENT],
 349                      .PerThreadScratchSpace                    = scratch_space(&wm_prog_data->base),
 350
 351                      .MaximumNumberofThreads                   = device->info.max_wm_threads - 1,
 352                      .PushConstantEnable                       = wm_prog_data->base.nr_params > 0,
 353                      .AttributeEnable                          = wm_prog_data->num_varying_inputs > 0,
 354                      .oMaskPresenttoRenderTarget               = wm_prog_data->uses_omask,
 355
 356                      .RenderTargetFastClearEnable              = false,
 357                      .DualSourceBlendEnable                    = false,
 358                      .RenderTargetResolveEnable                = false,
 359
 360                      .PositionXYOffsetSelect                   = wm_prog_data->uses_pos_offset ?
 361                      POSOFFSET_SAMPLE : POSOFFSET_NONE,
 362
 363                      ._32PixelDispatchEnable                   = false,
 364                      ._16PixelDispatchEnable                   = pipeline->ps_simd16 != NO_KERNEL,
 365                      ._8PixelDispatchEnable                    = pipeline->ps_simd8 != NO_KERNEL,
 366
 367                      .DispatchGRFStartRegisterforConstantSetupData0 = pipeline->ps_grf_start0,
 368                      .DispatchGRFStartRegisterforConstantSetupData1 = 0,
 369                      .DispatchGRFStartRegisterforConstantSetupData2 = pipeline->ps_grf_start2,
 370
 371 #if 0
 372                      /* Haswell requires the sample mask to be set in this packet as well as
 373                       * in 3DSTATE_SAMPLE_MASK; the values should match. */
 374                      /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 375 #endif
 376
 377                      .KernelStartPointer1                      = 0,
 378                      .KernelStartPointer2                      = pipeline->ps_ksp2);
 379
 380       /* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
 381       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM),
 382                      .StatisticsEnable                         = true,
 383                      .ThreadDispatchEnable                     = true,
 384                      .LineEndCapAntialiasingRegionWidth        = 0, /* 0.5 pixels */
 385                      .LineAntialiasingRegionWidth              = 1, /* 1.0 pixels */
 386                      .EarlyDepthStencilControl                 = EDSC_NORMAL,
 387                      .PointRasterizationRule                   = RASTRULE_UPPER_RIGHT,
 388                      .PixelShaderComputedDepthMode             = wm_prog_data->computed_depth_mode,
 389                      .PixelShaderUsesSourceDepth               = wm_prog_data->uses_src_depth,
 390                      .PixelShaderUsesSourceW                   = wm_prog_data->uses_src_w,
 391                      .PixelShaderUsesInputCoverageMask         = wm_prog_data->uses_sample_mask,
 392                      .BarycentricInterpolationMode             = wm_prog_data->barycentric_interp_modes);
 393    }
 394
 395    *pPipeline = anv_pipeline_to_handle(pipeline);
 396
 397    return VK_SUCCESS;
 398 }