src/intel/vulkan/gen7_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #include "genX_pipeline_util.h"
  36
  37 static void
  38 gen7_emit_rs_state(struct anv_pipeline *pipeline,
  39                    const VkPipelineRasterizationStateCreateInfo *info,
  40                    const struct anv_graphics_pipeline_create_info *extra)
  41 {
  42    struct GENX(3DSTATE_SF) sf = {
  43       GENX(3DSTATE_SF_header),
  44
  45       /* LegacyGlobalDepthBiasEnable */
  46
  47       .StatisticsEnable                         = true,
  48       .FrontFaceFillMode                        = vk_to_gen_fillmode[info->polygonMode],
  49       .BackFaceFillMode                         = vk_to_gen_fillmode[info->polygonMode],
  50       .ViewTransformEnable                      = !(extra && extra->use_rectlist),
  51       .FrontWinding                             = vk_to_gen_front_face[info->frontFace],
  52       /* bool                                         AntiAliasingEnable; */
  53
  54       .CullMode                                 = vk_to_gen_cullmode[info->cullMode],
  55
  56       /* uint32_t                                     LineEndCapAntialiasingRegionWidth; */
  57       .ScissorRectangleEnable                   =  !(extra && extra->use_rectlist),
  58
  59       /* uint32_t                                     MultisampleRasterizationMode; */
  60       /* bool                                         LastPixelEnable; */
  61
  62       .TriangleStripListProvokingVertexSelect   = 0,
  63       .LineStripListProvokingVertexSelect       = 0,
  64       .TriangleFanProvokingVertexSelect         = 1,
  65
  66       /* uint32_t                                     AALineDistanceMode; */
  67       /* uint32_t                                     VertexSubPixelPrecisionSelect; */
  68       .UsePointWidthState                       = false,
  69       .PointWidth                               = 1.0,
  70       .GlobalDepthOffsetEnableSolid             = info->depthBiasEnable,
  71       .GlobalDepthOffsetEnableWireframe         = info->depthBiasEnable,
  72       .GlobalDepthOffsetEnablePoint             = info->depthBiasEnable,
  73    };
  74
  75    GENX(3DSTATE_SF_pack)(NULL, &pipeline->gen7.sf, &sf);
  76 }
  77
  78 static void
  79 gen7_emit_cb_state(struct anv_pipeline *pipeline,
  80                    const VkPipelineColorBlendStateCreateInfo *info,
  81                    const VkPipelineMultisampleStateCreateInfo *ms_info)
  82 {
  83    struct anv_device *device = pipeline->device;
  84
  85    if (info == NULL || info->attachmentCount == 0) {
  86       pipeline->blend_state =
  87          anv_state_pool_emit(&device->dynamic_state_pool,
  88             GENX(BLEND_STATE), 64,
  89             .ColorBufferBlendEnable = false,
  90             .WriteDisableAlpha = true,
  91             .WriteDisableRed = true,
  92             .WriteDisableGreen = true,
  93             .WriteDisableBlue = true);
  94    } else {
  95       const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[0];
  96       struct GENX(BLEND_STATE) blend = {
  97          .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
  98          .AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable,
  99
 100          .LogicOpEnable = info->logicOpEnable,
 101          .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
 102          .ColorBufferBlendEnable = a->blendEnable,
 103          .ColorClampRange = COLORCLAMP_RTFORMAT,
 104          .PreBlendColorClampEnable = true,
 105          .PostBlendColorClampEnable = true,
 106          .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
 107          .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
 108          .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
 109          .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
 110          .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
 111          .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
 112          .WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
 113          .WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
 114          .WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
 115          .WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
 116       };
 117
 118       /* Our hardware applies the blend factor prior to the blend function
 119        * regardless of what function is used.  Technically, this means the
 120        * hardware can do MORE than GL or Vulkan specify.  However, it also
 121        * means that, for MIN and MAX, we have to stomp the blend factor to
 122        * ONE to make it a no-op.
 123        */
 124       if (a->colorBlendOp == VK_BLEND_OP_MIN ||
 125           a->colorBlendOp == VK_BLEND_OP_MAX) {
 126          blend.SourceBlendFactor = BLENDFACTOR_ONE;
 127          blend.DestinationBlendFactor = BLENDFACTOR_ONE;
 128       }
 129       if (a->alphaBlendOp == VK_BLEND_OP_MIN ||
 130           a->alphaBlendOp == VK_BLEND_OP_MAX) {
 131          blend.SourceAlphaBlendFactor = BLENDFACTOR_ONE;
 132          blend.DestinationAlphaBlendFactor = BLENDFACTOR_ONE;
 133       }
 134
 135       pipeline->blend_state = anv_state_pool_alloc(&device->dynamic_state_pool,
 136                                                    GENX(BLEND_STATE_length) * 4,
 137                                                    64);
 138       GENX(BLEND_STATE_pack)(NULL, pipeline->blend_state.map, &blend);
 139       if (pipeline->device->info.has_llc)
 140          anv_state_clflush(pipeline->blend_state);
 141     }
 142
 143    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_BLEND_STATE_POINTERS), bsp) {
 144       bsp.BlendStatePointer = pipeline->blend_state.offset;
 145    }
 146 }
 147
 148 VkResult
 149 genX(graphics_pipeline_create)(
 150     VkDevice                                    _device,
 151     struct anv_pipeline_cache *                 cache,
 152     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
 153     const struct anv_graphics_pipeline_create_info *extra,
 154     const VkAllocationCallbacks*                pAllocator,
 155     VkPipeline*                                 pPipeline)
 156 {
 157    ANV_FROM_HANDLE(anv_device, device, _device);
 158    struct anv_pipeline *pipeline;
 159    VkResult result;
 160
 161    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
 162
 163    pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
 164                          VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 165    if (pipeline == NULL)
 166       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 167
 168    result = anv_pipeline_init(pipeline, device, cache,
 169                               pCreateInfo, extra, pAllocator);
 170    if (result != VK_SUCCESS) {
 171       anv_free2(&device->alloc, pAllocator, pipeline);
 172       return result;
 173    }
 174
 175    assert(pCreateInfo->pVertexInputState);
 176    emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
 177
 178    assert(pCreateInfo->pRasterizationState);
 179    gen7_emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
 180
 181    emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
 182
 183    gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
 184                                 pCreateInfo->pMultisampleState);
 185
 186    emit_urb_setup(pipeline);
 187
 188    const VkPipelineRasterizationStateCreateInfo *rs_info =
 189       pCreateInfo->pRasterizationState;
 190
 191    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_CLIP), clip) {
 192       clip.FrontWinding             = vk_to_gen_front_face[rs_info->frontFace],
 193       clip.CullMode                 = vk_to_gen_cullmode[rs_info->cullMode],
 194       clip.ClipEnable               = !(extra && extra->use_rectlist),
 195       clip.APIMode                  = APIMODE_OGL,
 196       clip.ViewportXYClipTestEnable = true,
 197       clip.ClipMode                 = CLIPMODE_NORMAL,
 198
 199       clip.TriangleStripListProvokingVertexSelect   = 0,
 200       clip.LineStripListProvokingVertexSelect       = 0,
 201       clip.TriangleFanProvokingVertexSelect         = 1,
 202
 203       clip.MinimumPointWidth        = 0.125,
 204       clip.MaximumPointWidth        = 255.875,
 205       clip.MaximumVPIndex = pCreateInfo->pViewportState->viewportCount - 1;
 206    }
 207
 208    if (pCreateInfo->pMultisampleState &&
 209        pCreateInfo->pMultisampleState->rasterizationSamples > 1)
 210       anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO");
 211
 212    uint32_t samples = 1;
 213    uint32_t log2_samples = __builtin_ffs(samples) - 1;
 214
 215    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_MULTISAMPLE), ms) {
 216       ms.PixelLocation        = PIXLOC_CENTER;
 217       ms.NumberofMultisamples = log2_samples;
 218    }
 219
 220    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SAMPLE_MASK), sm) {
 221       sm.SampleMask = 0xff;
 222    }
 223
 224    const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
 225
 226 #if 0
 227    /* From gen7_vs_state.c */
 228
 229    /**
 230     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
 231     * Geometry > Geometry Shader > State:
 232     *
 233     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
 234     *     whole fixed function pipeline when the GS enable changes value in
 235     *     the 3DSTATE_GS."
 236     *
 237     * The hardware architects have clarified that in this context "flush the
 238     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
 239     * Stall" bit set.
 240     */
 241    if (!brw->is_haswell && !brw->is_baytrail)
 242       gen7_emit_vs_workaround_flush(brw);
 243 #endif
 244
 245    if (pipeline->vs_vec4 == NO_KERNEL || (extra && extra->disable_vs))
 246       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs);
 247    else
 248       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
 249          vs.KernelStartPointer         = pipeline->vs_vec4;
 250          vs.ScratchSpaceBaseOffset     = pipeline->scratch_start[MESA_SHADER_VERTEX];
 251          vs.PerThreadScratchSpace      = scratch_space(&vs_prog_data->base.base);
 252
 253          vs.DispatchGRFStartRegisterforURBData    =
 254             vs_prog_data->base.base.dispatch_grf_start_reg;
 255
 256          vs.VertexURBEntryReadLength   = vs_prog_data->base.urb_read_length;
 257          vs.VertexURBEntryReadOffset   = 0;
 258          vs.MaximumNumberofThreads     = device->info.max_vs_threads - 1;
 259          vs.StatisticsEnable           = true;
 260          vs.VSFunctionEnable           = true;
 261       }
 262
 263    const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
 264
 265    if (pipeline->gs_kernel == NO_KERNEL || (extra && extra->disable_vs)) {
 266       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs);
 267    } else {
 268       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs) {
 269          gs.KernelStartPointer         = pipeline->gs_kernel;
 270          gs.ScratchSpaceBasePointer    = pipeline->scratch_start[MESA_SHADER_GEOMETRY];
 271          gs.PerThreadScratchSpace      = scratch_space(&gs_prog_data->base.base);
 272
 273          gs.OutputVertexSize           = gs_prog_data->output_vertex_size_hwords * 2 - 1;
 274          gs.OutputTopology             = gs_prog_data->output_topology;
 275          gs.VertexURBEntryReadLength   = gs_prog_data->base.urb_read_length;
 276          gs.IncludeVertexHandles       = gs_prog_data->base.include_vue_handles;
 277
 278          gs.DispatchGRFStartRegisterforURBData =
 279             gs_prog_data->base.base.dispatch_grf_start_reg;
 280
 281          gs.MaximumNumberofThreads     = device->info.max_gs_threads - 1;
 282          /* This in the next dword on HSW. */
 283          gs.ControlDataFormat          = gs_prog_data->control_data_format;
 284          gs.ControlDataHeaderSize      = gs_prog_data->control_data_header_size_hwords;
 285          gs.InstanceControl            = MAX2(gs_prog_data->invocations, 1) - 1;
 286          gs.DispatchMode               = gs_prog_data->base.dispatch_mode;
 287          gs.GSStatisticsEnable         = true;
 288          gs.IncludePrimitiveID         = gs_prog_data->include_primitive_id;
 289 #     if (GEN_IS_HASWELL)
 290          gs.ReorderMode                = REORDER_TRAILING;
 291 #     else
 292          gs.ReorderEnable              = true;
 293 #     endif
 294          gs.GSEnable                   = true;
 295       }
 296    }
 297
 298    if (pipeline->ps_ksp0 == NO_KERNEL) {
 299       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE), sbe);
 300
 301       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM), wm) {
 302          wm.StatisticsEnable                    = true;
 303          wm.ThreadDispatchEnable                = false;
 304          wm.LineEndCapAntialiasingRegionWidth   = 0; /* 0.5 pixels */
 305          wm.LineAntialiasingRegionWidth         = 1; /* 1.0 pixels */
 306          wm.EarlyDepthStencilControl            = EDSC_NORMAL;
 307          wm.PointRasterizationRule              = RASTRULE_UPPER_RIGHT;
 308       }
 309
 310       /* Even if no fragments are ever dispatched, the hardware hangs if we
 311        * don't at least set the maximum number of threads.
 312        */
 313       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) {
 314          ps.MaximumNumberofThreads = device->info.max_wm_threads - 1;
 315       }
 316    } else {
 317       const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
 318       if (wm_prog_data->urb_setup[VARYING_SLOT_BFC0] != -1 ||
 319           wm_prog_data->urb_setup[VARYING_SLOT_BFC1] != -1)
 320          anv_finishme("two-sided color needs sbe swizzling setup");
 321       if (wm_prog_data->urb_setup[VARYING_SLOT_PRIMITIVE_ID] != -1)
 322          anv_finishme("primitive_id needs sbe swizzling setup");
 323
 324       emit_3dstate_sbe(pipeline);
 325
 326       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) {
 327          ps.KernelStartPointer0           = pipeline->ps_ksp0;
 328          ps.ScratchSpaceBasePointer       = pipeline->scratch_start[MESA_SHADER_FRAGMENT];
 329          ps.PerThreadScratchSpace         = scratch_space(&wm_prog_data->base);
 330          ps.MaximumNumberofThreads        = device->info.max_wm_threads - 1;
 331          ps.PushConstantEnable            = wm_prog_data->base.nr_params > 0;
 332          ps.AttributeEnable               = wm_prog_data->num_varying_inputs > 0;
 333          ps.oMaskPresenttoRenderTarget    = wm_prog_data->uses_omask;
 334
 335          ps.RenderTargetFastClearEnable   = false;
 336          ps.DualSourceBlendEnable         = false;
 337          ps.RenderTargetResolveEnable     = false;
 338
 339          ps.PositionXYOffsetSelect        = wm_prog_data->uses_pos_offset ?
 340                                             POSOFFSET_SAMPLE : POSOFFSET_NONE;
 341
 342          ps._32PixelDispatchEnable        = false;
 343          ps._16PixelDispatchEnable        = wm_prog_data->dispatch_16;
 344          ps._8PixelDispatchEnable         = wm_prog_data->dispatch_8;
 345
 346          ps.DispatchGRFStartRegisterforConstantSetupData0 =
 347             wm_prog_data->base.dispatch_grf_start_reg,
 348          ps.DispatchGRFStartRegisterforConstantSetupData1 = 0,
 349          ps.DispatchGRFStartRegisterforConstantSetupData2 =
 350             wm_prog_data->dispatch_grf_start_reg_2,
 351
 352          /* Haswell requires the sample mask to be set in this packet as well as
 353           * in 3DSTATE_SAMPLE_MASK; the values should match. */
 354          /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 355
 356          ps.KernelStartPointer1           = 0;
 357          ps.KernelStartPointer2           = pipeline->ps_ksp0 + wm_prog_data->prog_offset_2;
 358       }
 359
 360       /* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
 361       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM), wm) {
 362          wm.StatisticsEnable                    = true;
 363          wm.ThreadDispatchEnable                = true;
 364          wm.LineEndCapAntialiasingRegionWidth   = 0; /* 0.5 pixels */
 365          wm.LineAntialiasingRegionWidth         = 1; /* 1.0 pixels */
 366          wm.EarlyDepthStencilControl            = EDSC_NORMAL;
 367          wm.PointRasterizationRule              = RASTRULE_UPPER_RIGHT;
 368          wm.PixelShaderComputedDepthMode        = wm_prog_data->computed_depth_mode;
 369          wm.PixelShaderUsesSourceDepth          = wm_prog_data->uses_src_depth;
 370          wm.PixelShaderUsesSourceW              = wm_prog_data->uses_src_w;
 371          wm.PixelShaderUsesInputCoverageMask    = wm_prog_data->uses_sample_mask;
 372          wm.BarycentricInterpolationMode        = wm_prog_data->barycentric_interp_modes;
 373       }
 374    }
 375
 376    *pPipeline = anv_pipeline_to_handle(pipeline);
 377
 378    return VK_SUCCESS;
 379 }