2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
35 #include "genX_pipeline_util.h"
38 gen7_emit_rs_state(struct anv_pipeline
*pipeline
,
39 const VkPipelineRasterizationStateCreateInfo
*info
,
40 const struct anv_graphics_pipeline_create_info
*extra
)
42 struct GENX(3DSTATE_SF
) sf
= {
43 GENX(3DSTATE_SF_header
),
45 /* LegacyGlobalDepthBiasEnable */
47 .StatisticsEnable
= true,
48 .FrontFaceFillMode
= vk_to_gen_fillmode
[info
->polygonMode
],
49 .BackFaceFillMode
= vk_to_gen_fillmode
[info
->polygonMode
],
50 .ViewTransformEnable
= !(extra
&& extra
->use_rectlist
),
51 .FrontWinding
= vk_to_gen_front_face
[info
->frontFace
],
52 /* bool AntiAliasingEnable; */
54 .CullMode
= vk_to_gen_cullmode
[info
->cullMode
],
56 /* uint32_t LineEndCapAntialiasingRegionWidth; */
57 .ScissorRectangleEnable
= !(extra
&& extra
->use_rectlist
),
59 /* uint32_t MultisampleRasterizationMode; */
60 /* bool LastPixelEnable; */
62 .TriangleStripListProvokingVertexSelect
= 0,
63 .LineStripListProvokingVertexSelect
= 0,
64 .TriangleFanProvokingVertexSelect
= 1,
66 /* uint32_t AALineDistanceMode; */
67 /* uint32_t VertexSubPixelPrecisionSelect; */
68 .UsePointWidthState
= false,
70 .GlobalDepthOffsetEnableSolid
= info
->depthBiasEnable
,
71 .GlobalDepthOffsetEnableWireframe
= info
->depthBiasEnable
,
72 .GlobalDepthOffsetEnablePoint
= info
->depthBiasEnable
,
75 GENX(3DSTATE_SF_pack
)(NULL
, &pipeline
->gen7
.sf
, &sf
);
79 gen7_emit_ds_state(struct anv_pipeline
*pipeline
,
80 const VkPipelineDepthStencilStateCreateInfo
*info
)
83 /* We're going to OR this together with the dynamic state. We need
84 * to make sure it's initialized to something useful.
86 memset(pipeline
->gen7
.depth_stencil_state
, 0,
87 sizeof(pipeline
->gen7
.depth_stencil_state
));
91 struct GENX(DEPTH_STENCIL_STATE
) state
= {
92 .DepthTestEnable
= info
->depthTestEnable
,
93 .DepthBufferWriteEnable
= info
->depthWriteEnable
,
94 .DepthTestFunction
= vk_to_gen_compare_op
[info
->depthCompareOp
],
95 .DoubleSidedStencilEnable
= true,
97 .StencilTestEnable
= info
->stencilTestEnable
,
98 .StencilBufferWriteEnable
= info
->stencilTestEnable
,
99 .StencilFailOp
= vk_to_gen_stencil_op
[info
->front
.failOp
],
100 .StencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->front
.passOp
],
101 .StencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
->front
.depthFailOp
],
102 .StencilTestFunction
= vk_to_gen_compare_op
[info
->front
.compareOp
],
104 .BackfaceStencilFailOp
= vk_to_gen_stencil_op
[info
->back
.failOp
],
105 .BackfaceStencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->back
.passOp
],
106 .BackfaceStencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
->back
.depthFailOp
],
107 .BackFaceStencilTestFunction
= vk_to_gen_compare_op
[info
->back
.compareOp
],
110 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, &pipeline
->gen7
.depth_stencil_state
, &state
);
114 gen7_emit_cb_state(struct anv_pipeline
*pipeline
,
115 const VkPipelineColorBlendStateCreateInfo
*info
,
116 const VkPipelineMultisampleStateCreateInfo
*ms_info
)
118 struct anv_device
*device
= pipeline
->device
;
120 if (info
== NULL
|| info
->attachmentCount
== 0) {
121 pipeline
->blend_state
=
122 anv_state_pool_emit(&device
->dynamic_state_pool
,
123 GENX(BLEND_STATE
), 64,
124 .ColorBufferBlendEnable
= false,
125 .WriteDisableAlpha
= true,
126 .WriteDisableRed
= true,
127 .WriteDisableGreen
= true,
128 .WriteDisableBlue
= true);
130 const VkPipelineColorBlendAttachmentState
*a
= &info
->pAttachments
[0];
131 struct GENX(BLEND_STATE
) blend
= {
132 .AlphaToCoverageEnable
= ms_info
&& ms_info
->alphaToCoverageEnable
,
133 .AlphaToOneEnable
= ms_info
&& ms_info
->alphaToOneEnable
,
135 .LogicOpEnable
= info
->logicOpEnable
,
136 .LogicOpFunction
= vk_to_gen_logic_op
[info
->logicOp
],
137 .ColorBufferBlendEnable
= a
->blendEnable
,
138 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
139 .PreBlendColorClampEnable
= true,
140 .PostBlendColorClampEnable
= true,
141 .SourceBlendFactor
= vk_to_gen_blend
[a
->srcColorBlendFactor
],
142 .DestinationBlendFactor
= vk_to_gen_blend
[a
->dstColorBlendFactor
],
143 .ColorBlendFunction
= vk_to_gen_blend_op
[a
->colorBlendOp
],
144 .SourceAlphaBlendFactor
= vk_to_gen_blend
[a
->srcAlphaBlendFactor
],
145 .DestinationAlphaBlendFactor
= vk_to_gen_blend
[a
->dstAlphaBlendFactor
],
146 .AlphaBlendFunction
= vk_to_gen_blend_op
[a
->alphaBlendOp
],
147 .WriteDisableAlpha
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_A_BIT
),
148 .WriteDisableRed
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_R_BIT
),
149 .WriteDisableGreen
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_G_BIT
),
150 .WriteDisableBlue
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_B_BIT
),
153 /* Our hardware applies the blend factor prior to the blend function
154 * regardless of what function is used. Technically, this means the
155 * hardware can do MORE than GL or Vulkan specify. However, it also
156 * means that, for MIN and MAX, we have to stomp the blend factor to
157 * ONE to make it a no-op.
159 if (a
->colorBlendOp
== VK_BLEND_OP_MIN
||
160 a
->colorBlendOp
== VK_BLEND_OP_MAX
) {
161 blend
.SourceBlendFactor
= BLENDFACTOR_ONE
;
162 blend
.DestinationBlendFactor
= BLENDFACTOR_ONE
;
164 if (a
->alphaBlendOp
== VK_BLEND_OP_MIN
||
165 a
->alphaBlendOp
== VK_BLEND_OP_MAX
) {
166 blend
.SourceAlphaBlendFactor
= BLENDFACTOR_ONE
;
167 blend
.DestinationAlphaBlendFactor
= BLENDFACTOR_ONE
;
170 pipeline
->blend_state
= anv_state_pool_alloc(&device
->dynamic_state_pool
,
171 GENX(BLEND_STATE_length
) * 4,
173 GENX(BLEND_STATE_pack
)(NULL
, pipeline
->blend_state
.map
, &blend
);
174 if (pipeline
->device
->info
.has_llc
)
175 anv_state_clflush(pipeline
->blend_state
);
178 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), bsp
) {
179 bsp
.BlendStatePointer
= pipeline
->blend_state
.offset
;
184 genX(graphics_pipeline_create
)(
186 struct anv_pipeline_cache
* cache
,
187 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
188 const struct anv_graphics_pipeline_create_info
*extra
,
189 const VkAllocationCallbacks
* pAllocator
,
190 VkPipeline
* pPipeline
)
192 ANV_FROM_HANDLE(anv_device
, device
, _device
);
193 struct anv_pipeline
*pipeline
;
196 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
198 pipeline
= anv_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
199 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
200 if (pipeline
== NULL
)
201 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
203 result
= anv_pipeline_init(pipeline
, device
, cache
,
204 pCreateInfo
, extra
, pAllocator
);
205 if (result
!= VK_SUCCESS
) {
206 anv_free2(&device
->alloc
, pAllocator
, pipeline
);
210 assert(pCreateInfo
->pVertexInputState
);
211 emit_vertex_input(pipeline
, pCreateInfo
->pVertexInputState
, extra
);
213 assert(pCreateInfo
->pRasterizationState
);
214 gen7_emit_rs_state(pipeline
, pCreateInfo
->pRasterizationState
, extra
);
216 gen7_emit_ds_state(pipeline
, pCreateInfo
->pDepthStencilState
);
218 gen7_emit_cb_state(pipeline
, pCreateInfo
->pColorBlendState
,
219 pCreateInfo
->pMultisampleState
);
221 emit_urb_setup(pipeline
);
223 const VkPipelineRasterizationStateCreateInfo
*rs_info
=
224 pCreateInfo
->pRasterizationState
;
226 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_CLIP
), clip
) {
227 clip
.FrontWinding
= vk_to_gen_front_face
[rs_info
->frontFace
],
228 clip
.CullMode
= vk_to_gen_cullmode
[rs_info
->cullMode
],
229 clip
.ClipEnable
= !(extra
&& extra
->use_rectlist
),
230 clip
.APIMode
= APIMODE_OGL
,
231 clip
.ViewportXYClipTestEnable
= true,
232 clip
.ClipMode
= CLIPMODE_NORMAL
,
234 clip
.TriangleStripListProvokingVertexSelect
= 0,
235 clip
.LineStripListProvokingVertexSelect
= 0,
236 clip
.TriangleFanProvokingVertexSelect
= 1,
238 clip
.MinimumPointWidth
= 0.125,
239 clip
.MaximumPointWidth
= 255.875,
240 clip
.MaximumVPIndex
= pCreateInfo
->pViewportState
->viewportCount
- 1;
243 if (pCreateInfo
->pMultisampleState
&&
244 pCreateInfo
->pMultisampleState
->rasterizationSamples
> 1)
245 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO");
247 uint32_t samples
= 1;
248 uint32_t log2_samples
= __builtin_ffs(samples
) - 1;
250 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
251 ms
.PixelLocation
= PIXLOC_CENTER
;
252 ms
.NumberofMultisamples
= log2_samples
;
255 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
256 sm
.SampleMask
= 0xff;
259 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
262 /* From gen7_vs_state.c */
265 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
266 * Geometry > Geometry Shader > State:
268 * "Note: Because of corruption in IVB:GT2, software needs to flush the
269 * whole fixed function pipeline when the GS enable changes value in
272 * The hardware architects have clarified that in this context "flush the
273 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
276 if (!brw
->is_haswell
&& !brw
->is_baytrail
)
277 gen7_emit_vs_workaround_flush(brw
);
280 if (pipeline
->vs_vec4
== NO_KERNEL
|| (extra
&& extra
->disable_vs
))
281 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VS
), vs
);
283 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VS
), vs
) {
284 vs
.KernelStartPointer
= pipeline
->vs_vec4
;
285 vs
.ScratchSpaceBaseOffset
= pipeline
->scratch_start
[MESA_SHADER_VERTEX
];
286 vs
.PerThreadScratchSpace
= scratch_space(&vs_prog_data
->base
.base
);
288 vs
.DispatchGRFStartRegisterforURBData
=
289 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
291 vs
.VertexURBEntryReadLength
= vs_prog_data
->base
.urb_read_length
;
292 vs
.VertexURBEntryReadOffset
= 0;
293 vs
.MaximumNumberofThreads
= device
->info
.max_vs_threads
- 1;
294 vs
.StatisticsEnable
= true;
295 vs
.VSFunctionEnable
= true;
298 const struct brw_gs_prog_data
*gs_prog_data
= get_gs_prog_data(pipeline
);
300 if (pipeline
->gs_kernel
== NO_KERNEL
|| (extra
&& extra
->disable_vs
)) {
301 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_GS
), gs
);
303 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_GS
), gs
) {
304 gs
.KernelStartPointer
= pipeline
->gs_kernel
;
305 gs
.ScratchSpaceBasePointer
= pipeline
->scratch_start
[MESA_SHADER_GEOMETRY
];
306 gs
.PerThreadScratchSpace
= scratch_space(&gs_prog_data
->base
.base
);
308 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
309 gs
.OutputTopology
= gs_prog_data
->output_topology
;
310 gs
.VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
;
311 gs
.IncludeVertexHandles
= gs_prog_data
->base
.include_vue_handles
;
313 gs
.DispatchGRFStartRegisterforURBData
=
314 gs_prog_data
->base
.base
.dispatch_grf_start_reg
;
316 gs
.MaximumNumberofThreads
= device
->info
.max_gs_threads
- 1;
317 /* This in the next dword on HSW. */
318 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
319 gs
.ControlDataHeaderSize
= gs_prog_data
->control_data_header_size_hwords
;
320 gs
.InstanceControl
= MAX2(gs_prog_data
->invocations
, 1) - 1;
321 gs
.DispatchMode
= gs_prog_data
->base
.dispatch_mode
;
322 gs
.GSStatisticsEnable
= true;
323 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
324 # if (GEN_IS_HASWELL)
325 gs
.ReorderMode
= REORDER_TRAILING
;
327 gs
.ReorderEnable
= true;
333 if (pipeline
->ps_ksp0
== NO_KERNEL
) {
334 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_SBE
), sbe
);
336 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_WM
), wm
) {
337 wm
.StatisticsEnable
= true;
338 wm
.ThreadDispatchEnable
= false;
339 wm
.LineEndCapAntialiasingRegionWidth
= 0; /* 0.5 pixels */
340 wm
.LineAntialiasingRegionWidth
= 1; /* 1.0 pixels */
341 wm
.EarlyDepthStencilControl
= EDSC_NORMAL
;
342 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
345 /* Even if no fragments are ever dispatched, the hardware hangs if we
346 * don't at least set the maximum number of threads.
348 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS
), ps
) {
349 ps
.MaximumNumberofThreads
= device
->info
.max_wm_threads
- 1;
352 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
353 if (wm_prog_data
->urb_setup
[VARYING_SLOT_BFC0
] != -1 ||
354 wm_prog_data
->urb_setup
[VARYING_SLOT_BFC1
] != -1)
355 anv_finishme("two-sided color needs sbe swizzling setup");
356 if (wm_prog_data
->urb_setup
[VARYING_SLOT_PRIMITIVE_ID
] != -1)
357 anv_finishme("primitive_id needs sbe swizzling setup");
359 emit_3dstate_sbe(pipeline
);
361 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS
), ps
) {
362 ps
.KernelStartPointer0
= pipeline
->ps_ksp0
;
363 ps
.ScratchSpaceBasePointer
= pipeline
->scratch_start
[MESA_SHADER_FRAGMENT
];
364 ps
.PerThreadScratchSpace
= scratch_space(&wm_prog_data
->base
);
365 ps
.MaximumNumberofThreads
= device
->info
.max_wm_threads
- 1;
366 ps
.PushConstantEnable
= wm_prog_data
->base
.nr_params
> 0;
367 ps
.AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0;
368 ps
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
370 ps
.RenderTargetFastClearEnable
= false;
371 ps
.DualSourceBlendEnable
= false;
372 ps
.RenderTargetResolveEnable
= false;
374 ps
.PositionXYOffsetSelect
= wm_prog_data
->uses_pos_offset
?
375 POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
377 ps
._32PixelDispatchEnable
= false;
378 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
379 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
381 ps
.DispatchGRFStartRegisterforConstantSetupData0
=
382 wm_prog_data
->base
.dispatch_grf_start_reg
,
383 ps
.DispatchGRFStartRegisterforConstantSetupData1
= 0,
384 ps
.DispatchGRFStartRegisterforConstantSetupData2
=
385 wm_prog_data
->dispatch_grf_start_reg_2
,
387 /* Haswell requires the sample mask to be set in this packet as well as
388 * in 3DSTATE_SAMPLE_MASK; the values should match. */
389 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
391 ps
.KernelStartPointer1
= 0;
392 ps
.KernelStartPointer2
= pipeline
->ps_ksp0
+ wm_prog_data
->prog_offset_2
;
395 /* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
396 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_WM
), wm
) {
397 wm
.StatisticsEnable
= true;
398 wm
.ThreadDispatchEnable
= true;
399 wm
.LineEndCapAntialiasingRegionWidth
= 0; /* 0.5 pixels */
400 wm
.LineAntialiasingRegionWidth
= 1; /* 1.0 pixels */
401 wm
.EarlyDepthStencilControl
= EDSC_NORMAL
;
402 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
403 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
404 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
405 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
406 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
407 wm
.BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
;
411 *pPipeline
= anv_pipeline_to_handle(pipeline
);