2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
35 #include "genX_pipeline_util.h"
38 gen7_emit_rs_state(struct anv_pipeline
*pipeline
,
39 const VkPipelineRasterizationStateCreateInfo
*info
,
40 const struct anv_graphics_pipeline_create_info
*extra
)
42 struct GENX(3DSTATE_SF
) sf
= {
43 GENX(3DSTATE_SF_header
),
45 /* LegacyGlobalDepthBiasEnable */
47 .StatisticsEnable
= true,
48 .FrontFaceFillMode
= vk_to_gen_fillmode
[info
->polygonMode
],
49 .BackFaceFillMode
= vk_to_gen_fillmode
[info
->polygonMode
],
50 .ViewTransformEnable
= !(extra
&& extra
->disable_viewport
),
51 .FrontWinding
= vk_to_gen_front_face
[info
->frontFace
],
52 /* bool AntiAliasingEnable; */
54 .CullMode
= vk_to_gen_cullmode
[info
->cullMode
],
56 /* uint32_t LineEndCapAntialiasingRegionWidth; */
57 .ScissorRectangleEnable
= !(extra
&& extra
->disable_scissor
),
59 /* uint32_t MultisampleRasterizationMode; */
60 /* bool LastPixelEnable; */
62 .TriangleStripListProvokingVertexSelect
= 0,
63 .LineStripListProvokingVertexSelect
= 0,
64 .TriangleFanProvokingVertexSelect
= 1,
66 /* uint32_t AALineDistanceMode; */
67 /* uint32_t VertexSubPixelPrecisionSelect; */
68 .UsePointWidthState
= !pipeline
->writes_point_size
,
70 .GlobalDepthOffsetConstant
= info
->depthBiasEnable
,
71 .GlobalDepthOffsetScale
= info
->depthBiasEnable
,
72 .GlobalDepthOffsetClamp
= info
->depthBiasEnable
,
75 GENX(3DSTATE_SF_pack
)(NULL
, &pipeline
->gen7
.sf
, &sf
);
79 gen7_emit_ds_state(struct anv_pipeline
*pipeline
,
80 const VkPipelineDepthStencilStateCreateInfo
*info
)
83 /* We're going to OR this together with the dynamic state. We need
84 * to make sure it's initialized to something useful.
86 memset(pipeline
->gen7
.depth_stencil_state
, 0,
87 sizeof(pipeline
->gen7
.depth_stencil_state
));
91 struct GENX(DEPTH_STENCIL_STATE
) state
= {
92 .DepthTestEnable
= info
->depthTestEnable
,
93 .DepthBufferWriteEnable
= info
->depthWriteEnable
,
94 .DepthTestFunction
= vk_to_gen_compare_op
[info
->depthCompareOp
],
95 .DoubleSidedStencilEnable
= true,
97 .StencilTestEnable
= info
->stencilTestEnable
,
98 .StencilBufferWriteEnable
= info
->stencilTestEnable
,
99 .StencilFailOp
= vk_to_gen_stencil_op
[info
->front
.failOp
],
100 .StencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->front
.passOp
],
101 .StencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
->front
.depthFailOp
],
102 .StencilTestFunction
= vk_to_gen_compare_op
[info
->front
.compareOp
],
104 .BackfaceStencilFailOp
= vk_to_gen_stencil_op
[info
->back
.failOp
],
105 .BackfaceStencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->back
.passOp
],
106 .BackfaceStencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
->back
.depthFailOp
],
107 .BackFaceStencilTestFunction
= vk_to_gen_compare_op
[info
->back
.compareOp
],
110 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, &pipeline
->gen7
.depth_stencil_state
, &state
);
114 gen7_emit_cb_state(struct anv_pipeline
*pipeline
,
115 const VkPipelineColorBlendStateCreateInfo
*info
,
116 const VkPipelineMultisampleStateCreateInfo
*ms_info
)
118 struct anv_device
*device
= pipeline
->device
;
120 if (info
== NULL
|| info
->attachmentCount
== 0) {
121 pipeline
->blend_state
=
122 anv_state_pool_emit(&device
->dynamic_state_pool
,
123 GENX(BLEND_STATE
), 64,
124 .ColorBufferBlendEnable
= false,
125 .WriteDisableAlpha
= true,
126 .WriteDisableRed
= true,
127 .WriteDisableGreen
= true,
128 .WriteDisableBlue
= true);
130 const VkPipelineColorBlendAttachmentState
*a
= &info
->pAttachments
[0];
131 struct GENX(BLEND_STATE
) blend
= {
132 .AlphaToCoverageEnable
= ms_info
&& ms_info
->alphaToCoverageEnable
,
133 .AlphaToOneEnable
= ms_info
&& ms_info
->alphaToOneEnable
,
135 .LogicOpEnable
= info
->logicOpEnable
,
136 .LogicOpFunction
= vk_to_gen_logic_op
[info
->logicOp
],
137 .ColorBufferBlendEnable
= a
->blendEnable
,
138 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
139 .PreBlendColorClampEnable
= true,
140 .PostBlendColorClampEnable
= true,
141 .SourceBlendFactor
= vk_to_gen_blend
[a
->srcColorBlendFactor
],
142 .DestinationBlendFactor
= vk_to_gen_blend
[a
->dstColorBlendFactor
],
143 .ColorBlendFunction
= vk_to_gen_blend_op
[a
->colorBlendOp
],
144 .SourceAlphaBlendFactor
= vk_to_gen_blend
[a
->srcAlphaBlendFactor
],
145 .DestinationAlphaBlendFactor
= vk_to_gen_blend
[a
->dstAlphaBlendFactor
],
146 .AlphaBlendFunction
= vk_to_gen_blend_op
[a
->alphaBlendOp
],
147 .WriteDisableAlpha
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_A_BIT
),
148 .WriteDisableRed
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_R_BIT
),
149 .WriteDisableGreen
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_G_BIT
),
150 .WriteDisableBlue
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_B_BIT
),
153 /* Our hardware applies the blend factor prior to the blend function
154 * regardless of what function is used. Technically, this means the
155 * hardware can do MORE than GL or Vulkan specify. However, it also
156 * means that, for MIN and MAX, we have to stomp the blend factor to
157 * ONE to make it a no-op.
159 if (a
->colorBlendOp
== VK_BLEND_OP_MIN
||
160 a
->colorBlendOp
== VK_BLEND_OP_MAX
) {
161 blend
.SourceBlendFactor
= BLENDFACTOR_ONE
;
162 blend
.DestinationBlendFactor
= BLENDFACTOR_ONE
;
164 if (a
->alphaBlendOp
== VK_BLEND_OP_MIN
||
165 a
->alphaBlendOp
== VK_BLEND_OP_MAX
) {
166 blend
.SourceAlphaBlendFactor
= BLENDFACTOR_ONE
;
167 blend
.DestinationAlphaBlendFactor
= BLENDFACTOR_ONE
;
170 pipeline
->blend_state
= anv_state_pool_alloc(&device
->dynamic_state_pool
,
171 GENX(BLEND_STATE_length
) * 4,
173 GENX(BLEND_STATE_pack
)(NULL
, pipeline
->blend_state
.map
, &blend
);
174 if (pipeline
->device
->info
.has_llc
)
175 anv_state_clflush(pipeline
->blend_state
);
178 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
),
179 .BlendStatePointer
= pipeline
->blend_state
.offset
);
183 genX(graphics_pipeline_create
)(
185 struct anv_pipeline_cache
* cache
,
186 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
187 const struct anv_graphics_pipeline_create_info
*extra
,
188 const VkAllocationCallbacks
* pAllocator
,
189 VkPipeline
* pPipeline
)
191 ANV_FROM_HANDLE(anv_device
, device
, _device
);
192 struct anv_pipeline
*pipeline
;
195 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
197 pipeline
= anv_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
198 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
199 if (pipeline
== NULL
)
200 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
202 result
= anv_pipeline_init(pipeline
, device
, cache
,
203 pCreateInfo
, extra
, pAllocator
);
204 if (result
!= VK_SUCCESS
) {
205 anv_free2(&device
->alloc
, pAllocator
, pipeline
);
209 assert(pCreateInfo
->pVertexInputState
);
210 emit_vertex_input(pipeline
, pCreateInfo
->pVertexInputState
, extra
);
212 assert(pCreateInfo
->pRasterizationState
);
213 gen7_emit_rs_state(pipeline
, pCreateInfo
->pRasterizationState
, extra
);
215 gen7_emit_ds_state(pipeline
, pCreateInfo
->pDepthStencilState
);
217 gen7_emit_cb_state(pipeline
, pCreateInfo
->pColorBlendState
,
218 pCreateInfo
->pMultisampleState
);
220 emit_urb_setup(pipeline
);
222 const VkPipelineRasterizationStateCreateInfo
*rs_info
=
223 pCreateInfo
->pRasterizationState
;
225 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_CLIP
),
226 .FrontWinding
= vk_to_gen_front_face
[rs_info
->frontFace
],
227 .CullMode
= vk_to_gen_cullmode
[rs_info
->cullMode
],
229 .APIMode
= APIMODE_OGL
,
230 .ViewportXYClipTestEnable
= !(extra
&& extra
->disable_viewport
),
231 .ClipMode
= CLIPMODE_NORMAL
,
232 .TriangleStripListProvokingVertexSelect
= 0,
233 .LineStripListProvokingVertexSelect
= 0,
234 .TriangleFanProvokingVertexSelect
= 1,
235 .MinimumPointWidth
= 0.125,
236 .MaximumPointWidth
= 255.875,
237 .MaximumVPIndex
= pCreateInfo
->pViewportState
->viewportCount
- 1);
239 if (pCreateInfo
->pMultisampleState
&&
240 pCreateInfo
->pMultisampleState
->rasterizationSamples
> 1)
241 anv_finishme("VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO");
243 uint32_t samples
= 1;
244 uint32_t log2_samples
= __builtin_ffs(samples
) - 1;
246 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_MULTISAMPLE
),
247 .PixelLocation
= PIXLOC_CENTER
,
248 .NumberofMultisamples
= log2_samples
);
250 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_SAMPLE_MASK
),
253 const struct brw_vue_prog_data
*vue_prog_data
= &pipeline
->vs_prog_data
.base
;
256 /* From gen7_vs_state.c */
259 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
260 * Geometry > Geometry Shader > State:
262 * "Note: Because of corruption in IVB:GT2, software needs to flush the
263 * whole fixed function pipeline when the GS enable changes value in
266 * The hardware architects have clarified that in this context "flush the
267 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
270 if (!brw
->is_haswell
&& !brw
->is_baytrail
)
271 gen7_emit_vs_workaround_flush(brw
);
274 if (pipeline
->vs_vec4
== NO_KERNEL
|| (extra
&& extra
->disable_vs
))
275 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VS
), .VSFunctionEnable
= false);
277 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VS
),
278 .KernelStartPointer
= pipeline
->vs_vec4
,
279 .ScratchSpaceBaseOffset
= pipeline
->scratch_start
[MESA_SHADER_VERTEX
],
280 .PerThreadScratchSpace
= scratch_space(&vue_prog_data
->base
),
282 .DispatchGRFStartRegisterforURBData
=
283 vue_prog_data
->base
.dispatch_grf_start_reg
,
284 .VertexURBEntryReadLength
= vue_prog_data
->urb_read_length
,
285 .VertexURBEntryReadOffset
= 0,
287 .MaximumNumberofThreads
= device
->info
.max_vs_threads
- 1,
288 .StatisticsEnable
= true,
289 .VSFunctionEnable
= true);
291 const struct brw_gs_prog_data
*gs_prog_data
= &pipeline
->gs_prog_data
;
293 if (pipeline
->gs_kernel
== NO_KERNEL
|| (extra
&& extra
->disable_vs
)) {
294 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_GS
), .GSEnable
= false);
296 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_GS
),
297 .KernelStartPointer
= pipeline
->gs_kernel
,
298 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[MESA_SHADER_GEOMETRY
],
299 .PerThreadScratchSpace
= scratch_space(&gs_prog_data
->base
.base
),
301 .OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1,
302 .OutputTopology
= gs_prog_data
->output_topology
,
303 .VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
,
304 .IncludeVertexHandles
= gs_prog_data
->base
.include_vue_handles
,
305 .DispatchGRFStartRegisterforURBData
=
306 gs_prog_data
->base
.base
.dispatch_grf_start_reg
,
308 .MaximumNumberofThreads
= device
->info
.max_gs_threads
- 1,
309 /* This in the next dword on HSW. */
310 .ControlDataFormat
= gs_prog_data
->control_data_format
,
311 .ControlDataHeaderSize
= gs_prog_data
->control_data_header_size_hwords
,
312 .InstanceControl
= MAX2(gs_prog_data
->invocations
, 1) - 1,
313 .DispatchMode
= gs_prog_data
->base
.dispatch_mode
,
314 .GSStatisticsEnable
= true,
315 .IncludePrimitiveID
= gs_prog_data
->include_primitive_id
,
316 # if (GEN_IS_HASWELL)
317 .ReorderMode
= REORDER_TRAILING
,
319 .ReorderEnable
= true,
324 if (pipeline
->ps_ksp0
== NO_KERNEL
) {
325 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_SBE
));
327 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_WM
),
328 .StatisticsEnable
= true,
329 .ThreadDispatchEnable
= false,
330 .LineEndCapAntialiasingRegionWidth
= 0, /* 0.5 pixels */
331 .LineAntialiasingRegionWidth
= 1, /* 1.0 pixels */
332 .EarlyDepthStencilControl
= EDSC_NORMAL
,
333 .PointRasterizationRule
= RASTRULE_UPPER_RIGHT
);
335 /* Even if no fragments are ever dispatched, the hardware hangs if we
336 * don't at least set the maximum number of threads.
338 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS
),
339 .MaximumNumberofThreads
= device
->info
.max_wm_threads
- 1);
341 const struct brw_wm_prog_data
*wm_prog_data
= &pipeline
->wm_prog_data
;
342 if (wm_prog_data
->urb_setup
[VARYING_SLOT_BFC0
] != -1 ||
343 wm_prog_data
->urb_setup
[VARYING_SLOT_BFC1
] != -1)
344 anv_finishme("two-sided color needs sbe swizzling setup");
345 if (wm_prog_data
->urb_setup
[VARYING_SLOT_PRIMITIVE_ID
] != -1)
346 anv_finishme("primitive_id needs sbe swizzling setup");
348 emit_3dstate_sbe(pipeline
);
350 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS
),
351 .KernelStartPointer0
= pipeline
->ps_ksp0
,
352 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[MESA_SHADER_FRAGMENT
],
353 .PerThreadScratchSpace
= scratch_space(&wm_prog_data
->base
),
355 .MaximumNumberofThreads
= device
->info
.max_wm_threads
- 1,
356 .PushConstantEnable
= wm_prog_data
->base
.nr_params
> 0,
357 .AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0,
358 .oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
,
360 .RenderTargetFastClearEnable
= false,
361 .DualSourceBlendEnable
= false,
362 .RenderTargetResolveEnable
= false,
364 .PositionXYOffsetSelect
= wm_prog_data
->uses_pos_offset
?
365 POSOFFSET_SAMPLE
: POSOFFSET_NONE
,
367 ._32PixelDispatchEnable
= false,
368 ._16PixelDispatchEnable
= pipeline
->ps_simd16
!= NO_KERNEL
,
369 ._8PixelDispatchEnable
= pipeline
->ps_simd8
!= NO_KERNEL
,
371 .DispatchGRFStartRegisterforConstantSetupData0
= pipeline
->ps_grf_start0
,
372 .DispatchGRFStartRegisterforConstantSetupData1
= 0,
373 .DispatchGRFStartRegisterforConstantSetupData2
= pipeline
->ps_grf_start2
,
376 /* Haswell requires the sample mask to be set in this packet as well as
377 * in 3DSTATE_SAMPLE_MASK; the values should match. */
378 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
381 .KernelStartPointer1
= 0,
382 .KernelStartPointer2
= pipeline
->ps_ksp2
);
384 /* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
385 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_WM
),
386 .StatisticsEnable
= true,
387 .ThreadDispatchEnable
= true,
388 .LineEndCapAntialiasingRegionWidth
= 0, /* 0.5 pixels */
389 .LineAntialiasingRegionWidth
= 1, /* 1.0 pixels */
390 .EarlyDepthStencilControl
= EDSC_NORMAL
,
391 .PointRasterizationRule
= RASTRULE_UPPER_RIGHT
,
392 .PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
,
393 .PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
,
394 .PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
,
395 .PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
,
396 .BarycentricInterpolationMode
= wm_prog_data
->barycentric_interp_modes
);
399 *pPipeline
= anv_pipeline_to_handle(pipeline
);