2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
37 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
)
39 uint32_t count
= cmd_buffer
->state
.dynamic
.viewport
.count
;
40 const VkViewport
*viewports
= cmd_buffer
->state
.dynamic
.viewport
.viewports
;
41 struct anv_state sf_clip_state
=
42 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, count
* 64, 64);
44 for (uint32_t i
= 0; i
< count
; i
++) {
45 const VkViewport
*vp
= &viewports
[i
];
47 /* The gen7 state struct has just the matrix and guardband fields, the
48 * gen8 struct adds the min/max viewport fields. */
49 struct GENX(SF_CLIP_VIEWPORT
) sf_clip_viewport
= {
50 .ViewportMatrixElementm00
= vp
->width
/ 2,
51 .ViewportMatrixElementm11
= vp
->height
/ 2,
52 .ViewportMatrixElementm22
= 1.0,
53 .ViewportMatrixElementm30
= vp
->x
+ vp
->width
/ 2,
54 .ViewportMatrixElementm31
= vp
->y
+ vp
->height
/ 2,
55 .ViewportMatrixElementm32
= 0.0,
56 .XMinClipGuardband
= -1.0f
,
57 .XMaxClipGuardband
= 1.0f
,
58 .YMinClipGuardband
= -1.0f
,
59 .YMaxClipGuardband
= 1.0f
,
60 .XMinViewPort
= vp
->x
,
61 .XMaxViewPort
= vp
->x
+ vp
->width
- 1,
62 .YMinViewPort
= MIN2(vp
->y
, vp
->y
+ vp
->height
),
63 .YMaxViewPort
= MAX2(vp
->y
, vp
->y
+ vp
->height
) - 1,
66 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_state
.map
+ i
* 64,
70 anv_state_flush(cmd_buffer
->device
, sf_clip_state
);
72 anv_batch_emit(&cmd_buffer
->batch
,
73 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), clip
) {
74 clip
.SFClipViewportPointer
= sf_clip_state
.offset
;
79 gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
80 bool depth_clamp_enable
)
82 uint32_t count
= cmd_buffer
->state
.dynamic
.viewport
.count
;
83 const VkViewport
*viewports
= cmd_buffer
->state
.dynamic
.viewport
.viewports
;
84 struct anv_state cc_state
=
85 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, count
* 8, 32);
87 for (uint32_t i
= 0; i
< count
; i
++) {
88 const VkViewport
*vp
= &viewports
[i
];
90 struct GENX(CC_VIEWPORT
) cc_viewport
= {
91 .MinimumDepth
= depth_clamp_enable
? vp
->minDepth
: 0.0f
,
92 .MaximumDepth
= depth_clamp_enable
? vp
->maxDepth
: 1.0f
,
95 GENX(CC_VIEWPORT_pack
)(NULL
, cc_state
.map
+ i
* 8, &cc_viewport
);
98 anv_state_flush(cmd_buffer
->device
, cc_state
);
100 anv_batch_emit(&cmd_buffer
->batch
,
101 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), cc
) {
102 cc
.CCViewportPointer
= cc_state
.offset
;
108 genX(cmd_buffer_enable_pma_fix
)(struct anv_cmd_buffer
*cmd_buffer
, bool enable
)
110 if (cmd_buffer
->state
.pma_fix_enabled
== enable
)
113 cmd_buffer
->state
.pma_fix_enabled
= enable
;
115 /* According to the Broadwell PIPE_CONTROL documentation, software should
116 * emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set
117 * prior to the LRI. If stencil buffer writes are enabled, then a Render
118 * Cache Flush is also necessary.
120 * The Skylake docs say to use a depth stall rather than a command
121 * streamer stall. However, the hardware seems to violently disagree.
122 * A full command streamer stall seems to be needed in both cases.
124 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
125 pc
.DepthCacheFlushEnable
= true;
126 pc
.CommandStreamerStallEnable
= true;
127 pc
.RenderTargetCacheFlushEnable
= true;
133 anv_pack_struct(&cache_mode
, GENX(CACHE_MODE_0
),
134 .STCPMAOptimizationEnable
= enable
,
135 .STCPMAOptimizationEnableMask
= true);
136 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
137 lri
.RegisterOffset
= GENX(CACHE_MODE_0_num
);
138 lri
.DataDWord
= cache_mode
;
144 anv_pack_struct(&cache_mode
, GENX(CACHE_MODE_1
),
145 .NPPMAFixEnable
= enable
,
146 .NPEarlyZFailsDisable
= enable
,
147 .NPPMAFixEnableMask
= true,
148 .NPEarlyZFailsDisableMask
= true);
149 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
150 lri
.RegisterOffset
= GENX(CACHE_MODE_1_num
);
151 lri
.DataDWord
= cache_mode
;
154 #endif /* GEN_GEN == 8 */
156 /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
157 * Flush bits is often necessary. We do it regardless because it's easier.
158 * The render cache flush is also necessary if stencil writes are enabled.
160 * Again, the Skylake docs give a different set of flushes but the BDW
161 * flushes seem to work just as well.
163 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
164 pc
.DepthStallEnable
= true;
165 pc
.DepthCacheFlushEnable
= true;
166 pc
.RenderTargetCacheFlushEnable
= true;
171 want_depth_pma_fix(struct anv_cmd_buffer
*cmd_buffer
)
173 assert(GEN_GEN
== 8);
175 /* From the Broadwell PRM Vol. 2c CACHE_MODE_1::NP_PMA_FIX_ENABLE:
177 * SW must set this bit in order to enable this fix when following
178 * expression is TRUE.
180 * 3DSTATE_WM::ForceThreadDispatch != 1 &&
181 * !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) &&
182 * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
183 * (3DSTATE_DEPTH_BUFFER::HIZ Enable) &&
184 * !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) &&
185 * (3DSTATE_PS_EXTRA::PixelShaderValid) &&
186 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
187 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
188 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
189 * 3DSTATE_WM_HZ_OP::StencilBufferClear) &&
190 * (3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable) &&
191 * (((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
192 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
193 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
194 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
195 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) &&
196 * 3DSTATE_WM::ForceKillPix != ForceOff &&
197 * ((3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
198 * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE) ||
199 * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
200 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
201 * 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE))) ||
202 * (3DSTATE_PS_EXTRA:: Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
205 /* These are always true:
206 * 3DSTATE_WM::ForceThreadDispatch != 1 &&
207 * !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0)
210 /* We only enable the PMA fix if we know for certain that HiZ is enabled.
211 * If we don't know whether HiZ is enabled or not, we disable the PMA fix
212 * and there is no harm.
214 * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
215 * 3DSTATE_DEPTH_BUFFER::HIZ Enable
217 if (!cmd_buffer
->state
.hiz_enabled
)
220 /* 3DSTATE_PS_EXTRA::PixelShaderValid */
221 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
222 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
))
225 /* !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) */
226 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
227 if (wm_prog_data
->early_fragment_tests
)
230 /* We never use anv_pipeline for HiZ ops so this is trivially true:
231 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
232 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
233 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
234 * 3DSTATE_WM_HZ_OP::StencilBufferClear)
237 /* 3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable */
238 if (!pipeline
->depth_test_enable
)
241 /* (((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
242 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
243 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
244 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
245 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) &&
246 * 3DSTATE_WM::ForceKillPix != ForceOff &&
247 * ((3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
248 * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE) ||
249 * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
250 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
251 * 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE))) ||
252 * (3DSTATE_PS_EXTRA:: Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
254 return (pipeline
->kill_pixel
&& (pipeline
->writes_depth
||
255 pipeline
->writes_stencil
)) ||
256 wm_prog_data
->computed_depth_mode
!= PSCDEPTH_OFF
;
260 want_stencil_pma_fix(struct anv_cmd_buffer
*cmd_buffer
)
262 assert(GEN_GEN
== 9);
264 /* From the Skylake PRM Vol. 2c CACHE_MODE_1::STC PMA Optimization Enable:
266 * Clearing this bit will force the STC cache to wait for pending
267 * retirement of pixels at the HZ-read stage and do the STC-test for
268 * Non-promoted, R-computed and Computed depth modes instead of
269 * postponing the STC-test to RCPFE.
271 * STC_TEST_EN = 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
272 * 3DSTATE_WM_DEPTH_STENCIL::StencilTestEnable
274 * STC_WRITE_EN = 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
275 * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
276 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE)
278 * COMP_STC_EN = STC_TEST_EN &&
279 * 3DSTATE_PS_EXTRA::PixelShaderComputesStencil
281 * SW parses the pipeline states to generate the following logical
282 * signal indicating if PMA FIX can be enabled.
285 * 3DSTATE_WM::ForceThreadDispatch != 1 &&
286 * !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) &&
287 * 3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
288 * 3DSTATE_DEPTH_BUFFER::HIZ Enable &&
289 * !(3DSTATE_WM::EDSC_Mode == 2) &&
290 * 3DSTATE_PS_EXTRA::PixelShaderValid &&
291 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
292 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
293 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
294 * 3DSTATE_WM_HZ_OP::StencilBufferClear) &&
295 * (COMP_STC_EN || STC_WRITE_EN) &&
296 * ((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
297 * 3DSTATE_WM::ForceKillPix == ON ||
298 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
299 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
300 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
301 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) ||
302 * (3DSTATE_PS_EXTRA::Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
305 /* These are always true:
306 * 3DSTATE_WM::ForceThreadDispatch != 1 &&
307 * !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0)
310 /* We only enable the PMA fix if we know for certain that HiZ is enabled.
311 * If we don't know whether HiZ is enabled or not, we disable the PMA fix
312 * and there is no harm.
314 * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
315 * 3DSTATE_DEPTH_BUFFER::HIZ Enable
317 if (!cmd_buffer
->state
.hiz_enabled
)
320 /* We can't possibly know if HiZ is enabled without the framebuffer */
321 assert(cmd_buffer
->state
.framebuffer
);
323 /* HiZ is enabled so we had better have a depth buffer with HiZ */
324 const struct anv_image_view
*ds_iview
=
325 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
326 assert(ds_iview
&& ds_iview
->image
->aux_usage
== ISL_AUX_USAGE_HIZ
);
328 /* 3DSTATE_PS_EXTRA::PixelShaderValid */
329 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
330 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
))
333 /* !(3DSTATE_WM::EDSC_Mode == 2) */
334 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
335 if (wm_prog_data
->early_fragment_tests
)
338 /* We never use anv_pipeline for HiZ ops so this is trivially true:
339 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
340 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
341 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
342 * 3DSTATE_WM_HZ_OP::StencilBufferClear)
345 /* 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
346 * 3DSTATE_WM_DEPTH_STENCIL::StencilTestEnable
348 const bool stc_test_en
=
349 (ds_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
350 pipeline
->stencil_test_enable
;
352 /* 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
353 * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
354 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE)
356 const bool stc_write_en
=
357 (ds_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
358 pipeline
->writes_stencil
;
360 /* STC_TEST_EN && 3DSTATE_PS_EXTRA::PixelShaderComputesStencil */
361 const bool comp_stc_en
= stc_test_en
&& wm_prog_data
->computed_stencil
;
363 /* COMP_STC_EN || STC_WRITE_EN */
364 if (!(comp_stc_en
|| stc_write_en
))
367 /* (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
368 * 3DSTATE_WM::ForceKillPix == ON ||
369 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
370 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
371 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
372 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) ||
373 * (3DSTATE_PS_EXTRA::Pixel Shader Computed Depth mode != PSCDEPTH_OFF)
375 return pipeline
->kill_pixel
||
376 wm_prog_data
->computed_depth_mode
!= PSCDEPTH_OFF
;
380 genX(cmd_buffer_flush_dynamic_state
)(struct anv_cmd_buffer
*cmd_buffer
)
382 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
384 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
385 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)) {
386 uint32_t sf_dw
[GENX(3DSTATE_SF_length
)];
387 struct GENX(3DSTATE_SF
) sf
= {
388 GENX(3DSTATE_SF_header
),
391 if (cmd_buffer
->device
->info
.is_cherryview
) {
392 sf
.CHVLineWidth
= cmd_buffer
->state
.dynamic
.line_width
;
394 sf
.LineWidth
= cmd_buffer
->state
.dynamic
.line_width
;
397 sf
.LineWidth
= cmd_buffer
->state
.dynamic
.line_width
,
399 GENX(3DSTATE_SF_pack
)(NULL
, sf_dw
, &sf
);
400 anv_batch_emit_merge(&cmd_buffer
->batch
, sf_dw
,
401 cmd_buffer
->state
.pipeline
->gen8
.sf
);
404 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
405 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)){
406 uint32_t raster_dw
[GENX(3DSTATE_RASTER_length
)];
407 struct GENX(3DSTATE_RASTER
) raster
= {
408 GENX(3DSTATE_RASTER_header
),
409 .GlobalDepthOffsetConstant
= cmd_buffer
->state
.dynamic
.depth_bias
.bias
,
410 .GlobalDepthOffsetScale
= cmd_buffer
->state
.dynamic
.depth_bias
.slope
,
411 .GlobalDepthOffsetClamp
= cmd_buffer
->state
.dynamic
.depth_bias
.clamp
413 GENX(3DSTATE_RASTER_pack
)(NULL
, raster_dw
, &raster
);
414 anv_batch_emit_merge(&cmd_buffer
->batch
, raster_dw
,
415 pipeline
->gen8
.raster
);
418 /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
419 * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
420 * across different state packets for gen8 and gen9. We handle that by
421 * using a big old #if switch here.
424 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
|
425 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
)) {
426 struct anv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
427 struct anv_state cc_state
=
428 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
429 GENX(COLOR_CALC_STATE_length
) * 4,
431 struct GENX(COLOR_CALC_STATE
) cc
= {
432 .BlendConstantColorRed
= cmd_buffer
->state
.dynamic
.blend_constants
[0],
433 .BlendConstantColorGreen
= cmd_buffer
->state
.dynamic
.blend_constants
[1],
434 .BlendConstantColorBlue
= cmd_buffer
->state
.dynamic
.blend_constants
[2],
435 .BlendConstantColorAlpha
= cmd_buffer
->state
.dynamic
.blend_constants
[3],
436 .StencilReferenceValue
= d
->stencil_reference
.front
& 0xff,
437 .BackfaceStencilReferenceValue
= d
->stencil_reference
.back
& 0xff,
439 GENX(COLOR_CALC_STATE_pack
)(NULL
, cc_state
.map
, &cc
);
441 anv_state_flush(cmd_buffer
->device
, cc_state
);
443 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ccp
) {
444 ccp
.ColorCalcStatePointer
= cc_state
.offset
;
445 ccp
.ColorCalcStatePointerValid
= true;
449 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
450 ANV_CMD_DIRTY_RENDER_TARGETS
|
451 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
|
452 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
)) {
453 uint32_t wm_depth_stencil_dw
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
454 struct anv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
456 struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil
) = {
457 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
459 .StencilTestMask
= d
->stencil_compare_mask
.front
& 0xff,
460 .StencilWriteMask
= d
->stencil_write_mask
.front
& 0xff,
462 .BackfaceStencilTestMask
= d
->stencil_compare_mask
.back
& 0xff,
463 .BackfaceStencilWriteMask
= d
->stencil_write_mask
.back
& 0xff,
465 .StencilBufferWriteEnable
=
466 (d
->stencil_write_mask
.front
|| d
->stencil_write_mask
.back
) &&
467 pipeline
->writes_stencil
,
469 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, wm_depth_stencil_dw
,
472 anv_batch_emit_merge(&cmd_buffer
->batch
, wm_depth_stencil_dw
,
473 pipeline
->gen8
.wm_depth_stencil
);
475 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
,
476 want_depth_pma_fix(cmd_buffer
));
479 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
) {
480 struct anv_state cc_state
=
481 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
482 GENX(COLOR_CALC_STATE_length
) * 4,
484 struct GENX(COLOR_CALC_STATE
) cc
= {
485 .BlendConstantColorRed
= cmd_buffer
->state
.dynamic
.blend_constants
[0],
486 .BlendConstantColorGreen
= cmd_buffer
->state
.dynamic
.blend_constants
[1],
487 .BlendConstantColorBlue
= cmd_buffer
->state
.dynamic
.blend_constants
[2],
488 .BlendConstantColorAlpha
= cmd_buffer
->state
.dynamic
.blend_constants
[3],
490 GENX(COLOR_CALC_STATE_pack
)(NULL
, cc_state
.map
, &cc
);
492 anv_state_flush(cmd_buffer
->device
, cc_state
);
494 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ccp
) {
495 ccp
.ColorCalcStatePointer
= cc_state
.offset
;
496 ccp
.ColorCalcStatePointerValid
= true;
500 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
501 ANV_CMD_DIRTY_RENDER_TARGETS
|
502 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
|
503 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
504 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
)) {
505 uint32_t dwords
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
506 struct anv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
507 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) wm_depth_stencil
= {
508 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
510 .StencilTestMask
= d
->stencil_compare_mask
.front
& 0xff,
511 .StencilWriteMask
= d
->stencil_write_mask
.front
& 0xff,
513 .BackfaceStencilTestMask
= d
->stencil_compare_mask
.back
& 0xff,
514 .BackfaceStencilWriteMask
= d
->stencil_write_mask
.back
& 0xff,
516 .StencilReferenceValue
= d
->stencil_reference
.front
& 0xff,
517 .BackfaceStencilReferenceValue
= d
->stencil_reference
.back
& 0xff,
519 .StencilBufferWriteEnable
=
520 (d
->stencil_write_mask
.front
|| d
->stencil_write_mask
.back
) &&
521 pipeline
->writes_stencil
,
523 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, dwords
, &wm_depth_stencil
);
525 anv_batch_emit_merge(&cmd_buffer
->batch
, dwords
,
526 pipeline
->gen9
.wm_depth_stencil
);
528 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
,
529 want_stencil_pma_fix(cmd_buffer
));
533 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
534 ANV_CMD_DIRTY_INDEX_BUFFER
)) {
535 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_VF
), vf
) {
536 vf
.IndexedDrawCutIndexEnable
= pipeline
->primitive_restart
;
537 vf
.CutIndex
= cmd_buffer
->state
.restart_index
;
541 cmd_buffer
->state
.dirty
= 0;
544 void genX(CmdBindIndexBuffer
)(
545 VkCommandBuffer commandBuffer
,
548 VkIndexType indexType
)
550 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
551 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
553 static const uint32_t vk_to_gen_index_type
[] = {
554 [VK_INDEX_TYPE_UINT16
] = INDEX_WORD
,
555 [VK_INDEX_TYPE_UINT32
] = INDEX_DWORD
,
558 static const uint32_t restart_index_for_type
[] = {
559 [VK_INDEX_TYPE_UINT16
] = UINT16_MAX
,
560 [VK_INDEX_TYPE_UINT32
] = UINT32_MAX
,
563 cmd_buffer
->state
.restart_index
= restart_index_for_type
[indexType
];
565 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
566 ib
.IndexFormat
= vk_to_gen_index_type
[indexType
];
567 ib
.MemoryObjectControlState
= GENX(MOCS
);
568 ib
.BufferStartingAddress
=
569 (struct anv_address
) { buffer
->bo
, buffer
->offset
+ offset
};
570 ib
.BufferSize
= buffer
->size
- offset
;
573 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_INDEX_BUFFER
;
576 /* Set of stage bits for which are pipelined, i.e. they get queued by the
577 * command streamer for later execution.
579 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
580 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
581 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
582 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
583 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
584 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
585 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
586 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
587 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
588 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
589 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
590 VK_PIPELINE_STAGE_TRANSFER_BIT | \
591 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
592 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
593 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
595 void genX(CmdSetEvent
)(
596 VkCommandBuffer commandBuffer
,
598 VkPipelineStageFlags stageMask
)
600 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
601 ANV_FROM_HANDLE(anv_event
, event
, _event
);
603 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
604 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
605 pc
.StallAtPixelScoreboard
= true;
606 pc
.CommandStreamerStallEnable
= true;
609 pc
.DestinationAddressType
= DAT_PPGTT
,
610 pc
.PostSyncOperation
= WriteImmediateData
,
611 pc
.Address
= (struct anv_address
) {
612 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
615 pc
.ImmediateData
= VK_EVENT_SET
;
619 void genX(CmdResetEvent
)(
620 VkCommandBuffer commandBuffer
,
622 VkPipelineStageFlags stageMask
)
624 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
625 ANV_FROM_HANDLE(anv_event
, event
, _event
);
627 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
628 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
629 pc
.StallAtPixelScoreboard
= true;
630 pc
.CommandStreamerStallEnable
= true;
633 pc
.DestinationAddressType
= DAT_PPGTT
;
634 pc
.PostSyncOperation
= WriteImmediateData
;
635 pc
.Address
= (struct anv_address
) {
636 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
639 pc
.ImmediateData
= VK_EVENT_RESET
;
643 void genX(CmdWaitEvents
)(
644 VkCommandBuffer commandBuffer
,
646 const VkEvent
* pEvents
,
647 VkPipelineStageFlags srcStageMask
,
648 VkPipelineStageFlags destStageMask
,
649 uint32_t memoryBarrierCount
,
650 const VkMemoryBarrier
* pMemoryBarriers
,
651 uint32_t bufferMemoryBarrierCount
,
652 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
653 uint32_t imageMemoryBarrierCount
,
654 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
656 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
657 for (uint32_t i
= 0; i
< eventCount
; i
++) {
658 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
660 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
661 sem
.WaitMode
= PollingMode
,
662 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
663 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
664 sem
.SemaphoreAddress
= (struct anv_address
) {
665 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
671 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
672 false, /* byRegion */
673 memoryBarrierCount
, pMemoryBarriers
,
674 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
675 imageMemoryBarrierCount
, pImageMemoryBarriers
);