2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
34 #include "common/gen_guardband.h"
38 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
)
40 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
41 uint32_t count
= cmd_buffer
->state
.gfx
.dynamic
.viewport
.count
;
42 const VkViewport
*viewports
=
43 cmd_buffer
->state
.gfx
.dynamic
.viewport
.viewports
;
44 struct anv_state sf_clip_state
=
45 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, count
* 64, 64);
47 for (uint32_t i
= 0; i
< count
; i
++) {
48 const VkViewport
*vp
= &viewports
[i
];
50 /* The gen7 state struct has just the matrix and guardband fields, the
51 * gen8 struct adds the min/max viewport fields. */
52 struct GENX(SF_CLIP_VIEWPORT
) sfv
= {
53 .ViewportMatrixElementm00
= vp
->width
/ 2,
54 .ViewportMatrixElementm11
= vp
->height
/ 2,
55 .ViewportMatrixElementm22
= vp
->maxDepth
- vp
->minDepth
,
56 .ViewportMatrixElementm30
= vp
->x
+ vp
->width
/ 2,
57 .ViewportMatrixElementm31
= vp
->y
+ vp
->height
/ 2,
58 .ViewportMatrixElementm32
= vp
->minDepth
,
59 .XMinClipGuardband
= -1.0f
,
60 .XMaxClipGuardband
= 1.0f
,
61 .YMinClipGuardband
= -1.0f
,
62 .YMaxClipGuardband
= 1.0f
,
63 .XMinViewPort
= vp
->x
,
64 .XMaxViewPort
= vp
->x
+ vp
->width
- 1,
65 .YMinViewPort
= MIN2(vp
->y
, vp
->y
+ vp
->height
),
66 .YMaxViewPort
= MAX2(vp
->y
, vp
->y
+ vp
->height
) - 1,
70 /* We can only calculate a "real" guardband clip if we know the
71 * framebuffer at the time we emit the packet. Otherwise, we have
72 * fall back to a worst-case guardband of [-1, 1].
74 gen_calculate_guardband_size(fb
->width
, fb
->height
,
75 sfv
.ViewportMatrixElementm00
,
76 sfv
.ViewportMatrixElementm11
,
77 sfv
.ViewportMatrixElementm30
,
78 sfv
.ViewportMatrixElementm31
,
79 &sfv
.XMinClipGuardband
,
80 &sfv
.XMaxClipGuardband
,
81 &sfv
.YMinClipGuardband
,
82 &sfv
.YMaxClipGuardband
);
85 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_state
.map
+ i
* 64, &sfv
);
88 anv_batch_emit(&cmd_buffer
->batch
,
89 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), clip
) {
90 clip
.SFClipViewportPointer
= sf_clip_state
.offset
;
95 gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
96 bool depth_clamp_enable
)
98 uint32_t count
= cmd_buffer
->state
.gfx
.dynamic
.viewport
.count
;
99 const VkViewport
*viewports
=
100 cmd_buffer
->state
.gfx
.dynamic
.viewport
.viewports
;
101 struct anv_state cc_state
=
102 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, count
* 8, 32);
104 for (uint32_t i
= 0; i
< count
; i
++) {
105 const VkViewport
*vp
= &viewports
[i
];
107 struct GENX(CC_VIEWPORT
) cc_viewport
= {
108 .MinimumDepth
= depth_clamp_enable
? vp
->minDepth
: 0.0f
,
109 .MaximumDepth
= depth_clamp_enable
? vp
->maxDepth
: 1.0f
,
112 GENX(CC_VIEWPORT_pack
)(NULL
, cc_state
.map
+ i
* 8, &cc_viewport
);
115 anv_batch_emit(&cmd_buffer
->batch
,
116 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), cc
) {
117 cc
.CCViewportPointer
= cc_state
.offset
;
123 genX(cmd_buffer_enable_pma_fix
)(struct anv_cmd_buffer
*cmd_buffer
, bool enable
)
125 if (cmd_buffer
->state
.pma_fix_enabled
== enable
)
128 cmd_buffer
->state
.pma_fix_enabled
= enable
;
130 /* According to the Broadwell PIPE_CONTROL documentation, software should
131 * emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set
132 * prior to the LRI. If stencil buffer writes are enabled, then a Render
133 * Cache Flush is also necessary.
135 * The Skylake docs say to use a depth stall rather than a command
136 * streamer stall. However, the hardware seems to violently disagree.
137 * A full command streamer stall seems to be needed in both cases.
139 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
140 pc
.DepthCacheFlushEnable
= true;
141 pc
.CommandStreamerStallEnable
= true;
142 pc
.RenderTargetCacheFlushEnable
= true;
148 anv_pack_struct(&cache_mode
, GENX(CACHE_MODE_0
),
149 .STCPMAOptimizationEnable
= enable
,
150 .STCPMAOptimizationEnableMask
= true);
151 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
152 lri
.RegisterOffset
= GENX(CACHE_MODE_0_num
);
153 lri
.DataDWord
= cache_mode
;
159 anv_pack_struct(&cache_mode
, GENX(CACHE_MODE_1
),
160 .NPPMAFixEnable
= enable
,
161 .NPEarlyZFailsDisable
= enable
,
162 .NPPMAFixEnableMask
= true,
163 .NPEarlyZFailsDisableMask
= true);
164 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
165 lri
.RegisterOffset
= GENX(CACHE_MODE_1_num
);
166 lri
.DataDWord
= cache_mode
;
169 #endif /* GEN_GEN == 8 */
171 /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
172 * Flush bits is often necessary. We do it regardless because it's easier.
173 * The render cache flush is also necessary if stencil writes are enabled.
175 * Again, the Skylake docs give a different set of flushes but the BDW
176 * flushes seem to work just as well.
178 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
179 pc
.DepthStallEnable
= true;
180 pc
.DepthCacheFlushEnable
= true;
181 pc
.RenderTargetCacheFlushEnable
= true;
186 want_depth_pma_fix(struct anv_cmd_buffer
*cmd_buffer
)
188 assert(GEN_GEN
== 8);
190 /* From the Broadwell PRM Vol. 2c CACHE_MODE_1::NP_PMA_FIX_ENABLE:
192 * SW must set this bit in order to enable this fix when following
193 * expression is TRUE.
195 * 3DSTATE_WM::ForceThreadDispatch != 1 &&
196 * !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) &&
197 * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
198 * (3DSTATE_DEPTH_BUFFER::HIZ Enable) &&
199 * !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) &&
200 * (3DSTATE_PS_EXTRA::PixelShaderValid) &&
201 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
202 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
203 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
204 * 3DSTATE_WM_HZ_OP::StencilBufferClear) &&
205 * (3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable) &&
206 * (((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
207 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
208 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
209 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
210 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) &&
211 * 3DSTATE_WM::ForceKillPix != ForceOff &&
212 * ((3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
213 * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE) ||
214 * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
215 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
216 * 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE))) ||
217 * (3DSTATE_PS_EXTRA:: Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
220 /* These are always true:
221 * 3DSTATE_WM::ForceThreadDispatch != 1 &&
222 * !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0)
225 /* We only enable the PMA fix if we know for certain that HiZ is enabled.
226 * If we don't know whether HiZ is enabled or not, we disable the PMA fix
227 * and there is no harm.
229 * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
230 * 3DSTATE_DEPTH_BUFFER::HIZ Enable
232 if (!cmd_buffer
->state
.hiz_enabled
)
235 /* 3DSTATE_PS_EXTRA::PixelShaderValid */
236 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
237 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
))
240 /* !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) */
241 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
242 if (wm_prog_data
->early_fragment_tests
)
245 /* We never use anv_pipeline for HiZ ops so this is trivially true:
246 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
247 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
248 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
249 * 3DSTATE_WM_HZ_OP::StencilBufferClear)
252 /* 3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable */
253 if (!pipeline
->depth_test_enable
)
256 /* (((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
257 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
258 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
259 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
260 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) &&
261 * 3DSTATE_WM::ForceKillPix != ForceOff &&
262 * ((3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
263 * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE) ||
264 * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
265 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
266 * 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE))) ||
267 * (3DSTATE_PS_EXTRA:: Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
269 return (pipeline
->kill_pixel
&& (pipeline
->writes_depth
||
270 pipeline
->writes_stencil
)) ||
271 wm_prog_data
->computed_depth_mode
!= PSCDEPTH_OFF
;
275 want_stencil_pma_fix(struct anv_cmd_buffer
*cmd_buffer
)
279 assert(GEN_GEN
== 9);
281 /* From the Skylake PRM Vol. 2c CACHE_MODE_1::STC PMA Optimization Enable:
283 * Clearing this bit will force the STC cache to wait for pending
284 * retirement of pixels at the HZ-read stage and do the STC-test for
285 * Non-promoted, R-computed and Computed depth modes instead of
286 * postponing the STC-test to RCPFE.
288 * STC_TEST_EN = 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
289 * 3DSTATE_WM_DEPTH_STENCIL::StencilTestEnable
291 * STC_WRITE_EN = 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
292 * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
293 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE)
295 * COMP_STC_EN = STC_TEST_EN &&
296 * 3DSTATE_PS_EXTRA::PixelShaderComputesStencil
298 * SW parses the pipeline states to generate the following logical
299 * signal indicating if PMA FIX can be enabled.
302 * 3DSTATE_WM::ForceThreadDispatch != 1 &&
303 * !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) &&
304 * 3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
305 * 3DSTATE_DEPTH_BUFFER::HIZ Enable &&
306 * !(3DSTATE_WM::EDSC_Mode == 2) &&
307 * 3DSTATE_PS_EXTRA::PixelShaderValid &&
308 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
309 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
310 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
311 * 3DSTATE_WM_HZ_OP::StencilBufferClear) &&
312 * (COMP_STC_EN || STC_WRITE_EN) &&
313 * ((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
314 * 3DSTATE_WM::ForceKillPix == ON ||
315 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
316 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
317 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
318 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) ||
319 * (3DSTATE_PS_EXTRA::Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
322 /* These are always true:
323 * 3DSTATE_WM::ForceThreadDispatch != 1 &&
324 * !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0)
327 /* We only enable the PMA fix if we know for certain that HiZ is enabled.
328 * If we don't know whether HiZ is enabled or not, we disable the PMA fix
329 * and there is no harm.
331 * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
332 * 3DSTATE_DEPTH_BUFFER::HIZ Enable
334 if (!cmd_buffer
->state
.hiz_enabled
)
337 /* We can't possibly know if HiZ is enabled without the framebuffer */
338 assert(cmd_buffer
->state
.framebuffer
);
340 /* HiZ is enabled so we had better have a depth buffer with HiZ */
341 const struct anv_image_view
*ds_iview
=
342 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
343 assert(ds_iview
&& ds_iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
345 /* 3DSTATE_PS_EXTRA::PixelShaderValid */
346 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
347 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
))
350 /* !(3DSTATE_WM::EDSC_Mode == 2) */
351 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
352 if (wm_prog_data
->early_fragment_tests
)
355 /* We never use anv_pipeline for HiZ ops so this is trivially true:
356 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
357 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
358 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
359 * 3DSTATE_WM_HZ_OP::StencilBufferClear)
362 /* 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
363 * 3DSTATE_WM_DEPTH_STENCIL::StencilTestEnable
365 const bool stc_test_en
=
366 (ds_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
367 pipeline
->stencil_test_enable
;
369 /* 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
370 * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
371 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE)
373 const bool stc_write_en
=
374 (ds_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
375 (cmd_buffer
->state
.gfx
.dynamic
.stencil_write_mask
.front
||
376 cmd_buffer
->state
.gfx
.dynamic
.stencil_write_mask
.back
) &&
377 pipeline
->writes_stencil
;
379 /* STC_TEST_EN && 3DSTATE_PS_EXTRA::PixelShaderComputesStencil */
380 const bool comp_stc_en
= stc_test_en
&& wm_prog_data
->computed_stencil
;
382 /* COMP_STC_EN || STC_WRITE_EN */
383 if (!(comp_stc_en
|| stc_write_en
))
386 /* (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
387 * 3DSTATE_WM::ForceKillPix == ON ||
388 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
389 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
390 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
391 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) ||
392 * (3DSTATE_PS_EXTRA::Pixel Shader Computed Depth mode != PSCDEPTH_OFF)
394 return pipeline
->kill_pixel
||
395 wm_prog_data
->computed_depth_mode
!= PSCDEPTH_OFF
;
399 genX(cmd_buffer_flush_dynamic_state
)(struct anv_cmd_buffer
*cmd_buffer
)
401 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
402 struct anv_dynamic_state
*d
= &cmd_buffer
->state
.gfx
.dynamic
;
404 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
405 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)) {
406 uint32_t sf_dw
[GENX(3DSTATE_SF_length
)];
407 struct GENX(3DSTATE_SF
) sf
= {
408 GENX(3DSTATE_SF_header
),
411 if (cmd_buffer
->device
->info
.is_cherryview
) {
412 sf
.CHVLineWidth
= d
->line_width
;
414 sf
.LineWidth
= d
->line_width
;
417 sf
.LineWidth
= d
->line_width
,
419 GENX(3DSTATE_SF_pack
)(NULL
, sf_dw
, &sf
);
420 anv_batch_emit_merge(&cmd_buffer
->batch
, sf_dw
, pipeline
->gen8
.sf
);
423 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
424 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)){
425 uint32_t raster_dw
[GENX(3DSTATE_RASTER_length
)];
426 struct GENX(3DSTATE_RASTER
) raster
= {
427 GENX(3DSTATE_RASTER_header
),
428 .GlobalDepthOffsetConstant
= d
->depth_bias
.bias
,
429 .GlobalDepthOffsetScale
= d
->depth_bias
.slope
,
430 .GlobalDepthOffsetClamp
= d
->depth_bias
.clamp
432 GENX(3DSTATE_RASTER_pack
)(NULL
, raster_dw
, &raster
);
433 anv_batch_emit_merge(&cmd_buffer
->batch
, raster_dw
,
434 pipeline
->gen8
.raster
);
437 /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
438 * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
439 * across different state packets for gen8 and gen9. We handle that by
440 * using a big old #if switch here.
443 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
|
444 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
)) {
445 struct anv_state cc_state
=
446 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
447 GENX(COLOR_CALC_STATE_length
) * 4,
449 struct GENX(COLOR_CALC_STATE
) cc
= {
450 .BlendConstantColorRed
= d
->blend_constants
[0],
451 .BlendConstantColorGreen
= d
->blend_constants
[1],
452 .BlendConstantColorBlue
= d
->blend_constants
[2],
453 .BlendConstantColorAlpha
= d
->blend_constants
[3],
454 .StencilReferenceValue
= d
->stencil_reference
.front
& 0xff,
455 .BackfaceStencilReferenceValue
= d
->stencil_reference
.back
& 0xff,
457 GENX(COLOR_CALC_STATE_pack
)(NULL
, cc_state
.map
, &cc
);
459 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ccp
) {
460 ccp
.ColorCalcStatePointer
= cc_state
.offset
;
461 ccp
.ColorCalcStatePointerValid
= true;
465 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
466 ANV_CMD_DIRTY_RENDER_TARGETS
|
467 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
|
468 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
)) {
469 uint32_t wm_depth_stencil_dw
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
471 struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil
) = {
472 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
474 .StencilTestMask
= d
->stencil_compare_mask
.front
& 0xff,
475 .StencilWriteMask
= d
->stencil_write_mask
.front
& 0xff,
477 .BackfaceStencilTestMask
= d
->stencil_compare_mask
.back
& 0xff,
478 .BackfaceStencilWriteMask
= d
->stencil_write_mask
.back
& 0xff,
480 .StencilBufferWriteEnable
=
481 (d
->stencil_write_mask
.front
|| d
->stencil_write_mask
.back
) &&
482 pipeline
->writes_stencil
,
484 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, wm_depth_stencil_dw
,
487 anv_batch_emit_merge(&cmd_buffer
->batch
, wm_depth_stencil_dw
,
488 pipeline
->gen8
.wm_depth_stencil
);
490 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
,
491 want_depth_pma_fix(cmd_buffer
));
494 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
) {
495 struct anv_state cc_state
=
496 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
497 GENX(COLOR_CALC_STATE_length
) * 4,
499 struct GENX(COLOR_CALC_STATE
) cc
= {
500 .BlendConstantColorRed
= d
->blend_constants
[0],
501 .BlendConstantColorGreen
= d
->blend_constants
[1],
502 .BlendConstantColorBlue
= d
->blend_constants
[2],
503 .BlendConstantColorAlpha
= d
->blend_constants
[3],
505 GENX(COLOR_CALC_STATE_pack
)(NULL
, cc_state
.map
, &cc
);
507 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ccp
) {
508 ccp
.ColorCalcStatePointer
= cc_state
.offset
;
509 ccp
.ColorCalcStatePointerValid
= true;
513 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
514 ANV_CMD_DIRTY_RENDER_TARGETS
|
515 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
|
516 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
517 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
)) {
518 uint32_t dwords
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
519 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) wm_depth_stencil
= {
520 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
522 .StencilTestMask
= d
->stencil_compare_mask
.front
& 0xff,
523 .StencilWriteMask
= d
->stencil_write_mask
.front
& 0xff,
525 .BackfaceStencilTestMask
= d
->stencil_compare_mask
.back
& 0xff,
526 .BackfaceStencilWriteMask
= d
->stencil_write_mask
.back
& 0xff,
528 .StencilReferenceValue
= d
->stencil_reference
.front
& 0xff,
529 .BackfaceStencilReferenceValue
= d
->stencil_reference
.back
& 0xff,
531 .StencilBufferWriteEnable
=
532 (d
->stencil_write_mask
.front
|| d
->stencil_write_mask
.back
) &&
533 pipeline
->writes_stencil
,
535 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, dwords
, &wm_depth_stencil
);
537 anv_batch_emit_merge(&cmd_buffer
->batch
, dwords
,
538 pipeline
->gen9
.wm_depth_stencil
);
540 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
,
541 want_stencil_pma_fix(cmd_buffer
));
545 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
546 ANV_CMD_DIRTY_INDEX_BUFFER
)) {
547 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_VF
), vf
) {
548 vf
.IndexedDrawCutIndexEnable
= pipeline
->primitive_restart
;
549 vf
.CutIndex
= cmd_buffer
->state
.restart_index
;
553 cmd_buffer
->state
.gfx
.dirty
= 0;
556 void genX(CmdBindIndexBuffer
)(
557 VkCommandBuffer commandBuffer
,
560 VkIndexType indexType
)
562 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
563 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
565 static const uint32_t vk_to_gen_index_type
[] = {
566 [VK_INDEX_TYPE_UINT16
] = INDEX_WORD
,
567 [VK_INDEX_TYPE_UINT32
] = INDEX_DWORD
,
570 static const uint32_t restart_index_for_type
[] = {
571 [VK_INDEX_TYPE_UINT16
] = UINT16_MAX
,
572 [VK_INDEX_TYPE_UINT32
] = UINT32_MAX
,
575 cmd_buffer
->state
.restart_index
= restart_index_for_type
[indexType
];
577 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
578 ib
.IndexFormat
= vk_to_gen_index_type
[indexType
];
579 ib
.MOCS
= anv_mocs_for_bo(cmd_buffer
->device
,
581 ib
.BufferStartingAddress
= anv_address_add(buffer
->address
, offset
);
582 ib
.BufferSize
= buffer
->size
- offset
;
585 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_INDEX_BUFFER
;