src/intel/vulkan/gen8_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #if GEN_GEN == 8
  36 static void
  37 emit_viewport_state(struct anv_cmd_buffer *cmd_buffer,
  38                     uint32_t count, const VkViewport *viewports)
  39 {
  40    struct anv_state sf_clip_state =
  41       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 64, 64);
  42    struct anv_state cc_state =
  43       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
  44
  45    for (uint32_t i = 0; i < count; i++) {
  46       const VkViewport *vp = &viewports[i];
  47
  48       /* The gen7 state struct has just the matrix and guardband fields, the
  49        * gen8 struct adds the min/max viewport fields. */
  50       struct GENX(SF_CLIP_VIEWPORT) sf_clip_viewport = {
  51          .ViewportMatrixElementm00 = vp->width / 2,
  52          .ViewportMatrixElementm11 = vp->height / 2,
  53          .ViewportMatrixElementm22 = 1.0,
  54          .ViewportMatrixElementm30 = vp->x + vp->width / 2,
  55          .ViewportMatrixElementm31 = vp->y + vp->height / 2,
  56          .ViewportMatrixElementm32 = 0.0,
  57          .XMinClipGuardband = -1.0f,
  58          .XMaxClipGuardband = 1.0f,
  59          .YMinClipGuardband = -1.0f,
  60          .YMaxClipGuardband = 1.0f,
  61          .XMinViewPort = vp->x,
  62          .XMaxViewPort = vp->x + vp->width - 1,
  63          .YMinViewPort = vp->y,
  64          .YMaxViewPort = vp->y + vp->height - 1,
  65       };
  66
  67       struct GENX(CC_VIEWPORT) cc_viewport = {
  68          .MinimumDepth = vp->minDepth,
  69          .MaximumDepth = vp->maxDepth
  70       };
  71
  72       GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64,
  73                                  &sf_clip_viewport);
  74       GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport);
  75    }
  76
  77    if (!cmd_buffer->device->info.has_llc) {
  78       anv_state_clflush(sf_clip_state);
  79       anv_state_clflush(cc_state);
  80    }
  81
  82    anv_batch_emit(&cmd_buffer->batch,
  83                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC),
  84                   .CCViewportPointer = cc_state.offset);
  85    anv_batch_emit(&cmd_buffer->batch,
  86                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP),
  87                   .SFClipViewportPointer = sf_clip_state.offset);
  88 }
  89
  90 void
  91 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer)
  92 {
  93    if (cmd_buffer->state.dynamic.viewport.count > 0) {
  94       emit_viewport_state(cmd_buffer, cmd_buffer->state.dynamic.viewport.count,
  95                           cmd_buffer->state.dynamic.viewport.viewports);
  96    } else {
  97       /* If viewport count is 0, this is taken to mean "use the default" */
  98       emit_viewport_state(cmd_buffer, 1,
  99                           &(VkViewport) {
 100                              .x = 0.0f,
 101                              .y = 0.0f,
 102                              .width = cmd_buffer->state.framebuffer->width,
 103                              .height = cmd_buffer->state.framebuffer->height,
 104                              .minDepth = 0.0f,
 105                              .maxDepth = 1.0f,
 106                           });
 107    }
 108 }
 109 #endif
 110
 111 #define emit_lri(batch, reg, imm)                       \
 112    anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM),    \
 113                   .RegisterOffset = __anv_reg_num(reg), \
 114                   .DataDWord = imm)
 115
 116 void
 117 genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, bool enable_slm)
 118 {
 119    /* References for GL state:
 120     *
 121     * - commits e307cfa..228d5a3
 122     * - src/mesa/drivers/dri/i965/gen7_l3_state.c
 123     */
 124
 125    uint32_t l3cr_slm, l3cr_noslm;
 126    anv_pack_struct(&l3cr_noslm, GENX(L3CNTLREG),
 127                    .URBAllocation = 48,
 128                    .AllAllocation = 48);
 129    anv_pack_struct(&l3cr_slm, GENX(L3CNTLREG),
 130                    .SLMEnable = 1,
 131                    .URBAllocation = 16,
 132                    .AllAllocation = 48);
 133    const uint32_t l3cr_val = enable_slm ? l3cr_slm : l3cr_noslm;
 134    bool changed = cmd_buffer->state.current_l3_config != l3cr_val;
 135
 136    if (changed) {
 137       /* According to the hardware docs, the L3 partitioning can only be changed
 138        * while the pipeline is completely drained and the caches are flushed,
 139        * which involves a first PIPE_CONTROL flush which stalls the pipeline and
 140        * initiates invalidation of the relevant caches...
 141        */
 142       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
 143                      .TextureCacheInvalidationEnable = true,
 144                      .ConstantCacheInvalidationEnable = true,
 145                      .InstructionCacheInvalidateEnable = true,
 146                      .DCFlushEnable = true,
 147                      .PostSyncOperation = NoWrite,
 148                      .CommandStreamerStallEnable = true);
 149
 150       /* ...followed by a second stalling flush which guarantees that
 151        * invalidation is complete when the L3 configuration registers are
 152        * modified.
 153        */
 154       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
 155                      .DCFlushEnable = true,
 156                      .PostSyncOperation = NoWrite,
 157                      .CommandStreamerStallEnable = true);
 158
 159       emit_lri(&cmd_buffer->batch, GENX(L3CNTLREG), l3cr_val);
 160       cmd_buffer->state.current_l3_config = l3cr_val;
 161    }
 162 }
 163
 164 static void
 165 __emit_genx_sf_state(struct anv_cmd_buffer *cmd_buffer)
 166 {
 167       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 168       struct GENX(3DSTATE_SF) sf = {
 169          GENX(3DSTATE_SF_header),
 170          .LineWidth = cmd_buffer->state.dynamic.line_width,
 171       };
 172       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 173       /* FIXME: gen9.fs */
 174       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw,
 175                            cmd_buffer->state.pipeline->gen8.sf);
 176 }
 177
 178 #include "genxml/gen9_pack.h"
 179 static void
 180 __emit_gen9_sf_state(struct anv_cmd_buffer *cmd_buffer)
 181 {
 182       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 183       struct GEN9_3DSTATE_SF sf = {
 184          GEN9_3DSTATE_SF_header,
 185          .LineWidth = cmd_buffer->state.dynamic.line_width,
 186       };
 187       GEN9_3DSTATE_SF_pack(NULL, sf_dw, &sf);
 188       /* FIXME: gen9.fs */
 189       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw,
 190                            cmd_buffer->state.pipeline->gen8.sf);
 191 }
 192
 193 static void
 194 __emit_sf_state(struct anv_cmd_buffer *cmd_buffer)
 195 {
 196    if (cmd_buffer->device->info.is_cherryview)
 197       __emit_gen9_sf_state(cmd_buffer);
 198    else
 199       __emit_genx_sf_state(cmd_buffer);
 200 }
 201
 202 void
 203 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 204 {
 205    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 206
 207    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 208                                   ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
 209       __emit_sf_state(cmd_buffer);
 210    }
 211
 212    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 213                                   ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)){
 214       uint32_t raster_dw[GENX(3DSTATE_RASTER_length)];
 215       struct GENX(3DSTATE_RASTER) raster = {
 216          GENX(3DSTATE_RASTER_header),
 217          .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
 218          .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
 219          .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
 220       };
 221       GENX(3DSTATE_RASTER_pack)(NULL, raster_dw, &raster);
 222       anv_batch_emit_merge(&cmd_buffer->batch, raster_dw,
 223                            pipeline->gen8.raster);
 224    }
 225
 226    /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
 227     * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
 228     * across different state packets for gen8 and gen9. We handle that by
 229     * using a big old #if switch here.
 230     */
 231 #if GEN_GEN == 8
 232    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 233                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 234       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 235       struct anv_state cc_state =
 236          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 237                                             GENX(COLOR_CALC_STATE_length) * 4,
 238                                             64);
 239       struct GENX(COLOR_CALC_STATE) cc = {
 240          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 241          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 242          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 243          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 244          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 245          .BackFaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 246       };
 247       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 248
 249       if (!cmd_buffer->device->info.has_llc)
 250          anv_state_clflush(cc_state);
 251
 252       anv_batch_emit(&cmd_buffer->batch,
 253                      GENX(3DSTATE_CC_STATE_POINTERS),
 254                      .ColorCalcStatePointer = cc_state.offset,
 255                      .ColorCalcStatePointerValid = true);
 256    }
 257
 258    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 259                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 260                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 261       uint32_t wm_depth_stencil_dw[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
 262       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 263
 264       struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
 265          GENX(3DSTATE_WM_DEPTH_STENCIL_header),
 266
 267          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 268          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 269
 270          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 271          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 272       };
 273       GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, wm_depth_stencil_dw,
 274                                           &wm_depth_stencil);
 275
 276       anv_batch_emit_merge(&cmd_buffer->batch, wm_depth_stencil_dw,
 277                            pipeline->gen8.wm_depth_stencil);
 278    }
 279 #else
 280    if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
 281       struct anv_state cc_state =
 282          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 283                                             GEN9_COLOR_CALC_STATE_length * 4,
 284                                             64);
 285       struct GEN9_COLOR_CALC_STATE cc = {
 286          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 287          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 288          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 289          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 290       };
 291       GEN9_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
 292
 293       if (!cmd_buffer->device->info.has_llc)
 294          anv_state_clflush(cc_state);
 295
 296       anv_batch_emit(&cmd_buffer->batch,
 297                      GEN9_3DSTATE_CC_STATE_POINTERS,
 298                      .ColorCalcStatePointer = cc_state.offset,
 299                      .ColorCalcStatePointerValid = true);
 300    }
 301
 302    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 303                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 304                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
 305                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 306       uint32_t dwords[GEN9_3DSTATE_WM_DEPTH_STENCIL_length];
 307       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 308       struct GEN9_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil = {
 309          GEN9_3DSTATE_WM_DEPTH_STENCIL_header,
 310
 311          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 312          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 313
 314          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 315          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 316
 317          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 318          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 319       };
 320       GEN9_3DSTATE_WM_DEPTH_STENCIL_pack(NULL, dwords, &wm_depth_stencil);
 321
 322       anv_batch_emit_merge(&cmd_buffer->batch, dwords,
 323                            pipeline->gen9.wm_depth_stencil);
 324    }
 325 #endif
 326
 327    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 328                                   ANV_CMD_DIRTY_INDEX_BUFFER)) {
 329       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF),
 330          .IndexedDrawCutIndexEnable = pipeline->primitive_restart,
 331          .CutIndex = cmd_buffer->state.restart_index,
 332       );
 333    }
 334
 335    cmd_buffer->state.dirty = 0;
 336 }
 337
 338 void genX(CmdBindIndexBuffer)(
 339     VkCommandBuffer                             commandBuffer,
 340     VkBuffer                                    _buffer,
 341     VkDeviceSize                                offset,
 342     VkIndexType                                 indexType)
 343 {
 344    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 345    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 346
 347    static const uint32_t vk_to_gen_index_type[] = {
 348       [VK_INDEX_TYPE_UINT16]                    = INDEX_WORD,
 349       [VK_INDEX_TYPE_UINT32]                    = INDEX_DWORD,
 350    };
 351
 352    static const uint32_t restart_index_for_type[] = {
 353       [VK_INDEX_TYPE_UINT16]                    = UINT16_MAX,
 354       [VK_INDEX_TYPE_UINT32]                    = UINT32_MAX,
 355    };
 356
 357    cmd_buffer->state.restart_index = restart_index_for_type[indexType];
 358
 359    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER),
 360                   .IndexFormat = vk_to_gen_index_type[indexType],
 361                   .MemoryObjectControlState = GENX(MOCS),
 362                   .BufferStartingAddress = { buffer->bo, buffer->offset + offset },
 363                   .BufferSize = buffer->size - offset);
 364
 365    cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 366 }
 367
 368 static VkResult
 369 flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
 370 {
 371    struct anv_device *device = cmd_buffer->device;
 372    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 373    struct anv_state surfaces = { 0, }, samplers = { 0, };
 374    VkResult result;
 375
 376    result = anv_cmd_buffer_emit_samplers(cmd_buffer,
 377                                          MESA_SHADER_COMPUTE, &samplers);
 378    if (result != VK_SUCCESS)
 379       return result;
 380    result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
 381                                               MESA_SHADER_COMPUTE, &surfaces);
 382    if (result != VK_SUCCESS)
 383       return result;
 384
 385    struct anv_state push_state = anv_cmd_buffer_cs_push_constants(cmd_buffer);
 386
 387    const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
 388    const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
 389
 390    unsigned local_id_dwords = cs_prog_data->local_invocation_id_regs * 8;
 391    unsigned push_constant_data_size =
 392       (prog_data->nr_params + local_id_dwords) * 4;
 393    unsigned reg_aligned_constant_size = ALIGN(push_constant_data_size, 32);
 394    unsigned push_constant_regs = reg_aligned_constant_size / 32;
 395
 396    if (push_state.alloc_size) {
 397       anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD),
 398                      .CURBETotalDataLength = push_state.alloc_size,
 399                      .CURBEDataStartAddress = push_state.offset);
 400    }
 401
 402    assert(prog_data->total_shared <= 64 * 1024);
 403    uint32_t slm_size = 0;
 404    if (prog_data->total_shared > 0) {
 405       /* slm_size is in 4k increments, but must be a power of 2. */
 406       slm_size = 4 * 1024;
 407       while (slm_size < prog_data->total_shared)
 408          slm_size <<= 1;
 409       slm_size /= 4 * 1024;
 410    }
 411
 412    struct anv_state state =
 413       anv_state_pool_emit(&device->dynamic_state_pool,
 414                           GENX(INTERFACE_DESCRIPTOR_DATA), 64,
 415                           .KernelStartPointer = pipeline->cs_simd,
 416                           .KernelStartPointerHigh = 0,
 417                           .BindingTablePointer = surfaces.offset,
 418                           .BindingTableEntryCount = 0,
 419                           .SamplerStatePointer = samplers.offset,
 420                           .SamplerCount = 0,
 421                           .ConstantIndirectURBEntryReadLength = push_constant_regs,
 422                           .ConstantURBEntryReadOffset = 0,
 423                           .BarrierEnable = cs_prog_data->uses_barrier,
 424                           .SharedLocalMemorySize = slm_size,
 425                           .NumberofThreadsinGPGPUThreadGroup =
 426                              pipeline->cs_thread_width_max);
 427
 428    uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
 429    anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD),
 430                   .InterfaceDescriptorTotalLength = size,
 431                   .InterfaceDescriptorDataStartAddress = state.offset);
 432
 433    return VK_SUCCESS;
 434 }
 435
 436 void
 437 genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
 438 {
 439    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 440    const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
 441    VkResult result;
 442
 443    assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
 444
 445    bool needs_slm = cs_prog_data->base.total_shared > 0;
 446    genX(cmd_buffer_config_l3)(cmd_buffer, needs_slm);
 447
 448    genX(flush_pipeline_select_gpgpu)(cmd_buffer);
 449
 450    if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
 451       anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
 452
 453    if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
 454        (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
 455       result = flush_compute_descriptor_set(cmd_buffer);
 456       assert(result == VK_SUCCESS);
 457       cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
 458    }
 459
 460    cmd_buffer->state.compute_dirty = 0;
 461 }
 462
 463 void genX(CmdSetEvent)(
 464     VkCommandBuffer                             commandBuffer,
 465     VkEvent                                     _event,
 466     VkPipelineStageFlags                        stageMask)
 467 {
 468    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 469    ANV_FROM_HANDLE(anv_event, event, _event);
 470
 471    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
 472                   .DestinationAddressType = DAT_PPGTT,
 473                   .PostSyncOperation = WriteImmediateData,
 474                   .Address = {
 475                      &cmd_buffer->device->dynamic_state_block_pool.bo,
 476                      event->state.offset
 477                    },
 478                   .ImmediateData = VK_EVENT_SET);
 479 }
 480
 481 void genX(CmdResetEvent)(
 482     VkCommandBuffer                             commandBuffer,
 483     VkEvent                                     _event,
 484     VkPipelineStageFlags                        stageMask)
 485 {
 486    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 487    ANV_FROM_HANDLE(anv_event, event, _event);
 488
 489    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
 490                   .DestinationAddressType = DAT_PPGTT,
 491                   .PostSyncOperation = WriteImmediateData,
 492                   .Address = {
 493                      &cmd_buffer->device->dynamic_state_block_pool.bo,
 494                      event->state.offset
 495                    },
 496                   .ImmediateData = VK_EVENT_RESET);
 497 }
 498
 499 void genX(CmdWaitEvents)(
 500     VkCommandBuffer                             commandBuffer,
 501     uint32_t                                    eventCount,
 502     const VkEvent*                              pEvents,
 503     VkPipelineStageFlags                        srcStageMask,
 504     VkPipelineStageFlags                        destStageMask,
 505     uint32_t                                    memoryBarrierCount,
 506     const VkMemoryBarrier*                      pMemoryBarriers,
 507     uint32_t                                    bufferMemoryBarrierCount,
 508     const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
 509     uint32_t                                    imageMemoryBarrierCount,
 510     const VkImageMemoryBarrier*                 pImageMemoryBarriers)
 511 {
 512    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 513    for (uint32_t i = 0; i < eventCount; i++) {
 514       ANV_FROM_HANDLE(anv_event, event, pEvents[i]);
 515
 516       anv_batch_emit(&cmd_buffer->batch, GENX(MI_SEMAPHORE_WAIT),
 517                      .WaitMode = PollingMode,
 518                      .CompareOperation = COMPARE_SAD_EQUAL_SDD,
 519                      .SemaphoreDataDword = VK_EVENT_SET,
 520                      .SemaphoreAddress = {
 521                         &cmd_buffer->device->dynamic_state_block_pool.bo,
 522                         event->state.offset
 523                      });
 524    }
 525
 526    genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
 527                             false, /* byRegion */
 528                             memoryBarrierCount, pMemoryBarriers,
 529                             bufferMemoryBarrierCount, pBufferMemoryBarriers,
 530                             imageMemoryBarrierCount, pImageMemoryBarriers);
 531 }