2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
37 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
)
39 uint32_t count
= cmd_buffer
->state
.dynamic
.viewport
.count
;
40 const VkViewport
*viewports
= cmd_buffer
->state
.dynamic
.viewport
.viewports
;
41 struct anv_state sf_clip_state
=
42 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, count
* 64, 64);
44 for (uint32_t i
= 0; i
< count
; i
++) {
45 const VkViewport
*vp
= &viewports
[i
];
47 /* The gen7 state struct has just the matrix and guardband fields, the
48 * gen8 struct adds the min/max viewport fields. */
49 struct GENX(SF_CLIP_VIEWPORT
) sf_clip_viewport
= {
50 .ViewportMatrixElementm00
= vp
->width
/ 2,
51 .ViewportMatrixElementm11
= vp
->height
/ 2,
52 .ViewportMatrixElementm22
= vp
->maxDepth
- vp
->minDepth
,
53 .ViewportMatrixElementm30
= vp
->x
+ vp
->width
/ 2,
54 .ViewportMatrixElementm31
= vp
->y
+ vp
->height
/ 2,
55 .ViewportMatrixElementm32
= vp
->minDepth
,
56 .XMinClipGuardband
= -1.0f
,
57 .XMaxClipGuardband
= 1.0f
,
58 .YMinClipGuardband
= -1.0f
,
59 .YMaxClipGuardband
= 1.0f
,
60 .XMinViewPort
= vp
->x
,
61 .XMaxViewPort
= vp
->x
+ vp
->width
- 1,
62 .YMinViewPort
= MIN2(vp
->y
, vp
->y
+ vp
->height
),
63 .YMaxViewPort
= MAX2(vp
->y
, vp
->y
+ vp
->height
) - 1,
66 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_state
.map
+ i
* 64,
70 anv_state_flush(cmd_buffer
->device
, sf_clip_state
);
72 anv_batch_emit(&cmd_buffer
->batch
,
73 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), clip
) {
74 clip
.SFClipViewportPointer
= sf_clip_state
.offset
;
79 gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
80 bool depth_clamp_enable
)
82 uint32_t count
= cmd_buffer
->state
.dynamic
.viewport
.count
;
83 const VkViewport
*viewports
= cmd_buffer
->state
.dynamic
.viewport
.viewports
;
84 struct anv_state cc_state
=
85 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, count
* 8, 32);
87 for (uint32_t i
= 0; i
< count
; i
++) {
88 const VkViewport
*vp
= &viewports
[i
];
90 struct GENX(CC_VIEWPORT
) cc_viewport
= {
91 .MinimumDepth
= depth_clamp_enable
? vp
->minDepth
: 0.0f
,
92 .MaximumDepth
= depth_clamp_enable
? vp
->maxDepth
: 1.0f
,
95 GENX(CC_VIEWPORT_pack
)(NULL
, cc_state
.map
+ i
* 8, &cc_viewport
);
98 anv_state_flush(cmd_buffer
->device
, cc_state
);
100 anv_batch_emit(&cmd_buffer
->batch
,
101 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), cc
) {
102 cc
.CCViewportPointer
= cc_state
.offset
;
108 genX(cmd_buffer_enable_pma_fix
)(struct anv_cmd_buffer
*cmd_buffer
, bool enable
)
110 if (cmd_buffer
->state
.pma_fix_enabled
== enable
)
113 cmd_buffer
->state
.pma_fix_enabled
= enable
;
115 /* According to the Broadwell PIPE_CONTROL documentation, software should
116 * emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set
117 * prior to the LRI. If stencil buffer writes are enabled, then a Render
118 * Cache Flush is also necessary.
120 * The Skylake docs say to use a depth stall rather than a command
121 * streamer stall. However, the hardware seems to violently disagree.
122 * A full command streamer stall seems to be needed in both cases.
124 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
125 pc
.DepthCacheFlushEnable
= true;
126 pc
.CommandStreamerStallEnable
= true;
127 pc
.RenderTargetCacheFlushEnable
= true;
133 anv_pack_struct(&cache_mode
, GENX(CACHE_MODE_0
),
134 .STCPMAOptimizationEnable
= enable
,
135 .STCPMAOptimizationEnableMask
= true);
136 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
137 lri
.RegisterOffset
= GENX(CACHE_MODE_0_num
);
138 lri
.DataDWord
= cache_mode
;
144 anv_pack_struct(&cache_mode
, GENX(CACHE_MODE_1
),
145 .NPPMAFixEnable
= enable
,
146 .NPEarlyZFailsDisable
= enable
,
147 .NPPMAFixEnableMask
= true,
148 .NPEarlyZFailsDisableMask
= true);
149 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
150 lri
.RegisterOffset
= GENX(CACHE_MODE_1_num
);
151 lri
.DataDWord
= cache_mode
;
154 #endif /* GEN_GEN == 8 */
156 /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
157 * Flush bits is often necessary. We do it regardless because it's easier.
158 * The render cache flush is also necessary if stencil writes are enabled.
160 * Again, the Skylake docs give a different set of flushes but the BDW
161 * flushes seem to work just as well.
163 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
164 pc
.DepthStallEnable
= true;
165 pc
.DepthCacheFlushEnable
= true;
166 pc
.RenderTargetCacheFlushEnable
= true;
171 want_depth_pma_fix(struct anv_cmd_buffer
*cmd_buffer
)
173 assert(GEN_GEN
== 8);
175 /* From the Broadwell PRM Vol. 2c CACHE_MODE_1::NP_PMA_FIX_ENABLE:
177 * SW must set this bit in order to enable this fix when following
178 * expression is TRUE.
180 * 3DSTATE_WM::ForceThreadDispatch != 1 &&
181 * !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) &&
182 * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
183 * (3DSTATE_DEPTH_BUFFER::HIZ Enable) &&
184 * !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) &&
185 * (3DSTATE_PS_EXTRA::PixelShaderValid) &&
186 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
187 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
188 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
189 * 3DSTATE_WM_HZ_OP::StencilBufferClear) &&
190 * (3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable) &&
191 * (((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
192 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
193 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
194 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
195 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) &&
196 * 3DSTATE_WM::ForceKillPix != ForceOff &&
197 * ((3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
198 * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE) ||
199 * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
200 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
201 * 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE))) ||
202 * (3DSTATE_PS_EXTRA:: Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
205 /* These are always true:
206 * 3DSTATE_WM::ForceThreadDispatch != 1 &&
207 * !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0)
210 /* We only enable the PMA fix if we know for certain that HiZ is enabled.
211 * If we don't know whether HiZ is enabled or not, we disable the PMA fix
212 * and there is no harm.
214 * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
215 * 3DSTATE_DEPTH_BUFFER::HIZ Enable
217 if (!cmd_buffer
->state
.hiz_enabled
)
220 /* 3DSTATE_PS_EXTRA::PixelShaderValid */
221 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
222 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
))
225 /* !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) */
226 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
227 if (wm_prog_data
->early_fragment_tests
)
230 /* We never use anv_pipeline for HiZ ops so this is trivially true:
231 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
232 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
233 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
234 * 3DSTATE_WM_HZ_OP::StencilBufferClear)
237 /* 3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable */
238 if (!pipeline
->depth_test_enable
)
241 /* (((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
242 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
243 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
244 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
245 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) &&
246 * 3DSTATE_WM::ForceKillPix != ForceOff &&
247 * ((3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
248 * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE) ||
249 * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
250 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
251 * 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE))) ||
252 * (3DSTATE_PS_EXTRA:: Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
254 return (pipeline
->kill_pixel
&& (pipeline
->writes_depth
||
255 pipeline
->writes_stencil
)) ||
256 wm_prog_data
->computed_depth_mode
!= PSCDEPTH_OFF
;
260 want_stencil_pma_fix(struct anv_cmd_buffer
*cmd_buffer
)
264 assert(GEN_GEN
== 9);
266 /* From the Skylake PRM Vol. 2c CACHE_MODE_1::STC PMA Optimization Enable:
268 * Clearing this bit will force the STC cache to wait for pending
269 * retirement of pixels at the HZ-read stage and do the STC-test for
270 * Non-promoted, R-computed and Computed depth modes instead of
271 * postponing the STC-test to RCPFE.
273 * STC_TEST_EN = 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
274 * 3DSTATE_WM_DEPTH_STENCIL::StencilTestEnable
276 * STC_WRITE_EN = 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
277 * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
278 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE)
280 * COMP_STC_EN = STC_TEST_EN &&
281 * 3DSTATE_PS_EXTRA::PixelShaderComputesStencil
283 * SW parses the pipeline states to generate the following logical
284 * signal indicating if PMA FIX can be enabled.
287 * 3DSTATE_WM::ForceThreadDispatch != 1 &&
288 * !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) &&
289 * 3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
290 * 3DSTATE_DEPTH_BUFFER::HIZ Enable &&
291 * !(3DSTATE_WM::EDSC_Mode == 2) &&
292 * 3DSTATE_PS_EXTRA::PixelShaderValid &&
293 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
294 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
295 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
296 * 3DSTATE_WM_HZ_OP::StencilBufferClear) &&
297 * (COMP_STC_EN || STC_WRITE_EN) &&
298 * ((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
299 * 3DSTATE_WM::ForceKillPix == ON ||
300 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
301 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
302 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
303 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) ||
304 * (3DSTATE_PS_EXTRA::Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
307 /* These are always true:
308 * 3DSTATE_WM::ForceThreadDispatch != 1 &&
309 * !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0)
312 /* We only enable the PMA fix if we know for certain that HiZ is enabled.
313 * If we don't know whether HiZ is enabled or not, we disable the PMA fix
314 * and there is no harm.
316 * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
317 * 3DSTATE_DEPTH_BUFFER::HIZ Enable
319 if (!cmd_buffer
->state
.hiz_enabled
)
322 /* We can't possibly know if HiZ is enabled without the framebuffer */
323 assert(cmd_buffer
->state
.framebuffer
);
325 /* HiZ is enabled so we had better have a depth buffer with HiZ */
326 const struct anv_image_view
*ds_iview
=
327 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
328 assert(ds_iview
&& ds_iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
330 /* 3DSTATE_PS_EXTRA::PixelShaderValid */
331 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
332 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
))
335 /* !(3DSTATE_WM::EDSC_Mode == 2) */
336 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
337 if (wm_prog_data
->early_fragment_tests
)
340 /* We never use anv_pipeline for HiZ ops so this is trivially true:
341 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
342 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
343 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
344 * 3DSTATE_WM_HZ_OP::StencilBufferClear)
347 /* 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
348 * 3DSTATE_WM_DEPTH_STENCIL::StencilTestEnable
350 const bool stc_test_en
=
351 (ds_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
352 pipeline
->stencil_test_enable
;
354 /* 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
355 * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
356 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE)
358 const bool stc_write_en
=
359 (ds_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
360 pipeline
->writes_stencil
;
362 /* STC_TEST_EN && 3DSTATE_PS_EXTRA::PixelShaderComputesStencil */
363 const bool comp_stc_en
= stc_test_en
&& wm_prog_data
->computed_stencil
;
365 /* COMP_STC_EN || STC_WRITE_EN */
366 if (!(comp_stc_en
|| stc_write_en
))
369 /* (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
370 * 3DSTATE_WM::ForceKillPix == ON ||
371 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
372 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
373 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
374 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) ||
375 * (3DSTATE_PS_EXTRA::Pixel Shader Computed Depth mode != PSCDEPTH_OFF)
377 return pipeline
->kill_pixel
||
378 wm_prog_data
->computed_depth_mode
!= PSCDEPTH_OFF
;
382 genX(cmd_buffer_flush_dynamic_state
)(struct anv_cmd_buffer
*cmd_buffer
)
384 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
386 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
387 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)) {
388 uint32_t sf_dw
[GENX(3DSTATE_SF_length
)];
389 struct GENX(3DSTATE_SF
) sf
= {
390 GENX(3DSTATE_SF_header
),
393 if (cmd_buffer
->device
->info
.is_cherryview
) {
394 sf
.CHVLineWidth
= cmd_buffer
->state
.dynamic
.line_width
;
396 sf
.LineWidth
= cmd_buffer
->state
.dynamic
.line_width
;
399 sf
.LineWidth
= cmd_buffer
->state
.dynamic
.line_width
,
401 GENX(3DSTATE_SF_pack
)(NULL
, sf_dw
, &sf
);
402 anv_batch_emit_merge(&cmd_buffer
->batch
, sf_dw
,
403 cmd_buffer
->state
.pipeline
->gen8
.sf
);
406 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
407 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)){
408 uint32_t raster_dw
[GENX(3DSTATE_RASTER_length
)];
409 struct GENX(3DSTATE_RASTER
) raster
= {
410 GENX(3DSTATE_RASTER_header
),
411 .GlobalDepthOffsetConstant
= cmd_buffer
->state
.dynamic
.depth_bias
.bias
,
412 .GlobalDepthOffsetScale
= cmd_buffer
->state
.dynamic
.depth_bias
.slope
,
413 .GlobalDepthOffsetClamp
= cmd_buffer
->state
.dynamic
.depth_bias
.clamp
415 GENX(3DSTATE_RASTER_pack
)(NULL
, raster_dw
, &raster
);
416 anv_batch_emit_merge(&cmd_buffer
->batch
, raster_dw
,
417 pipeline
->gen8
.raster
);
420 /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
421 * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
422 * across different state packets for gen8 and gen9. We handle that by
423 * using a big old #if switch here.
426 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
|
427 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
)) {
428 struct anv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
429 struct anv_state cc_state
=
430 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
431 GENX(COLOR_CALC_STATE_length
) * 4,
433 struct GENX(COLOR_CALC_STATE
) cc
= {
434 .BlendConstantColorRed
= cmd_buffer
->state
.dynamic
.blend_constants
[0],
435 .BlendConstantColorGreen
= cmd_buffer
->state
.dynamic
.blend_constants
[1],
436 .BlendConstantColorBlue
= cmd_buffer
->state
.dynamic
.blend_constants
[2],
437 .BlendConstantColorAlpha
= cmd_buffer
->state
.dynamic
.blend_constants
[3],
438 .StencilReferenceValue
= d
->stencil_reference
.front
& 0xff,
439 .BackfaceStencilReferenceValue
= d
->stencil_reference
.back
& 0xff,
441 GENX(COLOR_CALC_STATE_pack
)(NULL
, cc_state
.map
, &cc
);
443 anv_state_flush(cmd_buffer
->device
, cc_state
);
445 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ccp
) {
446 ccp
.ColorCalcStatePointer
= cc_state
.offset
;
447 ccp
.ColorCalcStatePointerValid
= true;
451 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
452 ANV_CMD_DIRTY_RENDER_TARGETS
|
453 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
|
454 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
)) {
455 uint32_t wm_depth_stencil_dw
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
456 struct anv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
458 struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil
) = {
459 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
461 .StencilTestMask
= d
->stencil_compare_mask
.front
& 0xff,
462 .StencilWriteMask
= d
->stencil_write_mask
.front
& 0xff,
464 .BackfaceStencilTestMask
= d
->stencil_compare_mask
.back
& 0xff,
465 .BackfaceStencilWriteMask
= d
->stencil_write_mask
.back
& 0xff,
467 .StencilBufferWriteEnable
=
468 (d
->stencil_write_mask
.front
|| d
->stencil_write_mask
.back
) &&
469 pipeline
->writes_stencil
,
471 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, wm_depth_stencil_dw
,
474 anv_batch_emit_merge(&cmd_buffer
->batch
, wm_depth_stencil_dw
,
475 pipeline
->gen8
.wm_depth_stencil
);
477 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
,
478 want_depth_pma_fix(cmd_buffer
));
481 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
) {
482 struct anv_state cc_state
=
483 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
484 GENX(COLOR_CALC_STATE_length
) * 4,
486 struct GENX(COLOR_CALC_STATE
) cc
= {
487 .BlendConstantColorRed
= cmd_buffer
->state
.dynamic
.blend_constants
[0],
488 .BlendConstantColorGreen
= cmd_buffer
->state
.dynamic
.blend_constants
[1],
489 .BlendConstantColorBlue
= cmd_buffer
->state
.dynamic
.blend_constants
[2],
490 .BlendConstantColorAlpha
= cmd_buffer
->state
.dynamic
.blend_constants
[3],
492 GENX(COLOR_CALC_STATE_pack
)(NULL
, cc_state
.map
, &cc
);
494 anv_state_flush(cmd_buffer
->device
, cc_state
);
496 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ccp
) {
497 ccp
.ColorCalcStatePointer
= cc_state
.offset
;
498 ccp
.ColorCalcStatePointerValid
= true;
502 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
503 ANV_CMD_DIRTY_RENDER_TARGETS
|
504 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
|
505 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
506 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
)) {
507 uint32_t dwords
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
508 struct anv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
509 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) wm_depth_stencil
= {
510 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
512 .StencilTestMask
= d
->stencil_compare_mask
.front
& 0xff,
513 .StencilWriteMask
= d
->stencil_write_mask
.front
& 0xff,
515 .BackfaceStencilTestMask
= d
->stencil_compare_mask
.back
& 0xff,
516 .BackfaceStencilWriteMask
= d
->stencil_write_mask
.back
& 0xff,
518 .StencilReferenceValue
= d
->stencil_reference
.front
& 0xff,
519 .BackfaceStencilReferenceValue
= d
->stencil_reference
.back
& 0xff,
521 .StencilBufferWriteEnable
=
522 (d
->stencil_write_mask
.front
|| d
->stencil_write_mask
.back
) &&
523 pipeline
->writes_stencil
,
525 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, dwords
, &wm_depth_stencil
);
527 anv_batch_emit_merge(&cmd_buffer
->batch
, dwords
,
528 pipeline
->gen9
.wm_depth_stencil
);
530 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
,
531 want_stencil_pma_fix(cmd_buffer
));
535 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
536 ANV_CMD_DIRTY_INDEX_BUFFER
)) {
537 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_VF
), vf
) {
538 vf
.IndexedDrawCutIndexEnable
= pipeline
->primitive_restart
;
539 vf
.CutIndex
= cmd_buffer
->state
.restart_index
;
543 cmd_buffer
->state
.dirty
= 0;
546 void genX(CmdBindIndexBuffer
)(
547 VkCommandBuffer commandBuffer
,
550 VkIndexType indexType
)
552 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
553 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
555 static const uint32_t vk_to_gen_index_type
[] = {
556 [VK_INDEX_TYPE_UINT16
] = INDEX_WORD
,
557 [VK_INDEX_TYPE_UINT32
] = INDEX_DWORD
,
560 static const uint32_t restart_index_for_type
[] = {
561 [VK_INDEX_TYPE_UINT16
] = UINT16_MAX
,
562 [VK_INDEX_TYPE_UINT32
] = UINT32_MAX
,
565 cmd_buffer
->state
.restart_index
= restart_index_for_type
[indexType
];
567 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
568 ib
.IndexFormat
= vk_to_gen_index_type
[indexType
];
569 ib
.MemoryObjectControlState
= GENX(MOCS
);
570 ib
.BufferStartingAddress
=
571 (struct anv_address
) { buffer
->bo
, buffer
->offset
+ offset
};
572 ib
.BufferSize
= buffer
->size
- offset
;
575 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_INDEX_BUFFER
;
578 /* Set of stage bits for which are pipelined, i.e. they get queued by the
579 * command streamer for later execution.
581 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
582 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
583 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
584 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
585 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
586 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
587 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
588 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
589 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
590 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
591 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
592 VK_PIPELINE_STAGE_TRANSFER_BIT | \
593 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
594 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
595 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
597 void genX(CmdSetEvent
)(
598 VkCommandBuffer commandBuffer
,
600 VkPipelineStageFlags stageMask
)
602 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
603 ANV_FROM_HANDLE(anv_event
, event
, _event
);
605 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
606 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
607 pc
.StallAtPixelScoreboard
= true;
608 pc
.CommandStreamerStallEnable
= true;
611 pc
.DestinationAddressType
= DAT_PPGTT
,
612 pc
.PostSyncOperation
= WriteImmediateData
,
613 pc
.Address
= (struct anv_address
) {
614 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
617 pc
.ImmediateData
= VK_EVENT_SET
;
621 void genX(CmdResetEvent
)(
622 VkCommandBuffer commandBuffer
,
624 VkPipelineStageFlags stageMask
)
626 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
627 ANV_FROM_HANDLE(anv_event
, event
, _event
);
629 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
630 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
631 pc
.StallAtPixelScoreboard
= true;
632 pc
.CommandStreamerStallEnable
= true;
635 pc
.DestinationAddressType
= DAT_PPGTT
;
636 pc
.PostSyncOperation
= WriteImmediateData
;
637 pc
.Address
= (struct anv_address
) {
638 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
641 pc
.ImmediateData
= VK_EVENT_RESET
;
645 void genX(CmdWaitEvents
)(
646 VkCommandBuffer commandBuffer
,
648 const VkEvent
* pEvents
,
649 VkPipelineStageFlags srcStageMask
,
650 VkPipelineStageFlags destStageMask
,
651 uint32_t memoryBarrierCount
,
652 const VkMemoryBarrier
* pMemoryBarriers
,
653 uint32_t bufferMemoryBarrierCount
,
654 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
655 uint32_t imageMemoryBarrierCount
,
656 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
658 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
659 for (uint32_t i
= 0; i
< eventCount
; i
++) {
660 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
662 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
663 sem
.WaitMode
= PollingMode
,
664 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
665 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
666 sem
.SemaphoreAddress
= (struct anv_address
) {
667 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
673 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
674 false, /* byRegion */
675 memoryBarrierCount
, pMemoryBarriers
,
676 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
677 imageMemoryBarrierCount
, pImageMemoryBarriers
);