src/intel/vulkan/gen8_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #if GEN_GEN == 8
  36 void
  37 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer)
  38 {
  39    uint32_t count = cmd_buffer->state.dynamic.viewport.count;
  40    const VkViewport *viewports = cmd_buffer->state.dynamic.viewport.viewports;
  41    struct anv_state sf_clip_state =
  42       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 64, 64);
  43
  44    for (uint32_t i = 0; i < count; i++) {
  45       const VkViewport *vp = &viewports[i];
  46
  47       /* The gen7 state struct has just the matrix and guardband fields, the
  48        * gen8 struct adds the min/max viewport fields. */
  49       struct GENX(SF_CLIP_VIEWPORT) sf_clip_viewport = {
  50          .ViewportMatrixElementm00 = vp->width / 2,
  51          .ViewportMatrixElementm11 = vp->height / 2,
  52          .ViewportMatrixElementm22 = 1.0,
  53          .ViewportMatrixElementm30 = vp->x + vp->width / 2,
  54          .ViewportMatrixElementm31 = vp->y + vp->height / 2,
  55          .ViewportMatrixElementm32 = 0.0,
  56          .XMinClipGuardband = -1.0f,
  57          .XMaxClipGuardband = 1.0f,
  58          .YMinClipGuardband = -1.0f,
  59          .YMaxClipGuardband = 1.0f,
  60          .XMinViewPort = vp->x,
  61          .XMaxViewPort = vp->x + vp->width - 1,
  62          .YMinViewPort = vp->y,
  63          .YMaxViewPort = vp->y + vp->height - 1,
  64       };
  65
  66       GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64,
  67                                  &sf_clip_viewport);
  68    }
  69
  70    if (!cmd_buffer->device->info.has_llc)
  71       anv_state_clflush(sf_clip_state);
  72
  73    anv_batch_emit(&cmd_buffer->batch,
  74                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), clip) {
  75       clip.SFClipViewportPointer = sf_clip_state.offset;
  76    }
  77 }
  78
  79 void
  80 gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
  81                                     bool depth_clamp_enable)
  82 {
  83    uint32_t count = cmd_buffer->state.dynamic.viewport.count;
  84    const VkViewport *viewports = cmd_buffer->state.dynamic.viewport.viewports;
  85    struct anv_state cc_state =
  86       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
  87
  88    for (uint32_t i = 0; i < count; i++) {
  89       const VkViewport *vp = &viewports[i];
  90
  91       struct GENX(CC_VIEWPORT) cc_viewport = {
  92          .MinimumDepth = depth_clamp_enable ? vp->minDepth : 0.0f,
  93          .MaximumDepth = depth_clamp_enable ? vp->maxDepth : 1.0f,
  94       };
  95
  96       GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport);
  97    }
  98
  99    if (!cmd_buffer->device->info.has_llc)
 100       anv_state_clflush(cc_state);
 101
 102    anv_batch_emit(&cmd_buffer->batch,
 103                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) {
 104       cc.CCViewportPointer = cc_state.offset;
 105    }
 106 }
 107 #endif
 108
 109 static void
 110 __emit_genx_sf_state(struct anv_cmd_buffer *cmd_buffer)
 111 {
 112       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 113       struct GENX(3DSTATE_SF) sf = {
 114          GENX(3DSTATE_SF_header),
 115          .LineWidth = cmd_buffer->state.dynamic.line_width,
 116       };
 117       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 118       /* FIXME: gen9.fs */
 119       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw,
 120                            cmd_buffer->state.pipeline->gen8.sf);
 121 }
 122
 123 void
 124 gen9_emit_sf_state(struct anv_cmd_buffer *cmd_buffer);
 125
 126 #if GEN_GEN == 9
 127
 128 void
 129 gen9_emit_sf_state(struct anv_cmd_buffer *cmd_buffer)
 130 {
 131    __emit_genx_sf_state(cmd_buffer);
 132 }
 133
 134 #endif
 135
 136 #if GEN_GEN == 8
 137
 138 static void
 139 __emit_sf_state(struct anv_cmd_buffer *cmd_buffer)
 140 {
 141    if (cmd_buffer->device->info.is_cherryview)
 142       gen9_emit_sf_state(cmd_buffer);
 143    else
 144       __emit_genx_sf_state(cmd_buffer);
 145 }
 146
 147 #else
 148
 149 static void
 150 __emit_sf_state(struct anv_cmd_buffer *cmd_buffer)
 151 {
 152    __emit_genx_sf_state(cmd_buffer);
 153 }
 154
 155 #endif
 156
 157 void
 158 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 159 {
 160    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 161
 162    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 163                                   ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
 164       __emit_sf_state(cmd_buffer);
 165    }
 166
 167    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 168                                   ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)){
 169       uint32_t raster_dw[GENX(3DSTATE_RASTER_length)];
 170       struct GENX(3DSTATE_RASTER) raster = {
 171          GENX(3DSTATE_RASTER_header),
 172          .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
 173          .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
 174          .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
 175       };
 176       GENX(3DSTATE_RASTER_pack)(NULL, raster_dw, &raster);
 177       anv_batch_emit_merge(&cmd_buffer->batch, raster_dw,
 178                            pipeline->gen8.raster);
 179    }
 180
 181    /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
 182     * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
 183     * across different state packets for gen8 and gen9. We handle that by
 184     * using a big old #if switch here.
 185     */
 186 #if GEN_GEN == 8
 187    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 188                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 189       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 190       struct anv_state cc_state =
 191          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 192                                             GENX(COLOR_CALC_STATE_length) * 4,
 193                                             64);
 194       struct GENX(COLOR_CALC_STATE) cc = {
 195          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 196          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 197          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 198          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 199          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 200          .BackFaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 201       };
 202       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 203
 204       if (!cmd_buffer->device->info.has_llc)
 205          anv_state_clflush(cc_state);
 206
 207       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
 208          ccp.ColorCalcStatePointer        = cc_state.offset;
 209          ccp.ColorCalcStatePointerValid   = true;
 210       }
 211    }
 212
 213    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 214                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 215                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 216       uint32_t wm_depth_stencil_dw[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
 217       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 218
 219       struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
 220          GENX(3DSTATE_WM_DEPTH_STENCIL_header),
 221
 222          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 223          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 224
 225          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 226          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 227       };
 228       GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, wm_depth_stencil_dw,
 229                                           &wm_depth_stencil);
 230
 231       anv_batch_emit_merge(&cmd_buffer->batch, wm_depth_stencil_dw,
 232                            pipeline->gen8.wm_depth_stencil);
 233    }
 234 #else
 235    if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
 236       struct anv_state cc_state =
 237          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 238                                             GEN9_COLOR_CALC_STATE_length * 4,
 239                                             64);
 240       struct GEN9_COLOR_CALC_STATE cc = {
 241          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 242          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 243          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 244          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 245       };
 246       GEN9_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
 247
 248       if (!cmd_buffer->device->info.has_llc)
 249          anv_state_clflush(cc_state);
 250
 251       anv_batch_emit(&cmd_buffer->batch, GEN9_3DSTATE_CC_STATE_POINTERS, ccp) {
 252          ccp.ColorCalcStatePointer = cc_state.offset;
 253          ccp.ColorCalcStatePointerValid = true;
 254       }
 255    }
 256
 257    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 258                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 259                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
 260                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 261       uint32_t dwords[GEN9_3DSTATE_WM_DEPTH_STENCIL_length];
 262       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 263       struct GEN9_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil = {
 264          GEN9_3DSTATE_WM_DEPTH_STENCIL_header,
 265
 266          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 267          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 268
 269          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 270          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 271
 272          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 273          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 274       };
 275       GEN9_3DSTATE_WM_DEPTH_STENCIL_pack(NULL, dwords, &wm_depth_stencil);
 276
 277       anv_batch_emit_merge(&cmd_buffer->batch, dwords,
 278                            pipeline->gen9.wm_depth_stencil);
 279    }
 280 #endif
 281
 282    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 283                                   ANV_CMD_DIRTY_INDEX_BUFFER)) {
 284       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF), vf) {
 285          vf.IndexedDrawCutIndexEnable  = pipeline->primitive_restart;
 286          vf.CutIndex                   = cmd_buffer->state.restart_index;
 287       }
 288    }
 289
 290    cmd_buffer->state.dirty = 0;
 291 }
 292
 293 void genX(CmdBindIndexBuffer)(
 294     VkCommandBuffer                             commandBuffer,
 295     VkBuffer                                    _buffer,
 296     VkDeviceSize                                offset,
 297     VkIndexType                                 indexType)
 298 {
 299    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 300    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 301
 302    static const uint32_t vk_to_gen_index_type[] = {
 303       [VK_INDEX_TYPE_UINT16]                    = INDEX_WORD,
 304       [VK_INDEX_TYPE_UINT32]                    = INDEX_DWORD,
 305    };
 306
 307    static const uint32_t restart_index_for_type[] = {
 308       [VK_INDEX_TYPE_UINT16]                    = UINT16_MAX,
 309       [VK_INDEX_TYPE_UINT32]                    = UINT32_MAX,
 310    };
 311
 312    cmd_buffer->state.restart_index = restart_index_for_type[indexType];
 313
 314    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
 315       ib.IndexFormat                = vk_to_gen_index_type[indexType];
 316       ib.MemoryObjectControlState   = GENX(MOCS);
 317       ib.BufferStartingAddress      =
 318          (struct anv_address) { buffer->bo, buffer->offset + offset };
 319       ib.BufferSize                 = buffer->size - offset;
 320    }
 321
 322    cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 323 }
 324
 325
 326 /**
 327  * Emit the HZ_OP packet in the sequence specified by the BDW PRM section
 328  * entitled: "Optimized Depth Buffer Clear and/or Stencil Buffer Clear."
 329  *
 330  * \todo Enable Stencil Buffer-only clears
 331  */
 332 void
 333 genX(cmd_buffer_emit_hz_op)(struct anv_cmd_buffer *cmd_buffer,
 334                           enum blorp_hiz_op op)
 335 {
 336    struct anv_cmd_state *cmd_state = &cmd_buffer->state;
 337    const struct anv_image_view *iview =
 338       anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
 339
 340    if (iview == NULL || iview->image->aux_usage != ISL_AUX_USAGE_HIZ)
 341       return;
 342
 343    const uint32_t ds = cmd_state->subpass->depth_stencil_attachment;
 344
 345    /* Section 7.4. of the Vulkan 1.0.27 spec states:
 346     *
 347     *   "The render area must be contained within the framebuffer dimensions."
 348     *
 349     * Therefore, the only way the extent of the render area can match that of
 350     * the image view is if the render area offset equals (0, 0).
 351     */
 352    const bool full_surface_op =
 353              cmd_state->render_area.extent.width == iview->extent.width &&
 354              cmd_state->render_area.extent.height == iview->extent.height;
 355    if (full_surface_op)
 356       assert(cmd_state->render_area.offset.x == 0 &&
 357              cmd_state->render_area.offset.y == 0);
 358
 359    bool depth_clear;
 360    bool stencil_clear;
 361
 362    /* This variable corresponds to the Pixel Dim column in the table below */
 363    struct isl_extent2d px_dim;
 364
 365    const uint32_t subpass_idx = cmd_state->subpass - cmd_state->pass->subpasses;
 366
 367    /* Validate that we can perform the HZ operation and that it's necessary. */
 368    switch (op) {
 369    case BLORP_HIZ_OP_DEPTH_CLEAR:
 370       stencil_clear = VK_IMAGE_ASPECT_STENCIL_BIT &
 371                   cmd_state->attachments[ds].pending_clear_aspects;
 372       depth_clear = VK_IMAGE_ASPECT_DEPTH_BIT &
 373                     cmd_state->attachments[ds].pending_clear_aspects;
 374
 375       /* Apply alignment restrictions. Despite the BDW PRM mentioning this is
 376        * only needed for a depth buffer surface type of D16_UNORM, testing
 377        * showed it to be necessary for other depth formats as well
 378        * (e.g., D32_FLOAT).
 379        */
 380 #if GEN_GEN == 8
 381       /* Pre-SKL, HiZ has an 8x4 sample block. As the number of samples
 382        * increases, the number of pixels representable by this block
 383        * decreases by a factor of the sample dimensions. Sample dimensions
 384        * scale following the MSAA interleaved pattern.
 385        *
 386        * Sample|Sample|Pixel
 387        * Count |Dim   |Dim
 388        * ===================
 389        *    1  | 1x1  | 8x4
 390        *    2  | 2x1  | 4x4
 391        *    4  | 2x2  | 4x2
 392        *    8  | 4x2  | 2x2
 393        *   16  | 4x4  | 2x1
 394        *
 395        * Table: Pixel Dimensions in a HiZ Sample Block Pre-SKL
 396        */
 397       /* This variable corresponds to the Sample Dim column in the table
 398        * above.
 399        */
 400       const struct isl_extent2d sa_dim =
 401          isl_get_interleaved_msaa_px_size_sa(iview->image->samples);
 402       px_dim.w = 8 / sa_dim.w;
 403       px_dim.h = 4 / sa_dim.h;
 404 #elif GEN_GEN >= 9
 405       /* SKL+, the sample block becomes a "pixel block" so the expected
 406        * pixel dimension is a constant 8x4 px for all sample counts.
 407        */
 408       px_dim = (struct isl_extent2d) { .w = 8, .h = 4};
 409 #endif
 410
 411       if (depth_clear && !full_surface_op) {
 412          /* Fast depth clears clear an entire sample block at a time. As a
 413           * result, the rectangle must be aligned to the pixel dimensions of
 414           * a sample block for a successful operation.
 415           *
 416           * Fast clears can still work if the offset is aligned and the render
 417           * area offset + extent touches the edge of a depth buffer whose extent
 418           * is unaligned. This is because each physical HiZ miplevel is padded
 419           * by the px_dim. In this case, the size of the clear rectangle will be
 420           * padded later on in this function.
 421           */
 422          if (cmd_state->render_area.offset.x % px_dim.w ||
 423              cmd_state->render_area.offset.y % px_dim.h)
 424             depth_clear = false;
 425          if (cmd_state->render_area.offset.x +
 426              cmd_state->render_area.extent.width != iview->extent.width &&
 427              cmd_state->render_area.extent.width % px_dim.w)
 428             depth_clear = false;
 429          if (cmd_state->render_area.offset.y +
 430              cmd_state->render_area.extent.height != iview->extent.height &&
 431              cmd_state->render_area.extent.height % px_dim.h)
 432             depth_clear = false;
 433       }
 434
 435       if (!depth_clear) {
 436          if (stencil_clear) {
 437             /* Stencil has no alignment requirements */
 438             px_dim = (struct isl_extent2d) { .w = 1, .h = 1};
 439          } else {
 440             /* Nothing to clear */
 441             return;
 442          }
 443       }
 444       break;
 445    case BLORP_HIZ_OP_DEPTH_RESOLVE:
 446       if (cmd_buffer->state.pass->attachments[ds].store_op !=
 447           VK_ATTACHMENT_STORE_OP_STORE &&
 448           subpass_idx == cmd_state->pass->subpass_count - 1)
 449          return;
 450       break;
 451    case BLORP_HIZ_OP_HIZ_RESOLVE:
 452       /* If the render area covers the entire surface *and* load_op is either
 453        * CLEAR or DONT_CARE then the previous contents of the depth buffer
 454        * will be entirely discarded.  In this case, we can skip the HiZ
 455        * resolve.
 456        *
 457        * If the render area is not the full surface, we need to do
 458        * the resolve because otherwise data outside the render area may get
 459        * garbled by the resolve at the end of the render pass.
 460        */
 461       if (full_surface_op &&
 462           cmd_buffer->state.pass->attachments[ds].load_op !=
 463           VK_ATTACHMENT_LOAD_OP_LOAD && subpass_idx == 0)
 464          return;
 465       break;
 466    case BLORP_HIZ_OP_NONE:
 467       unreachable("Invalid HiZ OP");
 468       break;
 469    }
 470
 471    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_WM_HZ_OP), hzp) {
 472       switch (op) {
 473       case BLORP_HIZ_OP_DEPTH_CLEAR:
 474          hzp.StencilBufferClearEnable = stencil_clear;
 475          hzp.DepthBufferClearEnable = depth_clear;
 476          hzp.FullSurfaceDepthandStencilClear = full_surface_op;
 477          hzp.StencilClearValue =
 478             cmd_state->attachments[ds].clear_value.depthStencil.stencil & 0xff;
 479          break;
 480       case BLORP_HIZ_OP_DEPTH_RESOLVE:
 481          hzp.DepthBufferResolveEnable = true;
 482          break;
 483       case BLORP_HIZ_OP_HIZ_RESOLVE:
 484          hzp.HierarchicalDepthBufferResolveEnable = true;
 485          break;
 486       case BLORP_HIZ_OP_NONE:
 487          unreachable("Invalid HiZ OP");
 488          break;
 489       }
 490
 491       if (op != BLORP_HIZ_OP_DEPTH_CLEAR) {
 492          /* The Optimized HiZ resolve rectangle must be the size of the full RT
 493           * and aligned to 8x4. The non-optimized Depth resolve rectangle must
 494           * be the size of the full RT. The same alignment is assumed to be
 495           * required.
 496           */
 497          hzp.ClearRectangleXMin = 0;
 498          hzp.ClearRectangleYMin = 0;
 499          hzp.ClearRectangleXMax = align_u32(iview->extent.width, 8);
 500          hzp.ClearRectangleYMax = align_u32(iview->extent.height, 4);
 501       } else {
 502          /* Contrary to the HW docs both fields are inclusive */
 503          hzp.ClearRectangleXMin = cmd_state->render_area.offset.x;
 504          hzp.ClearRectangleYMin = cmd_state->render_area.offset.y;
 505          /* Contrary to the HW docs both fields are exclusive */
 506          hzp.ClearRectangleXMax = cmd_state->render_area.offset.x +
 507             align_u32(cmd_state->render_area.extent.width, px_dim.width);
 508          hzp.ClearRectangleYMax = cmd_state->render_area.offset.y +
 509             align_u32(cmd_state->render_area.extent.height, px_dim.height);
 510       }
 511
 512
 513       /* Due to a hardware issue, this bit MBZ */
 514       hzp.ScissorRectangleEnable = false;
 515       hzp.NumberofMultisamples = ffs(iview->image->samples) - 1;
 516       hzp.SampleMask = 0xFFFF;
 517    }
 518
 519    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 520       pc.PostSyncOperation = WriteImmediateData;
 521       pc.Address =
 522          (struct anv_address){ &cmd_buffer->device->workaround_bo, 0 };
 523    }
 524
 525    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_WM_HZ_OP), hzp);
 526
 527    /* Perform clear specific flushing and state updates */
 528    if (op == BLORP_HIZ_OP_DEPTH_CLEAR) {
 529       if (depth_clear && !full_surface_op) {
 530          anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 531             pc.DepthStallEnable = true;
 532             pc.DepthCacheFlushEnable = true;
 533          }
 534       }
 535
 536       /* Remove cleared aspects from the pending mask */
 537       if (stencil_clear) {
 538          cmd_state->attachments[ds].pending_clear_aspects &=
 539             ~VK_IMAGE_ASPECT_STENCIL_BIT;
 540       }
 541       if (depth_clear) {
 542          cmd_state->attachments[ds].pending_clear_aspects &=
 543             ~VK_IMAGE_ASPECT_DEPTH_BIT;
 544       }
 545    }
 546 }
 547
 548 /* Set of stage bits for which are pipelined, i.e. they get queued by the
 549  * command streamer for later execution.
 550  */
 551 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
 552    (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
 553     VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
 554     VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
 555     VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
 556     VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
 557     VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
 558     VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
 559     VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
 560     VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
 561     VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
 562     VK_PIPELINE_STAGE_TRANSFER_BIT | \
 563     VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
 564     VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
 565     VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
 566
 567 void genX(CmdSetEvent)(
 568     VkCommandBuffer                             commandBuffer,
 569     VkEvent                                     _event,
 570     VkPipelineStageFlags                        stageMask)
 571 {
 572    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 573    ANV_FROM_HANDLE(anv_event, event, _event);
 574
 575    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 576       if (stageMask & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
 577          pc.StallAtPixelScoreboard = true;
 578          pc.CommandStreamerStallEnable = true;
 579       }
 580
 581       pc.DestinationAddressType  = DAT_PPGTT,
 582       pc.PostSyncOperation       = WriteImmediateData,
 583       pc.Address = (struct anv_address) {
 584          &cmd_buffer->device->dynamic_state_block_pool.bo,
 585          event->state.offset
 586       };
 587       pc.ImmediateData           = VK_EVENT_SET;
 588    }
 589 }
 590
 591 void genX(CmdResetEvent)(
 592     VkCommandBuffer                             commandBuffer,
 593     VkEvent                                     _event,
 594     VkPipelineStageFlags                        stageMask)
 595 {
 596    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 597    ANV_FROM_HANDLE(anv_event, event, _event);
 598
 599    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 600       if (stageMask & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
 601          pc.StallAtPixelScoreboard = true;
 602          pc.CommandStreamerStallEnable = true;
 603       }
 604
 605       pc.DestinationAddressType  = DAT_PPGTT;
 606       pc.PostSyncOperation       = WriteImmediateData;
 607       pc.Address = (struct anv_address) {
 608          &cmd_buffer->device->dynamic_state_block_pool.bo,
 609          event->state.offset
 610       };
 611       pc.ImmediateData           = VK_EVENT_RESET;
 612    }
 613 }
 614
 615 void genX(CmdWaitEvents)(
 616     VkCommandBuffer                             commandBuffer,
 617     uint32_t                                    eventCount,
 618     const VkEvent*                              pEvents,
 619     VkPipelineStageFlags                        srcStageMask,
 620     VkPipelineStageFlags                        destStageMask,
 621     uint32_t                                    memoryBarrierCount,
 622     const VkMemoryBarrier*                      pMemoryBarriers,
 623     uint32_t                                    bufferMemoryBarrierCount,
 624     const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
 625     uint32_t                                    imageMemoryBarrierCount,
 626     const VkImageMemoryBarrier*                 pImageMemoryBarriers)
 627 {
 628    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 629    for (uint32_t i = 0; i < eventCount; i++) {
 630       ANV_FROM_HANDLE(anv_event, event, pEvents[i]);
 631
 632       anv_batch_emit(&cmd_buffer->batch, GENX(MI_SEMAPHORE_WAIT), sem) {
 633          sem.WaitMode            = PollingMode,
 634          sem.CompareOperation    = COMPARE_SAD_EQUAL_SDD,
 635          sem.SemaphoreDataDword  = VK_EVENT_SET,
 636          sem.SemaphoreAddress = (struct anv_address) {
 637             &cmd_buffer->device->dynamic_state_block_pool.bo,
 638             event->state.offset
 639          };
 640       }
 641    }
 642
 643    genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
 644                             false, /* byRegion */
 645                             memoryBarrierCount, pMemoryBarriers,
 646                             bufferMemoryBarrierCount, pBufferMemoryBarriers,
 647                             imageMemoryBarrierCount, pImageMemoryBarriers);
 648 }