src/intel/vulkan/gen8_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34 #include "common/gen_guardband.h"
  35
  36 #if GEN_GEN == 8
  37 void
  38 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer)
  39 {
  40    struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
  41    uint32_t count = cmd_buffer->state.gfx.dynamic.viewport.count;
  42    const VkViewport *viewports =
  43       cmd_buffer->state.gfx.dynamic.viewport.viewports;
  44    struct anv_state sf_clip_state =
  45       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 64, 64);
  46
  47    for (uint32_t i = 0; i < count; i++) {
  48       const VkViewport *vp = &viewports[i];
  49
  50       /* The gen7 state struct has just the matrix and guardband fields, the
  51        * gen8 struct adds the min/max viewport fields. */
  52       struct GENX(SF_CLIP_VIEWPORT) sfv = {
  53          .ViewportMatrixElementm00 = vp->width / 2,
  54          .ViewportMatrixElementm11 = vp->height / 2,
  55          .ViewportMatrixElementm22 = vp->maxDepth - vp->minDepth,
  56          .ViewportMatrixElementm30 = vp->x + vp->width / 2,
  57          .ViewportMatrixElementm31 = vp->y + vp->height / 2,
  58          .ViewportMatrixElementm32 = vp->minDepth,
  59          .XMinClipGuardband = -1.0f,
  60          .XMaxClipGuardband = 1.0f,
  61          .YMinClipGuardband = -1.0f,
  62          .YMaxClipGuardband = 1.0f,
  63          .XMinViewPort = vp->x,
  64          .XMaxViewPort = vp->x + vp->width - 1,
  65          .YMinViewPort = MIN2(vp->y, vp->y + vp->height),
  66          .YMaxViewPort = MAX2(vp->y, vp->y + vp->height) - 1,
  67       };
  68
  69       if (fb) {
  70          /* We can only calculate a "real" guardband clip if we know the
  71           * framebuffer at the time we emit the packet.  Otherwise, we have
  72           * fall back to a worst-case guardband of [-1, 1].
  73           */
  74          gen_calculate_guardband_size(fb->width, fb->height,
  75                                       sfv.ViewportMatrixElementm00,
  76                                       sfv.ViewportMatrixElementm11,
  77                                       sfv.ViewportMatrixElementm30,
  78                                       sfv.ViewportMatrixElementm31,
  79                                       &sfv.XMinClipGuardband,
  80                                       &sfv.XMaxClipGuardband,
  81                                       &sfv.YMinClipGuardband,
  82                                       &sfv.YMaxClipGuardband);
  83       }
  84
  85       GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64, &sfv);
  86    }
  87
  88    anv_batch_emit(&cmd_buffer->batch,
  89                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), clip) {
  90       clip.SFClipViewportPointer = sf_clip_state.offset;
  91    }
  92 }
  93
  94 void
  95 gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
  96                                     bool depth_clamp_enable)
  97 {
  98    uint32_t count = cmd_buffer->state.gfx.dynamic.viewport.count;
  99    const VkViewport *viewports =
 100       cmd_buffer->state.gfx.dynamic.viewport.viewports;
 101    struct anv_state cc_state =
 102       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
 103
 104    for (uint32_t i = 0; i < count; i++) {
 105       const VkViewport *vp = &viewports[i];
 106
 107       struct GENX(CC_VIEWPORT) cc_viewport = {
 108          .MinimumDepth = depth_clamp_enable ? vp->minDepth : 0.0f,
 109          .MaximumDepth = depth_clamp_enable ? vp->maxDepth : 1.0f,
 110       };
 111
 112       GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport);
 113    }
 114
 115    anv_batch_emit(&cmd_buffer->batch,
 116                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) {
 117       cc.CCViewportPointer = cc_state.offset;
 118    }
 119 }
 120 #endif
 121
 122 void
 123 genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable)
 124 {
 125    if (cmd_buffer->state.pma_fix_enabled == enable)
 126       return;
 127
 128    cmd_buffer->state.pma_fix_enabled = enable;
 129
 130    /* According to the Broadwell PIPE_CONTROL documentation, software should
 131     * emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set
 132     * prior to the LRI.  If stencil buffer writes are enabled, then a Render
 133     * Cache Flush is also necessary.
 134     *
 135     * The Skylake docs say to use a depth stall rather than a command
 136     * streamer stall.  However, the hardware seems to violently disagree.
 137     * A full command streamer stall seems to be needed in both cases.
 138     */
 139    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 140       pc.DepthCacheFlushEnable = true;
 141       pc.CommandStreamerStallEnable = true;
 142       pc.RenderTargetCacheFlushEnable = true;
 143 #if GEN_GEN >= 12
 144       pc.TileCacheFlushEnable = true;
 145 #endif
 146    }
 147
 148 #if GEN_GEN == 9
 149
 150    uint32_t cache_mode;
 151    anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0),
 152                    .STCPMAOptimizationEnable = enable,
 153                    .STCPMAOptimizationEnableMask = true);
 154    anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 155       lri.RegisterOffset   = GENX(CACHE_MODE_0_num);
 156       lri.DataDWord        = cache_mode;
 157    }
 158
 159 #elif GEN_GEN == 8
 160
 161    uint32_t cache_mode;
 162    anv_pack_struct(&cache_mode, GENX(CACHE_MODE_1),
 163                    .NPPMAFixEnable = enable,
 164                    .NPEarlyZFailsDisable = enable,
 165                    .NPPMAFixEnableMask = true,
 166                    .NPEarlyZFailsDisableMask = true);
 167    anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 168       lri.RegisterOffset   = GENX(CACHE_MODE_1_num);
 169       lri.DataDWord        = cache_mode;
 170    }
 171
 172 #endif /* GEN_GEN == 8 */
 173
 174    /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
 175     * Flush bits is often necessary.  We do it regardless because it's easier.
 176     * The render cache flush is also necessary if stencil writes are enabled.
 177     *
 178     * Again, the Skylake docs give a different set of flushes but the BDW
 179     * flushes seem to work just as well.
 180     */
 181    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 182       pc.DepthStallEnable = true;
 183       pc.DepthCacheFlushEnable = true;
 184       pc.RenderTargetCacheFlushEnable = true;
 185 #if GEN_GEN >= 12
 186       pc.TileCacheFlushEnable = true;
 187 #endif
 188    }
 189 }
 190
 191 UNUSED static bool
 192 want_depth_pma_fix(struct anv_cmd_buffer *cmd_buffer)
 193 {
 194    assert(GEN_GEN == 8);
 195
 196    /* From the Broadwell PRM Vol. 2c CACHE_MODE_1::NP_PMA_FIX_ENABLE:
 197     *
 198     *    SW must set this bit in order to enable this fix when following
 199     *    expression is TRUE.
 200     *
 201     *    3DSTATE_WM::ForceThreadDispatch != 1 &&
 202     *    !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) &&
 203     *    (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
 204     *    (3DSTATE_DEPTH_BUFFER::HIZ Enable) &&
 205     *    !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) &&
 206     *    (3DSTATE_PS_EXTRA::PixelShaderValid) &&
 207     *    !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 208     *      3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 209     *      3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 210     *      3DSTATE_WM_HZ_OP::StencilBufferClear) &&
 211     *    (3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable) &&
 212     *    (((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
 213     *       3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
 214     *       3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
 215     *       3DSTATE_PS_BLEND::AlphaTestEnable ||
 216     *       3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) &&
 217     *      3DSTATE_WM::ForceKillPix != ForceOff &&
 218     *      ((3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
 219     *        3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE) ||
 220     *       (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
 221     *        3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
 222     *        3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE))) ||
 223     *     (3DSTATE_PS_EXTRA:: Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
 224     */
 225
 226    /* These are always true:
 227     *    3DSTATE_WM::ForceThreadDispatch != 1 &&
 228     *    !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0)
 229     */
 230
 231    /* We only enable the PMA fix if we know for certain that HiZ is enabled.
 232     * If we don't know whether HiZ is enabled or not, we disable the PMA fix
 233     * and there is no harm.
 234     *
 235     * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
 236     * 3DSTATE_DEPTH_BUFFER::HIZ Enable
 237     */
 238    if (!cmd_buffer->state.hiz_enabled)
 239       return false;
 240
 241    /* 3DSTATE_PS_EXTRA::PixelShaderValid */
 242    struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
 243    if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT))
 244       return false;
 245
 246    /* !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) */
 247    const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
 248    if (wm_prog_data->early_fragment_tests)
 249       return false;
 250
 251    /* We never use anv_pipeline for HiZ ops so this is trivially true:
 252     *    !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 253     *      3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 254     *      3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 255     *      3DSTATE_WM_HZ_OP::StencilBufferClear)
 256     */
 257
 258    /* 3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable */
 259    if (!pipeline->depth_test_enable)
 260       return false;
 261
 262    /* (((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
 263     *    3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
 264     *    3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
 265     *    3DSTATE_PS_BLEND::AlphaTestEnable ||
 266     *    3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) &&
 267     *   3DSTATE_WM::ForceKillPix != ForceOff &&
 268     *   ((3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
 269     *     3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE) ||
 270     *    (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
 271     *     3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
 272     *     3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE))) ||
 273     *  (3DSTATE_PS_EXTRA:: Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
 274     */
 275    return (pipeline->kill_pixel && (pipeline->writes_depth ||
 276                                     pipeline->writes_stencil)) ||
 277           wm_prog_data->computed_depth_mode != PSCDEPTH_OFF;
 278 }
 279
 280 UNUSED static bool
 281 want_stencil_pma_fix(struct anv_cmd_buffer *cmd_buffer)
 282 {
 283    if (GEN_GEN > 9)
 284       return false;
 285    assert(GEN_GEN == 9);
 286
 287    /* From the Skylake PRM Vol. 2c CACHE_MODE_1::STC PMA Optimization Enable:
 288     *
 289     *    Clearing this bit will force the STC cache to wait for pending
 290     *    retirement of pixels at the HZ-read stage and do the STC-test for
 291     *    Non-promoted, R-computed and Computed depth modes instead of
 292     *    postponing the STC-test to RCPFE.
 293     *
 294     *    STC_TEST_EN = 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
 295     *                  3DSTATE_WM_DEPTH_STENCIL::StencilTestEnable
 296     *
 297     *    STC_WRITE_EN = 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
 298     *                   (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
 299     *                    3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE)
 300     *
 301     *    COMP_STC_EN = STC_TEST_EN &&
 302     *                  3DSTATE_PS_EXTRA::PixelShaderComputesStencil
 303     *
 304     *    SW parses the pipeline states to generate the following logical
 305     *    signal indicating if PMA FIX can be enabled.
 306     *
 307     *    STC_PMA_OPT =
 308     *       3DSTATE_WM::ForceThreadDispatch != 1 &&
 309     *       !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) &&
 310     *       3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
 311     *       3DSTATE_DEPTH_BUFFER::HIZ Enable &&
 312     *       !(3DSTATE_WM::EDSC_Mode == 2) &&
 313     *       3DSTATE_PS_EXTRA::PixelShaderValid &&
 314     *       !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 315     *         3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 316     *         3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 317     *         3DSTATE_WM_HZ_OP::StencilBufferClear) &&
 318     *       (COMP_STC_EN || STC_WRITE_EN) &&
 319     *       ((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
 320     *         3DSTATE_WM::ForceKillPix == ON ||
 321     *         3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
 322     *         3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
 323     *         3DSTATE_PS_BLEND::AlphaTestEnable ||
 324     *         3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) ||
 325     *        (3DSTATE_PS_EXTRA::Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
 326     */
 327
 328    /* These are always true:
 329     *    3DSTATE_WM::ForceThreadDispatch != 1 &&
 330     *    !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0)
 331     */
 332
 333    /* We only enable the PMA fix if we know for certain that HiZ is enabled.
 334     * If we don't know whether HiZ is enabled or not, we disable the PMA fix
 335     * and there is no harm.
 336     *
 337     * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
 338     * 3DSTATE_DEPTH_BUFFER::HIZ Enable
 339     */
 340    if (!cmd_buffer->state.hiz_enabled)
 341       return false;
 342
 343    /* We can't possibly know if HiZ is enabled without the framebuffer */
 344    assert(cmd_buffer->state.framebuffer);
 345
 346    /* HiZ is enabled so we had better have a depth buffer with HiZ */
 347    const struct anv_image_view *ds_iview =
 348       anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
 349    assert(ds_iview && ds_iview->image->planes[0].aux_usage == ISL_AUX_USAGE_HIZ);
 350
 351    /* 3DSTATE_PS_EXTRA::PixelShaderValid */
 352    struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
 353    if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT))
 354       return false;
 355
 356    /* !(3DSTATE_WM::EDSC_Mode == 2) */
 357    const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
 358    if (wm_prog_data->early_fragment_tests)
 359       return false;
 360
 361    /* We never use anv_pipeline for HiZ ops so this is trivially true:
 362    *    !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 363     *      3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 364     *      3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 365     *      3DSTATE_WM_HZ_OP::StencilBufferClear)
 366     */
 367
 368    /* 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
 369     * 3DSTATE_WM_DEPTH_STENCIL::StencilTestEnable
 370     */
 371    const bool stc_test_en =
 372       (ds_iview->image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
 373       pipeline->stencil_test_enable;
 374
 375    /* 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
 376     * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
 377     *  3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE)
 378     */
 379    const bool stc_write_en =
 380       (ds_iview->image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
 381       (cmd_buffer->state.gfx.dynamic.stencil_write_mask.front ||
 382        cmd_buffer->state.gfx.dynamic.stencil_write_mask.back) &&
 383       pipeline->writes_stencil;
 384
 385    /* STC_TEST_EN && 3DSTATE_PS_EXTRA::PixelShaderComputesStencil */
 386    const bool comp_stc_en = stc_test_en && wm_prog_data->computed_stencil;
 387
 388    /* COMP_STC_EN || STC_WRITE_EN */
 389    if (!(comp_stc_en || stc_write_en))
 390       return false;
 391
 392    /* (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
 393     *  3DSTATE_WM::ForceKillPix == ON ||
 394     *  3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
 395     *  3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
 396     *  3DSTATE_PS_BLEND::AlphaTestEnable ||
 397     *  3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) ||
 398     * (3DSTATE_PS_EXTRA::Pixel Shader Computed Depth mode != PSCDEPTH_OFF)
 399     */
 400    return pipeline->kill_pixel ||
 401           wm_prog_data->computed_depth_mode != PSCDEPTH_OFF;
 402 }
 403
 404 void
 405 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 406 {
 407    struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
 408    struct anv_dynamic_state *d = &cmd_buffer->state.gfx.dynamic;
 409
 410    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 411                                       ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
 412       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 413       struct GENX(3DSTATE_SF) sf = {
 414          GENX(3DSTATE_SF_header),
 415       };
 416 #if GEN_GEN == 8
 417       if (cmd_buffer->device->info.is_cherryview) {
 418          sf.CHVLineWidth = d->line_width;
 419       } else {
 420          sf.LineWidth = d->line_width;
 421       }
 422 #else
 423       sf.LineWidth = d->line_width,
 424 #endif
 425       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 426       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen8.sf);
 427    }
 428
 429    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 430                                       ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)){
 431       uint32_t raster_dw[GENX(3DSTATE_RASTER_length)];
 432       struct GENX(3DSTATE_RASTER) raster = {
 433          GENX(3DSTATE_RASTER_header),
 434          .GlobalDepthOffsetConstant = d->depth_bias.bias,
 435          .GlobalDepthOffsetScale = d->depth_bias.slope,
 436          .GlobalDepthOffsetClamp = d->depth_bias.clamp
 437       };
 438       GENX(3DSTATE_RASTER_pack)(NULL, raster_dw, &raster);
 439       anv_batch_emit_merge(&cmd_buffer->batch, raster_dw,
 440                            pipeline->gen8.raster);
 441    }
 442
 443    /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
 444     * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
 445     * across different state packets for gen8 and gen9. We handle that by
 446     * using a big old #if switch here.
 447     */
 448 #if GEN_GEN == 8
 449    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 450                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 451       struct anv_state cc_state =
 452          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 453                                             GENX(COLOR_CALC_STATE_length) * 4,
 454                                             64);
 455       struct GENX(COLOR_CALC_STATE) cc = {
 456          .BlendConstantColorRed = d->blend_constants[0],
 457          .BlendConstantColorGreen = d->blend_constants[1],
 458          .BlendConstantColorBlue = d->blend_constants[2],
 459          .BlendConstantColorAlpha = d->blend_constants[3],
 460          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 461          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 462       };
 463       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 464
 465       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
 466          ccp.ColorCalcStatePointer        = cc_state.offset;
 467          ccp.ColorCalcStatePointerValid   = true;
 468       }
 469    }
 470
 471    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 472                                       ANV_CMD_DIRTY_RENDER_TARGETS |
 473                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 474                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 475       uint32_t wm_depth_stencil_dw[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
 476
 477       struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
 478          GENX(3DSTATE_WM_DEPTH_STENCIL_header),
 479
 480          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 481          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 482
 483          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 484          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 485
 486          .StencilBufferWriteEnable =
 487             (d->stencil_write_mask.front || d->stencil_write_mask.back) &&
 488             pipeline->writes_stencil,
 489       };
 490       GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, wm_depth_stencil_dw,
 491                                           &wm_depth_stencil);
 492
 493       anv_batch_emit_merge(&cmd_buffer->batch, wm_depth_stencil_dw,
 494                            pipeline->gen8.wm_depth_stencil);
 495
 496       genX(cmd_buffer_enable_pma_fix)(cmd_buffer,
 497                                       want_depth_pma_fix(cmd_buffer));
 498    }
 499 #else
 500    if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
 501       struct anv_state cc_state =
 502          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 503                                             GENX(COLOR_CALC_STATE_length) * 4,
 504                                             64);
 505       struct GENX(COLOR_CALC_STATE) cc = {
 506          .BlendConstantColorRed = d->blend_constants[0],
 507          .BlendConstantColorGreen = d->blend_constants[1],
 508          .BlendConstantColorBlue = d->blend_constants[2],
 509          .BlendConstantColorAlpha = d->blend_constants[3],
 510       };
 511       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 512
 513       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
 514          ccp.ColorCalcStatePointer = cc_state.offset;
 515          ccp.ColorCalcStatePointerValid = true;
 516       }
 517    }
 518
 519    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 520                                       ANV_CMD_DIRTY_RENDER_TARGETS |
 521                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 522                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
 523                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 524       uint32_t dwords[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
 525       struct GENX(3DSTATE_WM_DEPTH_STENCIL) wm_depth_stencil = {
 526          GENX(3DSTATE_WM_DEPTH_STENCIL_header),
 527
 528          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 529          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 530
 531          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 532          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 533
 534          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 535          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 536
 537          .StencilBufferWriteEnable =
 538             (d->stencil_write_mask.front || d->stencil_write_mask.back) &&
 539             pipeline->writes_stencil,
 540       };
 541       GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dwords, &wm_depth_stencil);
 542
 543       anv_batch_emit_merge(&cmd_buffer->batch, dwords,
 544                            pipeline->gen9.wm_depth_stencil);
 545
 546       genX(cmd_buffer_enable_pma_fix)(cmd_buffer,
 547                                       want_stencil_pma_fix(cmd_buffer));
 548    }
 549 #endif
 550
 551 #if GEN_GEN >= 12
 552    if(cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 553                                      ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
 554       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BOUNDS), db) {
 555          db.DepthBoundsTestValueModifyDisable = false;
 556          db.DepthBoundsTestEnableModifyDisable = false;
 557          db.DepthBoundsTestEnable = pipeline->depth_bounds_test_enable;
 558          db.DepthBoundsTestMinValue = d->depth_bounds.min;
 559          db.DepthBoundsTestMaxValue = d->depth_bounds.max;
 560       }
 561    }
 562 #endif
 563
 564    if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE) {
 565       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_LINE_STIPPLE), ls) {
 566          ls.LineStipplePattern = d->line_stipple.pattern;
 567          ls.LineStippleInverseRepeatCount =
 568             1.0f / MAX2(1, d->line_stipple.factor);
 569          ls.LineStippleRepeatCount = d->line_stipple.factor;
 570       }
 571    }
 572
 573    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 574                                       ANV_CMD_DIRTY_INDEX_BUFFER)) {
 575       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF), vf) {
 576          vf.IndexedDrawCutIndexEnable  = pipeline->primitive_restart;
 577          vf.CutIndex                   = cmd_buffer->state.restart_index;
 578       }
 579    }
 580
 581    cmd_buffer->state.gfx.dirty = 0;
 582 }
 583
 584 static uint32_t vk_to_gen_index_type(VkIndexType type)
 585 {
 586    switch (type) {
 587    case VK_INDEX_TYPE_UINT8_EXT:
 588       return INDEX_BYTE;
 589    case VK_INDEX_TYPE_UINT16:
 590       return INDEX_WORD;
 591    case VK_INDEX_TYPE_UINT32:
 592       return INDEX_DWORD;
 593    default:
 594       unreachable("invalid index type");
 595    }
 596 }
 597
 598 static uint32_t restart_index_for_type(VkIndexType type)
 599 {
 600    switch (type) {
 601    case VK_INDEX_TYPE_UINT8_EXT:
 602       return UINT8_MAX;
 603    case VK_INDEX_TYPE_UINT16:
 604       return UINT16_MAX;
 605    case VK_INDEX_TYPE_UINT32:
 606       return UINT32_MAX;
 607    default:
 608       unreachable("invalid index type");
 609    }
 610 }
 611
 612 void genX(CmdBindIndexBuffer)(
 613     VkCommandBuffer                             commandBuffer,
 614     VkBuffer                                    _buffer,
 615     VkDeviceSize                                offset,
 616     VkIndexType                                 indexType)
 617 {
 618    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 619    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 620
 621    cmd_buffer->state.restart_index = restart_index_for_type(indexType);
 622
 623    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
 624       ib.IndexFormat                = vk_to_gen_index_type(indexType);
 625       ib.MOCS                       = anv_mocs_for_bo(cmd_buffer->device,
 626                                                       buffer->address.bo);
 627       ib.BufferStartingAddress      = anv_address_add(buffer->address, offset);
 628       ib.BufferSize                 = buffer->size - offset;
 629    }
 630
 631    cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 632 }