2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
37 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
)
39 uint32_t count
= cmd_buffer
->state
.dynamic
.viewport
.count
;
40 const VkViewport
*viewports
= cmd_buffer
->state
.dynamic
.viewport
.viewports
;
41 struct anv_state sf_clip_state
=
42 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, count
* 64, 64);
44 for (uint32_t i
= 0; i
< count
; i
++) {
45 const VkViewport
*vp
= &viewports
[i
];
47 /* The gen7 state struct has just the matrix and guardband fields, the
48 * gen8 struct adds the min/max viewport fields. */
49 struct GENX(SF_CLIP_VIEWPORT
) sf_clip_viewport
= {
50 .ViewportMatrixElementm00
= vp
->width
/ 2,
51 .ViewportMatrixElementm11
= vp
->height
/ 2,
52 .ViewportMatrixElementm22
= 1.0,
53 .ViewportMatrixElementm30
= vp
->x
+ vp
->width
/ 2,
54 .ViewportMatrixElementm31
= vp
->y
+ vp
->height
/ 2,
55 .ViewportMatrixElementm32
= 0.0,
56 .XMinClipGuardband
= -1.0f
,
57 .XMaxClipGuardband
= 1.0f
,
58 .YMinClipGuardband
= -1.0f
,
59 .YMaxClipGuardband
= 1.0f
,
60 .XMinViewPort
= vp
->x
,
61 .XMaxViewPort
= vp
->x
+ vp
->width
- 1,
62 .YMinViewPort
= vp
->y
,
63 .YMaxViewPort
= vp
->y
+ vp
->height
- 1,
66 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_state
.map
+ i
* 64,
70 if (!cmd_buffer
->device
->info
.has_llc
)
71 anv_state_clflush(sf_clip_state
);
73 anv_batch_emit(&cmd_buffer
->batch
,
74 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), clip
) {
75 clip
.SFClipViewportPointer
= sf_clip_state
.offset
;
80 gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
81 bool depth_clamp_enable
)
83 uint32_t count
= cmd_buffer
->state
.dynamic
.viewport
.count
;
84 const VkViewport
*viewports
= cmd_buffer
->state
.dynamic
.viewport
.viewports
;
85 struct anv_state cc_state
=
86 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, count
* 8, 32);
88 for (uint32_t i
= 0; i
< count
; i
++) {
89 const VkViewport
*vp
= &viewports
[i
];
91 struct GENX(CC_VIEWPORT
) cc_viewport
= {
92 .MinimumDepth
= depth_clamp_enable
? vp
->minDepth
: 0.0f
,
93 .MaximumDepth
= depth_clamp_enable
? vp
->maxDepth
: 1.0f
,
96 GENX(CC_VIEWPORT_pack
)(NULL
, cc_state
.map
+ i
* 8, &cc_viewport
);
99 if (!cmd_buffer
->device
->info
.has_llc
)
100 anv_state_clflush(cc_state
);
102 anv_batch_emit(&cmd_buffer
->batch
,
103 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), cc
) {
104 cc
.CCViewportPointer
= cc_state
.offset
;
110 __emit_genx_sf_state(struct anv_cmd_buffer
*cmd_buffer
)
112 uint32_t sf_dw
[GENX(3DSTATE_SF_length
)];
113 struct GENX(3DSTATE_SF
) sf
= {
114 GENX(3DSTATE_SF_header
),
115 .LineWidth
= cmd_buffer
->state
.dynamic
.line_width
,
117 GENX(3DSTATE_SF_pack
)(NULL
, sf_dw
, &sf
);
119 anv_batch_emit_merge(&cmd_buffer
->batch
, sf_dw
,
120 cmd_buffer
->state
.pipeline
->gen8
.sf
);
123 #include "genxml/gen9_pack.h"
125 __emit_gen9_sf_state(struct anv_cmd_buffer
*cmd_buffer
)
127 uint32_t sf_dw
[GENX(3DSTATE_SF_length
)];
128 struct GEN9_3DSTATE_SF sf
= {
129 GEN9_3DSTATE_SF_header
,
130 .LineWidth
= cmd_buffer
->state
.dynamic
.line_width
,
132 GEN9_3DSTATE_SF_pack(NULL
, sf_dw
, &sf
);
134 anv_batch_emit_merge(&cmd_buffer
->batch
, sf_dw
,
135 cmd_buffer
->state
.pipeline
->gen8
.sf
);
139 __emit_sf_state(struct anv_cmd_buffer
*cmd_buffer
)
141 if (cmd_buffer
->device
->info
.is_cherryview
)
142 __emit_gen9_sf_state(cmd_buffer
);
144 __emit_genx_sf_state(cmd_buffer
);
148 genX(cmd_buffer_flush_dynamic_state
)(struct anv_cmd_buffer
*cmd_buffer
)
150 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
152 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
153 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)) {
154 __emit_sf_state(cmd_buffer
);
157 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
158 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)){
159 uint32_t raster_dw
[GENX(3DSTATE_RASTER_length
)];
160 struct GENX(3DSTATE_RASTER
) raster
= {
161 GENX(3DSTATE_RASTER_header
),
162 .GlobalDepthOffsetConstant
= cmd_buffer
->state
.dynamic
.depth_bias
.bias
,
163 .GlobalDepthOffsetScale
= cmd_buffer
->state
.dynamic
.depth_bias
.slope
,
164 .GlobalDepthOffsetClamp
= cmd_buffer
->state
.dynamic
.depth_bias
.clamp
166 GENX(3DSTATE_RASTER_pack
)(NULL
, raster_dw
, &raster
);
167 anv_batch_emit_merge(&cmd_buffer
->batch
, raster_dw
,
168 pipeline
->gen8
.raster
);
171 /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
172 * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
173 * across different state packets for gen8 and gen9. We handle that by
174 * using a big old #if switch here.
177 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
|
178 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
)) {
179 struct anv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
180 struct anv_state cc_state
=
181 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
182 GENX(COLOR_CALC_STATE_length
) * 4,
184 struct GENX(COLOR_CALC_STATE
) cc
= {
185 .BlendConstantColorRed
= cmd_buffer
->state
.dynamic
.blend_constants
[0],
186 .BlendConstantColorGreen
= cmd_buffer
->state
.dynamic
.blend_constants
[1],
187 .BlendConstantColorBlue
= cmd_buffer
->state
.dynamic
.blend_constants
[2],
188 .BlendConstantColorAlpha
= cmd_buffer
->state
.dynamic
.blend_constants
[3],
189 .StencilReferenceValue
= d
->stencil_reference
.front
& 0xff,
190 .BackFaceStencilReferenceValue
= d
->stencil_reference
.back
& 0xff,
192 GENX(COLOR_CALC_STATE_pack
)(NULL
, cc_state
.map
, &cc
);
194 if (!cmd_buffer
->device
->info
.has_llc
)
195 anv_state_clflush(cc_state
);
197 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ccp
) {
198 ccp
.ColorCalcStatePointer
= cc_state
.offset
;
199 ccp
.ColorCalcStatePointerValid
= true;
203 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
204 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
|
205 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
)) {
206 uint32_t wm_depth_stencil_dw
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
207 struct anv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
209 struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil
) = {
210 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
212 .StencilTestMask
= d
->stencil_compare_mask
.front
& 0xff,
213 .StencilWriteMask
= d
->stencil_write_mask
.front
& 0xff,
215 .BackfaceStencilTestMask
= d
->stencil_compare_mask
.back
& 0xff,
216 .BackfaceStencilWriteMask
= d
->stencil_write_mask
.back
& 0xff,
218 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, wm_depth_stencil_dw
,
221 anv_batch_emit_merge(&cmd_buffer
->batch
, wm_depth_stencil_dw
,
222 pipeline
->gen8
.wm_depth_stencil
);
225 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
) {
226 struct anv_state cc_state
=
227 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
228 GEN9_COLOR_CALC_STATE_length
* 4,
230 struct GEN9_COLOR_CALC_STATE cc
= {
231 .BlendConstantColorRed
= cmd_buffer
->state
.dynamic
.blend_constants
[0],
232 .BlendConstantColorGreen
= cmd_buffer
->state
.dynamic
.blend_constants
[1],
233 .BlendConstantColorBlue
= cmd_buffer
->state
.dynamic
.blend_constants
[2],
234 .BlendConstantColorAlpha
= cmd_buffer
->state
.dynamic
.blend_constants
[3],
236 GEN9_COLOR_CALC_STATE_pack(NULL
, cc_state
.map
, &cc
);
238 if (!cmd_buffer
->device
->info
.has_llc
)
239 anv_state_clflush(cc_state
);
241 anv_batch_emit(&cmd_buffer
->batch
, GEN9_3DSTATE_CC_STATE_POINTERS
, ccp
) {
242 ccp
.ColorCalcStatePointer
= cc_state
.offset
;
243 ccp
.ColorCalcStatePointerValid
= true;
247 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
248 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
|
249 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
250 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
)) {
251 uint32_t dwords
[GEN9_3DSTATE_WM_DEPTH_STENCIL_length
];
252 struct anv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
253 struct GEN9_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil
= {
254 GEN9_3DSTATE_WM_DEPTH_STENCIL_header
,
256 .StencilTestMask
= d
->stencil_compare_mask
.front
& 0xff,
257 .StencilWriteMask
= d
->stencil_write_mask
.front
& 0xff,
259 .BackfaceStencilTestMask
= d
->stencil_compare_mask
.back
& 0xff,
260 .BackfaceStencilWriteMask
= d
->stencil_write_mask
.back
& 0xff,
262 .StencilReferenceValue
= d
->stencil_reference
.front
& 0xff,
263 .BackfaceStencilReferenceValue
= d
->stencil_reference
.back
& 0xff,
265 GEN9_3DSTATE_WM_DEPTH_STENCIL_pack(NULL
, dwords
, &wm_depth_stencil
);
267 anv_batch_emit_merge(&cmd_buffer
->batch
, dwords
,
268 pipeline
->gen9
.wm_depth_stencil
);
272 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
273 ANV_CMD_DIRTY_INDEX_BUFFER
)) {
274 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_VF
), vf
) {
275 vf
.IndexedDrawCutIndexEnable
= pipeline
->primitive_restart
;
276 vf
.CutIndex
= cmd_buffer
->state
.restart_index
;
280 cmd_buffer
->state
.dirty
= 0;
283 void genX(CmdBindIndexBuffer
)(
284 VkCommandBuffer commandBuffer
,
287 VkIndexType indexType
)
289 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
290 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
292 static const uint32_t vk_to_gen_index_type
[] = {
293 [VK_INDEX_TYPE_UINT16
] = INDEX_WORD
,
294 [VK_INDEX_TYPE_UINT32
] = INDEX_DWORD
,
297 static const uint32_t restart_index_for_type
[] = {
298 [VK_INDEX_TYPE_UINT16
] = UINT16_MAX
,
299 [VK_INDEX_TYPE_UINT32
] = UINT32_MAX
,
302 cmd_buffer
->state
.restart_index
= restart_index_for_type
[indexType
];
304 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
305 ib
.IndexFormat
= vk_to_gen_index_type
[indexType
];
306 ib
.MemoryObjectControlState
= GENX(MOCS
);
307 ib
.BufferStartingAddress
=
308 (struct anv_address
) { buffer
->bo
, buffer
->offset
+ offset
};
309 ib
.BufferSize
= buffer
->size
- offset
;
312 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_INDEX_BUFFER
;
317 * Emit the HZ_OP packet in the sequence specified by the BDW PRM section
318 * entitled: "Optimized Depth Buffer Clear and/or Stencil Buffer Clear."
320 * \todo Enable Stencil Buffer-only clears
323 genX(cmd_buffer_emit_hz_op
)(struct anv_cmd_buffer
*cmd_buffer
,
324 enum blorp_hiz_op op
)
326 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
327 const struct anv_image_view
*iview
=
328 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
330 if (iview
== NULL
|| !anv_image_has_hiz(iview
->image
))
333 /* FINISHME: Implement multi-subpass HiZ */
334 if (cmd_buffer
->state
.pass
->subpass_count
> 1)
337 const uint32_t ds
= cmd_state
->subpass
->depth_stencil_attachment
;
339 /* Section 7.4. of the Vulkan 1.0.27 spec states:
341 * "The render area must be contained within the framebuffer dimensions."
343 * Therefore, the only way the extent of the render area can match that of
344 * the image view is if the render area offset equals (0, 0).
346 const bool full_surface_op
=
347 cmd_state
->render_area
.extent
.width
== iview
->extent
.width
&&
348 cmd_state
->render_area
.extent
.height
== iview
->extent
.height
;
350 assert(cmd_state
->render_area
.offset
.x
== 0 &&
351 cmd_state
->render_area
.offset
.y
== 0);
353 /* This variable corresponds to the Pixel Dim column in the table below */
354 struct isl_extent2d px_dim
;
356 /* Validate that we can perform the HZ operation and that it's necessary. */
358 case BLORP_HIZ_OP_DEPTH_CLEAR
:
359 if (cmd_buffer
->state
.pass
->attachments
[ds
].load_op
!=
360 VK_ATTACHMENT_LOAD_OP_CLEAR
)
363 /* Apply alignment restrictions. Despite the BDW PRM mentioning this is
364 * only needed for a depth buffer surface type of D16_UNORM, testing
365 * showed it to be necessary for other depth formats as well
369 /* Pre-SKL, HiZ has an 8x4 sample block. As the number of samples
370 * increases, the number of pixels representable by this block
371 * decreases by a factor of the sample dimensions. Sample dimensions
372 * scale following the MSAA interleaved pattern.
374 * Sample|Sample|Pixel
376 * ===================
383 * Table: Pixel Dimensions in a HiZ Sample Block Pre-SKL
385 /* This variable corresponds to the Sample Dim column in the table
388 const struct isl_extent2d sa_dim
=
389 isl_get_interleaved_msaa_px_size_sa(iview
->image
->samples
);
390 px_dim
.w
= 8 / sa_dim
.w
;
391 px_dim
.h
= 4 / sa_dim
.h
;
393 /* SKL+, the sample block becomes a "pixel block" so the expected
394 * pixel dimension is a constant 8x4 px for all sample counts.
396 px_dim
= (struct isl_extent2d
) { .w
= 8, .h
= 4};
399 if (!full_surface_op
) {
400 /* Fast depth clears clear an entire sample block at a time. As a
401 * result, the rectangle must be aligned to the pixel dimensions of
402 * a sample block for a successful operation.
404 * Fast clears can still work if the offset is aligned and the render
405 * area offset + extent touches the edge of a depth buffer whose extent
406 * is unaligned. This is because each physical HiZ miplevel is padded
407 * by the px_dim. In this case, the size of the clear rectangle will be
408 * padded later on in this function.
410 if (cmd_state
->render_area
.offset
.x
% px_dim
.w
||
411 cmd_state
->render_area
.offset
.y
% px_dim
.h
)
413 if (cmd_state
->render_area
.offset
.x
+
414 cmd_state
->render_area
.extent
.width
!= iview
->extent
.width
&&
415 cmd_state
->render_area
.extent
.width
% px_dim
.w
)
417 if (cmd_state
->render_area
.offset
.y
+
418 cmd_state
->render_area
.extent
.height
!= iview
->extent
.height
&&
419 cmd_state
->render_area
.extent
.height
% px_dim
.h
)
423 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
424 if (cmd_buffer
->state
.pass
->attachments
[ds
].store_op
!=
425 VK_ATTACHMENT_STORE_OP_STORE
)
428 case BLORP_HIZ_OP_HIZ_RESOLVE
:
429 /* If the render area covers the entire surface *and* load_op is either
430 * CLEAR or DONT_CARE then the previous contents of the depth buffer
431 * will be entirely discarded. In this case, we can skip the HiZ
434 * If the render area is not the full surface, we need to do
435 * the resolve because otherwise data outside the render area may get
436 * garbled by the resolve at the end of the render pass.
438 if (full_surface_op
&&
439 cmd_buffer
->state
.pass
->attachments
[ds
].load_op
!=
440 VK_ATTACHMENT_LOAD_OP_LOAD
)
443 case BLORP_HIZ_OP_NONE
:
444 unreachable("Invalid HiZ OP");
448 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
) {
450 case BLORP_HIZ_OP_DEPTH_CLEAR
:
451 hzp
.StencilBufferClearEnable
= VK_IMAGE_ASPECT_STENCIL_BIT
&
452 cmd_state
->attachments
[ds
].pending_clear_aspects
;
453 hzp
.DepthBufferClearEnable
= VK_IMAGE_ASPECT_DEPTH_BIT
&
454 cmd_state
->attachments
[ds
].pending_clear_aspects
;
455 hzp
.FullSurfaceDepthandStencilClear
= full_surface_op
;
456 hzp
.StencilClearValue
=
457 cmd_state
->attachments
[ds
].clear_value
.depthStencil
.stencil
& 0xff;
459 /* Mark aspects as cleared */
460 cmd_state
->attachments
[ds
].pending_clear_aspects
= 0;
462 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
463 hzp
.DepthBufferResolveEnable
= true;
465 case BLORP_HIZ_OP_HIZ_RESOLVE
:
466 hzp
.HierarchicalDepthBufferResolveEnable
= true;
468 case BLORP_HIZ_OP_NONE
:
469 unreachable("Invalid HiZ OP");
473 if (op
!= BLORP_HIZ_OP_DEPTH_CLEAR
) {
474 /* The Optimized HiZ resolve rectangle must be the size of the full RT
475 * and aligned to 8x4. The non-optimized Depth resolve rectangle must
476 * be the size of the full RT. The same alignment is assumed to be
479 hzp
.ClearRectangleXMin
= 0;
480 hzp
.ClearRectangleYMin
= 0;
481 hzp
.ClearRectangleXMax
= align_u32(iview
->extent
.width
, 8);
482 hzp
.ClearRectangleYMax
= align_u32(iview
->extent
.height
, 4);
484 /* This clear rectangle is aligned */
485 hzp
.ClearRectangleXMin
= cmd_state
->render_area
.offset
.x
;
486 hzp
.ClearRectangleYMin
= cmd_state
->render_area
.offset
.y
;
487 hzp
.ClearRectangleXMax
= cmd_state
->render_area
.offset
.x
+
488 align_u32(cmd_state
->render_area
.extent
.width
, px_dim
.width
);
489 hzp
.ClearRectangleYMax
= cmd_state
->render_area
.offset
.y
+
490 align_u32(cmd_state
->render_area
.extent
.height
, px_dim
.height
);
494 /* Due to a hardware issue, this bit MBZ */
495 hzp
.ScissorRectangleEnable
= false;
496 hzp
.NumberofMultisamples
= ffs(iview
->image
->samples
) - 1;
497 hzp
.SampleMask
= 0xFFFF;
500 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
501 pc
.PostSyncOperation
= WriteImmediateData
;
503 (struct anv_address
){ &cmd_buffer
->device
->workaround_bo
, 0 };
506 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
);
508 if (!full_surface_op
&& op
== BLORP_HIZ_OP_DEPTH_CLEAR
) {
509 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
510 pc
.DepthStallEnable
= true;
511 pc
.DepthCacheFlushEnable
= true;
516 /* Set of stage bits for which are pipelined, i.e. they get queued by the
517 * command streamer for later execution.
519 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
520 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
521 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
522 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
523 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
524 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
525 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
526 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
527 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
528 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
529 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
530 VK_PIPELINE_STAGE_TRANSFER_BIT | \
531 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
532 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
533 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
535 void genX(CmdSetEvent
)(
536 VkCommandBuffer commandBuffer
,
538 VkPipelineStageFlags stageMask
)
540 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
541 ANV_FROM_HANDLE(anv_event
, event
, _event
);
543 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
544 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
545 pc
.StallAtPixelScoreboard
= true;
546 pc
.CommandStreamerStallEnable
= true;
549 pc
.DestinationAddressType
= DAT_PPGTT
,
550 pc
.PostSyncOperation
= WriteImmediateData
,
551 pc
.Address
= (struct anv_address
) {
552 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
,
555 pc
.ImmediateData
= VK_EVENT_SET
;
559 void genX(CmdResetEvent
)(
560 VkCommandBuffer commandBuffer
,
562 VkPipelineStageFlags stageMask
)
564 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
565 ANV_FROM_HANDLE(anv_event
, event
, _event
);
567 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
568 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
569 pc
.StallAtPixelScoreboard
= true;
570 pc
.CommandStreamerStallEnable
= true;
573 pc
.DestinationAddressType
= DAT_PPGTT
;
574 pc
.PostSyncOperation
= WriteImmediateData
;
575 pc
.Address
= (struct anv_address
) {
576 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
,
579 pc
.ImmediateData
= VK_EVENT_RESET
;
583 void genX(CmdWaitEvents
)(
584 VkCommandBuffer commandBuffer
,
586 const VkEvent
* pEvents
,
587 VkPipelineStageFlags srcStageMask
,
588 VkPipelineStageFlags destStageMask
,
589 uint32_t memoryBarrierCount
,
590 const VkMemoryBarrier
* pMemoryBarriers
,
591 uint32_t bufferMemoryBarrierCount
,
592 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
593 uint32_t imageMemoryBarrierCount
,
594 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
596 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
597 for (uint32_t i
= 0; i
< eventCount
; i
++) {
598 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
600 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
601 sem
.WaitMode
= PollingMode
,
602 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
603 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
604 sem
.SemaphoreAddress
= (struct anv_address
) {
605 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
,
611 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
612 false, /* byRegion */
613 memoryBarrierCount
, pMemoryBarriers
,
614 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
615 imageMemoryBarrierCount
, pImageMemoryBarriers
);