src/intel/vulkan/gen8_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #if GEN_GEN == 8
  36 static void
  37 emit_viewport_state(struct anv_cmd_buffer *cmd_buffer,
  38                     uint32_t count, const VkViewport *viewports)
  39 {
  40    struct anv_state sf_clip_state =
  41       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 64, 64);
  42    struct anv_state cc_state =
  43       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
  44
  45    for (uint32_t i = 0; i < count; i++) {
  46       const VkViewport *vp = &viewports[i];
  47
  48       /* The gen7 state struct has just the matrix and guardband fields, the
  49        * gen8 struct adds the min/max viewport fields. */
  50       struct GENX(SF_CLIP_VIEWPORT) sf_clip_viewport = {
  51          .ViewportMatrixElementm00 = vp->width / 2,
  52          .ViewportMatrixElementm11 = vp->height / 2,
  53          .ViewportMatrixElementm22 = 1.0,
  54          .ViewportMatrixElementm30 = vp->x + vp->width / 2,
  55          .ViewportMatrixElementm31 = vp->y + vp->height / 2,
  56          .ViewportMatrixElementm32 = 0.0,
  57          .XMinClipGuardband = -1.0f,
  58          .XMaxClipGuardband = 1.0f,
  59          .YMinClipGuardband = -1.0f,
  60          .YMaxClipGuardband = 1.0f,
  61          .XMinViewPort = vp->x,
  62          .XMaxViewPort = vp->x + vp->width - 1,
  63          .YMinViewPort = vp->y,
  64          .YMaxViewPort = vp->y + vp->height - 1,
  65       };
  66
  67       struct GENX(CC_VIEWPORT) cc_viewport = {
  68          .MinimumDepth = vp->minDepth,
  69          .MaximumDepth = vp->maxDepth
  70       };
  71
  72       GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64,
  73                                  &sf_clip_viewport);
  74       GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport);
  75    }
  76
  77    if (!cmd_buffer->device->info.has_llc) {
  78       anv_state_clflush(sf_clip_state);
  79       anv_state_clflush(cc_state);
  80    }
  81
  82    anv_batch_emit(&cmd_buffer->batch,
  83                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC),
  84                   .CCViewportPointer = cc_state.offset);
  85    anv_batch_emit(&cmd_buffer->batch,
  86                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP),
  87                   .SFClipViewportPointer = sf_clip_state.offset);
  88 }
  89
  90 void
  91 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer)
  92 {
  93    if (cmd_buffer->state.dynamic.viewport.count > 0) {
  94       emit_viewport_state(cmd_buffer, cmd_buffer->state.dynamic.viewport.count,
  95                           cmd_buffer->state.dynamic.viewport.viewports);
  96    } else {
  97       /* If viewport count is 0, this is taken to mean "use the default" */
  98       emit_viewport_state(cmd_buffer, 1,
  99                           &(VkViewport) {
 100                              .x = 0.0f,
 101                              .y = 0.0f,
 102                              .width = cmd_buffer->state.framebuffer->width,
 103                              .height = cmd_buffer->state.framebuffer->height,
 104                              .minDepth = 0.0f,
 105                              .maxDepth = 1.0f,
 106                           });
 107    }
 108 }
 109 #endif
 110
 111 static void
 112 emit_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
 113 {
 114    anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM),
 115                   .RegisterOffset = reg,
 116                   .DataDWord = imm);
 117 }
 118
 119 #define GEN8_L3CNTLREG                  0x7034
 120
 121 void
 122 genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, bool enable_slm)
 123 {
 124    /* References for GL state:
 125     *
 126     * - commits e307cfa..228d5a3
 127     * - src/mesa/drivers/dri/i965/gen7_l3_state.c
 128     */
 129
 130    uint32_t val = enable_slm ?
 131       /* All = 48 ways; URB = 16 ways; DC and RO = 0, SLM = 1 */
 132       0x60000021 :
 133       /* All = 48 ways; URB = 48 ways; DC, RO and SLM = 0 */
 134       0x60000060;
 135    bool changed = cmd_buffer->state.current_l3_config != val;
 136
 137    if (changed) {
 138       /* According to the hardware docs, the L3 partitioning can only be changed
 139        * while the pipeline is completely drained and the caches are flushed,
 140        * which involves a first PIPE_CONTROL flush which stalls the pipeline and
 141        * initiates invalidation of the relevant caches...
 142        */
 143       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
 144                      .TextureCacheInvalidationEnable = true,
 145                      .ConstantCacheInvalidationEnable = true,
 146                      .InstructionCacheInvalidateEnable = true,
 147                      .DCFlushEnable = true,
 148                      .PostSyncOperation = NoWrite,
 149                      .CommandStreamerStallEnable = true);
 150
 151       /* ...followed by a second stalling flush which guarantees that
 152        * invalidation is complete when the L3 configuration registers are
 153        * modified.
 154        */
 155       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
 156                      .DCFlushEnable = true,
 157                      .PostSyncOperation = NoWrite,
 158                      .CommandStreamerStallEnable = true);
 159
 160       emit_lri(&cmd_buffer->batch, GEN8_L3CNTLREG, val);
 161       cmd_buffer->state.current_l3_config = val;
 162    }
 163 }
 164
 165 static void
 166 __emit_genx_sf_state(struct anv_cmd_buffer *cmd_buffer)
 167 {
 168       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 169       struct GENX(3DSTATE_SF) sf = {
 170          GENX(3DSTATE_SF_header),
 171          .LineWidth = cmd_buffer->state.dynamic.line_width,
 172       };
 173       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 174       /* FIXME: gen9.fs */
 175       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw,
 176                            cmd_buffer->state.pipeline->gen8.sf);
 177 }
 178
 179 #include "genxml/gen9_pack.h"
 180 static void
 181 __emit_gen9_sf_state(struct anv_cmd_buffer *cmd_buffer)
 182 {
 183       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 184       struct GEN9_3DSTATE_SF sf = {
 185          GEN9_3DSTATE_SF_header,
 186          .LineWidth = cmd_buffer->state.dynamic.line_width,
 187       };
 188       GEN9_3DSTATE_SF_pack(NULL, sf_dw, &sf);
 189       /* FIXME: gen9.fs */
 190       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw,
 191                            cmd_buffer->state.pipeline->gen8.sf);
 192 }
 193
 194 static void
 195 __emit_sf_state(struct anv_cmd_buffer *cmd_buffer)
 196 {
 197    if (cmd_buffer->device->info.is_cherryview)
 198       __emit_gen9_sf_state(cmd_buffer);
 199    else
 200       __emit_genx_sf_state(cmd_buffer);
 201 }
 202
 203 void
 204 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 205 {
 206    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 207
 208    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 209                                   ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
 210       __emit_sf_state(cmd_buffer);
 211    }
 212
 213    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 214                                   ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)){
 215       uint32_t raster_dw[GENX(3DSTATE_RASTER_length)];
 216       struct GENX(3DSTATE_RASTER) raster = {
 217          GENX(3DSTATE_RASTER_header),
 218          .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
 219          .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
 220          .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
 221       };
 222       GENX(3DSTATE_RASTER_pack)(NULL, raster_dw, &raster);
 223       anv_batch_emit_merge(&cmd_buffer->batch, raster_dw,
 224                            pipeline->gen8.raster);
 225    }
 226
 227    /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
 228     * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
 229     * across different state packets for gen8 and gen9. We handle that by
 230     * using a big old #if switch here.
 231     */
 232 #if GEN_GEN == 8
 233    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 234                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 235       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 236       struct anv_state cc_state =
 237          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 238                                             GENX(COLOR_CALC_STATE_length) * 4,
 239                                             64);
 240       struct GENX(COLOR_CALC_STATE) cc = {
 241          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 242          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 243          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 244          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 245          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 246          .BackFaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 247       };
 248       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 249
 250       if (!cmd_buffer->device->info.has_llc)
 251          anv_state_clflush(cc_state);
 252
 253       anv_batch_emit(&cmd_buffer->batch,
 254                      GENX(3DSTATE_CC_STATE_POINTERS),
 255                      .ColorCalcStatePointer = cc_state.offset,
 256                      .ColorCalcStatePointerValid = true);
 257    }
 258
 259    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 260                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 261                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 262       uint32_t wm_depth_stencil_dw[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
 263       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 264
 265       struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
 266          GENX(3DSTATE_WM_DEPTH_STENCIL_header),
 267
 268          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 269          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 270
 271          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 272          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 273       };
 274       GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, wm_depth_stencil_dw,
 275                                           &wm_depth_stencil);
 276
 277       anv_batch_emit_merge(&cmd_buffer->batch, wm_depth_stencil_dw,
 278                            pipeline->gen8.wm_depth_stencil);
 279    }
 280 #else
 281    if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
 282       struct anv_state cc_state =
 283          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 284                                             GEN9_COLOR_CALC_STATE_length * 4,
 285                                             64);
 286       struct GEN9_COLOR_CALC_STATE cc = {
 287          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 288          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 289          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 290          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 291       };
 292       GEN9_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
 293
 294       if (!cmd_buffer->device->info.has_llc)
 295          anv_state_clflush(cc_state);
 296
 297       anv_batch_emit(&cmd_buffer->batch,
 298                      GEN9_3DSTATE_CC_STATE_POINTERS,
 299                      .ColorCalcStatePointer = cc_state.offset,
 300                      .ColorCalcStatePointerValid = true);
 301    }
 302
 303    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 304                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 305                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
 306                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 307       uint32_t dwords[GEN9_3DSTATE_WM_DEPTH_STENCIL_length];
 308       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 309       struct GEN9_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil = {
 310          GEN9_3DSTATE_WM_DEPTH_STENCIL_header,
 311
 312          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 313          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 314
 315          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 316          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 317
 318          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 319          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 320       };
 321       GEN9_3DSTATE_WM_DEPTH_STENCIL_pack(NULL, dwords, &wm_depth_stencil);
 322
 323       anv_batch_emit_merge(&cmd_buffer->batch, dwords,
 324                            pipeline->gen9.wm_depth_stencil);
 325    }
 326 #endif
 327
 328    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 329                                   ANV_CMD_DIRTY_INDEX_BUFFER)) {
 330       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF),
 331          .IndexedDrawCutIndexEnable = pipeline->primitive_restart,
 332          .CutIndex = cmd_buffer->state.restart_index,
 333       );
 334    }
 335
 336    cmd_buffer->state.dirty = 0;
 337 }
 338
 339 void genX(CmdBindIndexBuffer)(
 340     VkCommandBuffer                             commandBuffer,
 341     VkBuffer                                    _buffer,
 342     VkDeviceSize                                offset,
 343     VkIndexType                                 indexType)
 344 {
 345    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 346    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 347
 348    static const uint32_t vk_to_gen_index_type[] = {
 349       [VK_INDEX_TYPE_UINT16]                    = INDEX_WORD,
 350       [VK_INDEX_TYPE_UINT32]                    = INDEX_DWORD,
 351    };
 352
 353    static const uint32_t restart_index_for_type[] = {
 354       [VK_INDEX_TYPE_UINT16]                    = UINT16_MAX,
 355       [VK_INDEX_TYPE_UINT32]                    = UINT32_MAX,
 356    };
 357
 358    cmd_buffer->state.restart_index = restart_index_for_type[indexType];
 359
 360    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER),
 361                   .IndexFormat = vk_to_gen_index_type[indexType],
 362                   .MemoryObjectControlState = GENX(MOCS),
 363                   .BufferStartingAddress = { buffer->bo, buffer->offset + offset },
 364                   .BufferSize = buffer->size - offset);
 365
 366    cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 367 }
 368
 369 static VkResult
 370 flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
 371 {
 372    struct anv_device *device = cmd_buffer->device;
 373    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 374    struct anv_state surfaces = { 0, }, samplers = { 0, };
 375    VkResult result;
 376
 377    result = anv_cmd_buffer_emit_samplers(cmd_buffer,
 378                                          MESA_SHADER_COMPUTE, &samplers);
 379    if (result != VK_SUCCESS)
 380       return result;
 381    result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
 382                                               MESA_SHADER_COMPUTE, &surfaces);
 383    if (result != VK_SUCCESS)
 384       return result;
 385
 386    struct anv_state push_state = anv_cmd_buffer_cs_push_constants(cmd_buffer);
 387
 388    const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
 389    const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
 390
 391    unsigned local_id_dwords = cs_prog_data->local_invocation_id_regs * 8;
 392    unsigned push_constant_data_size =
 393       (prog_data->nr_params + local_id_dwords) * 4;
 394    unsigned reg_aligned_constant_size = ALIGN(push_constant_data_size, 32);
 395    unsigned push_constant_regs = reg_aligned_constant_size / 32;
 396
 397    if (push_state.alloc_size) {
 398       anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD),
 399                      .CURBETotalDataLength = push_state.alloc_size,
 400                      .CURBEDataStartAddress = push_state.offset);
 401    }
 402
 403    assert(prog_data->total_shared <= 64 * 1024);
 404    uint32_t slm_size = 0;
 405    if (prog_data->total_shared > 0) {
 406       /* slm_size is in 4k increments, but must be a power of 2. */
 407       slm_size = 4 * 1024;
 408       while (slm_size < prog_data->total_shared)
 409          slm_size <<= 1;
 410       slm_size /= 4 * 1024;
 411    }
 412
 413    struct anv_state state =
 414       anv_state_pool_emit(&device->dynamic_state_pool,
 415                           GENX(INTERFACE_DESCRIPTOR_DATA), 64,
 416                           .KernelStartPointer = pipeline->cs_simd,
 417                           .KernelStartPointerHigh = 0,
 418                           .BindingTablePointer = surfaces.offset,
 419                           .BindingTableEntryCount = 0,
 420                           .SamplerStatePointer = samplers.offset,
 421                           .SamplerCount = 0,
 422                           .ConstantIndirectURBEntryReadLength = push_constant_regs,
 423                           .ConstantURBEntryReadOffset = 0,
 424                           .BarrierEnable = cs_prog_data->uses_barrier,
 425                           .SharedLocalMemorySize = slm_size,
 426                           .NumberofThreadsinGPGPUThreadGroup =
 427                              pipeline->cs_thread_width_max);
 428
 429    uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
 430    anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD),
 431                   .InterfaceDescriptorTotalLength = size,
 432                   .InterfaceDescriptorDataStartAddress = state.offset);
 433
 434    return VK_SUCCESS;
 435 }
 436
 437 void
 438 genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
 439 {
 440    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 441    const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
 442    VkResult result;
 443
 444    assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
 445
 446    bool needs_slm = cs_prog_data->base.total_shared > 0;
 447    genX(cmd_buffer_config_l3)(cmd_buffer, needs_slm);
 448
 449    genX(flush_pipeline_select_gpgpu)(cmd_buffer);
 450
 451    if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
 452       anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
 453
 454    if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
 455        (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
 456       result = flush_compute_descriptor_set(cmd_buffer);
 457       assert(result == VK_SUCCESS);
 458       cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
 459    }
 460
 461    cmd_buffer->state.compute_dirty = 0;
 462 }
 463
 464 void genX(CmdSetEvent)(
 465     VkCommandBuffer                             commandBuffer,
 466     VkEvent                                     _event,
 467     VkPipelineStageFlags                        stageMask)
 468 {
 469    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 470    ANV_FROM_HANDLE(anv_event, event, _event);
 471
 472    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
 473                   .DestinationAddressType = DAT_PPGTT,
 474                   .PostSyncOperation = WriteImmediateData,
 475                   .Address = {
 476                      &cmd_buffer->device->dynamic_state_block_pool.bo,
 477                      event->state.offset
 478                    },
 479                   .ImmediateData = VK_EVENT_SET);
 480 }
 481
 482 void genX(CmdResetEvent)(
 483     VkCommandBuffer                             commandBuffer,
 484     VkEvent                                     _event,
 485     VkPipelineStageFlags                        stageMask)
 486 {
 487    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 488    ANV_FROM_HANDLE(anv_event, event, _event);
 489
 490    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
 491                   .DestinationAddressType = DAT_PPGTT,
 492                   .PostSyncOperation = WriteImmediateData,
 493                   .Address = {
 494                      &cmd_buffer->device->dynamic_state_block_pool.bo,
 495                      event->state.offset
 496                    },
 497                   .ImmediateData = VK_EVENT_RESET);
 498 }
 499
 500 void genX(CmdWaitEvents)(
 501     VkCommandBuffer                             commandBuffer,
 502     uint32_t                                    eventCount,
 503     const VkEvent*                              pEvents,
 504     VkPipelineStageFlags                        srcStageMask,
 505     VkPipelineStageFlags                        destStageMask,
 506     uint32_t                                    memoryBarrierCount,
 507     const VkMemoryBarrier*                      pMemoryBarriers,
 508     uint32_t                                    bufferMemoryBarrierCount,
 509     const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
 510     uint32_t                                    imageMemoryBarrierCount,
 511     const VkImageMemoryBarrier*                 pImageMemoryBarriers)
 512 {
 513    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 514    for (uint32_t i = 0; i < eventCount; i++) {
 515       ANV_FROM_HANDLE(anv_event, event, pEvents[i]);
 516
 517       anv_batch_emit(&cmd_buffer->batch, GENX(MI_SEMAPHORE_WAIT),
 518                      .WaitMode = PollingMode,
 519                      .CompareOperation = COMPARE_SAD_EQUAL_SDD,
 520                      .SemaphoreDataDword = VK_EVENT_SET,
 521                      .SemaphoreAddress = {
 522                         &cmd_buffer->device->dynamic_state_block_pool.bo,
 523                         event->state.offset
 524                      });
 525    }
 526
 527    genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
 528                             false, /* byRegion */
 529                             memoryBarrierCount, pMemoryBarriers,
 530                             bufferMemoryBarrierCount, pBufferMemoryBarriers,
 531                             imageMemoryBarrierCount, pImageMemoryBarriers);
 532 }