src/intel/vulkan/gen8_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #if GEN_GEN == 8
  36 void
  37 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer)
  38 {
  39    uint32_t count = cmd_buffer->state.dynamic.viewport.count;
  40    const VkViewport *viewports = cmd_buffer->state.dynamic.viewport.viewports;
  41    struct anv_state sf_clip_state =
  42       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 64, 64);
  43
  44    for (uint32_t i = 0; i < count; i++) {
  45       const VkViewport *vp = &viewports[i];
  46
  47       /* The gen7 state struct has just the matrix and guardband fields, the
  48        * gen8 struct adds the min/max viewport fields. */
  49       struct GENX(SF_CLIP_VIEWPORT) sf_clip_viewport = {
  50          .ViewportMatrixElementm00 = vp->width / 2,
  51          .ViewportMatrixElementm11 = vp->height / 2,
  52          .ViewportMatrixElementm22 = 1.0,
  53          .ViewportMatrixElementm30 = vp->x + vp->width / 2,
  54          .ViewportMatrixElementm31 = vp->y + vp->height / 2,
  55          .ViewportMatrixElementm32 = 0.0,
  56          .XMinClipGuardband = -1.0f,
  57          .XMaxClipGuardband = 1.0f,
  58          .YMinClipGuardband = -1.0f,
  59          .YMaxClipGuardband = 1.0f,
  60          .XMinViewPort = vp->x,
  61          .XMaxViewPort = vp->x + vp->width - 1,
  62          .YMinViewPort = vp->y,
  63          .YMaxViewPort = vp->y + vp->height - 1,
  64       };
  65
  66       GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64,
  67                                  &sf_clip_viewport);
  68    }
  69
  70    if (!cmd_buffer->device->info.has_llc)
  71       anv_state_clflush(sf_clip_state);
  72
  73    anv_batch_emit(&cmd_buffer->batch,
  74                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), clip) {
  75       clip.SFClipViewportPointer = sf_clip_state.offset;
  76    }
  77 }
  78
  79 void
  80 gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
  81                                     bool depth_clamp_enable)
  82 {
  83    uint32_t count = cmd_buffer->state.dynamic.viewport.count;
  84    const VkViewport *viewports = cmd_buffer->state.dynamic.viewport.viewports;
  85    struct anv_state cc_state =
  86       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
  87
  88    for (uint32_t i = 0; i < count; i++) {
  89       const VkViewport *vp = &viewports[i];
  90
  91       struct GENX(CC_VIEWPORT) cc_viewport = {
  92          .MinimumDepth = depth_clamp_enable ? vp->minDepth : 0.0f,
  93          .MaximumDepth = depth_clamp_enable ? vp->maxDepth : 1.0f,
  94       };
  95
  96       GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport);
  97    }
  98
  99    if (!cmd_buffer->device->info.has_llc)
 100       anv_state_clflush(cc_state);
 101
 102    anv_batch_emit(&cmd_buffer->batch,
 103                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) {
 104       cc.CCViewportPointer = cc_state.offset;
 105    }
 106 }
 107 #endif
 108
 109 static void
 110 __emit_genx_sf_state(struct anv_cmd_buffer *cmd_buffer)
 111 {
 112       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 113       struct GENX(3DSTATE_SF) sf = {
 114          GENX(3DSTATE_SF_header),
 115          .LineWidth = cmd_buffer->state.dynamic.line_width,
 116       };
 117       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 118       /* FIXME: gen9.fs */
 119       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw,
 120                            cmd_buffer->state.pipeline->gen8.sf);
 121 }
 122
 123 #include "genxml/gen9_pack.h"
 124 static void
 125 __emit_gen9_sf_state(struct anv_cmd_buffer *cmd_buffer)
 126 {
 127       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 128       struct GEN9_3DSTATE_SF sf = {
 129          GEN9_3DSTATE_SF_header,
 130          .LineWidth = cmd_buffer->state.dynamic.line_width,
 131       };
 132       GEN9_3DSTATE_SF_pack(NULL, sf_dw, &sf);
 133       /* FIXME: gen9.fs */
 134       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw,
 135                            cmd_buffer->state.pipeline->gen8.sf);
 136 }
 137
 138 static void
 139 __emit_sf_state(struct anv_cmd_buffer *cmd_buffer)
 140 {
 141    if (cmd_buffer->device->info.is_cherryview)
 142       __emit_gen9_sf_state(cmd_buffer);
 143    else
 144       __emit_genx_sf_state(cmd_buffer);
 145 }
 146
 147 void
 148 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 149 {
 150    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 151
 152    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 153                                   ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
 154       __emit_sf_state(cmd_buffer);
 155    }
 156
 157    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 158                                   ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)){
 159       uint32_t raster_dw[GENX(3DSTATE_RASTER_length)];
 160       struct GENX(3DSTATE_RASTER) raster = {
 161          GENX(3DSTATE_RASTER_header),
 162          .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
 163          .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
 164          .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
 165       };
 166       GENX(3DSTATE_RASTER_pack)(NULL, raster_dw, &raster);
 167       anv_batch_emit_merge(&cmd_buffer->batch, raster_dw,
 168                            pipeline->gen8.raster);
 169    }
 170
 171    /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
 172     * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
 173     * across different state packets for gen8 and gen9. We handle that by
 174     * using a big old #if switch here.
 175     */
 176 #if GEN_GEN == 8
 177    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 178                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 179       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 180       struct anv_state cc_state =
 181          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 182                                             GENX(COLOR_CALC_STATE_length) * 4,
 183                                             64);
 184       struct GENX(COLOR_CALC_STATE) cc = {
 185          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 186          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 187          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 188          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 189          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 190          .BackFaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 191       };
 192       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 193
 194       if (!cmd_buffer->device->info.has_llc)
 195          anv_state_clflush(cc_state);
 196
 197       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
 198          ccp.ColorCalcStatePointer        = cc_state.offset;
 199          ccp.ColorCalcStatePointerValid   = true;
 200       }
 201    }
 202
 203    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 204                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 205                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 206       uint32_t wm_depth_stencil_dw[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
 207       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 208
 209       struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
 210          GENX(3DSTATE_WM_DEPTH_STENCIL_header),
 211
 212          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 213          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 214
 215          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 216          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 217       };
 218       GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, wm_depth_stencil_dw,
 219                                           &wm_depth_stencil);
 220
 221       anv_batch_emit_merge(&cmd_buffer->batch, wm_depth_stencil_dw,
 222                            pipeline->gen8.wm_depth_stencil);
 223    }
 224 #else
 225    if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
 226       struct anv_state cc_state =
 227          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 228                                             GEN9_COLOR_CALC_STATE_length * 4,
 229                                             64);
 230       struct GEN9_COLOR_CALC_STATE cc = {
 231          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 232          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 233          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 234          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 235       };
 236       GEN9_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
 237
 238       if (!cmd_buffer->device->info.has_llc)
 239          anv_state_clflush(cc_state);
 240
 241       anv_batch_emit(&cmd_buffer->batch, GEN9_3DSTATE_CC_STATE_POINTERS, ccp) {
 242          ccp.ColorCalcStatePointer = cc_state.offset;
 243          ccp.ColorCalcStatePointerValid = true;
 244       }
 245    }
 246
 247    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 248                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 249                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
 250                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 251       uint32_t dwords[GEN9_3DSTATE_WM_DEPTH_STENCIL_length];
 252       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 253       struct GEN9_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil = {
 254          GEN9_3DSTATE_WM_DEPTH_STENCIL_header,
 255
 256          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 257          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 258
 259          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 260          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 261
 262          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 263          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 264       };
 265       GEN9_3DSTATE_WM_DEPTH_STENCIL_pack(NULL, dwords, &wm_depth_stencil);
 266
 267       anv_batch_emit_merge(&cmd_buffer->batch, dwords,
 268                            pipeline->gen9.wm_depth_stencil);
 269    }
 270 #endif
 271
 272    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 273                                   ANV_CMD_DIRTY_INDEX_BUFFER)) {
 274       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF), vf) {
 275          vf.IndexedDrawCutIndexEnable  = pipeline->primitive_restart;
 276          vf.CutIndex                   = cmd_buffer->state.restart_index;
 277       }
 278    }
 279
 280    cmd_buffer->state.dirty = 0;
 281 }
 282
 283 void genX(CmdBindIndexBuffer)(
 284     VkCommandBuffer                             commandBuffer,
 285     VkBuffer                                    _buffer,
 286     VkDeviceSize                                offset,
 287     VkIndexType                                 indexType)
 288 {
 289    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 290    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 291
 292    static const uint32_t vk_to_gen_index_type[] = {
 293       [VK_INDEX_TYPE_UINT16]                    = INDEX_WORD,
 294       [VK_INDEX_TYPE_UINT32]                    = INDEX_DWORD,
 295    };
 296
 297    static const uint32_t restart_index_for_type[] = {
 298       [VK_INDEX_TYPE_UINT16]                    = UINT16_MAX,
 299       [VK_INDEX_TYPE_UINT32]                    = UINT32_MAX,
 300    };
 301
 302    cmd_buffer->state.restart_index = restart_index_for_type[indexType];
 303
 304    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
 305       ib.IndexFormat                = vk_to_gen_index_type[indexType];
 306       ib.MemoryObjectControlState   = GENX(MOCS);
 307       ib.BufferStartingAddress      =
 308          (struct anv_address) { buffer->bo, buffer->offset + offset };
 309       ib.BufferSize                 = buffer->size - offset;
 310    }
 311
 312    cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 313 }
 314
 315
 316 /**
 317  * Emit the HZ_OP packet in the sequence specified by the BDW PRM section
 318  * entitled: "Optimized Depth Buffer Clear and/or Stencil Buffer Clear."
 319  *
 320  * \todo Enable Stencil Buffer-only clears
 321  */
 322 void
 323 genX(cmd_buffer_emit_hz_op)(struct anv_cmd_buffer *cmd_buffer,
 324                           enum blorp_hiz_op op)
 325 {
 326    struct anv_cmd_state *cmd_state = &cmd_buffer->state;
 327    const struct anv_image_view *iview =
 328       anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
 329
 330    if (iview == NULL || !anv_image_has_hiz(iview->image))
 331       return;
 332
 333    /* FINISHME: Implement multi-subpass HiZ */
 334    if (cmd_buffer->state.pass->subpass_count > 1)
 335       return;
 336
 337    const uint32_t ds = cmd_state->subpass->depth_stencil_attachment;
 338
 339    /* Section 7.4. of the Vulkan 1.0.27 spec states:
 340     *
 341     *   "The render area must be contained within the framebuffer dimensions."
 342     *
 343     * Therefore, the only way the extent of the render area can match that of
 344     * the image view is if the render area offset equals (0, 0).
 345     */
 346    const bool full_surface_op =
 347              cmd_state->render_area.extent.width == iview->extent.width &&
 348              cmd_state->render_area.extent.height == iview->extent.height;
 349    if (full_surface_op)
 350       assert(cmd_state->render_area.offset.x == 0 &&
 351              cmd_state->render_area.offset.y == 0);
 352
 353    bool depth_clear;
 354    bool stencil_clear;
 355
 356    /* This variable corresponds to the Pixel Dim column in the table below */
 357    struct isl_extent2d px_dim;
 358
 359    /* Validate that we can perform the HZ operation and that it's necessary. */
 360    switch (op) {
 361    case BLORP_HIZ_OP_DEPTH_CLEAR:
 362       stencil_clear = VK_IMAGE_ASPECT_STENCIL_BIT &
 363                   cmd_state->attachments[ds].pending_clear_aspects;
 364       depth_clear = VK_IMAGE_ASPECT_DEPTH_BIT &
 365                     cmd_state->attachments[ds].pending_clear_aspects;
 366
 367       /* Apply alignment restrictions. Despite the BDW PRM mentioning this is
 368        * only needed for a depth buffer surface type of D16_UNORM, testing
 369        * showed it to be necessary for other depth formats as well
 370        * (e.g., D32_FLOAT).
 371        */
 372 #if GEN_GEN == 8
 373       /* Pre-SKL, HiZ has an 8x4 sample block. As the number of samples
 374        * increases, the number of pixels representable by this block
 375        * decreases by a factor of the sample dimensions. Sample dimensions
 376        * scale following the MSAA interleaved pattern.
 377        *
 378        * Sample|Sample|Pixel
 379        * Count |Dim   |Dim
 380        * ===================
 381        *    1  | 1x1  | 8x4
 382        *    2  | 2x1  | 4x4
 383        *    4  | 2x2  | 4x2
 384        *    8  | 4x2  | 2x2
 385        *   16  | 4x4  | 2x1
 386        *
 387        * Table: Pixel Dimensions in a HiZ Sample Block Pre-SKL
 388        */
 389       /* This variable corresponds to the Sample Dim column in the table
 390        * above.
 391        */
 392       const struct isl_extent2d sa_dim =
 393          isl_get_interleaved_msaa_px_size_sa(iview->image->samples);
 394       px_dim.w = 8 / sa_dim.w;
 395       px_dim.h = 4 / sa_dim.h;
 396 #elif GEN_GEN >= 9
 397       /* SKL+, the sample block becomes a "pixel block" so the expected
 398        * pixel dimension is a constant 8x4 px for all sample counts.
 399        */
 400       px_dim = (struct isl_extent2d) { .w = 8, .h = 4};
 401 #endif
 402
 403       if (depth_clear && !full_surface_op) {
 404          /* Fast depth clears clear an entire sample block at a time. As a
 405           * result, the rectangle must be aligned to the pixel dimensions of
 406           * a sample block for a successful operation.
 407           *
 408           * Fast clears can still work if the offset is aligned and the render
 409           * area offset + extent touches the edge of a depth buffer whose extent
 410           * is unaligned. This is because each physical HiZ miplevel is padded
 411           * by the px_dim. In this case, the size of the clear rectangle will be
 412           * padded later on in this function.
 413           */
 414          if (cmd_state->render_area.offset.x % px_dim.w ||
 415              cmd_state->render_area.offset.y % px_dim.h)
 416             depth_clear = false;
 417          if (cmd_state->render_area.offset.x +
 418              cmd_state->render_area.extent.width != iview->extent.width &&
 419              cmd_state->render_area.extent.width % px_dim.w)
 420             depth_clear = false;
 421          if (cmd_state->render_area.offset.y +
 422              cmd_state->render_area.extent.height != iview->extent.height &&
 423              cmd_state->render_area.extent.height % px_dim.h)
 424             depth_clear = false;
 425       }
 426
 427       if (!depth_clear) {
 428          if (stencil_clear) {
 429             /* Stencil has no alignment requirements */
 430             px_dim = (struct isl_extent2d) { .w = 1, .h = 1};
 431          } else {
 432             /* Nothing to clear */
 433             return;
 434          }
 435       }
 436       break;
 437    case BLORP_HIZ_OP_DEPTH_RESOLVE:
 438       if (cmd_buffer->state.pass->attachments[ds].store_op !=
 439           VK_ATTACHMENT_STORE_OP_STORE)
 440          return;
 441       break;
 442    case BLORP_HIZ_OP_HIZ_RESOLVE:
 443       /* If the render area covers the entire surface *and* load_op is either
 444        * CLEAR or DONT_CARE then the previous contents of the depth buffer
 445        * will be entirely discarded.  In this case, we can skip the HiZ
 446        * resolve.
 447        *
 448        * If the render area is not the full surface, we need to do
 449        * the resolve because otherwise data outside the render area may get
 450        * garbled by the resolve at the end of the render pass.
 451        */
 452       if (full_surface_op &&
 453           cmd_buffer->state.pass->attachments[ds].load_op !=
 454           VK_ATTACHMENT_LOAD_OP_LOAD)
 455          return;
 456       break;
 457    case BLORP_HIZ_OP_NONE:
 458       unreachable("Invalid HiZ OP");
 459       break;
 460    }
 461
 462    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_WM_HZ_OP), hzp) {
 463       switch (op) {
 464       case BLORP_HIZ_OP_DEPTH_CLEAR:
 465          hzp.StencilBufferClearEnable = stencil_clear;
 466          hzp.DepthBufferClearEnable = depth_clear;
 467          hzp.FullSurfaceDepthandStencilClear = full_surface_op;
 468          hzp.StencilClearValue =
 469             cmd_state->attachments[ds].clear_value.depthStencil.stencil & 0xff;
 470          break;
 471       case BLORP_HIZ_OP_DEPTH_RESOLVE:
 472          hzp.DepthBufferResolveEnable = true;
 473          break;
 474       case BLORP_HIZ_OP_HIZ_RESOLVE:
 475          hzp.HierarchicalDepthBufferResolveEnable = true;
 476          break;
 477       case BLORP_HIZ_OP_NONE:
 478          unreachable("Invalid HiZ OP");
 479          break;
 480       }
 481
 482       if (op != BLORP_HIZ_OP_DEPTH_CLEAR) {
 483          /* The Optimized HiZ resolve rectangle must be the size of the full RT
 484           * and aligned to 8x4. The non-optimized Depth resolve rectangle must
 485           * be the size of the full RT. The same alignment is assumed to be
 486           * required.
 487           */
 488          hzp.ClearRectangleXMin = 0;
 489          hzp.ClearRectangleYMin = 0;
 490          hzp.ClearRectangleXMax = align_u32(iview->extent.width, 8);
 491          hzp.ClearRectangleYMax = align_u32(iview->extent.height, 4);
 492       } else {
 493          /* Contrary to the HW docs both fields are inclusive */
 494          hzp.ClearRectangleXMin = cmd_state->render_area.offset.x;
 495          hzp.ClearRectangleYMin = cmd_state->render_area.offset.y;
 496          /* Contrary to the HW docs both fields are exclusive */
 497          hzp.ClearRectangleXMax = cmd_state->render_area.offset.x +
 498             align_u32(cmd_state->render_area.extent.width, px_dim.width);
 499          hzp.ClearRectangleYMax = cmd_state->render_area.offset.y +
 500             align_u32(cmd_state->render_area.extent.height, px_dim.height);
 501       }
 502
 503
 504       /* Due to a hardware issue, this bit MBZ */
 505       hzp.ScissorRectangleEnable = false;
 506       hzp.NumberofMultisamples = ffs(iview->image->samples) - 1;
 507       hzp.SampleMask = 0xFFFF;
 508    }
 509
 510    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 511       pc.PostSyncOperation = WriteImmediateData;
 512       pc.Address =
 513          (struct anv_address){ &cmd_buffer->device->workaround_bo, 0 };
 514    }
 515
 516    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_WM_HZ_OP), hzp);
 517
 518    /* Perform clear specific flushing and state updates */
 519    if (op == BLORP_HIZ_OP_DEPTH_CLEAR) {
 520       if (depth_clear && !full_surface_op) {
 521          anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 522             pc.DepthStallEnable = true;
 523             pc.DepthCacheFlushEnable = true;
 524          }
 525       }
 526
 527       /* Remove cleared aspects from the pending mask */
 528       if (stencil_clear) {
 529          cmd_state->attachments[ds].pending_clear_aspects &=
 530             ~VK_IMAGE_ASPECT_STENCIL_BIT;
 531       }
 532       if (depth_clear) {
 533          cmd_state->attachments[ds].pending_clear_aspects &=
 534             ~VK_IMAGE_ASPECT_DEPTH_BIT;
 535       }
 536    }
 537 }
 538
 539 /* Set of stage bits for which are pipelined, i.e. they get queued by the
 540  * command streamer for later execution.
 541  */
 542 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
 543    (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
 544     VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
 545     VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
 546     VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
 547     VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
 548     VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
 549     VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
 550     VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
 551     VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
 552     VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
 553     VK_PIPELINE_STAGE_TRANSFER_BIT | \
 554     VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
 555     VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
 556     VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
 557
 558 void genX(CmdSetEvent)(
 559     VkCommandBuffer                             commandBuffer,
 560     VkEvent                                     _event,
 561     VkPipelineStageFlags                        stageMask)
 562 {
 563    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 564    ANV_FROM_HANDLE(anv_event, event, _event);
 565
 566    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 567       if (stageMask & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
 568          pc.StallAtPixelScoreboard = true;
 569          pc.CommandStreamerStallEnable = true;
 570       }
 571
 572       pc.DestinationAddressType  = DAT_PPGTT,
 573       pc.PostSyncOperation       = WriteImmediateData,
 574       pc.Address = (struct anv_address) {
 575          &cmd_buffer->device->dynamic_state_block_pool.bo,
 576          event->state.offset
 577       };
 578       pc.ImmediateData           = VK_EVENT_SET;
 579    }
 580 }
 581
 582 void genX(CmdResetEvent)(
 583     VkCommandBuffer                             commandBuffer,
 584     VkEvent                                     _event,
 585     VkPipelineStageFlags                        stageMask)
 586 {
 587    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 588    ANV_FROM_HANDLE(anv_event, event, _event);
 589
 590    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 591       if (stageMask & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
 592          pc.StallAtPixelScoreboard = true;
 593          pc.CommandStreamerStallEnable = true;
 594       }
 595
 596       pc.DestinationAddressType  = DAT_PPGTT;
 597       pc.PostSyncOperation       = WriteImmediateData;
 598       pc.Address = (struct anv_address) {
 599          &cmd_buffer->device->dynamic_state_block_pool.bo,
 600          event->state.offset
 601       };
 602       pc.ImmediateData           = VK_EVENT_RESET;
 603    }
 604 }
 605
 606 void genX(CmdWaitEvents)(
 607     VkCommandBuffer                             commandBuffer,
 608     uint32_t                                    eventCount,
 609     const VkEvent*                              pEvents,
 610     VkPipelineStageFlags                        srcStageMask,
 611     VkPipelineStageFlags                        destStageMask,
 612     uint32_t                                    memoryBarrierCount,
 613     const VkMemoryBarrier*                      pMemoryBarriers,
 614     uint32_t                                    bufferMemoryBarrierCount,
 615     const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
 616     uint32_t                                    imageMemoryBarrierCount,
 617     const VkImageMemoryBarrier*                 pImageMemoryBarriers)
 618 {
 619    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 620    for (uint32_t i = 0; i < eventCount; i++) {
 621       ANV_FROM_HANDLE(anv_event, event, pEvents[i]);
 622
 623       anv_batch_emit(&cmd_buffer->batch, GENX(MI_SEMAPHORE_WAIT), sem) {
 624          sem.WaitMode            = PollingMode,
 625          sem.CompareOperation    = COMPARE_SAD_EQUAL_SDD,
 626          sem.SemaphoreDataDword  = VK_EVENT_SET,
 627          sem.SemaphoreAddress = (struct anv_address) {
 628             &cmd_buffer->device->dynamic_state_block_pool.bo,
 629             event->state.offset
 630          };
 631       }
 632    }
 633
 634    genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
 635                             false, /* byRegion */
 636                             memoryBarrierCount, pMemoryBarriers,
 637                             bufferMemoryBarrierCount, pBufferMemoryBarriers,
 638                             imageMemoryBarrierCount, pImageMemoryBarriers);
 639 }