2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
37 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
)
39 uint32_t count
= cmd_buffer
->state
.dynamic
.viewport
.count
;
40 const VkViewport
*viewports
= cmd_buffer
->state
.dynamic
.viewport
.viewports
;
41 struct anv_state sf_clip_state
=
42 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, count
* 64, 64);
44 for (uint32_t i
= 0; i
< count
; i
++) {
45 const VkViewport
*vp
= &viewports
[i
];
47 /* The gen7 state struct has just the matrix and guardband fields, the
48 * gen8 struct adds the min/max viewport fields. */
49 struct GENX(SF_CLIP_VIEWPORT
) sf_clip_viewport
= {
50 .ViewportMatrixElementm00
= vp
->width
/ 2,
51 .ViewportMatrixElementm11
= vp
->height
/ 2,
52 .ViewportMatrixElementm22
= 1.0,
53 .ViewportMatrixElementm30
= vp
->x
+ vp
->width
/ 2,
54 .ViewportMatrixElementm31
= vp
->y
+ vp
->height
/ 2,
55 .ViewportMatrixElementm32
= 0.0,
56 .XMinClipGuardband
= -1.0f
,
57 .XMaxClipGuardband
= 1.0f
,
58 .YMinClipGuardband
= -1.0f
,
59 .YMaxClipGuardband
= 1.0f
,
60 .XMinViewPort
= vp
->x
,
61 .XMaxViewPort
= vp
->x
+ vp
->width
- 1,
62 .YMinViewPort
= vp
->y
,
63 .YMaxViewPort
= vp
->y
+ vp
->height
- 1,
66 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_state
.map
+ i
* 64,
70 if (!cmd_buffer
->device
->info
.has_llc
)
71 anv_state_clflush(sf_clip_state
);
73 anv_batch_emit(&cmd_buffer
->batch
,
74 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), clip
) {
75 clip
.SFClipViewportPointer
= sf_clip_state
.offset
;
80 gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
81 bool depth_clamp_enable
)
83 uint32_t count
= cmd_buffer
->state
.dynamic
.viewport
.count
;
84 const VkViewport
*viewports
= cmd_buffer
->state
.dynamic
.viewport
.viewports
;
85 struct anv_state cc_state
=
86 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, count
* 8, 32);
88 for (uint32_t i
= 0; i
< count
; i
++) {
89 const VkViewport
*vp
= &viewports
[i
];
91 struct GENX(CC_VIEWPORT
) cc_viewport
= {
92 .MinimumDepth
= depth_clamp_enable
? vp
->minDepth
: 0.0f
,
93 .MaximumDepth
= depth_clamp_enable
? vp
->maxDepth
: 1.0f
,
96 GENX(CC_VIEWPORT_pack
)(NULL
, cc_state
.map
+ i
* 8, &cc_viewport
);
99 if (!cmd_buffer
->device
->info
.has_llc
)
100 anv_state_clflush(cc_state
);
102 anv_batch_emit(&cmd_buffer
->batch
,
103 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), cc
) {
104 cc
.CCViewportPointer
= cc_state
.offset
;
110 __emit_genx_sf_state(struct anv_cmd_buffer
*cmd_buffer
)
112 uint32_t sf_dw
[GENX(3DSTATE_SF_length
)];
113 struct GENX(3DSTATE_SF
) sf
= {
114 GENX(3DSTATE_SF_header
),
115 .LineWidth
= cmd_buffer
->state
.dynamic
.line_width
,
117 GENX(3DSTATE_SF_pack
)(NULL
, sf_dw
, &sf
);
119 anv_batch_emit_merge(&cmd_buffer
->batch
, sf_dw
,
120 cmd_buffer
->state
.pipeline
->gen8
.sf
);
123 #include "genxml/gen9_pack.h"
125 __emit_gen9_sf_state(struct anv_cmd_buffer
*cmd_buffer
)
127 uint32_t sf_dw
[GENX(3DSTATE_SF_length
)];
128 struct GEN9_3DSTATE_SF sf
= {
129 GEN9_3DSTATE_SF_header
,
130 .LineWidth
= cmd_buffer
->state
.dynamic
.line_width
,
132 GEN9_3DSTATE_SF_pack(NULL
, sf_dw
, &sf
);
134 anv_batch_emit_merge(&cmd_buffer
->batch
, sf_dw
,
135 cmd_buffer
->state
.pipeline
->gen8
.sf
);
139 __emit_sf_state(struct anv_cmd_buffer
*cmd_buffer
)
141 if (cmd_buffer
->device
->info
.is_cherryview
)
142 __emit_gen9_sf_state(cmd_buffer
);
144 __emit_genx_sf_state(cmd_buffer
);
148 genX(cmd_buffer_flush_dynamic_state
)(struct anv_cmd_buffer
*cmd_buffer
)
150 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
152 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
153 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)) {
154 __emit_sf_state(cmd_buffer
);
157 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
158 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)){
159 uint32_t raster_dw
[GENX(3DSTATE_RASTER_length
)];
160 struct GENX(3DSTATE_RASTER
) raster
= {
161 GENX(3DSTATE_RASTER_header
),
162 .GlobalDepthOffsetConstant
= cmd_buffer
->state
.dynamic
.depth_bias
.bias
,
163 .GlobalDepthOffsetScale
= cmd_buffer
->state
.dynamic
.depth_bias
.slope
,
164 .GlobalDepthOffsetClamp
= cmd_buffer
->state
.dynamic
.depth_bias
.clamp
166 GENX(3DSTATE_RASTER_pack
)(NULL
, raster_dw
, &raster
);
167 anv_batch_emit_merge(&cmd_buffer
->batch
, raster_dw
,
168 pipeline
->gen8
.raster
);
171 /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
172 * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
173 * across different state packets for gen8 and gen9. We handle that by
174 * using a big old #if switch here.
177 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
|
178 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
)) {
179 struct anv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
180 struct anv_state cc_state
=
181 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
182 GENX(COLOR_CALC_STATE_length
) * 4,
184 struct GENX(COLOR_CALC_STATE
) cc
= {
185 .BlendConstantColorRed
= cmd_buffer
->state
.dynamic
.blend_constants
[0],
186 .BlendConstantColorGreen
= cmd_buffer
->state
.dynamic
.blend_constants
[1],
187 .BlendConstantColorBlue
= cmd_buffer
->state
.dynamic
.blend_constants
[2],
188 .BlendConstantColorAlpha
= cmd_buffer
->state
.dynamic
.blend_constants
[3],
189 .StencilReferenceValue
= d
->stencil_reference
.front
& 0xff,
190 .BackFaceStencilReferenceValue
= d
->stencil_reference
.back
& 0xff,
192 GENX(COLOR_CALC_STATE_pack
)(NULL
, cc_state
.map
, &cc
);
194 if (!cmd_buffer
->device
->info
.has_llc
)
195 anv_state_clflush(cc_state
);
197 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ccp
) {
198 ccp
.ColorCalcStatePointer
= cc_state
.offset
;
199 ccp
.ColorCalcStatePointerValid
= true;
203 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
204 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
|
205 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
)) {
206 uint32_t wm_depth_stencil_dw
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
207 struct anv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
209 struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil
) = {
210 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
212 .StencilTestMask
= d
->stencil_compare_mask
.front
& 0xff,
213 .StencilWriteMask
= d
->stencil_write_mask
.front
& 0xff,
215 .BackfaceStencilTestMask
= d
->stencil_compare_mask
.back
& 0xff,
216 .BackfaceStencilWriteMask
= d
->stencil_write_mask
.back
& 0xff,
218 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, wm_depth_stencil_dw
,
221 anv_batch_emit_merge(&cmd_buffer
->batch
, wm_depth_stencil_dw
,
222 pipeline
->gen8
.wm_depth_stencil
);
225 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
) {
226 struct anv_state cc_state
=
227 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
228 GEN9_COLOR_CALC_STATE_length
* 4,
230 struct GEN9_COLOR_CALC_STATE cc
= {
231 .BlendConstantColorRed
= cmd_buffer
->state
.dynamic
.blend_constants
[0],
232 .BlendConstantColorGreen
= cmd_buffer
->state
.dynamic
.blend_constants
[1],
233 .BlendConstantColorBlue
= cmd_buffer
->state
.dynamic
.blend_constants
[2],
234 .BlendConstantColorAlpha
= cmd_buffer
->state
.dynamic
.blend_constants
[3],
236 GEN9_COLOR_CALC_STATE_pack(NULL
, cc_state
.map
, &cc
);
238 if (!cmd_buffer
->device
->info
.has_llc
)
239 anv_state_clflush(cc_state
);
241 anv_batch_emit(&cmd_buffer
->batch
, GEN9_3DSTATE_CC_STATE_POINTERS
, ccp
) {
242 ccp
.ColorCalcStatePointer
= cc_state
.offset
;
243 ccp
.ColorCalcStatePointerValid
= true;
247 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
248 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
|
249 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
250 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
)) {
251 uint32_t dwords
[GEN9_3DSTATE_WM_DEPTH_STENCIL_length
];
252 struct anv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
253 struct GEN9_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil
= {
254 GEN9_3DSTATE_WM_DEPTH_STENCIL_header
,
256 .StencilTestMask
= d
->stencil_compare_mask
.front
& 0xff,
257 .StencilWriteMask
= d
->stencil_write_mask
.front
& 0xff,
259 .BackfaceStencilTestMask
= d
->stencil_compare_mask
.back
& 0xff,
260 .BackfaceStencilWriteMask
= d
->stencil_write_mask
.back
& 0xff,
262 .StencilReferenceValue
= d
->stencil_reference
.front
& 0xff,
263 .BackfaceStencilReferenceValue
= d
->stencil_reference
.back
& 0xff,
265 GEN9_3DSTATE_WM_DEPTH_STENCIL_pack(NULL
, dwords
, &wm_depth_stencil
);
267 anv_batch_emit_merge(&cmd_buffer
->batch
, dwords
,
268 pipeline
->gen9
.wm_depth_stencil
);
272 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
273 ANV_CMD_DIRTY_INDEX_BUFFER
)) {
274 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_VF
), vf
) {
275 vf
.IndexedDrawCutIndexEnable
= pipeline
->primitive_restart
;
276 vf
.CutIndex
= cmd_buffer
->state
.restart_index
;
280 cmd_buffer
->state
.dirty
= 0;
283 void genX(CmdBindIndexBuffer
)(
284 VkCommandBuffer commandBuffer
,
287 VkIndexType indexType
)
289 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
290 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
292 static const uint32_t vk_to_gen_index_type
[] = {
293 [VK_INDEX_TYPE_UINT16
] = INDEX_WORD
,
294 [VK_INDEX_TYPE_UINT32
] = INDEX_DWORD
,
297 static const uint32_t restart_index_for_type
[] = {
298 [VK_INDEX_TYPE_UINT16
] = UINT16_MAX
,
299 [VK_INDEX_TYPE_UINT32
] = UINT32_MAX
,
302 cmd_buffer
->state
.restart_index
= restart_index_for_type
[indexType
];
304 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
305 ib
.IndexFormat
= vk_to_gen_index_type
[indexType
];
306 ib
.MemoryObjectControlState
= GENX(MOCS
);
307 ib
.BufferStartingAddress
=
308 (struct anv_address
) { buffer
->bo
, buffer
->offset
+ offset
};
309 ib
.BufferSize
= buffer
->size
- offset
;
312 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_INDEX_BUFFER
;
316 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
318 struct anv_device
*device
= cmd_buffer
->device
;
319 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
320 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
323 result
= anv_cmd_buffer_emit_samplers(cmd_buffer
,
324 MESA_SHADER_COMPUTE
, &samplers
);
325 if (result
!= VK_SUCCESS
)
327 result
= anv_cmd_buffer_emit_binding_table(cmd_buffer
,
328 MESA_SHADER_COMPUTE
, &surfaces
);
329 if (result
!= VK_SUCCESS
)
332 struct anv_state push_state
= anv_cmd_buffer_cs_push_constants(cmd_buffer
);
334 const struct brw_cs_prog_data
*cs_prog_data
= get_cs_prog_data(pipeline
);
335 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
337 if (push_state
.alloc_size
) {
338 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
339 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
340 curbe
.CURBEDataStartAddress
= push_state
.offset
;
344 const uint32_t slm_size
= encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
346 struct anv_state state
=
347 anv_state_pool_emit(&device
->dynamic_state_pool
,
348 GENX(INTERFACE_DESCRIPTOR_DATA
), 64,
349 .KernelStartPointer
= pipeline
->cs_simd
,
350 .KernelStartPointerHigh
= 0,
351 .BindingTablePointer
= surfaces
.offset
,
352 .BindingTableEntryCount
= 0,
353 .SamplerStatePointer
= samplers
.offset
,
355 .ConstantIndirectURBEntryReadLength
=
356 cs_prog_data
->push
.per_thread
.regs
,
357 .ConstantURBEntryReadOffset
= 0,
358 .BarrierEnable
= cs_prog_data
->uses_barrier
,
359 .SharedLocalMemorySize
= slm_size
,
360 .NumberofThreadsinGPGPUThreadGroup
=
361 cs_prog_data
->threads
,
362 .CrossThreadConstantDataReadLength
=
363 cs_prog_data
->push
.cross_thread
.regs
);
365 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
366 anv_batch_emit(&cmd_buffer
->batch
,
367 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
368 mid
.InterfaceDescriptorTotalLength
= size
;
369 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
376 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
378 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
379 MAYBE_UNUSED VkResult result
;
381 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
383 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
);
385 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
387 if (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)
388 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
390 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
391 (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)) {
392 result
= flush_compute_descriptor_set(cmd_buffer
);
393 assert(result
== VK_SUCCESS
);
394 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
397 cmd_buffer
->state
.compute_dirty
= 0;
399 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
402 void genX(CmdSetEvent
)(
403 VkCommandBuffer commandBuffer
,
405 VkPipelineStageFlags stageMask
)
407 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
408 ANV_FROM_HANDLE(anv_event
, event
, _event
);
410 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
411 pc
.DestinationAddressType
= DAT_PPGTT
,
412 pc
.PostSyncOperation
= WriteImmediateData
,
413 pc
.Address
= (struct anv_address
) {
414 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
,
417 pc
.ImmediateData
= VK_EVENT_SET
;
421 void genX(CmdResetEvent
)(
422 VkCommandBuffer commandBuffer
,
424 VkPipelineStageFlags stageMask
)
426 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
427 ANV_FROM_HANDLE(anv_event
, event
, _event
);
429 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
430 pc
.DestinationAddressType
= DAT_PPGTT
;
431 pc
.PostSyncOperation
= WriteImmediateData
;
432 pc
.Address
= (struct anv_address
) {
433 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
,
436 pc
.ImmediateData
= VK_EVENT_RESET
;
440 void genX(CmdWaitEvents
)(
441 VkCommandBuffer commandBuffer
,
443 const VkEvent
* pEvents
,
444 VkPipelineStageFlags srcStageMask
,
445 VkPipelineStageFlags destStageMask
,
446 uint32_t memoryBarrierCount
,
447 const VkMemoryBarrier
* pMemoryBarriers
,
448 uint32_t bufferMemoryBarrierCount
,
449 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
450 uint32_t imageMemoryBarrierCount
,
451 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
453 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
454 for (uint32_t i
= 0; i
< eventCount
; i
++) {
455 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
457 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
458 sem
.WaitMode
= PollingMode
,
459 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
460 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
461 sem
.SemaphoreAddress
= (struct anv_address
) {
462 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
,
468 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
469 false, /* byRegion */
470 memoryBarrierCount
, pMemoryBarriers
,
471 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
472 imageMemoryBarrierCount
, pImageMemoryBarriers
);