src/intel/vulkan/gen8_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #include "genX_pipeline_util.h"
  36
  37 static void
  38 emit_ia_state(struct anv_pipeline *pipeline,
  39               const VkPipelineInputAssemblyStateCreateInfo *info)
  40 {
  41    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_TOPOLOGY), vft) {
  42       vft.PrimitiveTopologyType = pipeline->topology;
  43    }
  44 }
  45
  46 VkResult
  47 genX(graphics_pipeline_create)(
  48     VkDevice                                    _device,
  49     struct anv_pipeline_cache *                 cache,
  50     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
  51     const VkAllocationCallbacks*                pAllocator,
  52     VkPipeline*                                 pPipeline)
  53 {
  54    ANV_FROM_HANDLE(anv_device, device, _device);
  55    ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
  56    const struct anv_physical_device *physical_device =
  57       &device->instance->physicalDevice;
  58    const struct gen_device_info *devinfo = &physical_device->info;
  59    struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
  60    struct anv_pipeline *pipeline;
  61    VkResult result;
  62
  63    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
  64
  65    pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
  66                          VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  67    if (pipeline == NULL)
  68       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
  69
  70    result = anv_pipeline_init(pipeline, device, cache,
  71                               pCreateInfo, pAllocator);
  72    if (result != VK_SUCCESS) {
  73       vk_free2(&device->alloc, pAllocator, pipeline);
  74       return result;
  75    }
  76
  77    assert(pCreateInfo->pVertexInputState);
  78    emit_vertex_input(pipeline, pCreateInfo->pVertexInputState);
  79    assert(pCreateInfo->pInputAssemblyState);
  80    emit_ia_state(pipeline, pCreateInfo->pInputAssemblyState);
  81    assert(pCreateInfo->pRasterizationState);
  82    emit_rs_state(pipeline, pCreateInfo->pRasterizationState,
  83                  pCreateInfo->pMultisampleState, pass, subpass);
  84    emit_ms_state(pipeline, pCreateInfo->pMultisampleState);
  85    emit_ds_state(pipeline, pCreateInfo->pDepthStencilState, pass, subpass);
  86    emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
  87                            pCreateInfo->pMultisampleState);
  88
  89    emit_urb_setup(pipeline);
  90
  91    emit_3dstate_clip(pipeline, pCreateInfo->pViewportState,
  92                      pCreateInfo->pRasterizationState);
  93    emit_3dstate_streamout(pipeline, pCreateInfo->pRasterizationState);
  94
  95    const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
  96    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM), wm) {
  97       wm.StatisticsEnable                    = true;
  98       wm.LineEndCapAntialiasingRegionWidth   = _05pixels;
  99       wm.LineAntialiasingRegionWidth         = _10pixels;
 100       wm.ForceThreadDispatchEnable           = NORMAL;
 101       wm.PointRasterizationRule              = RASTRULE_UPPER_RIGHT;
 102
 103       if (wm_prog_data && wm_prog_data->early_fragment_tests) {
 104          wm.EarlyDepthStencilControl         = PREPS;
 105       } else if (wm_prog_data && wm_prog_data->has_side_effects) {
 106          wm.EarlyDepthStencilControl         = PSEXEC;
 107       } else {
 108          wm.EarlyDepthStencilControl         = NORMAL;
 109       }
 110
 111       wm.BarycentricInterpolationMode =
 112          wm_prog_data ? wm_prog_data->barycentric_interp_modes : 0;
 113    }
 114
 115    if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) {
 116       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs);
 117    } else {
 118       const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
 119       const struct anv_shader_bin *gs_bin =
 120          pipeline->shaders[MESA_SHADER_GEOMETRY];
 121
 122       uint32_t offset = 1;
 123       uint32_t length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
 124
 125       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs) {
 126          gs.SingleProgramFlow       = false;
 127          gs.KernelStartPointer      = gs_bin->kernel.offset;
 128          gs.VectorMaskEnable        = false;
 129          gs.SamplerCount            = get_sampler_count(gs_bin);
 130          gs.BindingTableEntryCount  = get_binding_table_entry_count(gs_bin);
 131          gs.ExpectedVertexCount     = gs_prog_data->vertices_in;
 132
 133          gs.ScratchSpaceBasePointer = (struct anv_address) {
 134             .bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
 135                                          MESA_SHADER_GEOMETRY,
 136                                          gs_prog_data->base.base.total_scratch),
 137             .offset = 0,
 138          };
 139          gs.PerThreadScratchSpace   = scratch_space(&gs_prog_data->base.base);
 140          gs.OutputVertexSize        = gs_prog_data->output_vertex_size_hwords * 2 - 1;
 141          gs.OutputTopology          = gs_prog_data->output_topology;
 142          gs.VertexURBEntryReadLength = gs_prog_data->base.urb_read_length;
 143          gs.IncludeVertexHandles    = gs_prog_data->base.include_vue_handles;
 144
 145          gs.DispatchGRFStartRegisterForURBData =
 146             gs_prog_data->base.base.dispatch_grf_start_reg;
 147
 148          gs.MaximumNumberofThreads  = devinfo->max_gs_threads / 2 - 1;
 149          gs.ControlDataHeaderSize   = gs_prog_data->control_data_header_size_hwords;
 150          gs.DispatchMode            = gs_prog_data->base.dispatch_mode;
 151          gs.StatisticsEnable        = true;
 152          gs.IncludePrimitiveID      = gs_prog_data->include_primitive_id;
 153          gs.ReorderMode             = TRAILING;
 154          gs.FunctionEnable          = true;
 155
 156          gs.ControlDataFormat       = gs_prog_data->control_data_format;
 157
 158          gs.StaticOutput            = gs_prog_data->static_vertex_count >= 0;
 159          gs.StaticOutputVertexCount =
 160             gs_prog_data->static_vertex_count >= 0 ?
 161             gs_prog_data->static_vertex_count : 0;
 162
 163          /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
 164           * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
 165           * UserClipDistanceCullTestEnableBitmask(v)
 166           */
 167
 168          gs.VertexURBEntryOutputReadOffset = offset;
 169          gs.VertexURBEntryOutputLength = length;
 170       }
 171    }
 172
 173    emit_3dstate_vs(pipeline);
 174
 175    const int num_thread_bias = GEN_GEN == 8 ? 2 : 1;
 176    if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
 177       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps);
 178       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA), extra) {
 179          extra.PixelShaderValid = false;
 180       }
 181    } else {
 182       const struct anv_shader_bin *fs_bin =
 183          pipeline->shaders[MESA_SHADER_FRAGMENT];
 184
 185       emit_3dstate_sbe(pipeline);
 186
 187       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) {
 188          ps.KernelStartPointer0     = fs_bin->kernel.offset;
 189          ps.KernelStartPointer1     = 0;
 190          ps.KernelStartPointer2     = fs_bin->kernel.offset +
 191                                       wm_prog_data->prog_offset_2;
 192          ps._8PixelDispatchEnable   = wm_prog_data->dispatch_8;
 193          ps._16PixelDispatchEnable  = wm_prog_data->dispatch_16;
 194          ps._32PixelDispatchEnable  = false;
 195          ps.SingleProgramFlow       = false;
 196          ps.VectorMaskEnable        = true;
 197          ps.SamplerCount            = get_sampler_count(fs_bin);
 198          ps.BindingTableEntryCount  = get_binding_table_entry_count(fs_bin);
 199          ps.PushConstantEnable      = wm_prog_data->base.nr_params > 0;
 200          ps.PositionXYOffsetSelect  = wm_prog_data->uses_pos_offset ?
 201             POSOFFSET_SAMPLE: POSOFFSET_NONE;
 202
 203          ps.MaximumNumberofThreadsPerPSD = 64 - num_thread_bias;
 204
 205          ps.ScratchSpaceBasePointer = (struct anv_address) {
 206             .bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
 207                                          MESA_SHADER_FRAGMENT,
 208                                          wm_prog_data->base.total_scratch),
 209             .offset = 0,
 210          };
 211          ps.PerThreadScratchSpace   = scratch_space(&wm_prog_data->base);
 212
 213          ps.DispatchGRFStartRegisterForConstantSetupData0 =
 214             wm_prog_data->base.dispatch_grf_start_reg;
 215          ps.DispatchGRFStartRegisterForConstantSetupData1 = 0;
 216          ps.DispatchGRFStartRegisterForConstantSetupData2 =
 217             wm_prog_data->dispatch_grf_start_reg_2;
 218       }
 219
 220       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA), ps) {
 221          ps.PixelShaderValid              = true;
 222          ps.PixelShaderKillsPixel         = wm_prog_data->uses_kill;
 223          ps.PixelShaderComputedDepthMode  = wm_prog_data->computed_depth_mode;
 224          ps.AttributeEnable               = wm_prog_data->num_varying_inputs > 0;
 225          ps.oMaskPresenttoRenderTarget    = wm_prog_data->uses_omask;
 226          ps.PixelShaderIsPerSample        = wm_prog_data->persample_dispatch;
 227          ps.PixelShaderUsesSourceDepth    = wm_prog_data->uses_src_depth;
 228          ps.PixelShaderUsesSourceW        = wm_prog_data->uses_src_w;
 229 #if GEN_GEN >= 9
 230          ps.PixelShaderPullsBary    = wm_prog_data->pulls_bary;
 231          ps.InputCoverageMaskState  = wm_prog_data->uses_sample_mask ?
 232             ICMS_INNER_CONSERVATIVE : ICMS_NONE;
 233 #else
 234          ps.PixelShaderUsesInputCoverageMask = wm_prog_data->uses_sample_mask;
 235 #endif
 236       }
 237    }
 238
 239    *pPipeline = anv_pipeline_to_handle(pipeline);
 240
 241    return VK_SUCCESS;
 242 }