src/intel/vulkan/gen8_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #include "genX_pipeline_util.h"
  36
  37 static void
  38 emit_ia_state(struct anv_pipeline *pipeline,
  39               const VkPipelineInputAssemblyStateCreateInfo *info)
  40 {
  41    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_TOPOLOGY), vft) {
  42       vft.PrimitiveTopologyType = pipeline->topology;
  43    }
  44 }
  45
  46 VkResult
  47 genX(graphics_pipeline_create)(
  48     VkDevice                                    _device,
  49     struct anv_pipeline_cache *                 cache,
  50     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
  51     const VkAllocationCallbacks*                pAllocator,
  52     VkPipeline*                                 pPipeline)
  53 {
  54    ANV_FROM_HANDLE(anv_device, device, _device);
  55    ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
  56    const struct anv_physical_device *physical_device =
  57       &device->instance->physicalDevice;
  58    const struct gen_device_info *devinfo = &physical_device->info;
  59    struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
  60    struct anv_pipeline *pipeline;
  61    VkResult result;
  62    uint32_t offset, length;
  63
  64    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
  65
  66    pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
  67                          VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  68    if (pipeline == NULL)
  69       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
  70
  71    result = anv_pipeline_init(pipeline, device, cache,
  72                               pCreateInfo, pAllocator);
  73    if (result != VK_SUCCESS) {
  74       vk_free2(&device->alloc, pAllocator, pipeline);
  75       return result;
  76    }
  77
  78    assert(pCreateInfo->pVertexInputState);
  79    emit_vertex_input(pipeline, pCreateInfo->pVertexInputState);
  80    assert(pCreateInfo->pInputAssemblyState);
  81    emit_ia_state(pipeline, pCreateInfo->pInputAssemblyState);
  82    assert(pCreateInfo->pRasterizationState);
  83    emit_rs_state(pipeline, pCreateInfo->pRasterizationState,
  84                  pCreateInfo->pMultisampleState, pass, subpass);
  85    emit_ms_state(pipeline, pCreateInfo->pMultisampleState);
  86    emit_ds_state(pipeline, pCreateInfo->pDepthStencilState, pass, subpass);
  87    emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
  88                            pCreateInfo->pMultisampleState);
  89
  90    emit_urb_setup(pipeline);
  91
  92    emit_3dstate_clip(pipeline, pCreateInfo->pViewportState,
  93                      pCreateInfo->pRasterizationState);
  94    emit_3dstate_streamout(pipeline, pCreateInfo->pRasterizationState);
  95
  96    const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
  97    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM), wm) {
  98       wm.StatisticsEnable                    = true;
  99       wm.LineEndCapAntialiasingRegionWidth   = _05pixels;
 100       wm.LineAntialiasingRegionWidth         = _10pixels;
 101       wm.ForceThreadDispatchEnable           = NORMAL;
 102       wm.PointRasterizationRule              = RASTRULE_UPPER_RIGHT;
 103
 104       if (wm_prog_data && wm_prog_data->early_fragment_tests) {
 105          wm.EarlyDepthStencilControl         = PREPS;
 106       } else if (wm_prog_data && wm_prog_data->has_side_effects) {
 107          wm.EarlyDepthStencilControl         = PSEXEC;
 108       } else {
 109          wm.EarlyDepthStencilControl         = NORMAL;
 110       }
 111
 112       wm.BarycentricInterpolationMode =
 113          wm_prog_data ? wm_prog_data->barycentric_interp_modes : 0;
 114    }
 115
 116    if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) {
 117       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs);
 118    } else {
 119       const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
 120       const struct anv_shader_bin *gs_bin =
 121          pipeline->shaders[MESA_SHADER_GEOMETRY];
 122
 123       offset = 1;
 124       length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
 125
 126       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs) {
 127          gs.SingleProgramFlow       = false;
 128          gs.KernelStartPointer      = gs_bin->kernel.offset;
 129          gs.VectorMaskEnable        = false;
 130          gs.SamplerCount            = get_sampler_count(gs_bin);
 131          gs.BindingTableEntryCount  = get_binding_table_entry_count(gs_bin);
 132          gs.ExpectedVertexCount     = gs_prog_data->vertices_in;
 133
 134          gs.ScratchSpaceBasePointer = (struct anv_address) {
 135             .bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
 136                                          MESA_SHADER_GEOMETRY,
 137                                          gs_prog_data->base.base.total_scratch),
 138             .offset = 0,
 139          };
 140          gs.PerThreadScratchSpace   = scratch_space(&gs_prog_data->base.base);
 141          gs.OutputVertexSize        = gs_prog_data->output_vertex_size_hwords * 2 - 1;
 142          gs.OutputTopology          = gs_prog_data->output_topology;
 143          gs.VertexURBEntryReadLength = gs_prog_data->base.urb_read_length;
 144          gs.IncludeVertexHandles    = gs_prog_data->base.include_vue_handles;
 145
 146          gs.DispatchGRFStartRegisterForURBData =
 147             gs_prog_data->base.base.dispatch_grf_start_reg;
 148
 149          gs.MaximumNumberofThreads  = devinfo->max_gs_threads / 2 - 1;
 150          gs.ControlDataHeaderSize   = gs_prog_data->control_data_header_size_hwords;
 151          gs.DispatchMode            = gs_prog_data->base.dispatch_mode;
 152          gs.StatisticsEnable        = true;
 153          gs.IncludePrimitiveID      = gs_prog_data->include_primitive_id;
 154          gs.ReorderMode             = TRAILING;
 155          gs.Enable                  = true;
 156
 157          gs.ControlDataFormat       = gs_prog_data->control_data_format;
 158
 159          gs.StaticOutput            = gs_prog_data->static_vertex_count >= 0;
 160          gs.StaticOutputVertexCount =
 161             gs_prog_data->static_vertex_count >= 0 ?
 162             gs_prog_data->static_vertex_count : 0;
 163
 164          /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
 165           * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
 166           * UserClipDistanceCullTestEnableBitmask(v)
 167           */
 168
 169          gs.VertexURBEntryOutputReadOffset = offset;
 170          gs.VertexURBEntryOutputLength = length;
 171       }
 172    }
 173
 174    const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
 175    assert(!vs_prog_data->base.base.use_alt_mode);
 176    /* Skip the VUE header and position slots */
 177    offset = 1;
 178    length = (vs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
 179
 180    assert(anv_pipeline_has_stage(pipeline, MESA_SHADER_VERTEX));
 181    const struct anv_shader_bin *vs_bin =
 182       pipeline->shaders[MESA_SHADER_VERTEX];
 183    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
 184       vs.KernelStartPointer            = vs_bin->kernel.offset;
 185       vs.SingleVertexDispatch          = false;
 186       vs.VectorMaskEnable              = false;
 187
 188       vs.SamplerCount                  = get_sampler_count(vs_bin);
 189       vs.BindingTableEntryCount        = get_binding_table_entry_count(vs_bin);
 190
 191       vs.ThreadDispatchPriority        = false;
 192       vs.FloatingPointMode             = IEEE754;
 193       vs.IllegalOpcodeExceptionEnable  = false;
 194       vs.AccessesUAV                   = false;
 195       vs.SoftwareExceptionEnable       = false;
 196
 197       vs.ScratchSpaceBasePointer = (struct anv_address) {
 198          .bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
 199                                       MESA_SHADER_VERTEX,
 200                                       vs_prog_data->base.base.total_scratch),
 201          .offset = 0,
 202       };
 203       vs.PerThreadScratchSpace   = scratch_space(&vs_prog_data->base.base);
 204
 205       vs.DispatchGRFStartRegisterForURBData =
 206          vs_prog_data->base.base.dispatch_grf_start_reg;
 207
 208       vs.VertexURBEntryReadLength      = vs_prog_data->base.urb_read_length;
 209       vs.VertexURBEntryReadOffset      = 0;
 210
 211       vs.MaximumNumberofThreads        = devinfo->max_vs_threads - 1;
 212       vs.StatisticsEnable              = false;
 213       vs.SIMD8DispatchEnable           =
 214          vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8;
 215       vs.VertexCacheDisable            = false;
 216       vs.FunctionEnable                = true;
 217
 218       vs.VertexURBEntryOutputReadOffset = offset;
 219       vs.VertexURBEntryOutputLength    = length;
 220
 221       /* TODO */
 222       vs.UserClipDistanceClipTestEnableBitmask = 0;
 223       vs.UserClipDistanceCullTestEnableBitmask = 0;
 224    }
 225
 226    const int num_thread_bias = GEN_GEN == 8 ? 2 : 1;
 227    if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
 228       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps);
 229       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA), extra) {
 230          extra.PixelShaderValid = false;
 231       }
 232    } else {
 233       const struct anv_shader_bin *fs_bin =
 234          pipeline->shaders[MESA_SHADER_FRAGMENT];
 235
 236       emit_3dstate_sbe(pipeline);
 237
 238       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) {
 239          ps.KernelStartPointer0     = fs_bin->kernel.offset;
 240          ps.KernelStartPointer1     = 0;
 241          ps.KernelStartPointer2     = fs_bin->kernel.offset +
 242                                       wm_prog_data->prog_offset_2;
 243          ps._8PixelDispatchEnable   = wm_prog_data->dispatch_8;
 244          ps._16PixelDispatchEnable  = wm_prog_data->dispatch_16;
 245          ps._32PixelDispatchEnable  = false;
 246          ps.SingleProgramFlow       = false;
 247          ps.VectorMaskEnable        = true;
 248          ps.SamplerCount            = get_sampler_count(fs_bin);
 249          ps.BindingTableEntryCount  = get_binding_table_entry_count(fs_bin);
 250          ps.PushConstantEnable      = wm_prog_data->base.nr_params > 0;
 251          ps.PositionXYOffsetSelect  = wm_prog_data->uses_pos_offset ?
 252             POSOFFSET_SAMPLE: POSOFFSET_NONE;
 253
 254          ps.MaximumNumberofThreadsPerPSD = 64 - num_thread_bias;
 255
 256          ps.ScratchSpaceBasePointer = (struct anv_address) {
 257             .bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
 258                                          MESA_SHADER_FRAGMENT,
 259                                          wm_prog_data->base.total_scratch),
 260             .offset = 0,
 261          };
 262          ps.PerThreadScratchSpace   = scratch_space(&wm_prog_data->base);
 263
 264          ps.DispatchGRFStartRegisterForConstantSetupData0 =
 265             wm_prog_data->base.dispatch_grf_start_reg;
 266          ps.DispatchGRFStartRegisterForConstantSetupData1 = 0;
 267          ps.DispatchGRFStartRegisterForConstantSetupData2 =
 268             wm_prog_data->dispatch_grf_start_reg_2;
 269       }
 270
 271       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA), ps) {
 272          ps.PixelShaderValid              = true;
 273          ps.PixelShaderKillsPixel         = wm_prog_data->uses_kill;
 274          ps.PixelShaderComputedDepthMode  = wm_prog_data->computed_depth_mode;
 275          ps.AttributeEnable               = wm_prog_data->num_varying_inputs > 0;
 276          ps.oMaskPresenttoRenderTarget    = wm_prog_data->uses_omask;
 277          ps.PixelShaderIsPerSample        = wm_prog_data->persample_dispatch;
 278          ps.PixelShaderUsesSourceDepth    = wm_prog_data->uses_src_depth;
 279          ps.PixelShaderUsesSourceW        = wm_prog_data->uses_src_w;
 280 #if GEN_GEN >= 9
 281          ps.PixelShaderPullsBary    = wm_prog_data->pulls_bary;
 282          ps.InputCoverageMaskState  = wm_prog_data->uses_sample_mask ?
 283             ICMS_INNER_CONSERVATIVE : ICMS_NONE;
 284 #else
 285          ps.PixelShaderUsesInputCoverageMask = wm_prog_data->uses_sample_mask;
 286 #endif
 287       }
 288    }
 289
 290    *pPipeline = anv_pipeline_to_handle(pipeline);
 291
 292    return VK_SUCCESS;
 293 }