src/intel/vulkan/gen8_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #include "genX_pipeline_util.h"
  36
  37 static void
  38 emit_ia_state(struct anv_pipeline *pipeline,
  39               const VkPipelineInputAssemblyStateCreateInfo *info,
  40               const struct anv_graphics_pipeline_create_info *extra)
  41 {
  42    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_TOPOLOGY), vft) {
  43       vft.PrimitiveTopologyType = pipeline->topology;
  44    }
  45 }
  46
  47 VkResult
  48 genX(graphics_pipeline_create)(
  49     VkDevice                                    _device,
  50     struct anv_pipeline_cache *                 cache,
  51     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
  52     const struct anv_graphics_pipeline_create_info *extra,
  53     const VkAllocationCallbacks*                pAllocator,
  54     VkPipeline*                                 pPipeline)
  55 {
  56    ANV_FROM_HANDLE(anv_device, device, _device);
  57    ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
  58    struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
  59    struct anv_pipeline *pipeline;
  60    VkResult result;
  61    uint32_t offset, length;
  62
  63    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
  64
  65    pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
  66                          VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  67    if (pipeline == NULL)
  68       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
  69
  70    result = anv_pipeline_init(pipeline, device, cache,
  71                               pCreateInfo, extra, pAllocator);
  72    if (result != VK_SUCCESS) {
  73       anv_free2(&device->alloc, pAllocator, pipeline);
  74       return result;
  75    }
  76
  77    assert(pCreateInfo->pVertexInputState);
  78    emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
  79    assert(pCreateInfo->pInputAssemblyState);
  80    emit_ia_state(pipeline, pCreateInfo->pInputAssemblyState, extra);
  81    assert(pCreateInfo->pRasterizationState);
  82    emit_rs_state(pipeline, pCreateInfo->pRasterizationState,
  83                  pCreateInfo->pMultisampleState, pass, subpass, extra);
  84    emit_ms_state(pipeline, pCreateInfo->pMultisampleState);
  85    emit_ds_state(pipeline, pCreateInfo->pDepthStencilState, pass, subpass);
  86    emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
  87                            pCreateInfo->pMultisampleState);
  88
  89    emit_urb_setup(pipeline);
  90
  91    emit_3dstate_clip(pipeline, pCreateInfo->pViewportState,
  92                      pCreateInfo->pRasterizationState, extra);
  93    emit_3dstate_streamout(pipeline, pCreateInfo->pRasterizationState);
  94
  95    const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
  96    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM), wm) {
  97       wm.StatisticsEnable                    = true;
  98       wm.LineEndCapAntialiasingRegionWidth   = _05pixels;
  99       wm.LineAntialiasingRegionWidth         = _10pixels;
 100       wm.ForceThreadDispatchEnable           = NORMAL;
 101       wm.PointRasterizationRule              = RASTRULE_UPPER_RIGHT;
 102
 103       if (wm_prog_data && wm_prog_data->early_fragment_tests) {
 104          wm.EarlyDepthStencilControl         = PREPS;
 105       } else if (wm_prog_data && wm_prog_data->has_side_effects) {
 106          wm.EarlyDepthStencilControl         = PSEXEC;
 107       } else {
 108          wm.EarlyDepthStencilControl         = NORMAL;
 109       }
 110
 111       wm.BarycentricInterpolationMode = pipeline->ps_ksp0 == NO_KERNEL ?
 112          0 : wm_prog_data->barycentric_interp_modes;
 113    }
 114
 115    if (pipeline->gs_kernel == NO_KERNEL) {
 116       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs);
 117    } else {
 118       const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
 119       offset = 1;
 120       length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
 121
 122       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs) {
 123          gs.SingleProgramFlow       = false;
 124          gs.KernelStartPointer      = pipeline->gs_kernel;
 125          gs.VectorMaskEnable        = false;
 126          gs.SamplerCount            = 0;
 127          gs.BindingTableEntryCount  = 0;
 128          gs.ExpectedVertexCount     = gs_prog_data->vertices_in;
 129
 130          gs.ScratchSpaceBasePointer = (struct anv_address) {
 131             .bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
 132                                          MESA_SHADER_GEOMETRY,
 133                                          gs_prog_data->base.base.total_scratch),
 134             .offset = 0,
 135          };
 136          gs.PerThreadScratchSpace   = scratch_space(&gs_prog_data->base.base);
 137          gs.OutputVertexSize        = gs_prog_data->output_vertex_size_hwords * 2 - 1;
 138          gs.OutputTopology          = gs_prog_data->output_topology;
 139          gs.VertexURBEntryReadLength = gs_prog_data->base.urb_read_length;
 140          gs.IncludeVertexHandles    = gs_prog_data->base.include_vue_handles;
 141
 142          gs.DispatchGRFStartRegisterForURBData =
 143             gs_prog_data->base.base.dispatch_grf_start_reg;
 144
 145          gs.MaximumNumberofThreads  = device->info.max_gs_threads / 2 - 1;
 146          gs.ControlDataHeaderSize   = gs_prog_data->control_data_header_size_hwords;
 147          gs.DispatchMode            = gs_prog_data->base.dispatch_mode;
 148          gs.StatisticsEnable        = true;
 149          gs.IncludePrimitiveID      = gs_prog_data->include_primitive_id;
 150          gs.ReorderMode             = TRAILING;
 151          gs.Enable                  = true;
 152
 153          gs.ControlDataFormat       = gs_prog_data->control_data_format;
 154
 155          gs.StaticOutput            = gs_prog_data->static_vertex_count >= 0;
 156          gs.StaticOutputVertexCount =
 157             gs_prog_data->static_vertex_count >= 0 ?
 158             gs_prog_data->static_vertex_count : 0;
 159
 160          /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
 161           * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
 162           * UserClipDistanceCullTestEnableBitmask(v)
 163           */
 164
 165          gs.VertexURBEntryOutputReadOffset = offset;
 166          gs.VertexURBEntryOutputLength = length;
 167       }
 168    }
 169
 170    const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
 171    /* Skip the VUE header and position slots */
 172    offset = 1;
 173    length = (vs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
 174
 175    uint32_t vs_start = pipeline->vs_simd8 != NO_KERNEL ? pipeline->vs_simd8 :
 176                                                          pipeline->vs_vec4;
 177
 178    if (vs_start == NO_KERNEL || (extra && extra->disable_vs)) {
 179       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
 180          vs.FunctionEnable = false;
 181          /* Even if VS is disabled, SBE still gets the amount of
 182           * vertex data to read from this field. */
 183          vs.VertexURBEntryOutputReadOffset = offset;
 184          vs.VertexURBEntryOutputLength = length;
 185       }
 186    } else {
 187       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
 188          vs.KernelStartPointer            = vs_start;
 189          vs.SingleVertexDispatch          = false;
 190          vs.VectorMaskEnable              = false;
 191          vs.SamplerCount                  = 0;
 192
 193          vs.BindingTableEntryCount =
 194             vs_prog_data->base.base.binding_table.size_bytes / 4,
 195
 196          vs.ThreadDispatchPriority        = false;
 197          vs.FloatingPointMode             = IEEE754;
 198          vs.IllegalOpcodeExceptionEnable  = false;
 199          vs.AccessesUAV                   = false;
 200          vs.SoftwareExceptionEnable       = false;
 201
 202          vs.ScratchSpaceBasePointer = (struct anv_address) {
 203             .bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
 204                                          MESA_SHADER_VERTEX,
 205                                          vs_prog_data->base.base.total_scratch),
 206             .offset = 0,
 207          };
 208          vs.PerThreadScratchSpace   = scratch_space(&vs_prog_data->base.base);
 209
 210          vs.DispatchGRFStartRegisterForURBData =
 211             vs_prog_data->base.base.dispatch_grf_start_reg;
 212
 213          vs.VertexURBEntryReadLength      = vs_prog_data->base.urb_read_length;
 214          vs.VertexURBEntryReadOffset      = 0;
 215
 216          vs.MaximumNumberofThreads        = device->info.max_vs_threads - 1;
 217          vs.StatisticsEnable              = false;
 218          vs.SIMD8DispatchEnable           = pipeline->vs_simd8 != NO_KERNEL;
 219          vs.VertexCacheDisable            = false;
 220          vs.FunctionEnable                = true;
 221
 222          vs.VertexURBEntryOutputReadOffset = offset;
 223          vs.VertexURBEntryOutputLength    = length;
 224
 225          /* TODO */
 226          vs.UserClipDistanceClipTestEnableBitmask = 0;
 227          vs.UserClipDistanceCullTestEnableBitmask = 0;
 228       }
 229    }
 230
 231    const int num_thread_bias = GEN_GEN == 8 ? 2 : 1;
 232    if (pipeline->ps_ksp0 == NO_KERNEL) {
 233       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps);
 234       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA), extra) {
 235          extra.PixelShaderValid = false;
 236       }
 237    } else {
 238       emit_3dstate_sbe(pipeline);
 239
 240       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) {
 241          ps.KernelStartPointer0     = pipeline->ps_ksp0;
 242          ps.KernelStartPointer1     = 0;
 243          ps.KernelStartPointer2     = pipeline->ps_ksp0 + wm_prog_data->prog_offset_2;
 244          ps._8PixelDispatchEnable   = wm_prog_data->dispatch_8;
 245          ps._16PixelDispatchEnable  = wm_prog_data->dispatch_16;
 246          ps._32PixelDispatchEnable  = false;
 247          ps.SingleProgramFlow       = false;
 248          ps.VectorMaskEnable        = true;
 249          ps.SamplerCount            = 1;
 250          ps.PushConstantEnable      = wm_prog_data->base.nr_params > 0;
 251          ps.PositionXYOffsetSelect  = wm_prog_data->uses_pos_offset ?
 252             POSOFFSET_SAMPLE: POSOFFSET_NONE;
 253
 254          ps.MaximumNumberofThreadsPerPSD = 64 - num_thread_bias;
 255
 256          ps.ScratchSpaceBasePointer = (struct anv_address) {
 257             .bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
 258                                          MESA_SHADER_FRAGMENT,
 259                                          wm_prog_data->base.total_scratch),
 260             .offset = 0,
 261          };
 262          ps.PerThreadScratchSpace   = scratch_space(&wm_prog_data->base);
 263
 264          ps.DispatchGRFStartRegisterForConstantSetupData0 =
 265             wm_prog_data->base.dispatch_grf_start_reg;
 266          ps.DispatchGRFStartRegisterForConstantSetupData1 = 0;
 267          ps.DispatchGRFStartRegisterForConstantSetupData2 =
 268             wm_prog_data->dispatch_grf_start_reg_2;
 269       }
 270
 271       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA), ps) {
 272          ps.PixelShaderValid              = true;
 273          ps.PixelShaderKillsPixel         = wm_prog_data->uses_kill;
 274          ps.PixelShaderComputedDepthMode  = wm_prog_data->computed_depth_mode;
 275          ps.AttributeEnable               = wm_prog_data->num_varying_inputs > 0;
 276          ps.oMaskPresenttoRenderTarget    = wm_prog_data->uses_omask;
 277          ps.PixelShaderIsPerSample        = wm_prog_data->persample_dispatch;
 278          ps.PixelShaderUsesSourceDepth    = wm_prog_data->uses_src_depth;
 279          ps.PixelShaderUsesSourceW        = wm_prog_data->uses_src_w;
 280 #if GEN_GEN >= 9
 281          ps.PixelShaderPullsBary    = wm_prog_data->pulls_bary;
 282          ps.InputCoverageMaskState  = wm_prog_data->uses_sample_mask ?
 283             ICMS_INNER_CONSERVATIVE : ICMS_NONE;
 284 #else
 285          ps.PixelShaderUsesInputCoverageMask = wm_prog_data->uses_sample_mask;
 286 #endif
 287       }
 288    }
 289
 290    *pPipeline = anv_pipeline_to_handle(pipeline);
 291
 292    return VK_SUCCESS;
 293 }