src/intel/vulkan/gen8_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #include "genX_pipeline_util.h"
  36
  37 static void
  38 emit_ia_state(struct anv_pipeline *pipeline,
  39               const VkPipelineInputAssemblyStateCreateInfo *info,
  40               const struct anv_graphics_pipeline_create_info *extra)
  41 {
  42    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_TOPOLOGY), vft) {
  43       vft.PrimitiveTopologyType = pipeline->topology;
  44    }
  45 }
  46
  47 static void
  48 emit_rs_state(struct anv_pipeline *pipeline,
  49               const VkPipelineRasterizationStateCreateInfo *info,
  50               const VkPipelineMultisampleStateCreateInfo *ms_info,
  51               const struct anv_graphics_pipeline_create_info *extra)
  52 {
  53    uint32_t samples = 1;
  54
  55    if (ms_info)
  56       samples = ms_info->rasterizationSamples;
  57
  58    struct GENX(3DSTATE_SF) sf = {
  59       GENX(3DSTATE_SF_header),
  60       .ViewportTransformEnable = !(extra && extra->use_rectlist),
  61       .TriangleStripListProvokingVertexSelect = 0,
  62       .LineStripListProvokingVertexSelect = 0,
  63       .TriangleFanProvokingVertexSelect = 1,
  64       .PointWidthSource = Vertex,
  65       .PointWidth = 1.0,
  66    };
  67
  68    /* FINISHME: VkBool32 rasterizerDiscardEnable; */
  69
  70    GENX(3DSTATE_SF_pack)(NULL, pipeline->gen8.sf, &sf);
  71
  72    struct GENX(3DSTATE_RASTER) raster = {
  73       GENX(3DSTATE_RASTER_header),
  74
  75       /* For details on 3DSTATE_RASTER multisample state, see the BSpec table
  76        * "Multisample Modes State".
  77        */
  78       .DXMultisampleRasterizationEnable = samples > 1,
  79       .ForcedSampleCount = FSC_NUMRASTSAMPLES_0,
  80       .ForceMultisampling = false,
  81
  82       .FrontWinding = vk_to_gen_front_face[info->frontFace],
  83       .CullMode = vk_to_gen_cullmode[info->cullMode],
  84       .FrontFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
  85       .BackFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
  86       .ScissorRectangleEnable = !(extra && extra->use_rectlist),
  87 #if GEN_GEN == 8
  88       .ViewportZClipTestEnable = true,
  89 #else
  90       /* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
  91       .ViewportZFarClipTestEnable = true,
  92       .ViewportZNearClipTestEnable = true,
  93 #endif
  94       .GlobalDepthOffsetEnableSolid = info->depthBiasEnable,
  95       .GlobalDepthOffsetEnableWireframe = info->depthBiasEnable,
  96       .GlobalDepthOffsetEnablePoint = info->depthBiasEnable,
  97    };
  98
  99    GENX(3DSTATE_RASTER_pack)(NULL, pipeline->gen8.raster, &raster);
 100 }
 101
 102 static void
 103 emit_cb_state(struct anv_pipeline *pipeline,
 104               const VkPipelineColorBlendStateCreateInfo *info,
 105               const VkPipelineMultisampleStateCreateInfo *ms_info)
 106 {
 107    struct anv_device *device = pipeline->device;
 108
 109    uint32_t num_dwords = GENX(BLEND_STATE_length);
 110    pipeline->blend_state =
 111       anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
 112
 113    struct GENX(BLEND_STATE) blend_state = {
 114       .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
 115       .AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable,
 116    };
 117
 118    /* Default everything to disabled */
 119    for (uint32_t i = 0; i < 8; i++) {
 120       blend_state.Entry[i].WriteDisableAlpha = true;
 121       blend_state.Entry[i].WriteDisableRed = true;
 122       blend_state.Entry[i].WriteDisableGreen = true;
 123       blend_state.Entry[i].WriteDisableBlue = true;
 124    }
 125
 126    struct anv_pipeline_bind_map *map =
 127       &pipeline->bindings[MESA_SHADER_FRAGMENT];
 128
 129    bool has_writeable_rt = false;
 130    for (unsigned i = 0; i < map->surface_count; i++) {
 131       struct anv_pipeline_binding *binding = &map->surface_to_descriptor[i];
 132
 133       /* All color attachments are at the beginning of the binding table */
 134       if (binding->set != ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS)
 135          break;
 136
 137       /* We can have at most 8 attachments */
 138       assert(i < 8);
 139
 140       if (binding->index >= info->attachmentCount)
 141          continue;
 142
 143       assert(binding->binding == 0);
 144       const VkPipelineColorBlendAttachmentState *a =
 145          &info->pAttachments[binding->index];
 146
 147       if (a->srcColorBlendFactor != a->srcAlphaBlendFactor ||
 148           a->dstColorBlendFactor != a->dstAlphaBlendFactor ||
 149           a->colorBlendOp != a->alphaBlendOp) {
 150          blend_state.IndependentAlphaBlendEnable = true;
 151       }
 152
 153       blend_state.Entry[i] = (struct GENX(BLEND_STATE_ENTRY)) {
 154          .LogicOpEnable = info->logicOpEnable,
 155          .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
 156          .ColorBufferBlendEnable = a->blendEnable,
 157          .PreBlendSourceOnlyClampEnable = false,
 158          .ColorClampRange = COLORCLAMP_RTFORMAT,
 159          .PreBlendColorClampEnable = true,
 160          .PostBlendColorClampEnable = true,
 161          .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
 162          .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
 163          .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
 164          .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
 165          .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
 166          .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
 167          .WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
 168          .WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
 169          .WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
 170          .WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
 171       };
 172
 173       if (a->colorWriteMask != 0)
 174          has_writeable_rt = true;
 175
 176       /* Our hardware applies the blend factor prior to the blend function
 177        * regardless of what function is used.  Technically, this means the
 178        * hardware can do MORE than GL or Vulkan specify.  However, it also
 179        * means that, for MIN and MAX, we have to stomp the blend factor to
 180        * ONE to make it a no-op.
 181        */
 182       if (a->colorBlendOp == VK_BLEND_OP_MIN ||
 183           a->colorBlendOp == VK_BLEND_OP_MAX) {
 184          blend_state.Entry[i].SourceBlendFactor = BLENDFACTOR_ONE;
 185          blend_state.Entry[i].DestinationBlendFactor = BLENDFACTOR_ONE;
 186       }
 187       if (a->alphaBlendOp == VK_BLEND_OP_MIN ||
 188           a->alphaBlendOp == VK_BLEND_OP_MAX) {
 189          blend_state.Entry[i].SourceAlphaBlendFactor = BLENDFACTOR_ONE;
 190          blend_state.Entry[i].DestinationAlphaBlendFactor = BLENDFACTOR_ONE;
 191       }
 192    }
 193
 194    struct GENX(BLEND_STATE_ENTRY) *bs0 = &blend_state.Entry[0];
 195
 196    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_BLEND), blend) {
 197       blend.AlphaToCoverageEnable         = blend_state.AlphaToCoverageEnable;
 198       blend.HasWriteableRT                = has_writeable_rt;
 199       blend.ColorBufferBlendEnable        = bs0->ColorBufferBlendEnable;
 200       blend.SourceAlphaBlendFactor        = bs0->SourceAlphaBlendFactor;
 201       blend.DestinationAlphaBlendFactor   = bs0->DestinationAlphaBlendFactor;
 202       blend.SourceBlendFactor             = bs0->SourceBlendFactor;
 203       blend.DestinationBlendFactor        = bs0->DestinationBlendFactor;
 204       blend.AlphaTestEnable               = false;
 205       blend.IndependentAlphaBlendEnable   =
 206          blend_state.IndependentAlphaBlendEnable;
 207    }
 208
 209    GENX(BLEND_STATE_pack)(NULL, pipeline->blend_state.map, &blend_state);
 210    if (!device->info.has_llc)
 211       anv_state_clflush(pipeline->blend_state);
 212
 213    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_BLEND_STATE_POINTERS), bsp) {
 214       bsp.BlendStatePointer      = pipeline->blend_state.offset;
 215       bsp.BlendStatePointerValid = true;
 216    }
 217 }
 218
 219 static void
 220 emit_ms_state(struct anv_pipeline *pipeline,
 221               const VkPipelineMultisampleStateCreateInfo *info)
 222 {
 223    uint32_t samples = 1;
 224    uint32_t log2_samples = 0;
 225
 226    /* From the Vulkan 1.0 spec:
 227     *    If pSampleMask is NULL, it is treated as if the mask has all bits
 228     *    enabled, i.e. no coverage is removed from fragments.
 229     *
 230     * 3DSTATE_SAMPLE_MASK.SampleMask is 16 bits.
 231     */
 232    uint32_t sample_mask = 0xffff;
 233
 234    if (info) {
 235       samples = info->rasterizationSamples;
 236       log2_samples = __builtin_ffs(samples) - 1;
 237    }
 238
 239    if (info && info->pSampleMask)
 240       sample_mask &= info->pSampleMask[0];
 241
 242    if (info && info->sampleShadingEnable)
 243       anv_finishme("VkPipelineMultisampleStateCreateInfo::sampleShadingEnable");
 244
 245    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_MULTISAMPLE), ms) {
 246       /* The PRM says that this bit is valid only for DX9:
 247        *
 248        *    SW can choose to set this bit only for DX9 API. DX10/OGL API's
 249        *    should not have any effect by setting or not setting this bit.
 250        */
 251       ms.PixelPositionOffsetEnable = false;
 252
 253       ms.PixelLocation = CENTER;
 254       ms.NumberofMultisamples = log2_samples;
 255    }
 256
 257    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SAMPLE_MASK), sm) {
 258       sm.SampleMask = sample_mask;
 259    }
 260 }
 261
 262 VkResult
 263 genX(graphics_pipeline_create)(
 264     VkDevice                                    _device,
 265     struct anv_pipeline_cache *                 cache,
 266     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
 267     const struct anv_graphics_pipeline_create_info *extra,
 268     const VkAllocationCallbacks*                pAllocator,
 269     VkPipeline*                                 pPipeline)
 270 {
 271    ANV_FROM_HANDLE(anv_device, device, _device);
 272    ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
 273    struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
 274    struct anv_pipeline *pipeline;
 275    VkResult result;
 276    uint32_t offset, length;
 277
 278    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
 279
 280    pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
 281                          VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 282    if (pipeline == NULL)
 283       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 284
 285    result = anv_pipeline_init(pipeline, device, cache,
 286                               pCreateInfo, extra, pAllocator);
 287    if (result != VK_SUCCESS) {
 288       anv_free2(&device->alloc, pAllocator, pipeline);
 289       return result;
 290    }
 291
 292    assert(pCreateInfo->pVertexInputState);
 293    emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
 294    assert(pCreateInfo->pInputAssemblyState);
 295    emit_ia_state(pipeline, pCreateInfo->pInputAssemblyState, extra);
 296    assert(pCreateInfo->pRasterizationState);
 297    emit_rs_state(pipeline, pCreateInfo->pRasterizationState,
 298                  pCreateInfo->pMultisampleState, extra);
 299    emit_ms_state(pipeline, pCreateInfo->pMultisampleState);
 300    emit_ds_state(pipeline, pCreateInfo->pDepthStencilState, pass, subpass);
 301    emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
 302                            pCreateInfo->pMultisampleState);
 303
 304    emit_urb_setup(pipeline);
 305
 306    const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
 307    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_CLIP), clip) {
 308       clip.ClipEnable               = !(extra && extra->use_rectlist);
 309       clip.EarlyCullEnable          = true;
 310       clip.APIMode                  = 1; /* D3D */
 311       clip.ViewportXYClipTestEnable = true;
 312
 313       clip.ClipMode =
 314          pCreateInfo->pRasterizationState->rasterizerDiscardEnable ?
 315          REJECT_ALL : NORMAL;
 316
 317       clip.NonPerspectiveBarycentricEnable = wm_prog_data ?
 318          (wm_prog_data->barycentric_interp_modes & 0x38) != 0 : 0;
 319
 320       clip.TriangleStripListProvokingVertexSelect  = 0;
 321       clip.LineStripListProvokingVertexSelect      = 0;
 322       clip.TriangleFanProvokingVertexSelect        = 1;
 323
 324       clip.MinimumPointWidth  = 0.125;
 325       clip.MaximumPointWidth  = 255.875;
 326       clip.MaximumVPIndex     = pCreateInfo->pViewportState->viewportCount - 1;
 327    }
 328
 329    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM), wm) {
 330       wm.StatisticsEnable                    = true;
 331       wm.LineEndCapAntialiasingRegionWidth   = _05pixels;
 332       wm.LineAntialiasingRegionWidth         = _10pixels;
 333       wm.ForceThreadDispatchEnable           = NORMAL;
 334       wm.PointRasterizationRule              = RASTRULE_UPPER_RIGHT;
 335
 336       if (wm_prog_data && wm_prog_data->early_fragment_tests) {
 337          wm.EarlyDepthStencilControl         = PREPS;
 338       } else if (wm_prog_data && wm_prog_data->has_side_effects) {
 339          wm.EarlyDepthStencilControl         = PSEXEC;
 340       } else {
 341          wm.EarlyDepthStencilControl         = NORMAL;
 342       }
 343
 344       wm.BarycentricInterpolationMode = pipeline->ps_ksp0 == NO_KERNEL ?
 345          0 : wm_prog_data->barycentric_interp_modes;
 346    }
 347
 348    if (pipeline->gs_kernel == NO_KERNEL) {
 349       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs);
 350    } else {
 351       const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
 352       offset = 1;
 353       length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
 354
 355       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs) {
 356          gs.SingleProgramFlow       = false;
 357          gs.KernelStartPointer      = pipeline->gs_kernel;
 358          gs.VectorMaskEnable        = false;
 359          gs.SamplerCount            = 0;
 360          gs.BindingTableEntryCount  = 0;
 361          gs.ExpectedVertexCount     = gs_prog_data->vertices_in;
 362
 363          gs.ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_GEOMETRY];
 364          gs.PerThreadScratchSpace   = scratch_space(&gs_prog_data->base.base);
 365          gs.OutputVertexSize        = gs_prog_data->output_vertex_size_hwords * 2 - 1;
 366          gs.OutputTopology          = gs_prog_data->output_topology;
 367          gs.VertexURBEntryReadLength = gs_prog_data->base.urb_read_length;
 368          gs.IncludeVertexHandles    = gs_prog_data->base.include_vue_handles;
 369
 370          gs.DispatchGRFStartRegisterForURBData =
 371             gs_prog_data->base.base.dispatch_grf_start_reg;
 372
 373          gs.MaximumNumberofThreads  = device->info.max_gs_threads / 2 - 1;
 374          gs.ControlDataHeaderSize   = gs_prog_data->control_data_header_size_hwords;
 375          gs.DispatchMode            = gs_prog_data->base.dispatch_mode;
 376          gs.StatisticsEnable        = true;
 377          gs.IncludePrimitiveID      = gs_prog_data->include_primitive_id;
 378          gs.ReorderMode             = TRAILING;
 379          gs.Enable                  = true;
 380
 381          gs.ControlDataFormat       = gs_prog_data->control_data_format;
 382
 383          gs.StaticOutput            = gs_prog_data->static_vertex_count >= 0;
 384          gs.StaticOutputVertexCount =
 385             gs_prog_data->static_vertex_count >= 0 ?
 386             gs_prog_data->static_vertex_count : 0;
 387
 388          /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
 389           * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
 390           * UserClipDistanceCullTestEnableBitmask(v)
 391           */
 392
 393          gs.VertexURBEntryOutputReadOffset = offset;
 394          gs.VertexURBEntryOutputLength = length;
 395       }
 396    }
 397
 398    const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
 399    /* Skip the VUE header and position slots */
 400    offset = 1;
 401    length = (vs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
 402
 403    uint32_t vs_start = pipeline->vs_simd8 != NO_KERNEL ? pipeline->vs_simd8 :
 404                                                          pipeline->vs_vec4;
 405
 406    if (vs_start == NO_KERNEL || (extra && extra->disable_vs)) {
 407       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
 408          vs.FunctionEnable = false;
 409          /* Even if VS is disabled, SBE still gets the amount of
 410           * vertex data to read from this field. */
 411          vs.VertexURBEntryOutputReadOffset = offset;
 412          vs.VertexURBEntryOutputLength = length;
 413       }
 414    } else {
 415       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
 416          vs.KernelStartPointer            = vs_start;
 417          vs.SingleVertexDispatch          = false;
 418          vs.VectorMaskEnable              = false;
 419          vs.SamplerCount                  = 0;
 420
 421          vs.BindingTableEntryCount =
 422             vs_prog_data->base.base.binding_table.size_bytes / 4,
 423
 424          vs.ThreadDispatchPriority        = false;
 425          vs.FloatingPointMode             = IEEE754;
 426          vs.IllegalOpcodeExceptionEnable  = false;
 427          vs.AccessesUAV                   = false;
 428          vs.SoftwareExceptionEnable       = false;
 429
 430          vs.ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_VERTEX],
 431          vs.PerThreadScratchSpace   = scratch_space(&vs_prog_data->base.base);
 432
 433          vs.DispatchGRFStartRegisterForURBData =
 434             vs_prog_data->base.base.dispatch_grf_start_reg;
 435
 436          vs.VertexURBEntryReadLength      = vs_prog_data->base.urb_read_length;
 437          vs.VertexURBEntryReadOffset      = 0;
 438
 439          vs.MaximumNumberofThreads        = device->info.max_vs_threads - 1;
 440          vs.StatisticsEnable              = false;
 441          vs.SIMD8DispatchEnable           = pipeline->vs_simd8 != NO_KERNEL;
 442          vs.VertexCacheDisable            = false;
 443          vs.FunctionEnable                = true;
 444
 445          vs.VertexURBEntryOutputReadOffset = offset;
 446          vs.VertexURBEntryOutputLength    = length;
 447
 448          /* TODO */
 449          vs.UserClipDistanceClipTestEnableBitmask = 0;
 450          vs.UserClipDistanceCullTestEnableBitmask = 0;
 451       }
 452    }
 453
 454    const int num_thread_bias = GEN_GEN == 8 ? 2 : 1;
 455    if (pipeline->ps_ksp0 == NO_KERNEL) {
 456       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps);
 457       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA), extra) {
 458          extra.PixelShaderValid = false;
 459       }
 460    } else {
 461       emit_3dstate_sbe(pipeline);
 462
 463       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) {
 464          ps.KernelStartPointer0     = pipeline->ps_ksp0;
 465          ps.KernelStartPointer1     = 0;
 466          ps.KernelStartPointer2     = pipeline->ps_ksp0 + wm_prog_data->prog_offset_2;
 467          ps._8PixelDispatchEnable   = wm_prog_data->dispatch_8;
 468          ps._16PixelDispatchEnable  = wm_prog_data->dispatch_16;
 469          ps._32PixelDispatchEnable  = false;
 470          ps.SingleProgramFlow       = false;
 471          ps.VectorMaskEnable        = true;
 472          ps.SamplerCount            = 1;
 473          ps.PushConstantEnable      = wm_prog_data->base.nr_params > 0;
 474          ps.PositionXYOffsetSelect  = wm_prog_data->uses_pos_offset ?
 475             POSOFFSET_SAMPLE: POSOFFSET_NONE;
 476
 477          ps.MaximumNumberofThreadsPerPSD = 64 - num_thread_bias;
 478
 479          ps.ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_FRAGMENT];
 480          ps.PerThreadScratchSpace   = scratch_space(&wm_prog_data->base);
 481
 482          ps.DispatchGRFStartRegisterForConstantSetupData0 =
 483             wm_prog_data->base.dispatch_grf_start_reg;
 484          ps.DispatchGRFStartRegisterForConstantSetupData1 = 0;
 485          ps.DispatchGRFStartRegisterForConstantSetupData2 =
 486             wm_prog_data->dispatch_grf_start_reg_2;
 487       }
 488
 489       bool per_sample_ps = pCreateInfo->pMultisampleState &&
 490                            pCreateInfo->pMultisampleState->sampleShadingEnable;
 491
 492       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA), ps) {
 493          ps.PixelShaderValid              = true;
 494          ps.PixelShaderKillsPixel         = wm_prog_data->uses_kill;
 495          ps.PixelShaderComputedDepthMode  = wm_prog_data->computed_depth_mode;
 496          ps.AttributeEnable               = wm_prog_data->num_varying_inputs > 0;
 497          ps.oMaskPresenttoRenderTarget    = wm_prog_data->uses_omask;
 498          ps.PixelShaderIsPerSample        = per_sample_ps;
 499          ps.PixelShaderUsesSourceDepth    = wm_prog_data->uses_src_depth;
 500          ps.PixelShaderUsesSourceW        = wm_prog_data->uses_src_w;
 501 #if GEN_GEN >= 9
 502          ps.PixelShaderPullsBary    = wm_prog_data->pulls_bary;
 503          ps.InputCoverageMaskState  = wm_prog_data->uses_sample_mask ?
 504             ICMS_INNER_CONSERVATIVE : ICMS_NONE;
 505 #else
 506          ps.PixelShaderUsesInputCoverageMask = wm_prog_data->uses_sample_mask;
 507 #endif
 508       }
 509    }
 510
 511    *pPipeline = anv_pipeline_to_handle(pipeline);
 512
 513    return VK_SUCCESS;
 514 }