src/intel/vulkan/gen8_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #include "genX_pipeline_util.h"
  36
  37 static void
  38 emit_ia_state(struct anv_pipeline *pipeline,
  39               const VkPipelineInputAssemblyStateCreateInfo *info,
  40               const struct anv_graphics_pipeline_create_info *extra)
  41 {
  42    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_TOPOLOGY),
  43                   .PrimitiveTopologyType = pipeline->topology);
  44 }
  45
  46 static void
  47 emit_rs_state(struct anv_pipeline *pipeline,
  48               const VkPipelineRasterizationStateCreateInfo *info,
  49               const VkPipelineMultisampleStateCreateInfo *ms_info,
  50               const struct anv_graphics_pipeline_create_info *extra)
  51 {
  52    uint32_t samples = 1;
  53
  54    if (ms_info)
  55       samples = ms_info->rasterizationSamples;
  56
  57    struct GENX(3DSTATE_SF) sf = {
  58       GENX(3DSTATE_SF_header),
  59       .ViewportTransformEnable = !(extra && extra->disable_viewport),
  60       .TriangleStripListProvokingVertexSelect = 0,
  61       .LineStripListProvokingVertexSelect = 0,
  62       .TriangleFanProvokingVertexSelect = 0,
  63       .PointWidthSource = pipeline->writes_point_size ? Vertex : State,
  64       .PointWidth = 1.0,
  65    };
  66
  67    /* FINISHME: VkBool32 rasterizerDiscardEnable; */
  68
  69    GENX(3DSTATE_SF_pack)(NULL, pipeline->gen8.sf, &sf);
  70
  71    struct GENX(3DSTATE_RASTER) raster = {
  72       GENX(3DSTATE_RASTER_header),
  73
  74       /* For details on 3DSTATE_RASTER multisample state, see the BSpec table
  75        * "Multisample Modes State".
  76        */
  77       .DXMultisampleRasterizationEnable = samples > 1,
  78       .ForcedSampleCount = FSC_NUMRASTSAMPLES_0,
  79       .ForceMultisampling = false,
  80
  81       .FrontWinding = vk_to_gen_front_face[info->frontFace],
  82       .CullMode = vk_to_gen_cullmode[info->cullMode],
  83       .FrontFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
  84       .BackFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
  85       .ScissorRectangleEnable = !(extra && extra->disable_scissor),
  86 #if GEN_GEN == 8
  87       .ViewportZClipTestEnable = true,
  88 #else
  89       /* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
  90       .ViewportZFarClipTestEnable = true,
  91       .ViewportZNearClipTestEnable = true,
  92 #endif
  93    };
  94
  95    GENX(3DSTATE_RASTER_pack)(NULL, pipeline->gen8.raster, &raster);
  96 }
  97
  98 static void
  99 emit_cb_state(struct anv_pipeline *pipeline,
 100               const VkPipelineColorBlendStateCreateInfo *info,
 101               const VkPipelineMultisampleStateCreateInfo *ms_info)
 102 {
 103    struct anv_device *device = pipeline->device;
 104
 105    uint32_t num_dwords = GENX(BLEND_STATE_length);
 106    pipeline->blend_state =
 107       anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
 108
 109    struct GENX(BLEND_STATE) blend_state = {
 110       .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
 111       .AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable,
 112    };
 113
 114    bool has_writeable_rt = false;
 115    for (uint32_t i = 0; i < info->attachmentCount; i++) {
 116       const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[i];
 117
 118       if (a->srcColorBlendFactor != a->srcAlphaBlendFactor ||
 119           a->dstColorBlendFactor != a->dstAlphaBlendFactor ||
 120           a->colorBlendOp != a->alphaBlendOp) {
 121          blend_state.IndependentAlphaBlendEnable = true;
 122       }
 123
 124       blend_state.Entry[i] = (struct GENX(BLEND_STATE_ENTRY)) {
 125          .LogicOpEnable = info->logicOpEnable,
 126          .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
 127          .ColorBufferBlendEnable = a->blendEnable,
 128          .PreBlendSourceOnlyClampEnable = false,
 129          .ColorClampRange = COLORCLAMP_RTFORMAT,
 130          .PreBlendColorClampEnable = true,
 131          .PostBlendColorClampEnable = true,
 132          .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
 133          .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
 134          .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
 135          .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
 136          .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
 137          .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
 138          .WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
 139          .WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
 140          .WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
 141          .WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
 142       };
 143
 144       if (a->colorWriteMask != 0)
 145          has_writeable_rt = true;
 146
 147       /* Our hardware applies the blend factor prior to the blend function
 148        * regardless of what function is used.  Technically, this means the
 149        * hardware can do MORE than GL or Vulkan specify.  However, it also
 150        * means that, for MIN and MAX, we have to stomp the blend factor to
 151        * ONE to make it a no-op.
 152        */
 153       if (a->colorBlendOp == VK_BLEND_OP_MIN ||
 154           a->colorBlendOp == VK_BLEND_OP_MAX) {
 155          blend_state.Entry[i].SourceBlendFactor = BLENDFACTOR_ONE;
 156          blend_state.Entry[i].DestinationBlendFactor = BLENDFACTOR_ONE;
 157       }
 158       if (a->alphaBlendOp == VK_BLEND_OP_MIN ||
 159           a->alphaBlendOp == VK_BLEND_OP_MAX) {
 160          blend_state.Entry[i].SourceAlphaBlendFactor = BLENDFACTOR_ONE;
 161          blend_state.Entry[i].DestinationAlphaBlendFactor = BLENDFACTOR_ONE;
 162       }
 163    }
 164
 165    for (uint32_t i = info->attachmentCount; i < 8; i++) {
 166       blend_state.Entry[i].WriteDisableAlpha = true;
 167       blend_state.Entry[i].WriteDisableRed = true;
 168       blend_state.Entry[i].WriteDisableGreen = true;
 169       blend_state.Entry[i].WriteDisableBlue = true;
 170    }
 171
 172    if (info->attachmentCount > 0) {
 173       struct GENX(BLEND_STATE_ENTRY) *bs = &blend_state.Entry[0];
 174
 175       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_BLEND),
 176                      .AlphaToCoverageEnable = blend_state.AlphaToCoverageEnable,
 177                      .HasWriteableRT = has_writeable_rt,
 178                      .ColorBufferBlendEnable = bs->ColorBufferBlendEnable,
 179                      .SourceAlphaBlendFactor = bs->SourceAlphaBlendFactor,
 180                      .DestinationAlphaBlendFactor =
 181                         bs->DestinationAlphaBlendFactor,
 182                      .SourceBlendFactor = bs->SourceBlendFactor,
 183                      .DestinationBlendFactor = bs->DestinationBlendFactor,
 184                      .AlphaTestEnable = false,
 185                      .IndependentAlphaBlendEnable =
 186                         blend_state.IndependentAlphaBlendEnable);
 187    } else {
 188       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_BLEND));
 189    }
 190
 191    GENX(BLEND_STATE_pack)(NULL, pipeline->blend_state.map, &blend_state);
 192    if (!device->info.has_llc)
 193       anv_state_clflush(pipeline->blend_state);
 194
 195    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_BLEND_STATE_POINTERS),
 196                   .BlendStatePointer = pipeline->blend_state.offset,
 197                   .BlendStatePointerValid = true);
 198 }
 199
 200 static void
 201 emit_ds_state(struct anv_pipeline *pipeline,
 202               const VkPipelineDepthStencilStateCreateInfo *info)
 203 {
 204    uint32_t *dw = GEN_GEN == 8 ?
 205       pipeline->gen8.wm_depth_stencil : pipeline->gen9.wm_depth_stencil;
 206
 207    if (info == NULL) {
 208       /* We're going to OR this together with the dynamic state.  We need
 209        * to make sure it's initialized to something useful.
 210        */
 211       memset(pipeline->gen8.wm_depth_stencil, 0,
 212              sizeof(pipeline->gen8.wm_depth_stencil));
 213       memset(pipeline->gen9.wm_depth_stencil, 0,
 214              sizeof(pipeline->gen9.wm_depth_stencil));
 215       return;
 216    }
 217
 218    /* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */
 219
 220    struct GENX(3DSTATE_WM_DEPTH_STENCIL) wm_depth_stencil = {
 221       .DepthTestEnable = info->depthTestEnable,
 222       .DepthBufferWriteEnable = info->depthWriteEnable,
 223       .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
 224       .DoubleSidedStencilEnable = true,
 225
 226       .StencilTestEnable = info->stencilTestEnable,
 227       .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
 228       .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
 229       .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
 230       .StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp],
 231       .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp],
 232       .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp],
 233       .BackfaceStencilPassDepthFailOp =vk_to_gen_stencil_op[info->back.depthFailOp],
 234       .BackfaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
 235    };
 236
 237    GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dw, &wm_depth_stencil);
 238 }
 239
 240 static void
 241 emit_ms_state(struct anv_pipeline *pipeline,
 242               const VkPipelineMultisampleStateCreateInfo *info)
 243 {
 244    uint32_t samples = 1;
 245    uint32_t log2_samples = 0;
 246
 247    /* From the Vulkan 1.0 spec:
 248     *    If pSampleMask is NULL, it is treated as if the mask has all bits
 249     *    enabled, i.e. no coverage is removed from fragments.
 250     *
 251     * 3DSTATE_SAMPLE_MASK.SampleMask is 16 bits.
 252     */
 253    uint32_t sample_mask = 0xffff;
 254
 255    if (info) {
 256       samples = info->rasterizationSamples;
 257       log2_samples = __builtin_ffs(samples) - 1;
 258    }
 259
 260    if (info && info->pSampleMask)
 261       sample_mask &= info->pSampleMask[0];
 262
 263    if (info && info->sampleShadingEnable)
 264       anv_finishme("VkPipelineMultisampleStateCreateInfo::sampleShadingEnable");
 265
 266    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_MULTISAMPLE),
 267
 268       /* The PRM says that this bit is valid only for DX9:
 269        *
 270        *    SW can choose to set this bit only for DX9 API. DX10/OGL API's
 271        *    should not have any effect by setting or not setting this bit.
 272        */
 273       .PixelPositionOffsetEnable = false,
 274
 275       .PixelLocation = CENTER,
 276       .NumberofMultisamples = log2_samples);
 277
 278    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SAMPLE_MASK),
 279       .SampleMask = sample_mask);
 280 }
 281
 282 VkResult
 283 genX(graphics_pipeline_create)(
 284     VkDevice                                    _device,
 285     struct anv_pipeline_cache *                 cache,
 286     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
 287     const struct anv_graphics_pipeline_create_info *extra,
 288     const VkAllocationCallbacks*                pAllocator,
 289     VkPipeline*                                 pPipeline)
 290 {
 291    ANV_FROM_HANDLE(anv_device, device, _device);
 292    struct anv_pipeline *pipeline;
 293    VkResult result;
 294    uint32_t offset, length;
 295
 296    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
 297
 298    pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
 299                          VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 300    if (pipeline == NULL)
 301       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 302
 303    result = anv_pipeline_init(pipeline, device, cache,
 304                               pCreateInfo, extra, pAllocator);
 305    if (result != VK_SUCCESS) {
 306       anv_free2(&device->alloc, pAllocator, pipeline);
 307       return result;
 308    }
 309
 310    assert(pCreateInfo->pVertexInputState);
 311    emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
 312    assert(pCreateInfo->pInputAssemblyState);
 313    emit_ia_state(pipeline, pCreateInfo->pInputAssemblyState, extra);
 314    assert(pCreateInfo->pRasterizationState);
 315    emit_rs_state(pipeline, pCreateInfo->pRasterizationState,
 316                  pCreateInfo->pMultisampleState, extra);
 317    emit_ms_state(pipeline, pCreateInfo->pMultisampleState);
 318    emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
 319    emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
 320                            pCreateInfo->pMultisampleState);
 321
 322    emit_urb_setup(pipeline);
 323
 324    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_CLIP),
 325                   .ClipEnable = true,
 326                   .ViewportXYClipTestEnable = !(extra && extra->disable_viewport),
 327                   .MinimumPointWidth = 0.125,
 328                   .MaximumPointWidth = 255.875,
 329                   .MaximumVPIndex = pCreateInfo->pViewportState->viewportCount - 1);
 330
 331    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM),
 332                   .StatisticsEnable = true,
 333                   .LineEndCapAntialiasingRegionWidth = _05pixels,
 334                   .LineAntialiasingRegionWidth = _10pixels,
 335                   .EarlyDepthStencilControl = NORMAL,
 336                   .ForceThreadDispatchEnable = NORMAL,
 337                   .PointRasterizationRule = RASTRULE_UPPER_RIGHT,
 338                   .BarycentricInterpolationMode =
 339                      pipeline->ps_ksp0 == NO_KERNEL ?
 340                      0 : pipeline->wm_prog_data.barycentric_interp_modes);
 341
 342    const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
 343    offset = 1;
 344    length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
 345
 346    if (pipeline->gs_kernel == NO_KERNEL)
 347       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .Enable = false);
 348    else
 349       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS),
 350                      .SingleProgramFlow = false,
 351                      .KernelStartPointer = pipeline->gs_kernel,
 352                      .VectorMaskEnable = false,
 353                      .SamplerCount = 0,
 354                      .BindingTableEntryCount = 0,
 355                      .ExpectedVertexCount = gs_prog_data->vertices_in,
 356
 357                      .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_GEOMETRY],
 358                      .PerThreadScratchSpace = scratch_space(&gs_prog_data->base.base),
 359
 360                      .OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1,
 361                      .OutputTopology = gs_prog_data->output_topology,
 362                      .VertexURBEntryReadLength = gs_prog_data->base.urb_read_length,
 363                      .IncludeVertexHandles = gs_prog_data->base.include_vue_handles,
 364                      .DispatchGRFStartRegisterForURBData =
 365                         gs_prog_data->base.base.dispatch_grf_start_reg,
 366
 367                      .MaximumNumberofThreads = device->info.max_gs_threads / 2 - 1,
 368                      .ControlDataHeaderSize = gs_prog_data->control_data_header_size_hwords,
 369                      .DispatchMode = gs_prog_data->base.dispatch_mode,
 370                      .StatisticsEnable = true,
 371                      .IncludePrimitiveID = gs_prog_data->include_primitive_id,
 372                      .ReorderMode = TRAILING,
 373                      .Enable = true,
 374
 375                      .ControlDataFormat = gs_prog_data->control_data_format,
 376
 377                      .StaticOutput = gs_prog_data->static_vertex_count >= 0,
 378                      .StaticOutputVertexCount =
 379                         gs_prog_data->static_vertex_count >= 0 ?
 380                         gs_prog_data->static_vertex_count : 0,
 381
 382                      /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
 383                       * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
 384                       * UserClipDistanceCullTestEnableBitmask(v)
 385                       */
 386
 387                      .VertexURBEntryOutputReadOffset = offset,
 388                      .VertexURBEntryOutputLength = length);
 389
 390    const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
 391    /* Skip the VUE header and position slots */
 392    offset = 1;
 393    length = (vue_prog_data->vue_map.num_slots + 1) / 2 - offset;
 394
 395    uint32_t vs_start = pipeline->vs_simd8 != NO_KERNEL ? pipeline->vs_simd8 :
 396                                                          pipeline->vs_vec4;
 397
 398    if (vs_start == NO_KERNEL || (extra && extra->disable_vs))
 399       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
 400                      .FunctionEnable = false,
 401                      /* Even if VS is disabled, SBE still gets the amount of
 402                       * vertex data to read from this field. */
 403                      .VertexURBEntryOutputReadOffset = offset,
 404                      .VertexURBEntryOutputLength = length);
 405    else
 406       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
 407                      .KernelStartPointer = vs_start,
 408                      .SingleVertexDispatch = false,
 409                      .VectorMaskEnable = false,
 410                      .SamplerCount = 0,
 411                      .BindingTableEntryCount =
 412                      vue_prog_data->base.binding_table.size_bytes / 4,
 413                      .ThreadDispatchPriority = false,
 414                      .FloatingPointMode = IEEE754,
 415                      .IllegalOpcodeExceptionEnable = false,
 416                      .AccessesUAV = false,
 417                      .SoftwareExceptionEnable = false,
 418
 419                      .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_VERTEX],
 420                      .PerThreadScratchSpace = scratch_space(&vue_prog_data->base),
 421
 422                      .DispatchGRFStartRegisterForURBData =
 423                      vue_prog_data->base.dispatch_grf_start_reg,
 424                      .VertexURBEntryReadLength = vue_prog_data->urb_read_length,
 425                      .VertexURBEntryReadOffset = 0,
 426
 427                      .MaximumNumberofThreads = device->info.max_vs_threads - 1,
 428                      .StatisticsEnable = false,
 429                      .SIMD8DispatchEnable = pipeline->vs_simd8 != NO_KERNEL,
 430                      .VertexCacheDisable = false,
 431                      .FunctionEnable = true,
 432
 433                      .VertexURBEntryOutputReadOffset = offset,
 434                      .VertexURBEntryOutputLength = length,
 435                      .UserClipDistanceClipTestEnableBitmask = 0,
 436                      .UserClipDistanceCullTestEnableBitmask = 0);
 437
 438    const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
 439
 440    const int num_thread_bias = GEN_GEN == 8 ? 2 : 1;
 441    if (pipeline->ps_ksp0 == NO_KERNEL) {
 442       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS));
 443       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA),
 444                      .PixelShaderValid = false);
 445    } else {
 446       /* TODO: We should clean this up.  Among other things, this is mostly
 447        * shared with other gens.
 448        */
 449       const struct brw_vue_map *fs_input_map;
 450       if (pipeline->gs_kernel == NO_KERNEL)
 451          fs_input_map = &vue_prog_data->vue_map;
 452       else
 453          fs_input_map = &gs_prog_data->base.vue_map;
 454
 455       struct GENX(3DSTATE_SBE_SWIZ) swiz = {
 456          GENX(3DSTATE_SBE_SWIZ_header),
 457       };
 458
 459       int max_source_attr = 0;
 460       for (int attr = 0; attr < VARYING_SLOT_MAX; attr++) {
 461          int input_index = wm_prog_data->urb_setup[attr];
 462
 463          if (input_index < 0)
 464             continue;
 465
 466          int source_attr = fs_input_map->varying_to_slot[attr];
 467          max_source_attr = MAX2(max_source_attr, source_attr);
 468
 469          if (input_index >= 16)
 470             continue;
 471
 472          if (source_attr == -1) {
 473             /* This attribute does not exist in the VUE--that means that the
 474              * vertex shader did not write to it.  It could be that it's a
 475              * regular varying read by the fragment shader but not written by
 476              * the vertex shader or it's gl_PrimitiveID. In the first case the
 477              * value is undefined, in the second it needs to be
 478              * gl_PrimitiveID.
 479              */
 480             swiz.Attribute[input_index].ConstantSource = PRIM_ID;
 481             swiz.Attribute[input_index].ComponentOverrideX = true;
 482             swiz.Attribute[input_index].ComponentOverrideY = true;
 483             swiz.Attribute[input_index].ComponentOverrideZ = true;
 484             swiz.Attribute[input_index].ComponentOverrideW = true;
 485          } else {
 486             /* We have to subtract two slots to accout for the URB entry output
 487              * read offset in the VS and GS stages.
 488              */
 489             swiz.Attribute[input_index].SourceAttribute = source_attr - 2;
 490          }
 491       }
 492
 493       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE),
 494                      .AttributeSwizzleEnable = true,
 495                      .ForceVertexURBEntryReadLength = false,
 496                      .ForceVertexURBEntryReadOffset = false,
 497                      .VertexURBEntryReadLength =
 498                         DIV_ROUND_UP(max_source_attr + 1, 2),
 499                      .PointSpriteTextureCoordinateOrigin = UPPERLEFT,
 500                      .NumberofSFOutputAttributes =
 501                      wm_prog_data->num_varying_inputs,
 502
 503 #if GEN_GEN >= 9
 504                      .Attribute0ActiveComponentFormat = ACF_XYZW,
 505                      .Attribute1ActiveComponentFormat = ACF_XYZW,
 506                      .Attribute2ActiveComponentFormat = ACF_XYZW,
 507                      .Attribute3ActiveComponentFormat = ACF_XYZW,
 508                      .Attribute4ActiveComponentFormat = ACF_XYZW,
 509                      .Attribute5ActiveComponentFormat = ACF_XYZW,
 510                      .Attribute6ActiveComponentFormat = ACF_XYZW,
 511                      .Attribute7ActiveComponentFormat = ACF_XYZW,
 512                      .Attribute8ActiveComponentFormat = ACF_XYZW,
 513                      .Attribute9ActiveComponentFormat = ACF_XYZW,
 514                      .Attribute10ActiveComponentFormat = ACF_XYZW,
 515                      .Attribute11ActiveComponentFormat = ACF_XYZW,
 516                      .Attribute12ActiveComponentFormat = ACF_XYZW,
 517                      .Attribute13ActiveComponentFormat = ACF_XYZW,
 518                      .Attribute14ActiveComponentFormat = ACF_XYZW,
 519                      .Attribute15ActiveComponentFormat = ACF_XYZW,
 520                      /* wow, much field, very attribute */
 521                      .Attribute16ActiveComponentFormat = ACF_XYZW,
 522                      .Attribute17ActiveComponentFormat = ACF_XYZW,
 523                      .Attribute18ActiveComponentFormat = ACF_XYZW,
 524                      .Attribute19ActiveComponentFormat = ACF_XYZW,
 525                      .Attribute20ActiveComponentFormat = ACF_XYZW,
 526                      .Attribute21ActiveComponentFormat = ACF_XYZW,
 527                      .Attribute22ActiveComponentFormat = ACF_XYZW,
 528                      .Attribute23ActiveComponentFormat = ACF_XYZW,
 529                      .Attribute24ActiveComponentFormat = ACF_XYZW,
 530                      .Attribute25ActiveComponentFormat = ACF_XYZW,
 531                      .Attribute26ActiveComponentFormat = ACF_XYZW,
 532                      .Attribute27ActiveComponentFormat = ACF_XYZW,
 533                      .Attribute28ActiveComponentFormat = ACF_XYZW,
 534                      .Attribute29ActiveComponentFormat = ACF_XYZW,
 535                      .Attribute28ActiveComponentFormat = ACF_XYZW,
 536                      .Attribute29ActiveComponentFormat = ACF_XYZW,
 537                      .Attribute30ActiveComponentFormat = ACF_XYZW,
 538 #endif
 539          );
 540
 541       uint32_t *dw = anv_batch_emit_dwords(&pipeline->batch,
 542                                            GENX(3DSTATE_SBE_SWIZ_length));
 543       GENX(3DSTATE_SBE_SWIZ_pack)(&pipeline->batch, dw, &swiz);
 544
 545       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
 546                      .KernelStartPointer0 = pipeline->ps_ksp0,
 547
 548                      .SingleProgramFlow = false,
 549                      .VectorMaskEnable = true,
 550                      .SamplerCount = 1,
 551
 552                      .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_FRAGMENT],
 553                      .PerThreadScratchSpace = scratch_space(&wm_prog_data->base),
 554
 555                      .MaximumNumberofThreadsPerPSD = 64 - num_thread_bias,
 556                      .PositionXYOffsetSelect = wm_prog_data->uses_pos_offset ?
 557                         POSOFFSET_SAMPLE: POSOFFSET_NONE,
 558                      .PushConstantEnable = wm_prog_data->base.nr_params > 0,
 559                      ._8PixelDispatchEnable = pipeline->ps_simd8 != NO_KERNEL,
 560                      ._16PixelDispatchEnable = pipeline->ps_simd16 != NO_KERNEL,
 561                      ._32PixelDispatchEnable = false,
 562
 563                      .DispatchGRFStartRegisterForConstantSetupData0 = pipeline->ps_grf_start0,
 564                      .DispatchGRFStartRegisterForConstantSetupData1 = 0,
 565                      .DispatchGRFStartRegisterForConstantSetupData2 = pipeline->ps_grf_start2,
 566
 567                      .KernelStartPointer1 = 0,
 568                      .KernelStartPointer2 = pipeline->ps_ksp2);
 569
 570       bool per_sample_ps = pCreateInfo->pMultisampleState &&
 571                            pCreateInfo->pMultisampleState->sampleShadingEnable;
 572
 573       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA),
 574                      .PixelShaderValid = true,
 575                      .PixelShaderKillsPixel = wm_prog_data->uses_kill,
 576                      .PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode,
 577                      .AttributeEnable = wm_prog_data->num_varying_inputs > 0,
 578                      .oMaskPresenttoRenderTarget = wm_prog_data->uses_omask,
 579                      .PixelShaderIsPerSample = per_sample_ps,
 580                      .PixelShaderUsesSourceDepth = wm_prog_data->uses_src_depth,
 581                      .PixelShaderUsesSourceW = wm_prog_data->uses_src_w,
 582 #if GEN_GEN >= 9
 583                      .PixelShaderPullsBary = wm_prog_data->pulls_bary,
 584                      .InputCoverageMaskState = wm_prog_data->uses_sample_mask ?
 585                         ICMS_INNER_CONSERVATIVE : ICMS_NONE,
 586 #else
 587                      .PixelShaderUsesInputCoverageMask =
 588                         wm_prog_data->uses_sample_mask,
 589 #endif
 590          );
 591    }
 592
 593    *pPipeline = anv_pipeline_to_handle(pipeline);
 594
 595    return VK_SUCCESS;
 596 }