src/intel/vulkan/gen8_pipeline.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #include "genX_pipeline_util.h"
  36
  37 static void
  38 emit_ia_state(struct anv_pipeline *pipeline,
  39               const VkPipelineInputAssemblyStateCreateInfo *info,
  40               const struct anv_graphics_pipeline_create_info *extra)
  41 {
  42    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_TOPOLOGY),
  43                   .PrimitiveTopologyType = pipeline->topology);
  44 }
  45
  46 static void
  47 emit_rs_state(struct anv_pipeline *pipeline,
  48               const VkPipelineRasterizationStateCreateInfo *info,
  49               const VkPipelineMultisampleStateCreateInfo *ms_info,
  50               const struct anv_graphics_pipeline_create_info *extra)
  51 {
  52    uint32_t samples = 1;
  53
  54    if (ms_info)
  55       samples = ms_info->rasterizationSamples;
  56
  57    struct GENX(3DSTATE_SF) sf = {
  58       GENX(3DSTATE_SF_header),
  59       .ViewportTransformEnable = !(extra && extra->disable_viewport),
  60       .TriangleStripListProvokingVertexSelect = 0,
  61       .LineStripListProvokingVertexSelect = 0,
  62       .TriangleFanProvokingVertexSelect = 1,
  63       .PointWidthSource = pipeline->writes_point_size ? Vertex : State,
  64       .PointWidth = 1.0,
  65    };
  66
  67    /* FINISHME: VkBool32 rasterizerDiscardEnable; */
  68
  69    GENX(3DSTATE_SF_pack)(NULL, pipeline->gen8.sf, &sf);
  70
  71    struct GENX(3DSTATE_RASTER) raster = {
  72       GENX(3DSTATE_RASTER_header),
  73
  74       /* For details on 3DSTATE_RASTER multisample state, see the BSpec table
  75        * "Multisample Modes State".
  76        */
  77       .DXMultisampleRasterizationEnable = samples > 1,
  78       .ForcedSampleCount = FSC_NUMRASTSAMPLES_0,
  79       .ForceMultisampling = false,
  80
  81       .FrontWinding = vk_to_gen_front_face[info->frontFace],
  82       .CullMode = vk_to_gen_cullmode[info->cullMode],
  83       .FrontFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
  84       .BackFaceFillMode = vk_to_gen_fillmode[info->polygonMode],
  85       .ScissorRectangleEnable = !(extra && extra->disable_scissor),
  86 #if GEN_GEN == 8
  87       .ViewportZClipTestEnable = true,
  88 #else
  89       /* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
  90       .ViewportZFarClipTestEnable = true,
  91       .ViewportZNearClipTestEnable = true,
  92 #endif
  93       .GlobalDepthOffsetEnableSolid = info->depthBiasEnable,
  94       .GlobalDepthOffsetEnableWireframe = info->depthBiasEnable,
  95       .GlobalDepthOffsetEnablePoint = info->depthBiasEnable,
  96    };
  97
  98    GENX(3DSTATE_RASTER_pack)(NULL, pipeline->gen8.raster, &raster);
  99 }
 100
 101 static void
 102 emit_cb_state(struct anv_pipeline *pipeline,
 103               const VkPipelineColorBlendStateCreateInfo *info,
 104               const VkPipelineMultisampleStateCreateInfo *ms_info)
 105 {
 106    struct anv_device *device = pipeline->device;
 107
 108    uint32_t num_dwords = GENX(BLEND_STATE_length);
 109    pipeline->blend_state =
 110       anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
 111
 112    struct GENX(BLEND_STATE) blend_state = {
 113       .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable,
 114       .AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable,
 115    };
 116
 117    bool has_writeable_rt = false;
 118    for (uint32_t i = 0; i < info->attachmentCount; i++) {
 119       const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[i];
 120
 121       if (a->srcColorBlendFactor != a->srcAlphaBlendFactor ||
 122           a->dstColorBlendFactor != a->dstAlphaBlendFactor ||
 123           a->colorBlendOp != a->alphaBlendOp) {
 124          blend_state.IndependentAlphaBlendEnable = true;
 125       }
 126
 127       blend_state.Entry[i] = (struct GENX(BLEND_STATE_ENTRY)) {
 128          .LogicOpEnable = info->logicOpEnable,
 129          .LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
 130          .ColorBufferBlendEnable = a->blendEnable,
 131          .PreBlendSourceOnlyClampEnable = false,
 132          .ColorClampRange = COLORCLAMP_RTFORMAT,
 133          .PreBlendColorClampEnable = true,
 134          .PostBlendColorClampEnable = true,
 135          .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor],
 136          .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor],
 137          .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp],
 138          .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor],
 139          .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor],
 140          .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp],
 141          .WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT),
 142          .WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT),
 143          .WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT),
 144          .WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT),
 145       };
 146
 147       if (a->colorWriteMask != 0)
 148          has_writeable_rt = true;
 149
 150       /* Our hardware applies the blend factor prior to the blend function
 151        * regardless of what function is used.  Technically, this means the
 152        * hardware can do MORE than GL or Vulkan specify.  However, it also
 153        * means that, for MIN and MAX, we have to stomp the blend factor to
 154        * ONE to make it a no-op.
 155        */
 156       if (a->colorBlendOp == VK_BLEND_OP_MIN ||
 157           a->colorBlendOp == VK_BLEND_OP_MAX) {
 158          blend_state.Entry[i].SourceBlendFactor = BLENDFACTOR_ONE;
 159          blend_state.Entry[i].DestinationBlendFactor = BLENDFACTOR_ONE;
 160       }
 161       if (a->alphaBlendOp == VK_BLEND_OP_MIN ||
 162           a->alphaBlendOp == VK_BLEND_OP_MAX) {
 163          blend_state.Entry[i].SourceAlphaBlendFactor = BLENDFACTOR_ONE;
 164          blend_state.Entry[i].DestinationAlphaBlendFactor = BLENDFACTOR_ONE;
 165       }
 166    }
 167
 168    for (uint32_t i = info->attachmentCount; i < 8; i++) {
 169       blend_state.Entry[i].WriteDisableAlpha = true;
 170       blend_state.Entry[i].WriteDisableRed = true;
 171       blend_state.Entry[i].WriteDisableGreen = true;
 172       blend_state.Entry[i].WriteDisableBlue = true;
 173    }
 174
 175    if (info->attachmentCount > 0) {
 176       struct GENX(BLEND_STATE_ENTRY) *bs = &blend_state.Entry[0];
 177
 178       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_BLEND),
 179                      .AlphaToCoverageEnable = blend_state.AlphaToCoverageEnable,
 180                      .HasWriteableRT = has_writeable_rt,
 181                      .ColorBufferBlendEnable = bs->ColorBufferBlendEnable,
 182                      .SourceAlphaBlendFactor = bs->SourceAlphaBlendFactor,
 183                      .DestinationAlphaBlendFactor =
 184                         bs->DestinationAlphaBlendFactor,
 185                      .SourceBlendFactor = bs->SourceBlendFactor,
 186                      .DestinationBlendFactor = bs->DestinationBlendFactor,
 187                      .AlphaTestEnable = false,
 188                      .IndependentAlphaBlendEnable =
 189                         blend_state.IndependentAlphaBlendEnable);
 190    } else {
 191       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_BLEND));
 192    }
 193
 194    GENX(BLEND_STATE_pack)(NULL, pipeline->blend_state.map, &blend_state);
 195    if (!device->info.has_llc)
 196       anv_state_clflush(pipeline->blend_state);
 197
 198    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_BLEND_STATE_POINTERS),
 199                   .BlendStatePointer = pipeline->blend_state.offset,
 200                   .BlendStatePointerValid = true);
 201 }
 202
 203 static void
 204 emit_ds_state(struct anv_pipeline *pipeline,
 205               const VkPipelineDepthStencilStateCreateInfo *info)
 206 {
 207    uint32_t *dw = GEN_GEN == 8 ?
 208       pipeline->gen8.wm_depth_stencil : pipeline->gen9.wm_depth_stencil;
 209
 210    if (info == NULL) {
 211       /* We're going to OR this together with the dynamic state.  We need
 212        * to make sure it's initialized to something useful.
 213        */
 214       memset(pipeline->gen8.wm_depth_stencil, 0,
 215              sizeof(pipeline->gen8.wm_depth_stencil));
 216       memset(pipeline->gen9.wm_depth_stencil, 0,
 217              sizeof(pipeline->gen9.wm_depth_stencil));
 218       return;
 219    }
 220
 221    /* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */
 222
 223    struct GENX(3DSTATE_WM_DEPTH_STENCIL) wm_depth_stencil = {
 224       .DepthTestEnable = info->depthTestEnable,
 225       .DepthBufferWriteEnable = info->depthWriteEnable,
 226       .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
 227       .DoubleSidedStencilEnable = true,
 228
 229       .StencilTestEnable = info->stencilTestEnable,
 230       .StencilBufferWriteEnable = info->stencilTestEnable,
 231       .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
 232       .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
 233       .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
 234       .StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp],
 235       .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp],
 236       .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp],
 237       .BackfaceStencilPassDepthFailOp =vk_to_gen_stencil_op[info->back.depthFailOp],
 238       .BackfaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
 239    };
 240
 241    GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dw, &wm_depth_stencil);
 242 }
 243
 244 static void
 245 emit_ms_state(struct anv_pipeline *pipeline,
 246               const VkPipelineMultisampleStateCreateInfo *info)
 247 {
 248    uint32_t samples = 1;
 249    uint32_t log2_samples = 0;
 250
 251    /* From the Vulkan 1.0 spec:
 252     *    If pSampleMask is NULL, it is treated as if the mask has all bits
 253     *    enabled, i.e. no coverage is removed from fragments.
 254     *
 255     * 3DSTATE_SAMPLE_MASK.SampleMask is 16 bits.
 256     */
 257    uint32_t sample_mask = 0xffff;
 258
 259    if (info) {
 260       samples = info->rasterizationSamples;
 261       log2_samples = __builtin_ffs(samples) - 1;
 262    }
 263
 264    if (info && info->pSampleMask)
 265       sample_mask &= info->pSampleMask[0];
 266
 267    if (info && info->sampleShadingEnable)
 268       anv_finishme("VkPipelineMultisampleStateCreateInfo::sampleShadingEnable");
 269
 270    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_MULTISAMPLE),
 271
 272       /* The PRM says that this bit is valid only for DX9:
 273        *
 274        *    SW can choose to set this bit only for DX9 API. DX10/OGL API's
 275        *    should not have any effect by setting or not setting this bit.
 276        */
 277       .PixelPositionOffsetEnable = false,
 278
 279       .PixelLocation = CENTER,
 280       .NumberofMultisamples = log2_samples);
 281
 282    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SAMPLE_MASK),
 283       .SampleMask = sample_mask);
 284 }
 285
 286 VkResult
 287 genX(graphics_pipeline_create)(
 288     VkDevice                                    _device,
 289     struct anv_pipeline_cache *                 cache,
 290     const VkGraphicsPipelineCreateInfo*         pCreateInfo,
 291     const struct anv_graphics_pipeline_create_info *extra,
 292     const VkAllocationCallbacks*                pAllocator,
 293     VkPipeline*                                 pPipeline)
 294 {
 295    ANV_FROM_HANDLE(anv_device, device, _device);
 296    struct anv_pipeline *pipeline;
 297    VkResult result;
 298    uint32_t offset, length;
 299
 300    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
 301
 302    pipeline = anv_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
 303                          VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 304    if (pipeline == NULL)
 305       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 306
 307    result = anv_pipeline_init(pipeline, device, cache,
 308                               pCreateInfo, extra, pAllocator);
 309    if (result != VK_SUCCESS) {
 310       anv_free2(&device->alloc, pAllocator, pipeline);
 311       return result;
 312    }
 313
 314    assert(pCreateInfo->pVertexInputState);
 315    emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
 316    assert(pCreateInfo->pInputAssemblyState);
 317    emit_ia_state(pipeline, pCreateInfo->pInputAssemblyState, extra);
 318    assert(pCreateInfo->pRasterizationState);
 319    emit_rs_state(pipeline, pCreateInfo->pRasterizationState,
 320                  pCreateInfo->pMultisampleState, extra);
 321    emit_ms_state(pipeline, pCreateInfo->pMultisampleState);
 322    emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
 323    emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
 324                            pCreateInfo->pMultisampleState);
 325
 326    emit_urb_setup(pipeline);
 327
 328    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_CLIP),
 329                   .ClipEnable = true,
 330                   .EarlyCullEnable = true,
 331                   .APIMode = 1, /* D3D */
 332                   .ViewportXYClipTestEnable = !(extra && extra->disable_viewport),
 333
 334                   .ClipMode =
 335                      pCreateInfo->pRasterizationState->rasterizerDiscardEnable ?
 336                      REJECT_ALL : NORMAL,
 337
 338                   .NonPerspectiveBarycentricEnable =
 339                      (pipeline->wm_prog_data.barycentric_interp_modes & 0x38) != 0,
 340
 341                   .TriangleStripListProvokingVertexSelect = 0,
 342                   .LineStripListProvokingVertexSelect = 0,
 343                   .TriangleFanProvokingVertexSelect = 1,
 344
 345                   .MinimumPointWidth = 0.125,
 346                   .MaximumPointWidth = 255.875,
 347                   .MaximumVPIndex = pCreateInfo->pViewportState->viewportCount - 1);
 348
 349    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM),
 350                   .StatisticsEnable = true,
 351                   .LineEndCapAntialiasingRegionWidth = _05pixels,
 352                   .LineAntialiasingRegionWidth = _10pixels,
 353                   .EarlyDepthStencilControl = NORMAL,
 354                   .ForceThreadDispatchEnable = NORMAL,
 355                   .PointRasterizationRule = RASTRULE_UPPER_RIGHT,
 356                   .BarycentricInterpolationMode =
 357                      pipeline->ps_ksp0 == NO_KERNEL ?
 358                      0 : pipeline->wm_prog_data.barycentric_interp_modes);
 359
 360    const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
 361    offset = 1;
 362    length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
 363
 364    if (pipeline->gs_kernel == NO_KERNEL)
 365       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .Enable = false);
 366    else
 367       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS),
 368                      .SingleProgramFlow = false,
 369                      .KernelStartPointer = pipeline->gs_kernel,
 370                      .VectorMaskEnable = false,
 371                      .SamplerCount = 0,
 372                      .BindingTableEntryCount = 0,
 373                      .ExpectedVertexCount = gs_prog_data->vertices_in,
 374
 375                      .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_GEOMETRY],
 376                      .PerThreadScratchSpace = scratch_space(&gs_prog_data->base.base),
 377
 378                      .OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1,
 379                      .OutputTopology = gs_prog_data->output_topology,
 380                      .VertexURBEntryReadLength = gs_prog_data->base.urb_read_length,
 381                      .IncludeVertexHandles = gs_prog_data->base.include_vue_handles,
 382                      .DispatchGRFStartRegisterForURBData =
 383                         gs_prog_data->base.base.dispatch_grf_start_reg,
 384
 385                      .MaximumNumberofThreads = device->info.max_gs_threads / 2 - 1,
 386                      .ControlDataHeaderSize = gs_prog_data->control_data_header_size_hwords,
 387                      .DispatchMode = gs_prog_data->base.dispatch_mode,
 388                      .StatisticsEnable = true,
 389                      .IncludePrimitiveID = gs_prog_data->include_primitive_id,
 390                      .ReorderMode = TRAILING,
 391                      .Enable = true,
 392
 393                      .ControlDataFormat = gs_prog_data->control_data_format,
 394
 395                      .StaticOutput = gs_prog_data->static_vertex_count >= 0,
 396                      .StaticOutputVertexCount =
 397                         gs_prog_data->static_vertex_count >= 0 ?
 398                         gs_prog_data->static_vertex_count : 0,
 399
 400                      /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
 401                       * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
 402                       * UserClipDistanceCullTestEnableBitmask(v)
 403                       */
 404
 405                      .VertexURBEntryOutputReadOffset = offset,
 406                      .VertexURBEntryOutputLength = length);
 407
 408    const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
 409    /* Skip the VUE header and position slots */
 410    offset = 1;
 411    length = (vue_prog_data->vue_map.num_slots + 1) / 2 - offset;
 412
 413    uint32_t vs_start = pipeline->vs_simd8 != NO_KERNEL ? pipeline->vs_simd8 :
 414                                                          pipeline->vs_vec4;
 415
 416    if (vs_start == NO_KERNEL || (extra && extra->disable_vs))
 417       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
 418                      .FunctionEnable = false,
 419                      /* Even if VS is disabled, SBE still gets the amount of
 420                       * vertex data to read from this field. */
 421                      .VertexURBEntryOutputReadOffset = offset,
 422                      .VertexURBEntryOutputLength = length);
 423    else
 424       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
 425                      .KernelStartPointer = vs_start,
 426                      .SingleVertexDispatch = false,
 427                      .VectorMaskEnable = false,
 428                      .SamplerCount = 0,
 429                      .BindingTableEntryCount =
 430                      vue_prog_data->base.binding_table.size_bytes / 4,
 431                      .ThreadDispatchPriority = false,
 432                      .FloatingPointMode = IEEE754,
 433                      .IllegalOpcodeExceptionEnable = false,
 434                      .AccessesUAV = false,
 435                      .SoftwareExceptionEnable = false,
 436
 437                      .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_VERTEX],
 438                      .PerThreadScratchSpace = scratch_space(&vue_prog_data->base),
 439
 440                      .DispatchGRFStartRegisterForURBData =
 441                      vue_prog_data->base.dispatch_grf_start_reg,
 442                      .VertexURBEntryReadLength = vue_prog_data->urb_read_length,
 443                      .VertexURBEntryReadOffset = 0,
 444
 445                      .MaximumNumberofThreads = device->info.max_vs_threads - 1,
 446                      .StatisticsEnable = false,
 447                      .SIMD8DispatchEnable = pipeline->vs_simd8 != NO_KERNEL,
 448                      .VertexCacheDisable = false,
 449                      .FunctionEnable = true,
 450
 451                      .VertexURBEntryOutputReadOffset = offset,
 452                      .VertexURBEntryOutputLength = length,
 453                      .UserClipDistanceClipTestEnableBitmask = 0,
 454                      .UserClipDistanceCullTestEnableBitmask = 0);
 455
 456    const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
 457
 458    const int num_thread_bias = GEN_GEN == 8 ? 2 : 1;
 459    if (pipeline->ps_ksp0 == NO_KERNEL) {
 460       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS));
 461       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA),
 462                      .PixelShaderValid = false);
 463    } else {
 464       emit_3dstate_sbe(pipeline);
 465
 466       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
 467                      .KernelStartPointer0 = pipeline->ps_ksp0,
 468
 469                      .SingleProgramFlow = false,
 470                      .VectorMaskEnable = true,
 471                      .SamplerCount = 1,
 472
 473                      .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_FRAGMENT],
 474                      .PerThreadScratchSpace = scratch_space(&wm_prog_data->base),
 475
 476                      .MaximumNumberofThreadsPerPSD = 64 - num_thread_bias,
 477                      .PositionXYOffsetSelect = wm_prog_data->uses_pos_offset ?
 478                         POSOFFSET_SAMPLE: POSOFFSET_NONE,
 479                      .PushConstantEnable = wm_prog_data->base.nr_params > 0,
 480                      ._8PixelDispatchEnable = pipeline->ps_simd8 != NO_KERNEL,
 481                      ._16PixelDispatchEnable = pipeline->ps_simd16 != NO_KERNEL,
 482                      ._32PixelDispatchEnable = false,
 483
 484                      .DispatchGRFStartRegisterForConstantSetupData0 = pipeline->ps_grf_start0,
 485                      .DispatchGRFStartRegisterForConstantSetupData1 = 0,
 486                      .DispatchGRFStartRegisterForConstantSetupData2 = pipeline->ps_grf_start2,
 487
 488                      .KernelStartPointer1 = 0,
 489                      .KernelStartPointer2 = pipeline->ps_ksp2);
 490
 491       bool per_sample_ps = pCreateInfo->pMultisampleState &&
 492                            pCreateInfo->pMultisampleState->sampleShadingEnable;
 493
 494       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA),
 495                      .PixelShaderValid = true,
 496                      .PixelShaderKillsPixel = wm_prog_data->uses_kill,
 497                      .PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode,
 498                      .AttributeEnable = wm_prog_data->num_varying_inputs > 0,
 499                      .oMaskPresenttoRenderTarget = wm_prog_data->uses_omask,
 500                      .PixelShaderIsPerSample = per_sample_ps,
 501                      .PixelShaderUsesSourceDepth = wm_prog_data->uses_src_depth,
 502                      .PixelShaderUsesSourceW = wm_prog_data->uses_src_w,
 503 #if GEN_GEN >= 9
 504                      .PixelShaderPullsBary = wm_prog_data->pulls_bary,
 505                      .InputCoverageMaskState = wm_prog_data->uses_sample_mask ?
 506                         ICMS_INNER_CONSERVATIVE : ICMS_NONE,
 507 #else
 508                      .PixelShaderUsesInputCoverageMask =
 509                         wm_prog_data->uses_sample_mask,
 510 #endif
 511          );
 512    }
 513
 514    *pPipeline = anv_pipeline_to_handle(pipeline);
 515
 516    return VK_SUCCESS;
 517 }