2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
35 #include "genX_pipeline_util.h"
38 emit_ia_state(struct anv_pipeline
*pipeline
,
39 const VkPipelineInputAssemblyStateCreateInfo
*info
,
40 const struct anv_graphics_pipeline_create_info
*extra
)
42 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_TOPOLOGY
),
43 .PrimitiveTopologyType
= pipeline
->topology
);
47 emit_rs_state(struct anv_pipeline
*pipeline
,
48 const VkPipelineRasterizationStateCreateInfo
*info
,
49 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
50 const struct anv_graphics_pipeline_create_info
*extra
)
55 samples
= ms_info
->rasterizationSamples
;
57 struct GENX(3DSTATE_SF
) sf
= {
58 GENX(3DSTATE_SF_header
),
59 .ViewportTransformEnable
= !(extra
&& extra
->use_rectlist
),
60 .TriangleStripListProvokingVertexSelect
= 0,
61 .LineStripListProvokingVertexSelect
= 0,
62 .TriangleFanProvokingVertexSelect
= 1,
63 .PointWidthSource
= Vertex
,
67 /* FINISHME: VkBool32 rasterizerDiscardEnable; */
69 GENX(3DSTATE_SF_pack
)(NULL
, pipeline
->gen8
.sf
, &sf
);
71 struct GENX(3DSTATE_RASTER
) raster
= {
72 GENX(3DSTATE_RASTER_header
),
74 /* For details on 3DSTATE_RASTER multisample state, see the BSpec table
75 * "Multisample Modes State".
77 .DXMultisampleRasterizationEnable
= samples
> 1,
78 .ForcedSampleCount
= FSC_NUMRASTSAMPLES_0
,
79 .ForceMultisampling
= false,
81 .FrontWinding
= vk_to_gen_front_face
[info
->frontFace
],
82 .CullMode
= vk_to_gen_cullmode
[info
->cullMode
],
83 .FrontFaceFillMode
= vk_to_gen_fillmode
[info
->polygonMode
],
84 .BackFaceFillMode
= vk_to_gen_fillmode
[info
->polygonMode
],
85 .ScissorRectangleEnable
= !(extra
&& extra
->disable_scissor
),
87 .ViewportZClipTestEnable
= true,
89 /* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
90 .ViewportZFarClipTestEnable
= true,
91 .ViewportZNearClipTestEnable
= true,
93 .GlobalDepthOffsetEnableSolid
= info
->depthBiasEnable
,
94 .GlobalDepthOffsetEnableWireframe
= info
->depthBiasEnable
,
95 .GlobalDepthOffsetEnablePoint
= info
->depthBiasEnable
,
98 GENX(3DSTATE_RASTER_pack
)(NULL
, pipeline
->gen8
.raster
, &raster
);
102 emit_cb_state(struct anv_pipeline
*pipeline
,
103 const VkPipelineColorBlendStateCreateInfo
*info
,
104 const VkPipelineMultisampleStateCreateInfo
*ms_info
)
106 struct anv_device
*device
= pipeline
->device
;
108 uint32_t num_dwords
= GENX(BLEND_STATE_length
);
109 pipeline
->blend_state
=
110 anv_state_pool_alloc(&device
->dynamic_state_pool
, num_dwords
* 4, 64);
112 struct GENX(BLEND_STATE
) blend_state
= {
113 .AlphaToCoverageEnable
= ms_info
&& ms_info
->alphaToCoverageEnable
,
114 .AlphaToOneEnable
= ms_info
&& ms_info
->alphaToOneEnable
,
117 /* Default everything to disabled */
118 for (uint32_t i
= 0; i
< 8; i
++) {
119 blend_state
.Entry
[i
].WriteDisableAlpha
= true;
120 blend_state
.Entry
[i
].WriteDisableRed
= true;
121 blend_state
.Entry
[i
].WriteDisableGreen
= true;
122 blend_state
.Entry
[i
].WriteDisableBlue
= true;
125 struct anv_pipeline_bind_map
*map
=
126 &pipeline
->bindings
[MESA_SHADER_FRAGMENT
];
128 bool has_writeable_rt
= false;
129 for (unsigned i
= 0; i
< map
->surface_count
; i
++) {
130 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[i
];
132 /* All color attachments are at the beginning of the binding table */
133 if (binding
->set
!= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
)
136 /* We can have at most 8 attachments */
139 if (binding
->offset
>= info
->attachmentCount
)
142 const VkPipelineColorBlendAttachmentState
*a
=
143 &info
->pAttachments
[binding
->offset
];
145 if (a
->srcColorBlendFactor
!= a
->srcAlphaBlendFactor
||
146 a
->dstColorBlendFactor
!= a
->dstAlphaBlendFactor
||
147 a
->colorBlendOp
!= a
->alphaBlendOp
) {
148 blend_state
.IndependentAlphaBlendEnable
= true;
151 blend_state
.Entry
[i
] = (struct GENX(BLEND_STATE_ENTRY
)) {
152 .LogicOpEnable
= info
->logicOpEnable
,
153 .LogicOpFunction
= vk_to_gen_logic_op
[info
->logicOp
],
154 .ColorBufferBlendEnable
= a
->blendEnable
,
155 .PreBlendSourceOnlyClampEnable
= false,
156 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
157 .PreBlendColorClampEnable
= true,
158 .PostBlendColorClampEnable
= true,
159 .SourceBlendFactor
= vk_to_gen_blend
[a
->srcColorBlendFactor
],
160 .DestinationBlendFactor
= vk_to_gen_blend
[a
->dstColorBlendFactor
],
161 .ColorBlendFunction
= vk_to_gen_blend_op
[a
->colorBlendOp
],
162 .SourceAlphaBlendFactor
= vk_to_gen_blend
[a
->srcAlphaBlendFactor
],
163 .DestinationAlphaBlendFactor
= vk_to_gen_blend
[a
->dstAlphaBlendFactor
],
164 .AlphaBlendFunction
= vk_to_gen_blend_op
[a
->alphaBlendOp
],
165 .WriteDisableAlpha
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_A_BIT
),
166 .WriteDisableRed
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_R_BIT
),
167 .WriteDisableGreen
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_G_BIT
),
168 .WriteDisableBlue
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_B_BIT
),
171 if (a
->colorWriteMask
!= 0)
172 has_writeable_rt
= true;
174 /* Our hardware applies the blend factor prior to the blend function
175 * regardless of what function is used. Technically, this means the
176 * hardware can do MORE than GL or Vulkan specify. However, it also
177 * means that, for MIN and MAX, we have to stomp the blend factor to
178 * ONE to make it a no-op.
180 if (a
->colorBlendOp
== VK_BLEND_OP_MIN
||
181 a
->colorBlendOp
== VK_BLEND_OP_MAX
) {
182 blend_state
.Entry
[i
].SourceBlendFactor
= BLENDFACTOR_ONE
;
183 blend_state
.Entry
[i
].DestinationBlendFactor
= BLENDFACTOR_ONE
;
185 if (a
->alphaBlendOp
== VK_BLEND_OP_MIN
||
186 a
->alphaBlendOp
== VK_BLEND_OP_MAX
) {
187 blend_state
.Entry
[i
].SourceAlphaBlendFactor
= BLENDFACTOR_ONE
;
188 blend_state
.Entry
[i
].DestinationAlphaBlendFactor
= BLENDFACTOR_ONE
;
192 struct GENX(BLEND_STATE_ENTRY
) *bs0
= &blend_state
.Entry
[0];
194 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS_BLEND
),
195 .AlphaToCoverageEnable
= blend_state
.AlphaToCoverageEnable
,
196 .HasWriteableRT
= has_writeable_rt
,
197 .ColorBufferBlendEnable
= bs0
->ColorBufferBlendEnable
,
198 .SourceAlphaBlendFactor
= bs0
->SourceAlphaBlendFactor
,
199 .DestinationAlphaBlendFactor
=
200 bs0
->DestinationAlphaBlendFactor
,
201 .SourceBlendFactor
= bs0
->SourceBlendFactor
,
202 .DestinationBlendFactor
= bs0
->DestinationBlendFactor
,
203 .AlphaTestEnable
= false,
204 .IndependentAlphaBlendEnable
=
205 blend_state
.IndependentAlphaBlendEnable
);
207 GENX(BLEND_STATE_pack
)(NULL
, pipeline
->blend_state
.map
, &blend_state
);
208 if (!device
->info
.has_llc
)
209 anv_state_clflush(pipeline
->blend_state
);
211 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
),
212 .BlendStatePointer
= pipeline
->blend_state
.offset
,
213 .BlendStatePointerValid
= true);
217 emit_ds_state(struct anv_pipeline
*pipeline
,
218 const VkPipelineDepthStencilStateCreateInfo
*info
)
220 uint32_t *dw
= GEN_GEN
== 8 ?
221 pipeline
->gen8
.wm_depth_stencil
: pipeline
->gen9
.wm_depth_stencil
;
224 /* We're going to OR this together with the dynamic state. We need
225 * to make sure it's initialized to something useful.
227 memset(pipeline
->gen8
.wm_depth_stencil
, 0,
228 sizeof(pipeline
->gen8
.wm_depth_stencil
));
229 memset(pipeline
->gen9
.wm_depth_stencil
, 0,
230 sizeof(pipeline
->gen9
.wm_depth_stencil
));
234 /* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */
236 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) wm_depth_stencil
= {
237 .DepthTestEnable
= info
->depthTestEnable
,
238 .DepthBufferWriteEnable
= info
->depthWriteEnable
,
239 .DepthTestFunction
= vk_to_gen_compare_op
[info
->depthCompareOp
],
240 .DoubleSidedStencilEnable
= true,
242 .StencilTestEnable
= info
->stencilTestEnable
,
243 .StencilBufferWriteEnable
= info
->stencilTestEnable
,
244 .StencilFailOp
= vk_to_gen_stencil_op
[info
->front
.failOp
],
245 .StencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->front
.passOp
],
246 .StencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
->front
.depthFailOp
],
247 .StencilTestFunction
= vk_to_gen_compare_op
[info
->front
.compareOp
],
248 .BackfaceStencilFailOp
= vk_to_gen_stencil_op
[info
->back
.failOp
],
249 .BackfaceStencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->back
.passOp
],
250 .BackfaceStencilPassDepthFailOp
=vk_to_gen_stencil_op
[info
->back
.depthFailOp
],
251 .BackfaceStencilTestFunction
= vk_to_gen_compare_op
[info
->back
.compareOp
],
254 /* From the Broadwell PRM:
256 * "If Depth_Test_Enable = 1 AND Depth_Test_func = EQUAL, the
257 * Depth_Write_Enable must be set to 0."
259 if (info
->depthTestEnable
&& info
->depthCompareOp
== VK_COMPARE_OP_EQUAL
)
260 wm_depth_stencil
.DepthBufferWriteEnable
= false;
262 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, dw
, &wm_depth_stencil
);
266 emit_ms_state(struct anv_pipeline
*pipeline
,
267 const VkPipelineMultisampleStateCreateInfo
*info
)
269 uint32_t samples
= 1;
270 uint32_t log2_samples
= 0;
272 /* From the Vulkan 1.0 spec:
273 * If pSampleMask is NULL, it is treated as if the mask has all bits
274 * enabled, i.e. no coverage is removed from fragments.
276 * 3DSTATE_SAMPLE_MASK.SampleMask is 16 bits.
278 uint32_t sample_mask
= 0xffff;
281 samples
= info
->rasterizationSamples
;
282 log2_samples
= __builtin_ffs(samples
) - 1;
285 if (info
&& info
->pSampleMask
)
286 sample_mask
&= info
->pSampleMask
[0];
288 if (info
&& info
->sampleShadingEnable
)
289 anv_finishme("VkPipelineMultisampleStateCreateInfo::sampleShadingEnable");
291 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_MULTISAMPLE
),
293 /* The PRM says that this bit is valid only for DX9:
295 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
296 * should not have any effect by setting or not setting this bit.
298 .PixelPositionOffsetEnable
= false,
300 .PixelLocation
= CENTER
,
301 .NumberofMultisamples
= log2_samples
);
303 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_SAMPLE_MASK
),
304 .SampleMask
= sample_mask
);
308 genX(graphics_pipeline_create
)(
310 struct anv_pipeline_cache
* cache
,
311 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
312 const struct anv_graphics_pipeline_create_info
*extra
,
313 const VkAllocationCallbacks
* pAllocator
,
314 VkPipeline
* pPipeline
)
316 ANV_FROM_HANDLE(anv_device
, device
, _device
);
317 struct anv_pipeline
*pipeline
;
319 uint32_t offset
, length
;
321 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
323 pipeline
= anv_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
324 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
325 if (pipeline
== NULL
)
326 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
328 result
= anv_pipeline_init(pipeline
, device
, cache
,
329 pCreateInfo
, extra
, pAllocator
);
330 if (result
!= VK_SUCCESS
) {
331 anv_free2(&device
->alloc
, pAllocator
, pipeline
);
335 assert(pCreateInfo
->pVertexInputState
);
336 emit_vertex_input(pipeline
, pCreateInfo
->pVertexInputState
, extra
);
337 assert(pCreateInfo
->pInputAssemblyState
);
338 emit_ia_state(pipeline
, pCreateInfo
->pInputAssemblyState
, extra
);
339 assert(pCreateInfo
->pRasterizationState
);
340 emit_rs_state(pipeline
, pCreateInfo
->pRasterizationState
,
341 pCreateInfo
->pMultisampleState
, extra
);
342 emit_ms_state(pipeline
, pCreateInfo
->pMultisampleState
);
343 emit_ds_state(pipeline
, pCreateInfo
->pDepthStencilState
);
344 emit_cb_state(pipeline
, pCreateInfo
->pColorBlendState
,
345 pCreateInfo
->pMultisampleState
);
347 emit_urb_setup(pipeline
);
349 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
350 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_CLIP
),
351 .ClipEnable
= !(extra
&& extra
->use_rectlist
),
352 .EarlyCullEnable
= true,
353 .APIMode
= 1, /* D3D */
354 .ViewportXYClipTestEnable
= !(extra
&& extra
->disable_viewport
),
357 pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
?
360 .NonPerspectiveBarycentricEnable
= wm_prog_data
?
361 (wm_prog_data
->barycentric_interp_modes
& 0x38) != 0 : 0,
363 .TriangleStripListProvokingVertexSelect
= 0,
364 .LineStripListProvokingVertexSelect
= 0,
365 .TriangleFanProvokingVertexSelect
= 1,
367 .MinimumPointWidth
= 0.125,
368 .MaximumPointWidth
= 255.875,
369 .MaximumVPIndex
= pCreateInfo
->pViewportState
->viewportCount
- 1);
371 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_WM
),
372 .StatisticsEnable
= true,
373 .LineEndCapAntialiasingRegionWidth
= _05pixels
,
374 .LineAntialiasingRegionWidth
= _10pixels
,
375 .EarlyDepthStencilControl
= NORMAL
,
376 .ForceThreadDispatchEnable
= NORMAL
,
377 .PointRasterizationRule
= RASTRULE_UPPER_RIGHT
,
378 .BarycentricInterpolationMode
=
379 pipeline
->ps_ksp0
== NO_KERNEL
?
380 0 : wm_prog_data
->barycentric_interp_modes
);
382 if (pipeline
->gs_kernel
== NO_KERNEL
) {
383 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_GS
), .Enable
= false);
385 const struct brw_gs_prog_data
*gs_prog_data
= get_gs_prog_data(pipeline
);
387 length
= (gs_prog_data
->base
.vue_map
.num_slots
+ 1) / 2 - offset
;
389 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_GS
),
390 .SingleProgramFlow
= false,
391 .KernelStartPointer
= pipeline
->gs_kernel
,
392 .VectorMaskEnable
= false,
394 .BindingTableEntryCount
= 0,
395 .ExpectedVertexCount
= gs_prog_data
->vertices_in
,
397 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[MESA_SHADER_GEOMETRY
],
398 .PerThreadScratchSpace
= scratch_space(&gs_prog_data
->base
.base
),
400 .OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1,
401 .OutputTopology
= gs_prog_data
->output_topology
,
402 .VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
,
403 .IncludeVertexHandles
= gs_prog_data
->base
.include_vue_handles
,
404 .DispatchGRFStartRegisterForURBData
=
405 gs_prog_data
->base
.base
.dispatch_grf_start_reg
,
407 .MaximumNumberofThreads
= device
->info
.max_gs_threads
/ 2 - 1,
408 .ControlDataHeaderSize
= gs_prog_data
->control_data_header_size_hwords
,
409 .DispatchMode
= gs_prog_data
->base
.dispatch_mode
,
410 .StatisticsEnable
= true,
411 .IncludePrimitiveID
= gs_prog_data
->include_primitive_id
,
412 .ReorderMode
= TRAILING
,
415 .ControlDataFormat
= gs_prog_data
->control_data_format
,
417 .StaticOutput
= gs_prog_data
->static_vertex_count
>= 0,
418 .StaticOutputVertexCount
=
419 gs_prog_data
->static_vertex_count
>= 0 ?
420 gs_prog_data
->static_vertex_count
: 0,
422 /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
423 * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
424 * UserClipDistanceCullTestEnableBitmask(v)
427 .VertexURBEntryOutputReadOffset
= offset
,
428 .VertexURBEntryOutputLength
= length
);
431 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
432 /* Skip the VUE header and position slots */
434 length
= (vs_prog_data
->base
.vue_map
.num_slots
+ 1) / 2 - offset
;
436 uint32_t vs_start
= pipeline
->vs_simd8
!= NO_KERNEL
? pipeline
->vs_simd8
:
439 if (vs_start
== NO_KERNEL
|| (extra
&& extra
->disable_vs
))
440 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VS
),
441 .FunctionEnable
= false,
442 /* Even if VS is disabled, SBE still gets the amount of
443 * vertex data to read from this field. */
444 .VertexURBEntryOutputReadOffset
= offset
,
445 .VertexURBEntryOutputLength
= length
);
447 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VS
),
448 .KernelStartPointer
= vs_start
,
449 .SingleVertexDispatch
= false,
450 .VectorMaskEnable
= false,
452 .BindingTableEntryCount
=
453 vs_prog_data
->base
.base
.binding_table
.size_bytes
/ 4,
454 .ThreadDispatchPriority
= false,
455 .FloatingPointMode
= IEEE754
,
456 .IllegalOpcodeExceptionEnable
= false,
457 .AccessesUAV
= false,
458 .SoftwareExceptionEnable
= false,
460 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[MESA_SHADER_VERTEX
],
461 .PerThreadScratchSpace
= scratch_space(&vs_prog_data
->base
.base
),
463 .DispatchGRFStartRegisterForURBData
=
464 vs_prog_data
->base
.base
.dispatch_grf_start_reg
,
465 .VertexURBEntryReadLength
= vs_prog_data
->base
.urb_read_length
,
466 .VertexURBEntryReadOffset
= 0,
468 .MaximumNumberofThreads
= device
->info
.max_vs_threads
- 1,
469 .StatisticsEnable
= false,
470 .SIMD8DispatchEnable
= pipeline
->vs_simd8
!= NO_KERNEL
,
471 .VertexCacheDisable
= false,
472 .FunctionEnable
= true,
474 .VertexURBEntryOutputReadOffset
= offset
,
475 .VertexURBEntryOutputLength
= length
,
476 .UserClipDistanceClipTestEnableBitmask
= 0,
477 .UserClipDistanceCullTestEnableBitmask
= 0);
479 const int num_thread_bias
= GEN_GEN
== 8 ? 2 : 1;
480 if (pipeline
->ps_ksp0
== NO_KERNEL
) {
481 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS
));
482 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS_EXTRA
),
483 .PixelShaderValid
= false);
485 emit_3dstate_sbe(pipeline
);
487 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS
),
488 .KernelStartPointer0
= pipeline
->ps_ksp0
,
490 .SingleProgramFlow
= false,
491 .VectorMaskEnable
= true,
494 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[MESA_SHADER_FRAGMENT
],
495 .PerThreadScratchSpace
= scratch_space(&wm_prog_data
->base
),
497 .MaximumNumberofThreadsPerPSD
= 64 - num_thread_bias
,
498 .PositionXYOffsetSelect
= wm_prog_data
->uses_pos_offset
?
499 POSOFFSET_SAMPLE
: POSOFFSET_NONE
,
500 .PushConstantEnable
= wm_prog_data
->base
.nr_params
> 0,
501 ._8PixelDispatchEnable
= pipeline
->ps_simd8
!= NO_KERNEL
,
502 ._16PixelDispatchEnable
= pipeline
->ps_simd16
!= NO_KERNEL
,
503 ._32PixelDispatchEnable
= false,
505 .DispatchGRFStartRegisterForConstantSetupData0
= pipeline
->ps_grf_start0
,
506 .DispatchGRFStartRegisterForConstantSetupData1
= 0,
507 .DispatchGRFStartRegisterForConstantSetupData2
= pipeline
->ps_grf_start2
,
509 .KernelStartPointer1
= 0,
510 .KernelStartPointer2
= pipeline
->ps_ksp2
);
512 bool per_sample_ps
= pCreateInfo
->pMultisampleState
&&
513 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
515 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS_EXTRA
),
516 .PixelShaderValid
= true,
517 .PixelShaderKillsPixel
= wm_prog_data
->uses_kill
,
518 .PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
,
519 .AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0,
520 .oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
,
521 .PixelShaderIsPerSample
= per_sample_ps
,
522 .PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
,
523 .PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
,
525 .PixelShaderPullsBary
= wm_prog_data
->pulls_bary
,
526 .InputCoverageMaskState
= wm_prog_data
->uses_sample_mask
?
527 ICMS_INNER_CONSERVATIVE
: ICMS_NONE
,
529 .PixelShaderUsesInputCoverageMask
=
530 wm_prog_data
->uses_sample_mask
,
535 *pPipeline
= anv_pipeline_to_handle(pipeline
);