2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
35 #include "genX_pipeline_util.h"
38 emit_ia_state(struct anv_pipeline
*pipeline
,
39 const VkPipelineInputAssemblyStateCreateInfo
*info
,
40 const struct anv_graphics_pipeline_create_info
*extra
)
42 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_TOPOLOGY
),
43 .PrimitiveTopologyType
= pipeline
->topology
);
47 emit_rs_state(struct anv_pipeline
*pipeline
,
48 const VkPipelineRasterizationStateCreateInfo
*info
,
49 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
50 const struct anv_graphics_pipeline_create_info
*extra
)
55 samples
= ms_info
->rasterizationSamples
;
57 struct GENX(3DSTATE_SF
) sf
= {
58 GENX(3DSTATE_SF_header
),
59 .ViewportTransformEnable
= !(extra
&& extra
->disable_viewport
),
60 .TriangleStripListProvokingVertexSelect
= 0,
61 .LineStripListProvokingVertexSelect
= 0,
62 .TriangleFanProvokingVertexSelect
= 0,
63 .PointWidthSource
= pipeline
->writes_point_size
? Vertex
: State
,
67 /* FINISHME: VkBool32 rasterizerDiscardEnable; */
69 GENX(3DSTATE_SF_pack
)(NULL
, pipeline
->gen8
.sf
, &sf
);
71 struct GENX(3DSTATE_RASTER
) raster
= {
72 GENX(3DSTATE_RASTER_header
),
74 /* For details on 3DSTATE_RASTER multisample state, see the BSpec table
75 * "Multisample Modes State".
77 .DXMultisampleRasterizationEnable
= samples
> 1,
78 .ForcedSampleCount
= FSC_NUMRASTSAMPLES_0
,
79 .ForceMultisampling
= false,
81 .FrontWinding
= vk_to_gen_front_face
[info
->frontFace
],
82 .CullMode
= vk_to_gen_cullmode
[info
->cullMode
],
83 .FrontFaceFillMode
= vk_to_gen_fillmode
[info
->polygonMode
],
84 .BackFaceFillMode
= vk_to_gen_fillmode
[info
->polygonMode
],
85 .ScissorRectangleEnable
= !(extra
&& extra
->disable_scissor
),
87 .ViewportZClipTestEnable
= true,
89 /* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
90 .ViewportZFarClipTestEnable
= true,
91 .ViewportZNearClipTestEnable
= true,
93 .GlobalDepthOffsetEnableSolid
= info
->depthBiasEnable
,
94 .GlobalDepthOffsetEnableWireframe
= info
->depthBiasEnable
,
95 .GlobalDepthOffsetEnablePoint
= info
->depthBiasEnable
,
98 GENX(3DSTATE_RASTER_pack
)(NULL
, pipeline
->gen8
.raster
, &raster
);
102 emit_cb_state(struct anv_pipeline
*pipeline
,
103 const VkPipelineColorBlendStateCreateInfo
*info
,
104 const VkPipelineMultisampleStateCreateInfo
*ms_info
)
106 struct anv_device
*device
= pipeline
->device
;
108 uint32_t num_dwords
= GENX(BLEND_STATE_length
);
109 pipeline
->blend_state
=
110 anv_state_pool_alloc(&device
->dynamic_state_pool
, num_dwords
* 4, 64);
112 struct GENX(BLEND_STATE
) blend_state
= {
113 .AlphaToCoverageEnable
= ms_info
&& ms_info
->alphaToCoverageEnable
,
114 .AlphaToOneEnable
= ms_info
&& ms_info
->alphaToOneEnable
,
117 bool has_writeable_rt
= false;
118 for (uint32_t i
= 0; i
< info
->attachmentCount
; i
++) {
119 const VkPipelineColorBlendAttachmentState
*a
= &info
->pAttachments
[i
];
121 if (a
->srcColorBlendFactor
!= a
->srcAlphaBlendFactor
||
122 a
->dstColorBlendFactor
!= a
->dstAlphaBlendFactor
||
123 a
->colorBlendOp
!= a
->alphaBlendOp
) {
124 blend_state
.IndependentAlphaBlendEnable
= true;
127 blend_state
.Entry
[i
] = (struct GENX(BLEND_STATE_ENTRY
)) {
128 .LogicOpEnable
= info
->logicOpEnable
,
129 .LogicOpFunction
= vk_to_gen_logic_op
[info
->logicOp
],
130 .ColorBufferBlendEnable
= a
->blendEnable
,
131 .PreBlendSourceOnlyClampEnable
= false,
132 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
133 .PreBlendColorClampEnable
= true,
134 .PostBlendColorClampEnable
= true,
135 .SourceBlendFactor
= vk_to_gen_blend
[a
->srcColorBlendFactor
],
136 .DestinationBlendFactor
= vk_to_gen_blend
[a
->dstColorBlendFactor
],
137 .ColorBlendFunction
= vk_to_gen_blend_op
[a
->colorBlendOp
],
138 .SourceAlphaBlendFactor
= vk_to_gen_blend
[a
->srcAlphaBlendFactor
],
139 .DestinationAlphaBlendFactor
= vk_to_gen_blend
[a
->dstAlphaBlendFactor
],
140 .AlphaBlendFunction
= vk_to_gen_blend_op
[a
->alphaBlendOp
],
141 .WriteDisableAlpha
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_A_BIT
),
142 .WriteDisableRed
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_R_BIT
),
143 .WriteDisableGreen
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_G_BIT
),
144 .WriteDisableBlue
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_B_BIT
),
147 if (a
->colorWriteMask
!= 0)
148 has_writeable_rt
= true;
150 /* Our hardware applies the blend factor prior to the blend function
151 * regardless of what function is used. Technically, this means the
152 * hardware can do MORE than GL or Vulkan specify. However, it also
153 * means that, for MIN and MAX, we have to stomp the blend factor to
154 * ONE to make it a no-op.
156 if (a
->colorBlendOp
== VK_BLEND_OP_MIN
||
157 a
->colorBlendOp
== VK_BLEND_OP_MAX
) {
158 blend_state
.Entry
[i
].SourceBlendFactor
= BLENDFACTOR_ONE
;
159 blend_state
.Entry
[i
].DestinationBlendFactor
= BLENDFACTOR_ONE
;
161 if (a
->alphaBlendOp
== VK_BLEND_OP_MIN
||
162 a
->alphaBlendOp
== VK_BLEND_OP_MAX
) {
163 blend_state
.Entry
[i
].SourceAlphaBlendFactor
= BLENDFACTOR_ONE
;
164 blend_state
.Entry
[i
].DestinationAlphaBlendFactor
= BLENDFACTOR_ONE
;
168 for (uint32_t i
= info
->attachmentCount
; i
< 8; i
++) {
169 blend_state
.Entry
[i
].WriteDisableAlpha
= true;
170 blend_state
.Entry
[i
].WriteDisableRed
= true;
171 blend_state
.Entry
[i
].WriteDisableGreen
= true;
172 blend_state
.Entry
[i
].WriteDisableBlue
= true;
175 if (info
->attachmentCount
> 0) {
176 struct GENX(BLEND_STATE_ENTRY
) *bs
= &blend_state
.Entry
[0];
178 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS_BLEND
),
179 .AlphaToCoverageEnable
= blend_state
.AlphaToCoverageEnable
,
180 .HasWriteableRT
= has_writeable_rt
,
181 .ColorBufferBlendEnable
= bs
->ColorBufferBlendEnable
,
182 .SourceAlphaBlendFactor
= bs
->SourceAlphaBlendFactor
,
183 .DestinationAlphaBlendFactor
=
184 bs
->DestinationAlphaBlendFactor
,
185 .SourceBlendFactor
= bs
->SourceBlendFactor
,
186 .DestinationBlendFactor
= bs
->DestinationBlendFactor
,
187 .AlphaTestEnable
= false,
188 .IndependentAlphaBlendEnable
=
189 blend_state
.IndependentAlphaBlendEnable
);
191 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS_BLEND
));
194 GENX(BLEND_STATE_pack
)(NULL
, pipeline
->blend_state
.map
, &blend_state
);
195 if (!device
->info
.has_llc
)
196 anv_state_clflush(pipeline
->blend_state
);
198 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
),
199 .BlendStatePointer
= pipeline
->blend_state
.offset
,
200 .BlendStatePointerValid
= true);
204 emit_ds_state(struct anv_pipeline
*pipeline
,
205 const VkPipelineDepthStencilStateCreateInfo
*info
)
207 uint32_t *dw
= GEN_GEN
== 8 ?
208 pipeline
->gen8
.wm_depth_stencil
: pipeline
->gen9
.wm_depth_stencil
;
211 /* We're going to OR this together with the dynamic state. We need
212 * to make sure it's initialized to something useful.
214 memset(pipeline
->gen8
.wm_depth_stencil
, 0,
215 sizeof(pipeline
->gen8
.wm_depth_stencil
));
216 memset(pipeline
->gen9
.wm_depth_stencil
, 0,
217 sizeof(pipeline
->gen9
.wm_depth_stencil
));
221 /* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */
223 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) wm_depth_stencil
= {
224 .DepthTestEnable
= info
->depthTestEnable
,
225 .DepthBufferWriteEnable
= info
->depthWriteEnable
,
226 .DepthTestFunction
= vk_to_gen_compare_op
[info
->depthCompareOp
],
227 .DoubleSidedStencilEnable
= true,
229 .StencilTestEnable
= info
->stencilTestEnable
,
230 .StencilFailOp
= vk_to_gen_stencil_op
[info
->front
.failOp
],
231 .StencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->front
.passOp
],
232 .StencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
->front
.depthFailOp
],
233 .StencilTestFunction
= vk_to_gen_compare_op
[info
->front
.compareOp
],
234 .BackfaceStencilFailOp
= vk_to_gen_stencil_op
[info
->back
.failOp
],
235 .BackfaceStencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
->back
.passOp
],
236 .BackfaceStencilPassDepthFailOp
=vk_to_gen_stencil_op
[info
->back
.depthFailOp
],
237 .BackfaceStencilTestFunction
= vk_to_gen_compare_op
[info
->back
.compareOp
],
240 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, dw
, &wm_depth_stencil
);
244 emit_ms_state(struct anv_pipeline
*pipeline
,
245 const VkPipelineMultisampleStateCreateInfo
*info
)
247 uint32_t samples
= 1;
248 uint32_t log2_samples
= 0;
250 /* From the Vulkan 1.0 spec:
251 * If pSampleMask is NULL, it is treated as if the mask has all bits
252 * enabled, i.e. no coverage is removed from fragments.
254 * 3DSTATE_SAMPLE_MASK.SampleMask is 16 bits.
256 uint32_t sample_mask
= 0xffff;
259 samples
= info
->rasterizationSamples
;
260 log2_samples
= __builtin_ffs(samples
) - 1;
263 if (info
&& info
->pSampleMask
)
264 sample_mask
&= info
->pSampleMask
[0];
266 if (info
&& info
->sampleShadingEnable
)
267 anv_finishme("VkPipelineMultisampleStateCreateInfo::sampleShadingEnable");
269 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_MULTISAMPLE
),
271 /* The PRM says that this bit is valid only for DX9:
273 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
274 * should not have any effect by setting or not setting this bit.
276 .PixelPositionOffsetEnable
= false,
278 .PixelLocation
= CENTER
,
279 .NumberofMultisamples
= log2_samples
);
281 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_SAMPLE_MASK
),
282 .SampleMask
= sample_mask
);
286 genX(graphics_pipeline_create
)(
288 struct anv_pipeline_cache
* cache
,
289 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
290 const struct anv_graphics_pipeline_create_info
*extra
,
291 const VkAllocationCallbacks
* pAllocator
,
292 VkPipeline
* pPipeline
)
294 ANV_FROM_HANDLE(anv_device
, device
, _device
);
295 struct anv_pipeline
*pipeline
;
297 uint32_t offset
, length
;
299 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
301 pipeline
= anv_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
302 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
303 if (pipeline
== NULL
)
304 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
306 result
= anv_pipeline_init(pipeline
, device
, cache
,
307 pCreateInfo
, extra
, pAllocator
);
308 if (result
!= VK_SUCCESS
) {
309 anv_free2(&device
->alloc
, pAllocator
, pipeline
);
313 assert(pCreateInfo
->pVertexInputState
);
314 emit_vertex_input(pipeline
, pCreateInfo
->pVertexInputState
, extra
);
315 assert(pCreateInfo
->pInputAssemblyState
);
316 emit_ia_state(pipeline
, pCreateInfo
->pInputAssemblyState
, extra
);
317 assert(pCreateInfo
->pRasterizationState
);
318 emit_rs_state(pipeline
, pCreateInfo
->pRasterizationState
,
319 pCreateInfo
->pMultisampleState
, extra
);
320 emit_ms_state(pipeline
, pCreateInfo
->pMultisampleState
);
321 emit_ds_state(pipeline
, pCreateInfo
->pDepthStencilState
);
322 emit_cb_state(pipeline
, pCreateInfo
->pColorBlendState
,
323 pCreateInfo
->pMultisampleState
);
325 emit_urb_setup(pipeline
);
327 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_CLIP
),
329 .ViewportXYClipTestEnable
= !(extra
&& extra
->disable_viewport
),
330 .MinimumPointWidth
= 0.125,
331 .MaximumPointWidth
= 255.875,
332 .MaximumVPIndex
= pCreateInfo
->pViewportState
->viewportCount
- 1);
334 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_WM
),
335 .StatisticsEnable
= true,
336 .LineEndCapAntialiasingRegionWidth
= _05pixels
,
337 .LineAntialiasingRegionWidth
= _10pixels
,
338 .EarlyDepthStencilControl
= NORMAL
,
339 .ForceThreadDispatchEnable
= NORMAL
,
340 .PointRasterizationRule
= RASTRULE_UPPER_RIGHT
,
341 .BarycentricInterpolationMode
=
342 pipeline
->ps_ksp0
== NO_KERNEL
?
343 0 : pipeline
->wm_prog_data
.barycentric_interp_modes
);
345 const struct brw_gs_prog_data
*gs_prog_data
= &pipeline
->gs_prog_data
;
347 length
= (gs_prog_data
->base
.vue_map
.num_slots
+ 1) / 2 - offset
;
349 if (pipeline
->gs_kernel
== NO_KERNEL
)
350 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_GS
), .Enable
= false);
352 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_GS
),
353 .SingleProgramFlow
= false,
354 .KernelStartPointer
= pipeline
->gs_kernel
,
355 .VectorMaskEnable
= false,
357 .BindingTableEntryCount
= 0,
358 .ExpectedVertexCount
= gs_prog_data
->vertices_in
,
360 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[MESA_SHADER_GEOMETRY
],
361 .PerThreadScratchSpace
= scratch_space(&gs_prog_data
->base
.base
),
363 .OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1,
364 .OutputTopology
= gs_prog_data
->output_topology
,
365 .VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
,
366 .IncludeVertexHandles
= gs_prog_data
->base
.include_vue_handles
,
367 .DispatchGRFStartRegisterForURBData
=
368 gs_prog_data
->base
.base
.dispatch_grf_start_reg
,
370 .MaximumNumberofThreads
= device
->info
.max_gs_threads
/ 2 - 1,
371 .ControlDataHeaderSize
= gs_prog_data
->control_data_header_size_hwords
,
372 .DispatchMode
= gs_prog_data
->base
.dispatch_mode
,
373 .StatisticsEnable
= true,
374 .IncludePrimitiveID
= gs_prog_data
->include_primitive_id
,
375 .ReorderMode
= TRAILING
,
378 .ControlDataFormat
= gs_prog_data
->control_data_format
,
380 .StaticOutput
= gs_prog_data
->static_vertex_count
>= 0,
381 .StaticOutputVertexCount
=
382 gs_prog_data
->static_vertex_count
>= 0 ?
383 gs_prog_data
->static_vertex_count
: 0,
385 /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
386 * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
387 * UserClipDistanceCullTestEnableBitmask(v)
390 .VertexURBEntryOutputReadOffset
= offset
,
391 .VertexURBEntryOutputLength
= length
);
393 const struct brw_vue_prog_data
*vue_prog_data
= &pipeline
->vs_prog_data
.base
;
394 /* Skip the VUE header and position slots */
396 length
= (vue_prog_data
->vue_map
.num_slots
+ 1) / 2 - offset
;
398 uint32_t vs_start
= pipeline
->vs_simd8
!= NO_KERNEL
? pipeline
->vs_simd8
:
401 if (vs_start
== NO_KERNEL
|| (extra
&& extra
->disable_vs
))
402 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VS
),
403 .FunctionEnable
= false,
404 /* Even if VS is disabled, SBE still gets the amount of
405 * vertex data to read from this field. */
406 .VertexURBEntryOutputReadOffset
= offset
,
407 .VertexURBEntryOutputLength
= length
);
409 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VS
),
410 .KernelStartPointer
= vs_start
,
411 .SingleVertexDispatch
= false,
412 .VectorMaskEnable
= false,
414 .BindingTableEntryCount
=
415 vue_prog_data
->base
.binding_table
.size_bytes
/ 4,
416 .ThreadDispatchPriority
= false,
417 .FloatingPointMode
= IEEE754
,
418 .IllegalOpcodeExceptionEnable
= false,
419 .AccessesUAV
= false,
420 .SoftwareExceptionEnable
= false,
422 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[MESA_SHADER_VERTEX
],
423 .PerThreadScratchSpace
= scratch_space(&vue_prog_data
->base
),
425 .DispatchGRFStartRegisterForURBData
=
426 vue_prog_data
->base
.dispatch_grf_start_reg
,
427 .VertexURBEntryReadLength
= vue_prog_data
->urb_read_length
,
428 .VertexURBEntryReadOffset
= 0,
430 .MaximumNumberofThreads
= device
->info
.max_vs_threads
- 1,
431 .StatisticsEnable
= false,
432 .SIMD8DispatchEnable
= pipeline
->vs_simd8
!= NO_KERNEL
,
433 .VertexCacheDisable
= false,
434 .FunctionEnable
= true,
436 .VertexURBEntryOutputReadOffset
= offset
,
437 .VertexURBEntryOutputLength
= length
,
438 .UserClipDistanceClipTestEnableBitmask
= 0,
439 .UserClipDistanceCullTestEnableBitmask
= 0);
441 const struct brw_wm_prog_data
*wm_prog_data
= &pipeline
->wm_prog_data
;
443 const int num_thread_bias
= GEN_GEN
== 8 ? 2 : 1;
444 if (pipeline
->ps_ksp0
== NO_KERNEL
) {
445 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS
));
446 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS_EXTRA
),
447 .PixelShaderValid
= false);
449 emit_3dstate_sbe(pipeline
);
451 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS
),
452 .KernelStartPointer0
= pipeline
->ps_ksp0
,
454 .SingleProgramFlow
= false,
455 .VectorMaskEnable
= true,
458 .ScratchSpaceBasePointer
= pipeline
->scratch_start
[MESA_SHADER_FRAGMENT
],
459 .PerThreadScratchSpace
= scratch_space(&wm_prog_data
->base
),
461 .MaximumNumberofThreadsPerPSD
= 64 - num_thread_bias
,
462 .PositionXYOffsetSelect
= wm_prog_data
->uses_pos_offset
?
463 POSOFFSET_SAMPLE
: POSOFFSET_NONE
,
464 .PushConstantEnable
= wm_prog_data
->base
.nr_params
> 0,
465 ._8PixelDispatchEnable
= pipeline
->ps_simd8
!= NO_KERNEL
,
466 ._16PixelDispatchEnable
= pipeline
->ps_simd16
!= NO_KERNEL
,
467 ._32PixelDispatchEnable
= false,
469 .DispatchGRFStartRegisterForConstantSetupData0
= pipeline
->ps_grf_start0
,
470 .DispatchGRFStartRegisterForConstantSetupData1
= 0,
471 .DispatchGRFStartRegisterForConstantSetupData2
= pipeline
->ps_grf_start2
,
473 .KernelStartPointer1
= 0,
474 .KernelStartPointer2
= pipeline
->ps_ksp2
);
476 bool per_sample_ps
= pCreateInfo
->pMultisampleState
&&
477 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
479 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS_EXTRA
),
480 .PixelShaderValid
= true,
481 .PixelShaderKillsPixel
= wm_prog_data
->uses_kill
,
482 .PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
,
483 .AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0,
484 .oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
,
485 .PixelShaderIsPerSample
= per_sample_ps
,
486 .PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
,
487 .PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
,
489 .PixelShaderPullsBary
= wm_prog_data
->pulls_bary
,
490 .InputCoverageMaskState
= wm_prog_data
->uses_sample_mask
?
491 ICMS_INNER_CONSERVATIVE
: ICMS_NONE
,
493 .PixelShaderUsesInputCoverageMask
=
494 wm_prog_data
->uses_sample_mask
,
499 *pPipeline
= anv_pipeline_to_handle(pipeline
);