intel/blorp: Emit VF cache invalidates for 48-bit bugs with softpin.
[mesa.git] / src / intel / vulkan / genX_blorp_exec.c
1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25
26 #include "anv_private.h"
27
28 /* These are defined in anv_private.h and blorp_genX_exec.h */
29 #undef __gen_address_type
30 #undef __gen_user_data
31 #undef __gen_combine_address
32
33 #include "common/gen_l3_config.h"
34 #include "common/gen_sample_positions.h"
35 #include "blorp/blorp_genX_exec.h"
36
37 static void *
38 blorp_emit_dwords(struct blorp_batch *batch, unsigned n)
39 {
40 struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
41 return anv_batch_emit_dwords(&cmd_buffer->batch, n);
42 }
43
44 static uint64_t
45 blorp_emit_reloc(struct blorp_batch *batch,
46 void *location, struct blorp_address address, uint32_t delta)
47 {
48 struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
49 assert(cmd_buffer->batch.start <= location &&
50 location < cmd_buffer->batch.end);
51 return anv_batch_emit_reloc(&cmd_buffer->batch, location,
52 address.buffer, address.offset + delta);
53 }
54
55 static void
56 blorp_surface_reloc(struct blorp_batch *batch, uint32_t ss_offset,
57 struct blorp_address address, uint32_t delta)
58 {
59 struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
60 VkResult result =
61 anv_reloc_list_add(&cmd_buffer->surface_relocs, &cmd_buffer->pool->alloc,
62 ss_offset, address.buffer, address.offset + delta);
63 if (result != VK_SUCCESS)
64 anv_batch_set_error(&cmd_buffer->batch, result);
65
66 void *dest = cmd_buffer->device->surface_state_pool.block_pool.map +
67 ss_offset;
68 uint64_t val = ((struct anv_bo*)address.buffer)->offset + address.offset +
69 delta;
70 write_reloc(cmd_buffer->device, dest, val, false);
71 }
72
73 #if GEN_GEN >= 7 && GEN_GEN < 10
74 static struct blorp_address
75 blorp_get_surface_base_address(struct blorp_batch *batch)
76 {
77 struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
78 return (struct blorp_address) {
79 .buffer = &cmd_buffer->device->surface_state_pool.block_pool.bo,
80 .offset = 0,
81 };
82 }
83 #endif
84
85 static void *
86 blorp_alloc_dynamic_state(struct blorp_batch *batch,
87 uint32_t size,
88 uint32_t alignment,
89 uint32_t *offset)
90 {
91 struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
92
93 struct anv_state state =
94 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, alignment);
95
96 *offset = state.offset;
97 return state.map;
98 }
99
100 static void
101 blorp_alloc_binding_table(struct blorp_batch *batch, unsigned num_entries,
102 unsigned state_size, unsigned state_alignment,
103 uint32_t *bt_offset,
104 uint32_t *surface_offsets, void **surface_maps)
105 {
106 struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
107
108 uint32_t state_offset;
109 struct anv_state bt_state;
110
111 VkResult result =
112 anv_cmd_buffer_alloc_blorp_binding_table(cmd_buffer, num_entries,
113 &state_offset, &bt_state);
114 if (result != VK_SUCCESS)
115 return;
116
117 uint32_t *bt_map = bt_state.map;
118 *bt_offset = bt_state.offset;
119
120 for (unsigned i = 0; i < num_entries; i++) {
121 struct anv_state surface_state =
122 anv_cmd_buffer_alloc_surface_state(cmd_buffer);
123 bt_map[i] = surface_state.offset + state_offset;
124 surface_offsets[i] = surface_state.offset;
125 surface_maps[i] = surface_state.map;
126 }
127
128 anv_state_flush(cmd_buffer->device, bt_state);
129 }
130
131 static void *
132 blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size,
133 struct blorp_address *addr)
134 {
135 struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
136
137 /* From the Skylake PRM, 3DSTATE_VERTEX_BUFFERS:
138 *
139 * "The VF cache needs to be invalidated before binding and then using
140 * Vertex Buffers that overlap with any previously bound Vertex Buffer
141 * (at a 64B granularity) since the last invalidation. A VF cache
142 * invalidate is performed by setting the "VF Cache Invalidation Enable"
143 * bit in PIPE_CONTROL."
144 *
145 * This restriction first appears in the Skylake PRM but the internal docs
146 * also list it as being an issue on Broadwell. In order to avoid this
147 * problem, we align all vertex buffer allocations to 64 bytes.
148 */
149 struct anv_state vb_state =
150 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, 64);
151
152 *addr = (struct blorp_address) {
153 .buffer = &cmd_buffer->device->dynamic_state_pool.block_pool.bo,
154 .offset = vb_state.offset,
155 .mocs = cmd_buffer->device->default_mocs,
156 };
157
158 return vb_state.map;
159 }
160
161 static void
162 blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch,
163 const struct blorp_address *addrs,
164 unsigned num_vbs)
165 {
166 /* anv forces all vertex buffers into the low 4GB so there are never any
167 * transitions that require a VF invalidation.
168 */
169 }
170
171 #if GEN_GEN >= 8
172 static struct blorp_address
173 blorp_get_workaround_page(struct blorp_batch *batch)
174 {
175 struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
176
177 return (struct blorp_address) {
178 .buffer = &cmd_buffer->device->workaround_bo,
179 };
180 }
181 #endif
182
183 static void
184 blorp_flush_range(struct blorp_batch *batch, void *start, size_t size)
185 {
186 struct anv_device *device = batch->blorp->driver_ctx;
187 if (!device->info.has_llc)
188 gen_flush_range(start, size);
189 }
190
191 static void
192 blorp_emit_urb_config(struct blorp_batch *batch,
193 unsigned vs_entry_size, unsigned sf_entry_size)
194 {
195 struct anv_device *device = batch->blorp->driver_ctx;
196 struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
197
198 assert(sf_entry_size == 0);
199
200 const unsigned entry_size[4] = { vs_entry_size, 1, 1, 1 };
201
202 genX(emit_urb_setup)(device, &cmd_buffer->batch,
203 cmd_buffer->state.current_l3_config,
204 VK_SHADER_STAGE_VERTEX_BIT |
205 VK_SHADER_STAGE_FRAGMENT_BIT,
206 entry_size);
207 }
208
209 void
210 genX(blorp_exec)(struct blorp_batch *batch,
211 const struct blorp_params *params)
212 {
213 struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
214
215 if (!cmd_buffer->state.current_l3_config) {
216 const struct gen_l3_config *cfg =
217 gen_get_default_l3_config(&cmd_buffer->device->info);
218 genX(cmd_buffer_config_l3)(cmd_buffer, cfg);
219 }
220
221 #if GEN_GEN >= 11
222 /* The PIPE_CONTROL command description says:
223 *
224 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
225 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
226 * Target Cache Flush by enabling this bit. When render target flush
227 * is set due to new association of BTI, PS Scoreboard Stall bit must
228 * be set in this packet."
229 */
230 cmd_buffer->state.pending_pipe_bits |=
231 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
232 ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
233 #endif
234
235 #if GEN_GEN == 7
236 /* The MI_LOAD/STORE_REGISTER_MEM commands which BLORP uses to implement
237 * indirect fast-clear colors can cause GPU hangs if we don't stall first.
238 * See genX(cmd_buffer_mi_memcpy) for more details.
239 */
240 if (params->src.clear_color_addr.buffer ||
241 params->dst.clear_color_addr.buffer)
242 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
243 #endif
244
245 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
246
247 genX(flush_pipeline_select_3d)(cmd_buffer);
248
249 genX(cmd_buffer_emit_gen7_depth_flush)(cmd_buffer);
250
251 /* BLORP doesn't do anything fancy with depth such as discards, so we want
252 * the PMA fix off. Also, off is always the safe option.
253 */
254 genX(cmd_buffer_enable_pma_fix)(cmd_buffer, false);
255
256 /* Disable VF statistics */
257 blorp_emit(batch, GENX(3DSTATE_VF_STATISTICS), vf) {
258 vf.StatisticsEnable = false;
259 }
260
261 blorp_exec(batch, params);
262
263 cmd_buffer->state.gfx.vb_dirty = ~0;
264 cmd_buffer->state.gfx.dirty = ~0;
265 cmd_buffer->state.push_constants_dirty = ~0;
266 }