src/intel/vulkan/genX_blorp_exec.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "anv_private.h"
  27 #include "genX_multisample.h"
  28
  29 /* These are defined in anv_private.h and blorp_genX_exec.h */
  30 #undef __gen_address_type
  31 #undef __gen_user_data
  32 #undef __gen_combine_address
  33
  34 #include "common/gen_l3_config.h"
  35 #include "blorp/blorp_genX_exec.h"
  36
  37 static void *
  38 blorp_emit_dwords(struct blorp_batch *batch, unsigned n)
  39 {
  40    struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
  41    return anv_batch_emit_dwords(&cmd_buffer->batch, n);
  42 }
  43
  44 static uint64_t
  45 blorp_emit_reloc(struct blorp_batch *batch,
  46                  void *location, struct blorp_address address, uint32_t delta)
  47 {
  48    struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
  49    assert(cmd_buffer->batch.start <= location &&
  50           location < cmd_buffer->batch.end);
  51    return anv_batch_emit_reloc(&cmd_buffer->batch, location,
  52                                address.buffer, address.offset + delta);
  53 }
  54
  55 static void
  56 blorp_surface_reloc(struct blorp_batch *batch, uint32_t ss_offset,
  57                     struct blorp_address address, uint32_t delta)
  58 {
  59    struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
  60    anv_reloc_list_add(&cmd_buffer->surface_relocs, &cmd_buffer->pool->alloc,
  61                       ss_offset, address.buffer, address.offset + delta);
  62 }
  63
  64 static void *
  65 blorp_alloc_dynamic_state(struct blorp_batch *batch,
  66                           enum aub_state_struct_type type,
  67                           uint32_t size,
  68                           uint32_t alignment,
  69                           uint32_t *offset)
  70 {
  71    struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
  72
  73    struct anv_state state =
  74       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, alignment);
  75
  76    *offset = state.offset;
  77    return state.map;
  78 }
  79
  80 static void
  81 blorp_alloc_binding_table(struct blorp_batch *batch, unsigned num_entries,
  82                           unsigned state_size, unsigned state_alignment,
  83                           uint32_t *bt_offset,
  84                           uint32_t *surface_offsets, void **surface_maps)
  85 {
  86    struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
  87
  88    uint32_t state_offset;
  89    struct anv_state bt_state =
  90       anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
  91                                          &state_offset);
  92    if (bt_state.map == NULL) {
  93       /* We ran out of space.  Grab a new binding table block. */
  94       VkResult result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
  95       assert(result == VK_SUCCESS);
  96
  97       /* Re-emit state base addresses so we get the new surface state base
  98        * address before we start emitting binding tables etc.
  99        */
 100       anv_cmd_buffer_emit_state_base_address(cmd_buffer);
 101
 102       bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
 103                                                     &state_offset);
 104       assert(bt_state.map != NULL);
 105    }
 106
 107    uint32_t *bt_map = bt_state.map;
 108    *bt_offset = bt_state.offset;
 109
 110    for (unsigned i = 0; i < num_entries; i++) {
 111       struct anv_state surface_state =
 112          anv_cmd_buffer_alloc_surface_state(cmd_buffer);
 113       bt_map[i] = surface_state.offset + state_offset;
 114       surface_offsets[i] = surface_state.offset;
 115       surface_maps[i] = surface_state.map;
 116    }
 117 }
 118
 119 static void *
 120 blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size,
 121                           struct blorp_address *addr)
 122 {
 123    struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
 124    struct anv_state vb_state =
 125       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, 16);
 126
 127    *addr = (struct blorp_address) {
 128       .buffer = &cmd_buffer->device->dynamic_state_block_pool.bo,
 129       .offset = vb_state.offset,
 130    };
 131
 132    return vb_state.map;
 133 }
 134
 135 static void
 136 blorp_emit_urb_config(struct blorp_batch *batch, unsigned vs_entry_size)
 137 {
 138    struct anv_device *device = batch->blorp->driver_ctx;
 139    struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
 140
 141    genX(emit_urb_setup)(device, &cmd_buffer->batch,
 142                         VK_SHADER_STAGE_VERTEX_BIT |
 143                         VK_SHADER_STAGE_FRAGMENT_BIT,
 144                         vs_entry_size, 0,
 145                         cmd_buffer->state.current_l3_config);
 146 }
 147
 148 static void
 149 blorp_emit_3dstate_multisample(struct blorp_batch *batch, unsigned samples)
 150 {
 151    blorp_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms) {
 152       ms.NumberofMultisamples       = __builtin_ffs(samples) - 1;
 153
 154 #if GEN_GEN >= 8
 155       /* The PRM says that this bit is valid only for DX9:
 156        *
 157        *    SW can choose to set this bit only for DX9 API. DX10/OGL API's
 158        *    should not have any effect by setting or not setting this bit.
 159        */
 160       ms.PixelPositionOffsetEnable  = false;
 161       ms.PixelLocation              = CENTER;
 162 #else
 163       ms.PixelLocation              = PIXLOC_CENTER;
 164
 165       switch (samples) {
 166       case 1:
 167          SAMPLE_POS_1X(ms.Sample);
 168          break;
 169       case 2:
 170          SAMPLE_POS_2X(ms.Sample);
 171          break;
 172       case 4:
 173          SAMPLE_POS_4X(ms.Sample);
 174          break;
 175       case 8:
 176          SAMPLE_POS_8X(ms.Sample);
 177          break;
 178       default:
 179          break;
 180       }
 181 #endif
 182    }
 183 }
 184
 185 void genX(blorp_exec)(struct blorp_batch *batch,
 186                       const struct blorp_params *params);
 187
 188 void
 189 genX(blorp_exec)(struct blorp_batch *batch,
 190                  const struct blorp_params *params)
 191 {
 192    struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
 193
 194    if (!cmd_buffer->state.current_l3_config) {
 195       const struct gen_l3_config *cfg =
 196          gen_get_default_l3_config(&cmd_buffer->device->info);
 197       genX(cmd_buffer_config_l3)(cmd_buffer, cfg);
 198    }
 199
 200    genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
 201
 202    if (cmd_buffer->state.current_pipeline != _3D) {
 203 #if GEN_GEN <= 7
 204       /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
 205        * PIPELINE_SELECT [DevBWR+]":
 206        *
 207        *   Project: DEVSNB+
 208        *
 209        *   Software must ensure all the write caches are flushed through a
 210        *   stalling PIPE_CONTROL command followed by another PIPE_CONTROL
 211        *   command to invalidate read only caches prior to programming
 212        *   MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
 213        */
 214       blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
 215          pc.RenderTargetCacheFlushEnable  = true;
 216          pc.DepthCacheFlushEnable         = true;
 217          pc.DCFlushEnable                 = true;
 218          pc.PostSyncOperation             = NoWrite;
 219          pc.CommandStreamerStallEnable    = true;
 220       }
 221
 222       blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
 223          pc.TextureCacheInvalidationEnable   = true;
 224          pc.ConstantCacheInvalidationEnable  = true;
 225          pc.StateCacheInvalidationEnable     = true;
 226          pc.InstructionCacheInvalidateEnable = true;
 227          pc.PostSyncOperation                = NoWrite;
 228       }
 229 #endif
 230
 231       blorp_emit(batch, GENX(PIPELINE_SELECT), ps) {
 232 #if GEN_GEN >= 9
 233          ps.MaskBits = 3;
 234 #endif
 235          ps.PipelineSelection = _3D;
 236       }
 237
 238       cmd_buffer->state.current_pipeline = _3D;
 239    }
 240
 241    blorp_exec(batch, params);
 242
 243    /* BLORP sets DRAWING_RECTANGLE but we always want it set to the maximum.
 244     * Since we set it once at driver init and never again, we have to set it
 245     * back after invoking blorp.
 246     *
 247     * TODO: BLORP should assume a max drawing rectangle
 248     */
 249    blorp_emit(batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
 250       rect.ClippedDrawingRectangleYMin = 0;
 251       rect.ClippedDrawingRectangleXMin = 0;
 252       rect.ClippedDrawingRectangleYMax = UINT16_MAX;
 253       rect.ClippedDrawingRectangleXMax = UINT16_MAX;
 254       rect.DrawingRectangleOriginY = 0;
 255       rect.DrawingRectangleOriginX = 0;
 256    }
 257
 258    cmd_buffer->state.vb_dirty = ~0;
 259    cmd_buffer->state.dirty = ~0;
 260    cmd_buffer->state.push_constants_dirty = ~0;
 261 }