2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "anv_private.h"
28 /* These are defined in anv_private.h and blorp_genX_exec.h */
29 #undef __gen_address_type
30 #undef __gen_user_data
31 #undef __gen_combine_address
33 #include "common/gen_l3_config.h"
34 #include "common/gen_sample_positions.h"
35 #include "blorp/blorp_genX_exec.h"
38 blorp_emit_dwords(struct blorp_batch
*batch
, unsigned n
)
40 struct anv_cmd_buffer
*cmd_buffer
= batch
->driver_batch
;
41 return anv_batch_emit_dwords(&cmd_buffer
->batch
, n
);
45 blorp_emit_reloc(struct blorp_batch
*batch
,
46 void *location
, struct blorp_address address
, uint32_t delta
)
48 struct anv_cmd_buffer
*cmd_buffer
= batch
->driver_batch
;
49 assert(cmd_buffer
->batch
.start
<= location
&&
50 location
< cmd_buffer
->batch
.end
);
51 return anv_batch_emit_reloc(&cmd_buffer
->batch
, location
,
52 address
.buffer
, address
.offset
+ delta
);
56 blorp_surface_reloc(struct blorp_batch
*batch
, uint32_t ss_offset
,
57 struct blorp_address address
, uint32_t delta
)
59 struct anv_cmd_buffer
*cmd_buffer
= batch
->driver_batch
;
61 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
62 ss_offset
, address
.buffer
, address
.offset
+ delta
);
63 if (result
!= VK_SUCCESS
)
64 anv_batch_set_error(&cmd_buffer
->batch
, result
);
67 #if GEN_GEN >= 7 && GEN_GEN < 10
68 static struct blorp_address
69 blorp_get_surface_base_address(struct blorp_batch
*batch
)
71 struct anv_cmd_buffer
*cmd_buffer
= batch
->driver_batch
;
72 return (struct blorp_address
) {
73 .buffer
= &cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
80 blorp_alloc_dynamic_state(struct blorp_batch
*batch
,
85 struct anv_cmd_buffer
*cmd_buffer
= batch
->driver_batch
;
87 struct anv_state state
=
88 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, alignment
);
90 *offset
= state
.offset
;
95 blorp_alloc_binding_table(struct blorp_batch
*batch
, unsigned num_entries
,
96 unsigned state_size
, unsigned state_alignment
,
98 uint32_t *surface_offsets
, void **surface_maps
)
100 struct anv_cmd_buffer
*cmd_buffer
= batch
->driver_batch
;
102 uint32_t state_offset
;
103 struct anv_state bt_state
;
106 anv_cmd_buffer_alloc_blorp_binding_table(cmd_buffer
, num_entries
,
107 &state_offset
, &bt_state
);
108 if (result
!= VK_SUCCESS
)
111 uint32_t *bt_map
= bt_state
.map
;
112 *bt_offset
= bt_state
.offset
;
114 for (unsigned i
= 0; i
< num_entries
; i
++) {
115 struct anv_state surface_state
=
116 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
117 bt_map
[i
] = surface_state
.offset
+ state_offset
;
118 surface_offsets
[i
] = surface_state
.offset
;
119 surface_maps
[i
] = surface_state
.map
;
122 anv_state_flush(cmd_buffer
->device
, bt_state
);
126 blorp_alloc_vertex_buffer(struct blorp_batch
*batch
, uint32_t size
,
127 struct blorp_address
*addr
)
129 struct anv_cmd_buffer
*cmd_buffer
= batch
->driver_batch
;
131 /* From the Skylake PRM, 3DSTATE_VERTEX_BUFFERS:
133 * "The VF cache needs to be invalidated before binding and then using
134 * Vertex Buffers that overlap with any previously bound Vertex Buffer
135 * (at a 64B granularity) since the last invalidation. A VF cache
136 * invalidate is performed by setting the "VF Cache Invalidation Enable"
137 * bit in PIPE_CONTROL."
139 * This restriction first appears in the Skylake PRM but the internal docs
140 * also list it as being an issue on Broadwell. In order to avoid this
141 * problem, we align all vertex buffer allocations to 64 bytes.
143 struct anv_state vb_state
=
144 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 64);
146 *addr
= (struct blorp_address
) {
147 .buffer
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
148 .offset
= vb_state
.offset
,
149 .mocs
= cmd_buffer
->device
->default_mocs
,
156 static struct blorp_address
157 blorp_get_workaround_page(struct blorp_batch
*batch
)
159 struct anv_cmd_buffer
*cmd_buffer
= batch
->driver_batch
;
161 return (struct blorp_address
) {
162 .buffer
= &cmd_buffer
->device
->workaround_bo
,
168 blorp_flush_range(struct blorp_batch
*batch
, void *start
, size_t size
)
170 struct anv_device
*device
= batch
->blorp
->driver_ctx
;
171 if (!device
->info
.has_llc
)
172 gen_flush_range(start
, size
);
176 blorp_emit_urb_config(struct blorp_batch
*batch
,
177 unsigned vs_entry_size
, unsigned sf_entry_size
)
179 struct anv_device
*device
= batch
->blorp
->driver_ctx
;
180 struct anv_cmd_buffer
*cmd_buffer
= batch
->driver_batch
;
182 assert(sf_entry_size
== 0);
184 const unsigned entry_size
[4] = { vs_entry_size
, 1, 1, 1 };
186 genX(emit_urb_setup
)(device
, &cmd_buffer
->batch
,
187 cmd_buffer
->state
.current_l3_config
,
188 VK_SHADER_STAGE_VERTEX_BIT
|
189 VK_SHADER_STAGE_FRAGMENT_BIT
,
194 genX(blorp_exec
)(struct blorp_batch
*batch
,
195 const struct blorp_params
*params
)
197 struct anv_cmd_buffer
*cmd_buffer
= batch
->driver_batch
;
199 if (!cmd_buffer
->state
.current_l3_config
) {
200 const struct gen_l3_config
*cfg
=
201 gen_get_default_l3_config(&cmd_buffer
->device
->info
);
202 genX(cmd_buffer_config_l3
)(cmd_buffer
, cfg
);
206 /* The PIPE_CONTROL command description says:
208 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
209 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
210 * Target Cache Flush by enabling this bit. When render target flush
211 * is set due to new association of BTI, PS Scoreboard Stall bit must
212 * be set in this packet."
214 cmd_buffer
->state
.pending_pipe_bits
|=
215 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
|
216 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
220 /* The MI_LOAD/STORE_REGISTER_MEM commands which BLORP uses to implement
221 * indirect fast-clear colors can cause GPU hangs if we don't stall first.
222 * See genX(cmd_buffer_mi_memcpy) for more details.
224 if (params
->src
.clear_color_addr
.buffer
||
225 params
->dst
.clear_color_addr
.buffer
)
226 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
229 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
231 genX(flush_pipeline_select_3d
)(cmd_buffer
);
233 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
235 /* BLORP doesn't do anything fancy with depth such as discards, so we want
236 * the PMA fix off. Also, off is always the safe option.
238 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
240 /* Disable VF statistics */
241 blorp_emit(batch
, GENX(3DSTATE_VF_STATISTICS
), vf
) {
242 vf
.StatisticsEnable
= false;
245 blorp_exec(batch
, params
);
247 cmd_buffer
->state
.gfx
.vb_dirty
= ~0;
248 cmd_buffer
->state
.gfx
.dirty
= ~0;
249 cmd_buffer
->state
.push_constants_dirty
= ~0;