2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_aux_map.h"
33 #include "common/gen_l3_config.h"
34 #include "genxml/gen_macros.h"
35 #include "genxml/genX_pack.h"
37 /* We reserve GPR 14 and 15 for conditional rendering */
38 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
39 #define __gen_get_batch_dwords anv_batch_emit_dwords
40 #define __gen_address_offset anv_address_add
41 #include "common/gen_mi_builder.h"
43 static void genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
47 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
49 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
50 lri
.RegisterOffset
= reg
;
56 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
58 struct anv_device
*device
= cmd_buffer
->device
;
59 UNUSED
const struct gen_device_info
*devinfo
= &device
->info
;
60 uint32_t mocs
= device
->isl_dev
.mocs
.internal
;
62 /* If we are emitting a new state base address we probably need to re-emit
65 cmd_buffer
->state
.descriptors_dirty
|= ~0;
67 /* Emit a render target cache flush.
69 * This isn't documented anywhere in the PRM. However, it seems to be
70 * necessary prior to changing the surface state base adress. Without
71 * this, we get GPU hangs when using multi-level command buffers which
72 * clear depth, reset state base address, and then go render stuff.
74 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
75 pc
.DCFlushEnable
= true;
76 pc
.RenderTargetCacheFlushEnable
= true;
77 pc
.CommandStreamerStallEnable
= true;
79 pc
.TileCacheFlushEnable
= true;
82 /* GEN:BUG:1606662791:
84 * Software must program PIPE_CONTROL command with "HDC Pipeline
85 * Flush" prior to programming of the below two non-pipeline state :
86 * * STATE_BASE_ADDRESS
87 * * 3DSTATE_BINDING_TABLE_POOL_ALLOC
89 if (devinfo
->revision
== 0 /* A0 */)
90 pc
.HDCPipelineFlushEnable
= true;
95 /* GEN:BUG:1607854226:
97 * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
98 * mode by putting the pipeline temporarily in 3D mode.
100 uint32_t gen12_wa_pipeline
= cmd_buffer
->state
.current_pipeline
;
101 genX(flush_pipeline_select_3d
)(cmd_buffer
);
104 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
105 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
106 sba
.GeneralStateMOCS
= mocs
;
107 sba
.GeneralStateBaseAddressModifyEnable
= true;
109 sba
.StatelessDataPortAccessMOCS
= mocs
;
111 sba
.SurfaceStateBaseAddress
=
112 anv_cmd_buffer_surface_base_address(cmd_buffer
);
113 sba
.SurfaceStateMOCS
= mocs
;
114 sba
.SurfaceStateBaseAddressModifyEnable
= true;
116 sba
.DynamicStateBaseAddress
=
117 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
118 sba
.DynamicStateMOCS
= mocs
;
119 sba
.DynamicStateBaseAddressModifyEnable
= true;
121 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
122 sba
.IndirectObjectMOCS
= mocs
;
123 sba
.IndirectObjectBaseAddressModifyEnable
= true;
125 sba
.InstructionBaseAddress
=
126 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
127 sba
.InstructionMOCS
= mocs
;
128 sba
.InstructionBaseAddressModifyEnable
= true;
131 /* Broadwell requires that we specify a buffer size for a bunch of
132 * these fields. However, since we will be growing the BO's live, we
133 * just set them all to the maximum.
135 sba
.GeneralStateBufferSize
= 0xfffff;
136 sba
.IndirectObjectBufferSize
= 0xfffff;
137 if (device
->physical
->use_softpin
) {
138 /* With softpin, we use fixed addresses so we actually know how big
139 * our base addresses are.
141 sba
.DynamicStateBufferSize
= DYNAMIC_STATE_POOL_SIZE
/ 4096;
142 sba
.InstructionBufferSize
= INSTRUCTION_STATE_POOL_SIZE
/ 4096;
144 sba
.DynamicStateBufferSize
= 0xfffff;
145 sba
.InstructionBufferSize
= 0xfffff;
147 sba
.GeneralStateBufferSizeModifyEnable
= true;
148 sba
.IndirectObjectBufferSizeModifyEnable
= true;
149 sba
.DynamicStateBufferSizeModifyEnable
= true;
150 sba
.InstructionBuffersizeModifyEnable
= true;
152 /* On gen7, we have upper bounds instead. According to the docs,
153 * setting an upper bound of zero means that no bounds checking is
154 * performed so, in theory, we should be able to leave them zero.
155 * However, border color is broken and the GPU bounds-checks anyway.
156 * To avoid this and other potential problems, we may as well set it
159 sba
.GeneralStateAccessUpperBound
=
160 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
161 sba
.GeneralStateAccessUpperBoundModifyEnable
= true;
162 sba
.DynamicStateAccessUpperBound
=
163 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
164 sba
.DynamicStateAccessUpperBoundModifyEnable
= true;
165 sba
.InstructionAccessUpperBound
=
166 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
167 sba
.InstructionAccessUpperBoundModifyEnable
= true;
170 if (cmd_buffer
->device
->physical
->use_softpin
) {
171 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) {
172 .bo
= device
->surface_state_pool
.block_pool
.bo
,
175 sba
.BindlessSurfaceStateSize
= (1 << 20) - 1;
177 sba
.BindlessSurfaceStateBaseAddress
= ANV_NULL_ADDRESS
;
178 sba
.BindlessSurfaceStateSize
= 0;
180 sba
.BindlessSurfaceStateMOCS
= mocs
;
181 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
184 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
185 sba
.BindlessSamplerStateMOCS
= mocs
;
186 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
187 sba
.BindlessSamplerStateBufferSize
= 0;
192 /* GEN:BUG:1607854226:
194 * Put the pipeline back into its current mode.
196 if (gen12_wa_pipeline
!= UINT32_MAX
)
197 genX(flush_pipeline_select
)(cmd_buffer
, gen12_wa_pipeline
);
200 /* After re-setting the surface state base address, we have to do some
201 * cache flusing so that the sampler engine will pick up the new
202 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
203 * Shared Function > 3D Sampler > State > State Caching (page 96):
205 * Coherency with system memory in the state cache, like the texture
206 * cache is handled partially by software. It is expected that the
207 * command stream or shader will issue Cache Flush operation or
208 * Cache_Flush sampler message to ensure that the L1 cache remains
209 * coherent with system memory.
213 * Whenever the value of the Dynamic_State_Base_Addr,
214 * Surface_State_Base_Addr are altered, the L1 state cache must be
215 * invalidated to ensure the new surface or sampler state is fetched
216 * from system memory.
218 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
219 * which, according the PIPE_CONTROL instruction documentation in the
222 * Setting this bit is independent of any other bit in this packet.
223 * This bit controls the invalidation of the L1 and L2 state caches
224 * at the top of the pipe i.e. at the parsing time.
226 * Unfortunately, experimentation seems to indicate that state cache
227 * invalidation through a PIPE_CONTROL does nothing whatsoever in
228 * regards to surface state and binding tables. In stead, it seems that
229 * invalidating the texture cache is what is actually needed.
231 * XXX: As far as we have been able to determine through
232 * experimentation, shows that flush the texture cache appears to be
233 * sufficient. The theory here is that all of the sampling/rendering
234 * units cache the binding table in the texture cache. However, we have
235 * yet to be able to actually confirm this.
237 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
238 pc
.TextureCacheInvalidationEnable
= true;
239 pc
.ConstantCacheInvalidationEnable
= true;
240 pc
.StateCacheInvalidationEnable
= true;
245 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
246 struct anv_state state
, struct anv_address addr
)
248 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
251 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
252 state
.offset
+ isl_dev
->ss
.addr_offset
,
253 addr
.bo
, addr
.offset
, NULL
);
254 if (result
!= VK_SUCCESS
)
255 anv_batch_set_error(&cmd_buffer
->batch
, result
);
259 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
260 struct anv_surface_state state
)
262 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
264 assert(!anv_address_is_null(state
.address
));
265 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
267 if (!anv_address_is_null(state
.aux_address
)) {
269 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
270 &cmd_buffer
->pool
->alloc
,
271 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
272 state
.aux_address
.bo
,
273 state
.aux_address
.offset
,
275 if (result
!= VK_SUCCESS
)
276 anv_batch_set_error(&cmd_buffer
->batch
, result
);
279 if (!anv_address_is_null(state
.clear_address
)) {
281 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
282 &cmd_buffer
->pool
->alloc
,
284 isl_dev
->ss
.clear_color_state_offset
,
285 state
.clear_address
.bo
,
286 state
.clear_address
.offset
,
288 if (result
!= VK_SUCCESS
)
289 anv_batch_set_error(&cmd_buffer
->batch
, result
);
294 color_attachment_compute_aux_usage(struct anv_device
* device
,
295 struct anv_cmd_state
* cmd_state
,
296 uint32_t att
, VkRect2D render_area
,
297 union isl_color_value
*fast_clear_color
)
299 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
300 struct anv_image_view
*iview
= cmd_state
->attachments
[att
].image_view
;
302 assert(iview
->n_planes
== 1);
304 if (iview
->planes
[0].isl
.base_array_layer
>=
305 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
306 iview
->planes
[0].isl
.base_level
)) {
307 /* There is no aux buffer which corresponds to the level and layer(s)
310 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
311 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
312 att_state
->fast_clear
= false;
316 att_state
->aux_usage
=
317 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
318 VK_IMAGE_ASPECT_COLOR_BIT
,
319 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
,
320 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
322 /* If we don't have aux, then we should have returned early in the layer
323 * check above. If we got here, we must have something.
325 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
327 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
328 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
329 att_state
->input_aux_usage
= att_state
->aux_usage
;
331 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
333 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
334 * setting is only allowed if Surface Format supported for Fast
335 * Clear. In addition, if the surface is bound to the sampling
336 * engine, Surface Format must be supported for Render Target
337 * Compression for surfaces bound to the sampling engine."
339 * In other words, we can only sample from a fast-cleared image if it
340 * also supports color compression.
342 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
) &&
343 isl_format_supports_ccs_d(&device
->info
, iview
->planes
[0].isl
.format
)) {
344 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
346 /* While fast-clear resolves and partial resolves are fairly cheap in the
347 * case where you render to most of the pixels, full resolves are not
348 * because they potentially involve reading and writing the entire
349 * framebuffer. If we can't texture with CCS_E, we should leave it off and
350 * limit ourselves to fast clears.
352 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
353 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
354 anv_perf_warn(device
, iview
->image
,
355 "Not temporarily enabling CCS_E.");
358 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
362 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
363 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
365 union isl_color_value clear_color
= {};
366 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
368 att_state
->clear_color_is_zero_one
=
369 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
370 att_state
->clear_color_is_zero
=
371 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
373 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
374 /* Start by getting the fast clear type. We use the first subpass
375 * layout here because we don't want to fast-clear if the first subpass
376 * to use the attachment can't handle fast-clears.
378 enum anv_fast_clear_type fast_clear_type
=
379 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
380 VK_IMAGE_ASPECT_COLOR_BIT
,
381 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
382 switch (fast_clear_type
) {
383 case ANV_FAST_CLEAR_NONE
:
384 att_state
->fast_clear
= false;
386 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
387 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
389 case ANV_FAST_CLEAR_ANY
:
390 att_state
->fast_clear
= true;
394 /* Potentially, we could do partial fast-clears but doing so has crazy
395 * alignment restrictions. It's easier to just restrict to full size
396 * fast clears for now.
398 if (render_area
.offset
.x
!= 0 ||
399 render_area
.offset
.y
!= 0 ||
400 render_area
.extent
.width
!= iview
->extent
.width
||
401 render_area
.extent
.height
!= iview
->extent
.height
)
402 att_state
->fast_clear
= false;
404 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
405 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
406 att_state
->fast_clear
= false;
408 /* We only allow fast clears to the first slice of an image (level 0,
409 * layer 0) and only for the entire slice. This guarantees us that, at
410 * any given time, there is only one clear color on any given image at
411 * any given time. At the time of our testing (Jan 17, 2018), there
412 * were no known applications which would benefit from fast-clearing
413 * more than just the first slice.
415 if (att_state
->fast_clear
&&
416 (iview
->planes
[0].isl
.base_level
> 0 ||
417 iview
->planes
[0].isl
.base_array_layer
> 0)) {
418 anv_perf_warn(device
, iview
->image
,
419 "Rendering with multi-lod or multi-layer framebuffer "
420 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
421 "baseArrayLayer > 0. Not fast clearing.");
422 att_state
->fast_clear
= false;
423 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
424 anv_perf_warn(device
, iview
->image
,
425 "Rendering to a multi-layer framebuffer with "
426 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
429 if (att_state
->fast_clear
)
430 *fast_clear_color
= clear_color
;
432 att_state
->fast_clear
= false;
437 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
438 struct anv_cmd_state
*cmd_state
,
439 uint32_t att
, VkRect2D render_area
)
441 struct anv_render_pass_attachment
*pass_att
=
442 &cmd_state
->pass
->attachments
[att
];
443 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
444 struct anv_image_view
*iview
= cmd_state
->attachments
[att
].image_view
;
446 /* These will be initialized after the first subpass transition. */
447 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
448 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
450 /* This is unused for depth/stencil but valgrind complains if it
453 att_state
->clear_color_is_zero_one
= false;
456 /* We don't do any HiZ or depth fast-clears on gen7 yet */
457 att_state
->fast_clear
= false;
461 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
462 /* If we're just clearing stencil, we can always HiZ clear */
463 att_state
->fast_clear
= true;
467 /* Default to false for now */
468 att_state
->fast_clear
= false;
470 /* We must have depth in order to have HiZ */
471 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
474 const enum isl_aux_usage first_subpass_aux_usage
=
475 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
476 VK_IMAGE_ASPECT_DEPTH_BIT
,
477 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
478 pass_att
->first_subpass_layout
);
479 if (!blorp_can_hiz_clear_depth(&device
->info
,
480 &iview
->image
->planes
[0].surface
.isl
,
481 first_subpass_aux_usage
,
482 iview
->planes
[0].isl
.base_level
,
483 iview
->planes
[0].isl
.base_array_layer
,
484 render_area
.offset
.x
,
485 render_area
.offset
.y
,
486 render_area
.offset
.x
+
487 render_area
.extent
.width
,
488 render_area
.offset
.y
+
489 render_area
.extent
.height
))
492 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
495 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
496 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
497 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
498 * only supports returning 0.0f. Gens prior to gen8 do not support this
504 /* If we got here, then we can fast clear */
505 att_state
->fast_clear
= true;
509 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
511 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
514 /* We only allocate input attachment states for color surfaces. Compression
515 * is not yet enabled for depth textures and stencil doesn't allow
516 * compression so we can just use the texture surface state from the view.
518 return vk_format_is_color(att
->format
);
521 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
522 * the initial layout is undefined, the HiZ buffer and depth buffer will
523 * represent the same data at the end of this operation.
526 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
527 const struct anv_image
*image
,
528 VkImageLayout initial_layout
,
529 VkImageLayout final_layout
)
531 uint32_t depth_plane
=
532 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
533 if (image
->planes
[depth_plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
536 const enum isl_aux_state initial_state
=
537 anv_layout_to_aux_state(&cmd_buffer
->device
->info
, image
,
538 VK_IMAGE_ASPECT_DEPTH_BIT
,
540 const enum isl_aux_state final_state
=
541 anv_layout_to_aux_state(&cmd_buffer
->device
->info
, image
,
542 VK_IMAGE_ASPECT_DEPTH_BIT
,
545 const bool initial_depth_valid
=
546 isl_aux_state_has_valid_primary(initial_state
);
547 const bool initial_hiz_valid
=
548 isl_aux_state_has_valid_aux(initial_state
);
549 const bool final_needs_depth
=
550 isl_aux_state_has_valid_primary(final_state
);
551 const bool final_needs_hiz
=
552 isl_aux_state_has_valid_aux(final_state
);
554 /* Getting into the pass-through state for Depth is tricky and involves
555 * both a resolve and an ambiguate. We don't handle that state right now
556 * as anv_layout_to_aux_state never returns it.
558 assert(final_state
!= ISL_AUX_STATE_PASS_THROUGH
);
560 if (final_needs_depth
&& !initial_depth_valid
) {
561 assert(initial_hiz_valid
);
562 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
563 0, 0, 1, ISL_AUX_OP_FULL_RESOLVE
);
564 } else if (final_needs_hiz
&& !initial_hiz_valid
) {
565 assert(initial_depth_valid
);
566 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
567 0, 0, 1, ISL_AUX_OP_AMBIGUATE
);
572 vk_image_layout_stencil_write_optimal(VkImageLayout layout
)
574 return layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
575 layout
== VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
||
576 layout
== VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
;
579 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
580 * the initial layout is undefined, the HiZ buffer and depth buffer will
581 * represent the same data at the end of this operation.
584 transition_stencil_buffer(struct anv_cmd_buffer
*cmd_buffer
,
585 const struct anv_image
*image
,
586 uint32_t base_level
, uint32_t level_count
,
587 uint32_t base_layer
, uint32_t layer_count
,
588 VkImageLayout initial_layout
,
589 VkImageLayout final_layout
)
592 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
593 VK_IMAGE_ASPECT_STENCIL_BIT
);
595 /* On gen7, we have to store a texturable version of the stencil buffer in
596 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
597 * forth at strategic points. Stencil writes are only allowed in following
600 * - VK_IMAGE_LAYOUT_GENERAL
601 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
602 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
603 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
604 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
606 * For general, we have no nice opportunity to transition so we do the copy
607 * to the shadow unconditionally at the end of the subpass. For transfer
608 * destinations, we can update it as part of the transfer op. For the other
609 * layouts, we delay the copy until a transition into some other layout.
611 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
612 vk_image_layout_stencil_write_optimal(initial_layout
) &&
613 !vk_image_layout_stencil_write_optimal(final_layout
)) {
614 anv_image_copy_to_shadow(cmd_buffer
, image
,
615 VK_IMAGE_ASPECT_STENCIL_BIT
,
616 base_level
, level_count
,
617 base_layer
, layer_count
);
619 #endif /* GEN_GEN == 7 */
622 #define MI_PREDICATE_SRC0 0x2400
623 #define MI_PREDICATE_SRC1 0x2408
624 #define MI_PREDICATE_RESULT 0x2418
627 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
628 const struct anv_image
*image
,
629 VkImageAspectFlagBits aspect
,
631 uint32_t base_layer
, uint32_t layer_count
,
634 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
636 /* We only have compression tracking for CCS_E */
637 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
640 for (uint32_t a
= 0; a
< layer_count
; a
++) {
641 uint32_t layer
= base_layer
+ a
;
642 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
643 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
646 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
652 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
653 const struct anv_image
*image
,
654 VkImageAspectFlagBits aspect
,
655 enum anv_fast_clear_type fast_clear
)
657 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
658 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
660 sdi
.ImmediateData
= fast_clear
;
663 /* Whenever we have fast-clear, we consider that slice to be compressed.
664 * This makes building predicates much easier.
666 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
667 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
670 /* This is only really practical on haswell and above because it requires
671 * MI math in order to get it correct.
673 #if GEN_GEN >= 8 || GEN_IS_HASWELL
675 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
676 const struct anv_image
*image
,
677 VkImageAspectFlagBits aspect
,
678 uint32_t level
, uint32_t array_layer
,
679 enum isl_aux_op resolve_op
,
680 enum anv_fast_clear_type fast_clear_supported
)
682 struct gen_mi_builder b
;
683 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
685 const struct gen_mi_value fast_clear_type
=
686 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
689 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
690 /* In this case, we're doing a full resolve which means we want the
691 * resolve to happen if any compression (including fast-clears) is
694 * In order to simplify the logic a bit, we make the assumption that,
695 * if the first slice has been fast-cleared, it is also marked as
696 * compressed. See also set_image_fast_clear_state.
698 const struct gen_mi_value compression_state
=
699 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer
->device
,
701 level
, array_layer
));
702 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
704 gen_mi_store(&b
, compression_state
, gen_mi_imm(0));
706 if (level
== 0 && array_layer
== 0) {
707 /* If the predicate is true, we want to write 0 to the fast clear type
708 * and, if it's false, leave it alone. We can do this by writing
710 * clear_type = clear_type & ~predicate;
712 struct gen_mi_value new_fast_clear_type
=
713 gen_mi_iand(&b
, fast_clear_type
,
714 gen_mi_inot(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
)));
715 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
717 } else if (level
== 0 && array_layer
== 0) {
718 /* In this case, we are doing a partial resolve to get rid of fast-clear
719 * colors. We don't care about the compression state but we do care
720 * about how much fast clear is allowed by the final layout.
722 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
723 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
725 /* We need to compute (fast_clear_supported < image->fast_clear) */
726 struct gen_mi_value pred
=
727 gen_mi_ult(&b
, gen_mi_imm(fast_clear_supported
), fast_clear_type
);
728 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
729 gen_mi_value_ref(&b
, pred
));
731 /* If the predicate is true, we want to write 0 to the fast clear type
732 * and, if it's false, leave it alone. We can do this by writing
734 * clear_type = clear_type & ~predicate;
736 struct gen_mi_value new_fast_clear_type
=
737 gen_mi_iand(&b
, fast_clear_type
, gen_mi_inot(&b
, pred
));
738 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
740 /* In this case, we're trying to do a partial resolve on a slice that
741 * doesn't have clear color. There's nothing to do.
743 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
747 /* Set src1 to 0 and use a != condition */
748 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
750 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
751 mip
.LoadOperation
= LOAD_LOADINV
;
752 mip
.CombineOperation
= COMBINE_SET
;
753 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
756 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
760 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
761 const struct anv_image
*image
,
762 VkImageAspectFlagBits aspect
,
763 uint32_t level
, uint32_t array_layer
,
764 enum isl_aux_op resolve_op
,
765 enum anv_fast_clear_type fast_clear_supported
)
767 struct gen_mi_builder b
;
768 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
770 struct gen_mi_value fast_clear_type_mem
=
771 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
774 /* This only works for partial resolves and only when the clear color is
775 * all or nothing. On the upside, this emits less command streamer code
776 * and works on Ivybridge and Bay Trail.
778 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
779 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
781 /* We don't support fast clears on anything other than the first slice. */
782 if (level
> 0 || array_layer
> 0)
785 /* On gen8, we don't have a concept of default clear colors because we
786 * can't sample from CCS surfaces. It's enough to just load the fast clear
787 * state into the predicate register.
789 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), fast_clear_type_mem
);
790 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
791 gen_mi_store(&b
, fast_clear_type_mem
, gen_mi_imm(0));
793 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
794 mip
.LoadOperation
= LOAD_LOADINV
;
795 mip
.CombineOperation
= COMBINE_SET
;
796 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
799 #endif /* GEN_GEN <= 8 */
802 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
803 const struct anv_image
*image
,
804 enum isl_format format
,
805 VkImageAspectFlagBits aspect
,
806 uint32_t level
, uint32_t array_layer
,
807 enum isl_aux_op resolve_op
,
808 enum anv_fast_clear_type fast_clear_supported
)
810 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
813 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
814 aspect
, level
, array_layer
,
815 resolve_op
, fast_clear_supported
);
816 #else /* GEN_GEN <= 8 */
817 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
818 aspect
, level
, array_layer
,
819 resolve_op
, fast_clear_supported
);
822 /* CCS_D only supports full resolves and BLORP will assert on us if we try
823 * to do a partial resolve on a CCS_D surface.
825 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
826 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_D
)
827 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
829 anv_image_ccs_op(cmd_buffer
, image
, format
, aspect
, level
,
830 array_layer
, 1, resolve_op
, NULL
, true);
834 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
835 const struct anv_image
*image
,
836 enum isl_format format
,
837 VkImageAspectFlagBits aspect
,
838 uint32_t array_layer
,
839 enum isl_aux_op resolve_op
,
840 enum anv_fast_clear_type fast_clear_supported
)
842 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
843 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
845 #if GEN_GEN >= 8 || GEN_IS_HASWELL
846 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
847 aspect
, 0, array_layer
,
848 resolve_op
, fast_clear_supported
);
850 anv_image_mcs_op(cmd_buffer
, image
, format
, aspect
,
851 array_layer
, 1, resolve_op
, NULL
, true);
853 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
858 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
859 const struct anv_image
*image
,
860 VkImageAspectFlagBits aspect
,
861 enum isl_aux_usage aux_usage
,
864 uint32_t layer_count
)
866 /* The aspect must be exactly one of the image aspects. */
867 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
869 /* The only compression types with more than just fast-clears are MCS,
870 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
871 * track the current fast-clear and compression state. This leaves us
872 * with just MCS and CCS_E.
874 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
875 aux_usage
!= ISL_AUX_USAGE_MCS
)
878 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
879 level
, base_layer
, layer_count
, true);
883 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
884 const struct anv_image
*image
,
885 VkImageAspectFlagBits aspect
)
887 assert(cmd_buffer
&& image
);
888 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
890 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
891 ANV_FAST_CLEAR_NONE
);
893 /* Initialize the struct fields that are accessed for fast-clears so that
894 * the HW restrictions on the field values are satisfied.
896 struct anv_address addr
=
897 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
900 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
901 const unsigned num_dwords
= GEN_GEN
>= 10 ?
902 isl_dev
->ss
.clear_color_state_size
/ 4 :
903 isl_dev
->ss
.clear_value_size
/ 4;
904 for (unsigned i
= 0; i
< num_dwords
; i
++) {
905 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
907 sdi
.Address
.offset
+= i
* 4;
908 sdi
.ImmediateData
= 0;
912 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
914 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
915 /* Pre-SKL, the dword containing the clear values also contains
916 * other fields, so we need to initialize those fields to match the
917 * values that would be in a color attachment.
919 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
920 ISL_CHANNEL_SELECT_GREEN
<< 22 |
921 ISL_CHANNEL_SELECT_BLUE
<< 19 |
922 ISL_CHANNEL_SELECT_ALPHA
<< 16;
923 } else if (GEN_GEN
== 7) {
924 /* On IVB, the dword containing the clear values also contains
925 * other fields that must be zero or can be zero.
927 sdi
.ImmediateData
= 0;
933 /* Copy the fast-clear value dword(s) between a surface state object and an
934 * image's fast clear state buffer.
937 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
938 struct anv_state surface_state
,
939 const struct anv_image
*image
,
940 VkImageAspectFlagBits aspect
,
941 bool copy_from_surface_state
)
943 assert(cmd_buffer
&& image
);
944 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
946 struct anv_address ss_clear_addr
= {
947 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
948 .offset
= surface_state
.offset
+
949 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
951 const struct anv_address entry_addr
=
952 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
953 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
956 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
957 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
958 * in-flight when they are issued even if the memory touched is not
959 * currently active for rendering. The weird bit is that it is not the
960 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
961 * rendering hangs such that the next stalling command after the
962 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
964 * It is unclear exactly why this hang occurs. Both MI commands come with
965 * warnings about the 3D pipeline but that doesn't seem to fully explain
966 * it. My (Jason's) best theory is that it has something to do with the
967 * fact that we're using a GPU state register as our temporary and that
968 * something with reading/writing it is causing problems.
970 * In order to work around this issue, we emit a PIPE_CONTROL with the
971 * command streamer stall bit set.
973 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
974 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
977 struct gen_mi_builder b
;
978 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
980 if (copy_from_surface_state
) {
981 gen_mi_memcpy(&b
, entry_addr
, ss_clear_addr
, copy_size
);
983 gen_mi_memcpy(&b
, ss_clear_addr
, entry_addr
, copy_size
);
985 /* Updating a surface state object may require that the state cache be
986 * invalidated. From the SKL PRM, Shared Functions -> State -> State
989 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
990 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
991 * modified [...], the L1 state cache must be invalidated to ensure
992 * the new surface or sampler state is fetched from system memory.
994 * In testing, SKL doesn't actually seem to need this, but HSW does.
996 cmd_buffer
->state
.pending_pipe_bits
|=
997 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1001 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
1005 anv_image_init_aux_tt(struct anv_cmd_buffer
*cmd_buffer
,
1006 const struct anv_image
*image
,
1007 VkImageAspectFlagBits aspect
,
1008 uint32_t base_level
, uint32_t level_count
,
1009 uint32_t base_layer
, uint32_t layer_count
)
1011 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
1013 uint64_t base_address
=
1014 anv_address_physical(image
->planes
[plane
].address
);
1016 const struct isl_surf
*isl_surf
= &image
->planes
[plane
].surface
.isl
;
1017 uint64_t format_bits
= gen_aux_map_format_bits_for_isl_surf(isl_surf
);
1019 /* We're about to live-update the AUX-TT. We really don't want anyone else
1020 * trying to read it while we're doing this. We could probably get away
1021 * with not having this stall in some cases if we were really careful but
1022 * it's better to play it safe. Full stall the GPU.
1024 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
1025 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1027 struct gen_mi_builder b
;
1028 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
1030 for (uint32_t a
= 0; a
< layer_count
; a
++) {
1031 const uint32_t layer
= base_layer
+ a
;
1033 uint64_t start_offset_B
= UINT64_MAX
, end_offset_B
= 0;
1034 for (uint32_t l
= 0; l
< level_count
; l
++) {
1035 const uint32_t level
= base_level
+ l
;
1037 uint32_t logical_array_layer
, logical_z_offset_px
;
1038 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1039 logical_array_layer
= 0;
1041 /* If the given miplevel does not have this layer, then any higher
1042 * miplevels won't either because miplevels only get smaller the
1045 assert(layer
< image
->extent
.depth
);
1046 if (layer
>= anv_minify(image
->extent
.depth
, level
))
1048 logical_z_offset_px
= layer
;
1050 assert(layer
< image
->array_size
);
1051 logical_array_layer
= layer
;
1052 logical_z_offset_px
= 0;
1055 uint32_t slice_start_offset_B
, slice_end_offset_B
;
1056 isl_surf_get_image_range_B_tile(isl_surf
, level
,
1057 logical_array_layer
,
1058 logical_z_offset_px
,
1059 &slice_start_offset_B
,
1060 &slice_end_offset_B
);
1062 start_offset_B
= MIN2(start_offset_B
, slice_start_offset_B
);
1063 end_offset_B
= MAX2(end_offset_B
, slice_end_offset_B
);
1066 /* Aux operates 64K at a time */
1067 start_offset_B
= align_down_u64(start_offset_B
, 64 * 1024);
1068 end_offset_B
= align_u64(end_offset_B
, 64 * 1024);
1070 for (uint64_t offset
= start_offset_B
;
1071 offset
< end_offset_B
; offset
+= 64 * 1024) {
1072 uint64_t address
= base_address
+ offset
;
1074 uint64_t aux_entry_addr64
, *aux_entry_map
;
1075 aux_entry_map
= gen_aux_map_get_entry(cmd_buffer
->device
->aux_map_ctx
,
1076 address
, &aux_entry_addr64
);
1078 assert(cmd_buffer
->device
->physical
->use_softpin
);
1079 struct anv_address aux_entry_address
= {
1081 .offset
= aux_entry_addr64
,
1084 const uint64_t old_aux_entry
= READ_ONCE(*aux_entry_map
);
1085 uint64_t new_aux_entry
=
1086 (old_aux_entry
& GEN_AUX_MAP_ADDRESS_MASK
) | format_bits
;
1088 if (isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
))
1089 new_aux_entry
|= GEN_AUX_MAP_ENTRY_VALID_BIT
;
1091 gen_mi_store(&b
, gen_mi_mem64(aux_entry_address
),
1092 gen_mi_imm(new_aux_entry
));
1096 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
;
1098 #endif /* GEN_GEN == 12 */
1101 * @brief Transitions a color buffer from one layout to another.
1103 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
1106 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
1107 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
1108 * this represents the maximum layers to transition at each
1109 * specified miplevel.
1112 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
1113 const struct anv_image
*image
,
1114 VkImageAspectFlagBits aspect
,
1115 const uint32_t base_level
, uint32_t level_count
,
1116 uint32_t base_layer
, uint32_t layer_count
,
1117 VkImageLayout initial_layout
,
1118 VkImageLayout final_layout
)
1120 struct anv_device
*device
= cmd_buffer
->device
;
1121 const struct gen_device_info
*devinfo
= &device
->info
;
1122 /* Validate the inputs. */
1124 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
1125 /* These values aren't supported for simplicity's sake. */
1126 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
1127 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
1128 /* Ensure the subresource range is valid. */
1129 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
1130 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
1131 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
1132 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
1133 assert(last_level_num
<= image
->levels
);
1134 /* The spec disallows these final layouts. */
1135 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
1136 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
1138 /* No work is necessary if the layout stays the same or if this subresource
1139 * range lacks auxiliary data.
1141 if (initial_layout
== final_layout
)
1144 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
1146 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
1147 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
1148 /* This surface is a linear compressed image with a tiled shadow surface
1149 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
1150 * we need to ensure the shadow copy is up-to-date.
1152 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1153 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
1154 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
1155 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
1157 anv_image_copy_to_shadow(cmd_buffer
, image
,
1158 VK_IMAGE_ASPECT_COLOR_BIT
,
1159 base_level
, level_count
,
1160 base_layer
, layer_count
);
1163 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
1166 assert(image
->planes
[plane
].surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
1168 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
1169 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
1171 if (device
->physical
->has_implicit_ccs
&& devinfo
->has_aux_map
) {
1172 anv_image_init_aux_tt(cmd_buffer
, image
, aspect
,
1173 base_level
, level_count
,
1174 base_layer
, layer_count
);
1177 assert(!(device
->physical
->has_implicit_ccs
&& devinfo
->has_aux_map
));
1180 /* A subresource in the undefined layout may have been aliased and
1181 * populated with any arrangement of bits. Therefore, we must initialize
1182 * the related aux buffer and clear buffer entry with desirable values.
1183 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
1184 * images with VK_IMAGE_TILING_OPTIMAL.
1186 * Initialize the relevant clear buffer entries.
1188 if (base_level
== 0 && base_layer
== 0)
1189 init_fast_clear_color(cmd_buffer
, image
, aspect
);
1191 /* Initialize the aux buffers to enable correct rendering. In order to
1192 * ensure that things such as storage images work correctly, aux buffers
1193 * need to be initialized to valid data.
1195 * Having an aux buffer with invalid data is a problem for two reasons:
1197 * 1) Having an invalid value in the buffer can confuse the hardware.
1198 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1199 * invalid and leads to the hardware doing strange things. It
1200 * doesn't hang as far as we can tell but rendering corruption can
1203 * 2) If this transition is into the GENERAL layout and we then use the
1204 * image as a storage image, then we must have the aux buffer in the
1205 * pass-through state so that, if we then go to texture from the
1206 * image, we get the results of our storage image writes and not the
1207 * fast clear color or other random data.
1209 * For CCS both of the problems above are real demonstrable issues. In
1210 * that case, the only thing we can do is to perform an ambiguate to
1211 * transition the aux surface into the pass-through state.
1213 * For MCS, (2) is never an issue because we don't support multisampled
1214 * storage images. In theory, issue (1) is a problem with MCS but we've
1215 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1216 * theory, be interpreted as something but we don't know that all bit
1217 * patterns are actually valid. For 2x and 8x, you could easily end up
1218 * with the MCS referring to an invalid plane because not all bits of
1219 * the MCS value are actually used. Even though we've never seen issues
1220 * in the wild, it's best to play it safe and initialize the MCS. We
1221 * can use a fast-clear for MCS because we only ever touch from render
1222 * and texture (no image load store).
1224 if (image
->samples
== 1) {
1225 for (uint32_t l
= 0; l
< level_count
; l
++) {
1226 const uint32_t level
= base_level
+ l
;
1228 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1229 if (base_layer
>= aux_layers
)
1230 break; /* We will only get fewer layers as level increases */
1231 uint32_t level_layer_count
=
1232 MIN2(layer_count
, aux_layers
- base_layer
);
1234 anv_image_ccs_op(cmd_buffer
, image
,
1235 image
->planes
[plane
].surface
.isl
.format
,
1236 aspect
, level
, base_layer
, level_layer_count
,
1237 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1239 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1240 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1241 level
, base_layer
, level_layer_count
,
1246 if (image
->samples
== 4 || image
->samples
== 16) {
1247 anv_perf_warn(cmd_buffer
->device
, image
,
1248 "Doing a potentially unnecessary fast-clear to "
1249 "define an MCS buffer.");
1252 assert(base_level
== 0 && level_count
== 1);
1253 anv_image_mcs_op(cmd_buffer
, image
,
1254 image
->planes
[plane
].surface
.isl
.format
,
1255 aspect
, base_layer
, layer_count
,
1256 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1261 const enum isl_aux_usage initial_aux_usage
=
1262 anv_layout_to_aux_usage(devinfo
, image
, aspect
, 0, initial_layout
);
1263 const enum isl_aux_usage final_aux_usage
=
1264 anv_layout_to_aux_usage(devinfo
, image
, aspect
, 0, final_layout
);
1266 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1267 * We can handle transitions between CCS_D/E to and from NONE. What we
1268 * don't yet handle is switching between CCS_E and CCS_D within a given
1269 * image. Doing so in a performant way requires more detailed aux state
1270 * tracking such as what is done in i965. For now, just assume that we
1271 * only have one type of compression.
1273 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1274 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1275 initial_aux_usage
== final_aux_usage
);
1277 /* If initial aux usage is NONE, there is nothing to resolve */
1278 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1281 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1283 /* If the initial layout supports more fast clear than the final layout
1284 * then we need at least a partial resolve.
1286 const enum anv_fast_clear_type initial_fast_clear
=
1287 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1288 const enum anv_fast_clear_type final_fast_clear
=
1289 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1290 if (final_fast_clear
< initial_fast_clear
)
1291 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1293 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1294 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1295 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1297 if (resolve_op
== ISL_AUX_OP_NONE
)
1300 /* Perform a resolve to synchronize data between the main and aux buffer.
1301 * Before we begin, we must satisfy the cache flushing requirement specified
1302 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1304 * Any transition from any value in {Clear, Render, Resolve} to a
1305 * different value in {Clear, Render, Resolve} requires end of pipe
1308 * We perform a flush of the write cache before and after the clear and
1309 * resolve operations to meet this requirement.
1311 * Unlike other drawing, fast clear operations are not properly
1312 * synchronized. The first PIPE_CONTROL here likely ensures that the
1313 * contents of the previous render or clear hit the render target before we
1314 * resolve and the second likely ensures that the resolve is complete before
1315 * we do any more rendering or clearing.
1317 cmd_buffer
->state
.pending_pipe_bits
|=
1318 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
1320 for (uint32_t l
= 0; l
< level_count
; l
++) {
1321 uint32_t level
= base_level
+ l
;
1323 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1324 if (base_layer
>= aux_layers
)
1325 break; /* We will only get fewer layers as level increases */
1326 uint32_t level_layer_count
=
1327 MIN2(layer_count
, aux_layers
- base_layer
);
1329 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1330 uint32_t array_layer
= base_layer
+ a
;
1331 if (image
->samples
== 1) {
1332 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1333 image
->planes
[plane
].surface
.isl
.format
,
1334 aspect
, level
, array_layer
, resolve_op
,
1337 /* We only support fast-clear on the first layer so partial
1338 * resolves should not be used on other layers as they will use
1339 * the clear color stored in memory that is only valid for layer0.
1341 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1345 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1346 image
->planes
[plane
].surface
.isl
.format
,
1347 aspect
, array_layer
, resolve_op
,
1353 cmd_buffer
->state
.pending_pipe_bits
|=
1354 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
1358 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1361 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1362 struct anv_render_pass
*pass
,
1363 const VkRenderPassBeginInfo
*begin
)
1365 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1366 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1367 struct anv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1369 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1371 if (pass
->attachment_count
> 0) {
1372 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1373 pass
->attachment_count
*
1374 sizeof(state
->attachments
[0]),
1375 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1376 if (state
->attachments
== NULL
) {
1377 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1378 return anv_batch_set_error(&cmd_buffer
->batch
,
1379 VK_ERROR_OUT_OF_HOST_MEMORY
);
1382 state
->attachments
= NULL
;
1385 /* Reserve one for the NULL state. */
1386 unsigned num_states
= 1;
1387 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1388 if (vk_format_is_color(pass
->attachments
[i
].format
))
1391 if (need_input_attachment_state(&pass
->attachments
[i
]))
1395 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1396 state
->render_pass_states
=
1397 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1398 num_states
* ss_stride
, isl_dev
->ss
.align
);
1400 struct anv_state next_state
= state
->render_pass_states
;
1401 next_state
.alloc_size
= isl_dev
->ss
.size
;
1403 state
->null_surface_state
= next_state
;
1404 next_state
.offset
+= ss_stride
;
1405 next_state
.map
+= ss_stride
;
1407 const VkRenderPassAttachmentBeginInfoKHR
*begin_attachment
=
1408 vk_find_struct_const(begin
, RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR
);
1410 if (begin
&& !begin_attachment
)
1411 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1413 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1414 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1415 state
->attachments
[i
].color
.state
= next_state
;
1416 next_state
.offset
+= ss_stride
;
1417 next_state
.map
+= ss_stride
;
1420 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1421 state
->attachments
[i
].input
.state
= next_state
;
1422 next_state
.offset
+= ss_stride
;
1423 next_state
.map
+= ss_stride
;
1426 if (begin_attachment
&& begin_attachment
->attachmentCount
!= 0) {
1427 assert(begin_attachment
->attachmentCount
== pass
->attachment_count
);
1428 ANV_FROM_HANDLE(anv_image_view
, iview
, begin_attachment
->pAttachments
[i
]);
1429 cmd_buffer
->state
.attachments
[i
].image_view
= iview
;
1430 } else if (framebuffer
&& i
< framebuffer
->attachment_count
) {
1431 cmd_buffer
->state
.attachments
[i
].image_view
= framebuffer
->attachments
[i
];
1434 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1435 state
->render_pass_states
.alloc_size
);
1438 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1439 isl_extent3d(framebuffer
->width
,
1440 framebuffer
->height
,
1441 framebuffer
->layers
));
1443 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1444 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1445 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1446 VkImageAspectFlags clear_aspects
= 0;
1447 VkImageAspectFlags load_aspects
= 0;
1449 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1450 /* color attachment */
1451 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1452 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1453 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1454 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1457 /* depthstencil attachment */
1458 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1459 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1460 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1461 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1462 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1465 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1466 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1467 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1468 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1469 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1474 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1475 state
->attachments
[i
].current_stencil_layout
= att
->stencil_initial_layout
;
1476 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1477 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1479 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1481 struct anv_image_view
*iview
= cmd_buffer
->state
.attachments
[i
].image_view
;
1482 anv_assert(iview
->vk_format
== att
->format
);
1484 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1485 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1487 union isl_color_value clear_color
= { .u32
= { 0, } };
1488 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1489 anv_assert(iview
->n_planes
== 1);
1490 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1491 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1492 state
, i
, begin
->renderArea
,
1495 anv_image_fill_surface_state(cmd_buffer
->device
,
1497 VK_IMAGE_ASPECT_COLOR_BIT
,
1498 &iview
->planes
[0].isl
,
1499 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1500 state
->attachments
[i
].aux_usage
,
1503 &state
->attachments
[i
].color
,
1506 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1508 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1513 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1514 anv_image_fill_surface_state(cmd_buffer
->device
,
1516 VK_IMAGE_ASPECT_COLOR_BIT
,
1517 &iview
->planes
[0].isl
,
1518 ISL_SURF_USAGE_TEXTURE_BIT
,
1519 state
->attachments
[i
].input_aux_usage
,
1522 &state
->attachments
[i
].input
,
1525 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1534 genX(BeginCommandBuffer
)(
1535 VkCommandBuffer commandBuffer
,
1536 const VkCommandBufferBeginInfo
* pBeginInfo
)
1538 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1540 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1541 * command buffer's state. Otherwise, we must *reset* its state. In both
1542 * cases we reset it.
1544 * From the Vulkan 1.0 spec:
1546 * If a command buffer is in the executable state and the command buffer
1547 * was allocated from a command pool with the
1548 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1549 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1550 * as if vkResetCommandBuffer had been called with
1551 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1552 * the command buffer in the recording state.
1554 anv_cmd_buffer_reset(cmd_buffer
);
1556 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1558 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1559 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1561 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1563 /* We sometimes store vertex data in the dynamic state buffer for blorp
1564 * operations and our dynamic state stream may re-use data from previous
1565 * command buffers. In order to prevent stale cache data, we flush the VF
1566 * cache. We could do this on every blorp call but that's not really
1567 * needed as all of the data will get written by the CPU prior to the GPU
1568 * executing anything. The chances are fairly high that they will use
1569 * blorp at least once per primary command buffer so it shouldn't be
1572 * There is also a workaround on gen8 which requires us to invalidate the
1573 * VF cache occasionally. It's easier if we can assume we start with a
1574 * fresh cache (See also genX(cmd_buffer_set_binding_for_gen8_vb_flush).)
1576 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1578 /* Re-emit the aux table register in every command buffer. This way we're
1579 * ensured that we have the table even if this command buffer doesn't
1580 * initialize any images.
1582 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
;
1584 /* We send an "Indirect State Pointers Disable" packet at
1585 * EndCommandBuffer, so all push contant packets are ignored during a
1586 * context restore. Documentation says after that command, we need to
1587 * emit push constants again before any rendering operation. So we
1588 * flag them dirty here to make sure they get emitted.
1590 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1592 VkResult result
= VK_SUCCESS
;
1593 if (cmd_buffer
->usage_flags
&
1594 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1595 assert(pBeginInfo
->pInheritanceInfo
);
1596 cmd_buffer
->state
.pass
=
1597 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1598 cmd_buffer
->state
.subpass
=
1599 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1601 /* This is optional in the inheritance info. */
1602 cmd_buffer
->state
.framebuffer
=
1603 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1605 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1606 cmd_buffer
->state
.pass
, NULL
);
1608 /* Record that HiZ is enabled if we can. */
1609 if (cmd_buffer
->state
.framebuffer
) {
1610 const struct anv_image_view
* const iview
=
1611 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1614 VkImageLayout layout
=
1615 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1617 enum isl_aux_usage aux_usage
=
1618 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1619 VK_IMAGE_ASPECT_DEPTH_BIT
,
1620 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
1623 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1627 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1630 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1631 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1632 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1633 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1635 /* If secondary buffer supports conditional rendering
1636 * we should emit commands as if conditional rendering is enabled.
1638 cmd_buffer
->state
.conditional_render_enabled
=
1639 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1646 /* From the PRM, Volume 2a:
1648 * "Indirect State Pointers Disable
1650 * At the completion of the post-sync operation associated with this pipe
1651 * control packet, the indirect state pointers in the hardware are
1652 * considered invalid; the indirect pointers are not saved in the context.
1653 * If any new indirect state commands are executed in the command stream
1654 * while the pipe control is pending, the new indirect state commands are
1657 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1658 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1659 * commands are only considered as Indirect State Pointers. Once ISP is
1660 * issued in a context, SW must initialize by programming push constant
1661 * commands for all the shaders (at least to zero length) before attempting
1662 * any rendering operation for the same context."
1664 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1665 * even though they point to a BO that has been already unreferenced at
1666 * the end of the previous batch buffer. This has been fine so far since
1667 * we are protected by these scratch page (every address not covered by
1668 * a BO should be pointing to the scratch page). But on CNL, it is
1669 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1672 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1673 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1674 * context restore, so the mentioned hang doesn't happen. However,
1675 * software must program push constant commands for all stages prior to
1676 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1678 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1679 * constants have been loaded into the EUs prior to disable the push constants
1680 * so that it doesn't hang a previous 3DPRIMITIVE.
1683 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1685 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1686 pc
.StallAtPixelScoreboard
= true;
1687 pc
.CommandStreamerStallEnable
= true;
1689 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1690 pc
.IndirectStatePointersDisable
= true;
1691 pc
.CommandStreamerStallEnable
= true;
1696 genX(EndCommandBuffer
)(
1697 VkCommandBuffer commandBuffer
)
1699 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1701 if (anv_batch_has_error(&cmd_buffer
->batch
))
1702 return cmd_buffer
->batch
.status
;
1704 /* We want every command buffer to start with the PMA fix in a known state,
1705 * so we disable it at the end of the command buffer.
1707 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1709 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1711 emit_isp_disable(cmd_buffer
);
1713 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1719 genX(CmdExecuteCommands
)(
1720 VkCommandBuffer commandBuffer
,
1721 uint32_t commandBufferCount
,
1722 const VkCommandBuffer
* pCmdBuffers
)
1724 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1726 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1728 if (anv_batch_has_error(&primary
->batch
))
1731 /* The secondary command buffers will assume that the PMA fix is disabled
1732 * when they begin executing. Make sure this is true.
1734 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1736 /* The secondary command buffer doesn't know which textures etc. have been
1737 * flushed prior to their execution. Apply those flushes now.
1739 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1741 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1742 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1744 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1745 assert(!anv_batch_has_error(&secondary
->batch
));
1747 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1748 if (secondary
->state
.conditional_render_enabled
) {
1749 if (!primary
->state
.conditional_render_enabled
) {
1750 /* Secondary buffer is constructed as if it will be executed
1751 * with conditional rendering, we should satisfy this dependency
1752 * regardless of conditional rendering being enabled in primary.
1754 struct gen_mi_builder b
;
1755 gen_mi_builder_init(&b
, &primary
->batch
);
1756 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
1757 gen_mi_imm(UINT64_MAX
));
1762 if (secondary
->usage_flags
&
1763 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1764 /* If we're continuing a render pass from the primary, we need to
1765 * copy the surface states for the current subpass into the storage
1766 * we allocated for them in BeginCommandBuffer.
1768 struct anv_bo
*ss_bo
=
1769 primary
->device
->surface_state_pool
.block_pool
.bo
;
1770 struct anv_state src_state
= primary
->state
.render_pass_states
;
1771 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1772 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1774 genX(cmd_buffer_so_memcpy
)(primary
,
1775 (struct anv_address
) {
1777 .offset
= dst_state
.offset
,
1779 (struct anv_address
) {
1781 .offset
= src_state
.offset
,
1783 src_state
.alloc_size
);
1786 anv_cmd_buffer_add_secondary(primary
, secondary
);
1789 /* The secondary isn't counted in our VF cache tracking so we need to
1790 * invalidate the whole thing.
1792 if (GEN_GEN
>= 8 && GEN_GEN
<= 9) {
1793 primary
->state
.pending_pipe_bits
|=
1794 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1797 /* The secondary may have selected a different pipeline (3D or compute) and
1798 * may have changed the current L3$ configuration. Reset our tracking
1799 * variables to invalid values to ensure that we re-emit these in the case
1800 * where we do any draws or compute dispatches from the primary after the
1801 * secondary has returned.
1803 primary
->state
.current_pipeline
= UINT32_MAX
;
1804 primary
->state
.current_l3_config
= NULL
;
1805 primary
->state
.current_hash_scale
= 0;
1807 /* Each of the secondary command buffers will use its own state base
1808 * address. We need to re-emit state base address for the primary after
1809 * all of the secondaries are done.
1811 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1814 genX(cmd_buffer_emit_state_base_address
)(primary
);
1817 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1818 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1819 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1822 * Program the hardware to use the specified L3 configuration.
1825 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1826 const struct gen_l3_config
*cfg
)
1829 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1832 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1833 intel_logd("L3 config transition: ");
1834 gen_dump_l3_config(cfg
, stderr
);
1837 UNUSED
const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1839 /* According to the hardware docs, the L3 partitioning can only be changed
1840 * while the pipeline is completely drained and the caches are flushed,
1841 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1843 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1844 pc
.DCFlushEnable
= true;
1845 pc
.PostSyncOperation
= NoWrite
;
1846 pc
.CommandStreamerStallEnable
= true;
1849 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1850 * invalidation of the relevant caches. Note that because RO invalidation
1851 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1852 * command is processed by the CS) we cannot combine it with the previous
1853 * stalling flush as the hardware documentation suggests, because that
1854 * would cause the CS to stall on previous rendering *after* RO
1855 * invalidation and wouldn't prevent the RO caches from being polluted by
1856 * concurrent rendering before the stall completes. This intentionally
1857 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1858 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1859 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1860 * already guarantee that there is no concurrent GPGPU kernel execution
1861 * (see SKL HSD 2132585).
1863 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1864 pc
.TextureCacheInvalidationEnable
= true;
1865 pc
.ConstantCacheInvalidationEnable
= true;
1866 pc
.InstructionCacheInvalidateEnable
= true;
1867 pc
.StateCacheInvalidationEnable
= true;
1868 pc
.PostSyncOperation
= NoWrite
;
1871 /* Now send a third stalling flush to make sure that invalidation is
1872 * complete when the L3 configuration registers are modified.
1874 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1875 pc
.DCFlushEnable
= true;
1876 pc
.PostSyncOperation
= NoWrite
;
1877 pc
.CommandStreamerStallEnable
= true;
1882 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1885 #define L3_ALLOCATION_REG GENX(L3ALLOC)
1886 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
1888 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
1889 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
1893 anv_pack_struct(&l3cr
, L3_ALLOCATION_REG
,
1895 .SLMEnable
= has_slm
,
1898 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1899 * in L3CNTLREG register. The default setting of the bit is not the
1900 * desirable behavior.
1902 .ErrorDetectionBehaviorControl
= true,
1903 .UseFullWays
= true,
1905 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1906 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1907 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1908 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1910 /* Set up the L3 partitioning. */
1911 emit_lri(&cmd_buffer
->batch
, L3_ALLOCATION_REG_num
, l3cr
);
1915 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1916 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1917 cfg
->n
[GEN_L3P_ALL
];
1918 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1919 cfg
->n
[GEN_L3P_ALL
];
1920 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1921 cfg
->n
[GEN_L3P_ALL
];
1923 assert(!cfg
->n
[GEN_L3P_ALL
]);
1925 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1926 * the matching space on the remaining banks has to be allocated to a
1927 * client (URB for all validated configurations) set to the
1928 * lower-bandwidth 2-bank address hashing mode.
1930 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1931 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1932 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1934 /* Minimum number of ways that can be allocated to the URB. */
1935 const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1936 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1938 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1939 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1940 .ConvertDC_UC
= !has_dc
,
1941 .ConvertIS_UC
= !has_is
,
1942 .ConvertC_UC
= !has_c
,
1943 .ConvertT_UC
= !has_t
);
1945 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1946 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1947 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1949 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1950 .SLMEnable
= has_slm
,
1951 .URBLowBandwidth
= urb_low_bw
,
1952 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1954 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1956 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1957 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1959 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1960 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1961 .ISLowBandwidth
= 0,
1962 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1964 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1965 .TLowBandwidth
= 0);
1967 /* Set up the L3 partitioning. */
1968 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1969 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1970 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1973 if (cmd_buffer
->device
->physical
->cmd_parser_version
>= 4) {
1974 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1975 * them disabled to avoid crashing the system hard.
1977 uint32_t scratch1
, chicken3
;
1978 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1979 .L3AtomicDisable
= !has_dc
);
1980 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1981 .L3AtomicDisableMask
= true,
1982 .L3AtomicDisable
= !has_dc
);
1983 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1984 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1990 cmd_buffer
->state
.current_l3_config
= cfg
;
1994 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1996 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1997 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1999 if (cmd_buffer
->device
->physical
->always_flush_cache
)
2000 bits
|= ANV_PIPE_FLUSH_BITS
| ANV_PIPE_INVALIDATE_BITS
;
2003 * From Sandybridge PRM, volume 2, "1.7.2 End-of-Pipe Synchronization":
2005 * Write synchronization is a special case of end-of-pipe
2006 * synchronization that requires that the render cache and/or depth
2007 * related caches are flushed to memory, where the data will become
2008 * globally visible. This type of synchronization is required prior to
2009 * SW (CPU) actually reading the result data from memory, or initiating
2010 * an operation that will use as a read surface (such as a texture
2011 * surface) a previous render target and/or depth/stencil buffer
2014 * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
2016 * Exercising the write cache flush bits (Render Target Cache Flush
2017 * Enable, Depth Cache Flush Enable, DC Flush) in PIPE_CONTROL only
2018 * ensures the write caches are flushed and doesn't guarantee the data
2019 * is globally visible.
2021 * SW can track the completion of the end-of-pipe-synchronization by
2022 * using "Notify Enable" and "PostSync Operation - Write Immediate
2023 * Data" in the PIPE_CONTROL command.
2025 * In other words, flushes are pipelined while invalidations are handled
2026 * immediately. Therefore, if we're flushing anything then we need to
2027 * schedule an end-of-pipe sync before any invalidations can happen.
2029 if (bits
& ANV_PIPE_FLUSH_BITS
)
2030 bits
|= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2033 /* HSD 1209978178: docs say that before programming the aux table:
2035 * "Driver must ensure that the engine is IDLE but ensure it doesn't
2036 * add extra flushes in the case it knows that the engine is already
2039 if (GEN_GEN
== 12 && ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
)
2040 bits
|= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2042 /* If we're going to do an invalidate and we have a pending end-of-pipe
2043 * sync that has yet to be resolved, we do the end-of-pipe sync now.
2045 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
2046 (bits
& ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
)) {
2047 bits
|= ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
2048 bits
&= ~ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2051 if (GEN_GEN
>= 12 &&
2052 ((bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
) ||
2053 (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
))) {
2054 /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
2057 * Unified Cache (Tile Cache Disabled):
2059 * When the Color and Depth (Z) streams are enabled to be cached in
2060 * the DC space of L2, Software must use "Render Target Cache Flush
2061 * Enable" and "Depth Cache Flush Enable" along with "Tile Cache
2062 * Flush" for getting the color and depth (Z) write data to be
2063 * globally observable. In this mode of operation it is not required
2064 * to set "CS Stall" upon setting "Tile Cache Flush" bit.
2066 bits
|= ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
2069 /* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which
2070 * invalidates the instruction cache
2072 if (GEN_GEN
== 12 && (bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
))
2073 bits
|= ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
2075 if ((GEN_GEN
>= 8 && GEN_GEN
<= 9) &&
2076 (bits
& ANV_PIPE_CS_STALL_BIT
) &&
2077 (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
)) {
2078 /* If we are doing a VF cache invalidate AND a CS stall (it must be
2079 * both) then we can reset our vertex cache tracking.
2081 memset(cmd_buffer
->state
.gfx
.vb_dirty_ranges
, 0,
2082 sizeof(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
2083 memset(&cmd_buffer
->state
.gfx
.ib_dirty_range
, 0,
2084 sizeof(cmd_buffer
->state
.gfx
.ib_dirty_range
));
2087 /* Project: SKL / Argument: LRI Post Sync Operation [23]
2089 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
2090 * programmed prior to programming a PIPECONTROL command with "LRI
2091 * Post Sync Operation" in GPGPU mode of operation (i.e when
2092 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
2094 * The same text exists a few rows below for Post Sync Op.
2096 * On Gen12 this is GEN:BUG:1607156449.
2098 if (bits
& ANV_PIPE_POST_SYNC_BIT
) {
2099 if ((GEN_GEN
== 9 || (GEN_GEN
== 12 && devinfo
->revision
== 0 /* A0 */)) &&
2100 cmd_buffer
->state
.current_pipeline
== GPGPU
)
2101 bits
|= ANV_PIPE_CS_STALL_BIT
;
2102 bits
&= ~ANV_PIPE_POST_SYNC_BIT
;
2105 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
|
2106 ANV_PIPE_END_OF_PIPE_SYNC_BIT
)) {
2107 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2109 pipe
.TileCacheFlushEnable
= bits
& ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
2111 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2112 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2113 pipe
.RenderTargetCacheFlushEnable
=
2114 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2116 /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
2117 * be set with any PIPE_CONTROL with Depth Flush Enable bit set.
2120 pipe
.DepthStallEnable
=
2121 pipe
.DepthCacheFlushEnable
|| (bits
& ANV_PIPE_DEPTH_STALL_BIT
);
2123 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
2126 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
2127 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
2129 /* From Sandybridge PRM, volume 2, "1.7.3.1 Writing a Value to Memory":
2131 * "The most common action to perform upon reaching a
2132 * synchronization point is to write a value out to memory. An
2133 * immediate value (included with the synchronization command) may
2137 * From Broadwell PRM, volume 7, "End-of-Pipe Synchronization":
2139 * "In case the data flushed out by the render engine is to be
2140 * read back in to the render engine in coherent manner, then the
2141 * render engine has to wait for the fence completion before
2142 * accessing the flushed data. This can be achieved by following
2143 * means on various products: PIPE_CONTROL command with CS Stall
2144 * and the required write caches flushed with Post-Sync-Operation
2145 * as Write Immediate Data.
2148 * - Workload-1 (3D/GPGPU/MEDIA)
2149 * - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write
2150 * Immediate Data, Required Write Cache Flush bits set)
2151 * - Workload-2 (Can use the data produce or output by
2154 if (bits
& ANV_PIPE_END_OF_PIPE_SYNC_BIT
) {
2155 pipe
.CommandStreamerStallEnable
= true;
2156 pipe
.PostSyncOperation
= WriteImmediateData
;
2157 pipe
.Address
= (struct anv_address
) {
2158 .bo
= cmd_buffer
->device
->workaround_bo
,
2164 * According to the Broadwell documentation, any PIPE_CONTROL with the
2165 * "Command Streamer Stall" bit set must also have another bit set,
2166 * with five different options:
2168 * - Render Target Cache Flush
2169 * - Depth Cache Flush
2170 * - Stall at Pixel Scoreboard
2171 * - Post-Sync Operation
2175 * I chose "Stall at Pixel Scoreboard" since that's what we use in
2176 * mesa and it seems to work fine. The choice is fairly arbitrary.
2178 if (pipe
.CommandStreamerStallEnable
&&
2179 !pipe
.RenderTargetCacheFlushEnable
&&
2180 !pipe
.DepthCacheFlushEnable
&&
2181 !pipe
.StallAtPixelScoreboard
&&
2182 !pipe
.PostSyncOperation
&&
2183 !pipe
.DepthStallEnable
&&
2184 !pipe
.DCFlushEnable
)
2185 pipe
.StallAtPixelScoreboard
= true;
2188 /* If a render target flush was emitted, then we can toggle off the bit
2189 * saying that render target writes are ongoing.
2191 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
2192 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
2194 if (GEN_IS_HASWELL
) {
2195 /* Haswell needs addition work-arounds:
2197 * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
2200 * PIPE_CONTROL command with the CS Stall and the required write
2201 * caches flushed with Post-SyncOperation as Write Immediate Data
2202 * followed by eight dummy MI_STORE_DATA_IMM (write to scratch
2207 * - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write
2208 * Immediate Data, Required Write Cache Flush bits set)
2209 * - MI_STORE_DATA_IMM (8 times) (Dummy data, Scratch Address)
2210 * - Workload-2 (Can use the data produce or output by
2213 * Unfortunately, both the PRMs and the internal docs are a bit
2214 * out-of-date in this regard. What the windows driver does (and
2215 * this appears to actually work) is to emit a register read from the
2216 * memory address written by the pipe control above.
2218 * What register we load into doesn't matter. We choose an indirect
2219 * rendering register because we know it always exists and it's one
2220 * of the first registers the command parser allows us to write. If
2221 * you don't have command parser support in your kernel (pre-4.2),
2222 * this will get turned into MI_NOOP and you won't get the
2223 * workaround. Unfortunately, there's just not much we can do in
2224 * that case. This register is perfectly safe to write since we
2225 * always re-load all of the indirect draw registers right before
2226 * 3DPRIMITIVE when needed anyway.
2228 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2229 lrm
.RegisterAddress
= 0x243C; /* GEN7_3DPRIM_START_INSTANCE */
2230 lrm
.MemoryAddress
= (struct anv_address
) {
2231 .bo
= cmd_buffer
->device
->workaround_bo
,
2237 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
|
2238 ANV_PIPE_END_OF_PIPE_SYNC_BIT
);
2241 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
2242 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
2244 * "If the VF Cache Invalidation Enable is set to a 1 in a
2245 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
2246 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
2247 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
2250 * This appears to hang Broadwell, so we restrict it to just gen9.
2252 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
2253 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
2255 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2256 pipe
.StateCacheInvalidationEnable
=
2257 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
2258 pipe
.ConstantCacheInvalidationEnable
=
2259 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2260 pipe
.VFCacheInvalidationEnable
=
2261 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2262 pipe
.TextureCacheInvalidationEnable
=
2263 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2264 pipe
.InstructionCacheInvalidateEnable
=
2265 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
2267 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
2269 * "When VF Cache Invalidate is set “Post Sync Operation” must be
2270 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
2271 * “Write Timestamp”.
2273 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
2274 pipe
.PostSyncOperation
= WriteImmediateData
;
2276 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
2281 if ((bits
& ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
) &&
2282 cmd_buffer
->device
->info
.has_aux_map
) {
2283 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
2284 lri
.RegisterOffset
= GENX(GFX_CCS_AUX_INV_num
);
2290 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
2293 cmd_buffer
->state
.pending_pipe_bits
= bits
;
2296 void genX(CmdPipelineBarrier
)(
2297 VkCommandBuffer commandBuffer
,
2298 VkPipelineStageFlags srcStageMask
,
2299 VkPipelineStageFlags destStageMask
,
2301 uint32_t memoryBarrierCount
,
2302 const VkMemoryBarrier
* pMemoryBarriers
,
2303 uint32_t bufferMemoryBarrierCount
,
2304 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
2305 uint32_t imageMemoryBarrierCount
,
2306 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
2308 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2310 /* XXX: Right now, we're really dumb and just flush whatever categories
2311 * the app asks for. One of these days we may make this a bit better
2312 * but right now that's all the hardware allows for in most areas.
2314 VkAccessFlags src_flags
= 0;
2315 VkAccessFlags dst_flags
= 0;
2317 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
2318 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
2319 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
2322 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
2323 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
2324 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
2327 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
2328 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
2329 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
2330 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
2331 const VkImageSubresourceRange
*range
=
2332 &pImageMemoryBarriers
[i
].subresourceRange
;
2334 uint32_t base_layer
, layer_count
;
2335 if (image
->type
== VK_IMAGE_TYPE_3D
) {
2337 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
2339 base_layer
= range
->baseArrayLayer
;
2340 layer_count
= anv_get_layerCount(image
, range
);
2343 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
2344 transition_depth_buffer(cmd_buffer
, image
,
2345 pImageMemoryBarriers
[i
].oldLayout
,
2346 pImageMemoryBarriers
[i
].newLayout
);
2349 if (range
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
2350 transition_stencil_buffer(cmd_buffer
, image
,
2351 range
->baseMipLevel
,
2352 anv_get_levelCount(image
, range
),
2353 base_layer
, layer_count
,
2354 pImageMemoryBarriers
[i
].oldLayout
,
2355 pImageMemoryBarriers
[i
].newLayout
);
2358 if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
2359 VkImageAspectFlags color_aspects
=
2360 anv_image_expand_aspects(image
, range
->aspectMask
);
2361 uint32_t aspect_bit
;
2362 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
2363 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
2364 range
->baseMipLevel
,
2365 anv_get_levelCount(image
, range
),
2366 base_layer
, layer_count
,
2367 pImageMemoryBarriers
[i
].oldLayout
,
2368 pImageMemoryBarriers
[i
].newLayout
);
2373 cmd_buffer
->state
.pending_pipe_bits
|=
2374 anv_pipe_flush_bits_for_access_flags(src_flags
) |
2375 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
2379 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
2381 VkShaderStageFlags stages
=
2382 cmd_buffer
->state
.gfx
.pipeline
->active_stages
;
2384 /* In order to avoid thrash, we assume that vertex and fragment stages
2385 * always exist. In the rare case where one is missing *and* the other
2386 * uses push concstants, this may be suboptimal. However, avoiding stalls
2387 * seems more important.
2389 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
2391 if (stages
== cmd_buffer
->state
.push_constant_stages
)
2395 const unsigned push_constant_kb
= 32;
2396 #elif GEN_IS_HASWELL
2397 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
2399 const unsigned push_constant_kb
= 16;
2402 const unsigned num_stages
=
2403 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
2404 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
2406 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
2407 * units of 2KB. Incidentally, these are the same platforms that have
2408 * 32KB worth of push constant space.
2410 if (push_constant_kb
== 32)
2411 size_per_stage
&= ~1u;
2413 uint32_t kb_used
= 0;
2414 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
2415 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
2416 anv_batch_emit(&cmd_buffer
->batch
,
2417 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
2418 alloc
._3DCommandSubOpcode
= 18 + i
;
2419 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
2420 alloc
.ConstantBufferSize
= push_size
;
2422 kb_used
+= push_size
;
2425 anv_batch_emit(&cmd_buffer
->batch
,
2426 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
2427 alloc
.ConstantBufferOffset
= kb_used
;
2428 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
2431 cmd_buffer
->state
.push_constant_stages
= stages
;
2433 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
2435 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
2436 * the next 3DPRIMITIVE command after programming the
2437 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
2439 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
2440 * pipeline setup, we need to dirty push constants.
2442 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
2445 static struct anv_address
2446 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
2447 struct anv_descriptor_set
*set
)
2450 /* This is a normal descriptor set */
2451 return (struct anv_address
) {
2452 .bo
= set
->pool
->bo
,
2453 .offset
= set
->desc_mem
.offset
,
2456 /* This is a push descriptor set. We have to flag it as used on the GPU
2457 * so that the next time we push descriptors, we grab a new memory.
2459 struct anv_push_descriptor_set
*push_set
=
2460 (struct anv_push_descriptor_set
*)set
;
2461 push_set
->set_used_on_gpu
= true;
2463 return (struct anv_address
) {
2464 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2465 .offset
= set
->desc_mem
.offset
,
2471 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2472 struct anv_cmd_pipeline_state
*pipe_state
,
2473 struct anv_shader_bin
*shader
,
2474 struct anv_state
*bt_state
)
2476 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2477 uint32_t state_offset
;
2479 struct anv_pipeline_bind_map
*map
= &shader
->bind_map
;
2480 if (map
->surface_count
== 0) {
2481 *bt_state
= (struct anv_state
) { 0, };
2485 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2488 uint32_t *bt_map
= bt_state
->map
;
2490 if (bt_state
->map
== NULL
)
2491 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2493 /* We only need to emit relocs if we're not using softpin. If we are using
2494 * softpin then we always keep all user-allocated memory objects resident.
2496 const bool need_client_mem_relocs
=
2497 !cmd_buffer
->device
->physical
->use_softpin
;
2499 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2500 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2502 struct anv_state surface_state
;
2504 switch (binding
->set
) {
2505 case ANV_DESCRIPTOR_SET_NULL
:
2509 case ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
:
2510 /* Color attachment binding */
2511 assert(shader
->stage
== MESA_SHADER_FRAGMENT
);
2512 if (binding
->index
< subpass
->color_count
) {
2513 const unsigned att
=
2514 subpass
->color_attachments
[binding
->index
].attachment
;
2516 /* From the Vulkan 1.0.46 spec:
2518 * "If any color or depth/stencil attachments are
2519 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2522 if (att
== VK_ATTACHMENT_UNUSED
) {
2523 surface_state
= cmd_buffer
->state
.null_surface_state
;
2525 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2528 surface_state
= cmd_buffer
->state
.null_surface_state
;
2531 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2534 case ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
: {
2535 struct anv_state surface_state
=
2536 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2538 struct anv_address constant_data
= {
2539 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2540 .offset
= shader
->constant_data
.offset
,
2542 unsigned constant_data_size
= shader
->constant_data_size
;
2544 const enum isl_format format
=
2545 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2546 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2547 surface_state
, format
,
2548 constant_data
, constant_data_size
, 1);
2550 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2551 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2555 case ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
: {
2556 /* This is always the first binding for compute shaders */
2557 assert(shader
->stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2559 struct anv_state surface_state
=
2560 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2562 const enum isl_format format
=
2563 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2564 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2566 cmd_buffer
->state
.compute
.num_workgroups
,
2568 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2569 if (need_client_mem_relocs
) {
2570 add_surface_reloc(cmd_buffer
, surface_state
,
2571 cmd_buffer
->state
.compute
.num_workgroups
);
2576 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2577 /* This is a descriptor set buffer so the set index is actually
2578 * given by binding->binding. (Yes, that's confusing.)
2580 struct anv_descriptor_set
*set
=
2581 pipe_state
->descriptors
[binding
->index
];
2582 assert(set
->desc_mem
.alloc_size
);
2583 assert(set
->desc_surface_state
.alloc_size
);
2584 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2585 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2586 anv_descriptor_set_address(cmd_buffer
, set
));
2591 assert(binding
->set
< MAX_SETS
);
2592 const struct anv_descriptor
*desc
=
2593 &pipe_state
->descriptors
[binding
->set
]->descriptors
[binding
->index
];
2595 switch (desc
->type
) {
2596 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2597 /* Nothing for us to do here */
2600 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2601 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2602 struct anv_surface_state sstate
=
2603 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2604 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2605 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2606 surface_state
= sstate
.state
;
2607 assert(surface_state
.alloc_size
);
2608 if (need_client_mem_relocs
)
2609 add_surface_state_relocs(cmd_buffer
, sstate
);
2612 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2613 assert(shader
->stage
== MESA_SHADER_FRAGMENT
);
2614 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2615 /* For depth and stencil input attachments, we treat it like any
2616 * old texture that a user may have bound.
2618 assert(desc
->image_view
->n_planes
== 1);
2619 struct anv_surface_state sstate
=
2620 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2621 desc
->image_view
->planes
[0].general_sampler_surface_state
:
2622 desc
->image_view
->planes
[0].optimal_sampler_surface_state
;
2623 surface_state
= sstate
.state
;
2624 assert(surface_state
.alloc_size
);
2625 if (need_client_mem_relocs
)
2626 add_surface_state_relocs(cmd_buffer
, sstate
);
2628 /* For color input attachments, we create the surface state at
2629 * vkBeginRenderPass time so that we can include aux and clear
2630 * color information.
2632 assert(binding
->input_attachment_index
< subpass
->input_count
);
2633 const unsigned subpass_att
= binding
->input_attachment_index
;
2634 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2635 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2639 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2640 struct anv_surface_state sstate
= (binding
->write_only
)
2641 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2642 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2643 surface_state
= sstate
.state
;
2644 assert(surface_state
.alloc_size
);
2645 if (need_client_mem_relocs
)
2646 add_surface_state_relocs(cmd_buffer
, sstate
);
2650 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2651 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2652 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2653 surface_state
= desc
->buffer_view
->surface_state
;
2654 assert(surface_state
.alloc_size
);
2655 if (need_client_mem_relocs
) {
2656 add_surface_reloc(cmd_buffer
, surface_state
,
2657 desc
->buffer_view
->address
);
2661 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2662 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2663 /* Compute the offset within the buffer */
2664 struct anv_push_constants
*push
=
2665 &cmd_buffer
->state
.push_constants
[shader
->stage
];
2667 uint32_t dynamic_offset
=
2668 push
->dynamic_offsets
[binding
->dynamic_offset_index
];
2669 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2670 /* Clamp to the buffer size */
2671 offset
= MIN2(offset
, desc
->buffer
->size
);
2672 /* Clamp the range to the buffer size */
2673 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2675 /* Align the range for consistency */
2676 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
)
2677 range
= align_u32(range
, ANV_UBO_BOUNDS_CHECK_ALIGNMENT
);
2679 struct anv_address address
=
2680 anv_address_add(desc
->buffer
->address
, offset
);
2683 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2684 enum isl_format format
=
2685 anv_isl_format_for_descriptor_type(desc
->type
);
2687 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2688 format
, address
, range
, 1);
2689 if (need_client_mem_relocs
)
2690 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2694 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2695 surface_state
= (binding
->write_only
)
2696 ? desc
->buffer_view
->writeonly_storage_surface_state
2697 : desc
->buffer_view
->storage_surface_state
;
2698 assert(surface_state
.alloc_size
);
2699 if (need_client_mem_relocs
) {
2700 add_surface_reloc(cmd_buffer
, surface_state
,
2701 desc
->buffer_view
->address
);
2706 assert(!"Invalid descriptor type");
2709 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2719 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2720 struct anv_cmd_pipeline_state
*pipe_state
,
2721 struct anv_shader_bin
*shader
,
2722 struct anv_state
*state
)
2724 struct anv_pipeline_bind_map
*map
= &shader
->bind_map
;
2725 if (map
->sampler_count
== 0) {
2726 *state
= (struct anv_state
) { 0, };
2730 uint32_t size
= map
->sampler_count
* 16;
2731 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2733 if (state
->map
== NULL
)
2734 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2736 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2737 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2738 const struct anv_descriptor
*desc
=
2739 &pipe_state
->descriptors
[binding
->set
]->descriptors
[binding
->index
];
2741 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2742 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2745 struct anv_sampler
*sampler
= desc
->sampler
;
2747 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2748 * happens to be zero.
2750 if (sampler
== NULL
)
2753 memcpy(state
->map
+ (s
* 16),
2754 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2761 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
,
2762 struct anv_cmd_pipeline_state
*pipe_state
,
2763 struct anv_shader_bin
**shaders
,
2764 uint32_t num_shaders
)
2766 const VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
;
2767 VkShaderStageFlags flushed
= 0;
2769 VkResult result
= VK_SUCCESS
;
2770 for (uint32_t i
= 0; i
< num_shaders
; i
++) {
2774 gl_shader_stage stage
= shaders
[i
]->stage
;
2775 VkShaderStageFlags vk_stage
= mesa_to_vk_shader_stage(stage
);
2776 if ((vk_stage
& dirty
) == 0)
2779 result
= emit_samplers(cmd_buffer
, pipe_state
, shaders
[i
],
2780 &cmd_buffer
->state
.samplers
[stage
]);
2781 if (result
!= VK_SUCCESS
)
2783 result
= emit_binding_table(cmd_buffer
, pipe_state
, shaders
[i
],
2784 &cmd_buffer
->state
.binding_tables
[stage
]);
2785 if (result
!= VK_SUCCESS
)
2788 flushed
|= vk_stage
;
2791 if (result
!= VK_SUCCESS
) {
2792 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2794 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2795 if (result
!= VK_SUCCESS
)
2798 /* Re-emit state base addresses so we get the new surface state base
2799 * address before we start emitting binding tables etc.
2801 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2803 /* Re-emit all active binding tables */
2806 for (uint32_t i
= 0; i
< num_shaders
; i
++) {
2810 gl_shader_stage stage
= shaders
[i
]->stage
;
2812 result
= emit_samplers(cmd_buffer
, pipe_state
, shaders
[i
],
2813 &cmd_buffer
->state
.samplers
[stage
]);
2814 if (result
!= VK_SUCCESS
) {
2815 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2818 result
= emit_binding_table(cmd_buffer
, pipe_state
, shaders
[i
],
2819 &cmd_buffer
->state
.binding_tables
[stage
]);
2820 if (result
!= VK_SUCCESS
) {
2821 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2825 flushed
|= mesa_to_vk_shader_stage(stage
);
2829 cmd_buffer
->state
.descriptors_dirty
&= ~flushed
;
2835 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2838 static const uint32_t sampler_state_opcodes
[] = {
2839 [MESA_SHADER_VERTEX
] = 43,
2840 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2841 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2842 [MESA_SHADER_GEOMETRY
] = 46,
2843 [MESA_SHADER_FRAGMENT
] = 47,
2844 [MESA_SHADER_COMPUTE
] = 0,
2847 static const uint32_t binding_table_opcodes
[] = {
2848 [MESA_SHADER_VERTEX
] = 38,
2849 [MESA_SHADER_TESS_CTRL
] = 39,
2850 [MESA_SHADER_TESS_EVAL
] = 40,
2851 [MESA_SHADER_GEOMETRY
] = 41,
2852 [MESA_SHADER_FRAGMENT
] = 42,
2853 [MESA_SHADER_COMPUTE
] = 0,
2856 anv_foreach_stage(s
, stages
) {
2857 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2858 assert(binding_table_opcodes
[s
] > 0);
2860 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2861 anv_batch_emit(&cmd_buffer
->batch
,
2862 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2863 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2864 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2868 /* Always emit binding table pointers if we're asked to, since on SKL
2869 * this is what flushes push constants. */
2870 anv_batch_emit(&cmd_buffer
->batch
,
2871 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2872 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2873 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2878 static struct anv_address
2879 get_push_range_address(struct anv_cmd_buffer
*cmd_buffer
,
2880 gl_shader_stage stage
,
2881 const struct anv_push_range
*range
)
2883 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2884 switch (range
->set
) {
2885 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2886 /* This is a descriptor set buffer so the set index is
2887 * actually given by binding->binding. (Yes, that's
2890 struct anv_descriptor_set
*set
=
2891 gfx_state
->base
.descriptors
[range
->index
];
2892 return anv_descriptor_set_address(cmd_buffer
, set
);
2895 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
: {
2896 struct anv_state state
=
2897 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2898 return (struct anv_address
) {
2899 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2900 .offset
= state
.offset
,
2905 assert(range
->set
< MAX_SETS
);
2906 struct anv_descriptor_set
*set
=
2907 gfx_state
->base
.descriptors
[range
->set
];
2908 const struct anv_descriptor
*desc
=
2909 &set
->descriptors
[range
->index
];
2911 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2912 return desc
->buffer_view
->address
;
2914 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2915 struct anv_push_constants
*push
=
2916 &cmd_buffer
->state
.push_constants
[stage
];
2917 uint32_t dynamic_offset
=
2918 push
->dynamic_offsets
[range
->dynamic_offset_index
];
2919 return anv_address_add(desc
->buffer
->address
,
2920 desc
->offset
+ dynamic_offset
);
2927 /** Returns the size in bytes of the bound buffer
2929 * The range is relative to the start of the buffer, not the start of the
2930 * range. The returned range may be smaller than
2932 * (range->start + range->length) * 32;
2935 get_push_range_bound_size(struct anv_cmd_buffer
*cmd_buffer
,
2936 gl_shader_stage stage
,
2937 const struct anv_push_range
*range
)
2939 assert(stage
!= MESA_SHADER_COMPUTE
);
2940 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2941 switch (range
->set
) {
2942 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2943 struct anv_descriptor_set
*set
=
2944 gfx_state
->base
.descriptors
[range
->index
];
2945 assert(range
->start
* 32 < set
->desc_mem
.alloc_size
);
2946 assert((range
->start
+ range
->length
) * 32 <= set
->desc_mem
.alloc_size
);
2947 return set
->desc_mem
.alloc_size
;
2950 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
:
2951 return (range
->start
+ range
->length
) * 32;
2954 assert(range
->set
< MAX_SETS
);
2955 struct anv_descriptor_set
*set
=
2956 gfx_state
->base
.descriptors
[range
->set
];
2957 const struct anv_descriptor
*desc
=
2958 &set
->descriptors
[range
->index
];
2960 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2961 return desc
->buffer_view
->range
;
2963 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2964 /* Compute the offset within the buffer */
2965 struct anv_push_constants
*push
=
2966 &cmd_buffer
->state
.push_constants
[stage
];
2967 uint32_t dynamic_offset
=
2968 push
->dynamic_offsets
[range
->dynamic_offset_index
];
2969 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2970 /* Clamp to the buffer size */
2971 offset
= MIN2(offset
, desc
->buffer
->size
);
2972 /* Clamp the range to the buffer size */
2973 uint32_t bound_range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2975 /* Align the range for consistency */
2976 bound_range
= align_u32(bound_range
, ANV_UBO_BOUNDS_CHECK_ALIGNMENT
);
2985 cmd_buffer_emit_push_constant(struct anv_cmd_buffer
*cmd_buffer
,
2986 gl_shader_stage stage
,
2987 struct anv_address
*buffers
,
2988 unsigned buffer_count
)
2990 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2991 const struct anv_graphics_pipeline
*pipeline
= gfx_state
->pipeline
;
2993 static const uint32_t push_constant_opcodes
[] = {
2994 [MESA_SHADER_VERTEX
] = 21,
2995 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2996 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2997 [MESA_SHADER_GEOMETRY
] = 22,
2998 [MESA_SHADER_FRAGMENT
] = 23,
2999 [MESA_SHADER_COMPUTE
] = 0,
3002 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
3003 assert(push_constant_opcodes
[stage
] > 0);
3005 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
3006 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3008 if (anv_pipeline_has_stage(pipeline
, stage
)) {
3009 const struct anv_pipeline_bind_map
*bind_map
=
3010 &pipeline
->shaders
[stage
]->bind_map
;
3013 c
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
;
3016 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3017 /* The Skylake PRM contains the following restriction:
3019 * "The driver must ensure The following case does not occur
3020 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3021 * buffer 3 read length equal to zero committed followed by a
3022 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3025 * To avoid this, we program the buffers in the highest slots.
3026 * This way, slot 0 is only used if slot 3 is also used.
3028 assert(buffer_count
<= 4);
3029 const unsigned shift
= 4 - buffer_count
;
3030 for (unsigned i
= 0; i
< buffer_count
; i
++) {
3031 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3033 /* At this point we only have non-empty ranges */
3034 assert(range
->length
> 0);
3036 /* For Ivy Bridge, make sure we only set the first range (actual
3039 assert((GEN_GEN
>= 8 || GEN_IS_HASWELL
) || i
== 0);
3041 c
.ConstantBody
.ReadLength
[i
+ shift
] = range
->length
;
3042 c
.ConstantBody
.Buffer
[i
+ shift
] =
3043 anv_address_add(buffers
[i
], range
->start
* 32);
3046 /* For Ivy Bridge, push constants are relative to dynamic state
3047 * base address and we only ever push actual push constants.
3049 if (bind_map
->push_ranges
[0].length
> 0) {
3050 assert(buffer_count
== 1);
3051 assert(bind_map
->push_ranges
[0].set
==
3052 ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
);
3053 assert(buffers
[0].bo
==
3054 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
);
3055 c
.ConstantBody
.ReadLength
[0] = bind_map
->push_ranges
[0].length
;
3056 c
.ConstantBody
.Buffer
[0].bo
= NULL
;
3057 c
.ConstantBody
.Buffer
[0].offset
= buffers
[0].offset
;
3059 assert(bind_map
->push_ranges
[1].length
== 0);
3060 assert(bind_map
->push_ranges
[2].length
== 0);
3061 assert(bind_map
->push_ranges
[3].length
== 0);
3069 cmd_buffer_emit_push_constant_all(struct anv_cmd_buffer
*cmd_buffer
,
3070 uint32_t shader_mask
,
3071 struct anv_address
*buffers
,
3072 uint32_t buffer_count
)
3074 if (buffer_count
== 0) {
3075 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_ALL
), c
) {
3076 c
.ShaderUpdateEnable
= shader_mask
;
3077 c
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
;
3082 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
3083 const struct anv_graphics_pipeline
*pipeline
= gfx_state
->pipeline
;
3085 static const uint32_t push_constant_opcodes
[] = {
3086 [MESA_SHADER_VERTEX
] = 21,
3087 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3088 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3089 [MESA_SHADER_GEOMETRY
] = 22,
3090 [MESA_SHADER_FRAGMENT
] = 23,
3091 [MESA_SHADER_COMPUTE
] = 0,
3094 gl_shader_stage stage
= vk_to_mesa_shader_stage(shader_mask
);
3095 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
3096 assert(push_constant_opcodes
[stage
] > 0);
3098 const struct anv_pipeline_bind_map
*bind_map
=
3099 &pipeline
->shaders
[stage
]->bind_map
;
3102 const uint32_t buffer_mask
= (1 << buffer_count
) - 1;
3103 const uint32_t num_dwords
= 2 + 2 * buffer_count
;
3105 dw
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
3106 GENX(3DSTATE_CONSTANT_ALL
),
3107 .ShaderUpdateEnable
= shader_mask
,
3108 .PointerBufferMask
= buffer_mask
,
3109 .MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
);
3111 for (int i
= 0; i
< buffer_count
; i
++) {
3112 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3113 GENX(3DSTATE_CONSTANT_ALL_DATA_pack
)(
3114 &cmd_buffer
->batch
, dw
+ 2 + i
* 2,
3115 &(struct GENX(3DSTATE_CONSTANT_ALL_DATA
)) {
3116 .PointerToConstantBuffer
=
3117 anv_address_add(buffers
[i
], range
->start
* 32),
3118 .ConstantBufferReadLength
= range
->length
,
3125 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
3126 VkShaderStageFlags dirty_stages
)
3128 VkShaderStageFlags flushed
= 0;
3129 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
3130 const struct anv_graphics_pipeline
*pipeline
= gfx_state
->pipeline
;
3133 uint32_t nobuffer_stages
= 0;
3136 anv_foreach_stage(stage
, dirty_stages
) {
3137 unsigned buffer_count
= 0;
3138 flushed
|= mesa_to_vk_shader_stage(stage
);
3139 UNUSED
uint32_t max_push_range
= 0;
3141 struct anv_address buffers
[4] = {};
3142 if (anv_pipeline_has_stage(pipeline
, stage
)) {
3143 const struct anv_pipeline_bind_map
*bind_map
=
3144 &pipeline
->shaders
[stage
]->bind_map
;
3145 struct anv_push_constants
*push
=
3146 &cmd_buffer
->state
.push_constants
[stage
];
3148 if (cmd_buffer
->device
->robust_buffer_access
) {
3149 for (unsigned i
= 0; i
< 4; i
++) {
3150 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3151 if (range
->length
== 0) {
3152 push
->push_ubo_sizes
[i
] = 0;
3154 push
->push_ubo_sizes
[i
] =
3155 get_push_range_bound_size(cmd_buffer
, stage
, range
);
3157 cmd_buffer
->state
.push_constants_dirty
|=
3158 mesa_to_vk_shader_stage(stage
);
3162 /* We have to gather buffer addresses as a second step because the
3163 * loop above puts data into the push constant area and the call to
3164 * get_push_range_address is what locks our push constants and copies
3165 * them into the actual GPU buffer. If we did the two loops at the
3166 * same time, we'd risk only having some of the sizes in the push
3167 * constant buffer when we did the copy.
3169 for (unsigned i
= 0; i
< 4; i
++) {
3170 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3171 if (range
->length
== 0)
3174 buffers
[i
] = get_push_range_address(cmd_buffer
, stage
, range
);
3175 max_push_range
= MAX2(max_push_range
, range
->length
);
3179 /* We have at most 4 buffers but they should be tightly packed */
3180 for (unsigned i
= buffer_count
; i
< 4; i
++)
3181 assert(bind_map
->push_ranges
[i
].length
== 0);
3185 /* If this stage doesn't have any push constants, emit it later in a
3186 * single CONSTANT_ALL packet.
3188 if (buffer_count
== 0) {
3189 nobuffer_stages
|= 1 << stage
;
3193 /* The Constant Buffer Read Length field from 3DSTATE_CONSTANT_ALL
3194 * contains only 5 bits, so we can only use it for buffers smaller than
3197 if (max_push_range
< 32) {
3198 cmd_buffer_emit_push_constant_all(cmd_buffer
, 1 << stage
,
3199 buffers
, buffer_count
);
3204 cmd_buffer_emit_push_constant(cmd_buffer
, stage
, buffers
, buffer_count
);
3208 if (nobuffer_stages
)
3209 cmd_buffer_emit_push_constant_all(cmd_buffer
, nobuffer_stages
, NULL
, 0);
3212 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
3216 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3218 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3221 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
3222 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
3223 vb_emit
|= pipeline
->vb_used
;
3225 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
3227 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->base
.l3_config
);
3229 genX(cmd_buffer_emit_hashing_mode
)(cmd_buffer
, UINT_MAX
, UINT_MAX
, 1);
3231 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3234 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
3235 const uint32_t num_dwords
= 1 + num_buffers
* 4;
3237 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
3238 GENX(3DSTATE_VERTEX_BUFFERS
));
3240 for_each_bit(vb
, vb_emit
) {
3241 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
3242 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
3244 struct GENX(VERTEX_BUFFER_STATE
) state
= {
3245 .VertexBufferIndex
= vb
,
3247 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
3249 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
3250 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
3253 .AddressModifyEnable
= true,
3254 .BufferPitch
= pipeline
->vb
[vb
].stride
,
3255 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
3258 .BufferSize
= buffer
->size
- offset
3260 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
3264 #if GEN_GEN >= 8 && GEN_GEN <= 9
3265 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(cmd_buffer
, vb
,
3266 state
.BufferStartingAddress
,
3270 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
3275 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
3278 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
3279 /* We don't need any per-buffer dirty tracking because you're not
3280 * allowed to bind different XFB buffers while XFB is enabled.
3282 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3283 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
3284 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3286 sob
.SOBufferIndex
= idx
;
3288 sob
._3DCommandOpcode
= 0;
3289 sob
._3DCommandSubOpcode
= SO_BUFFER_INDEX_0_CMD
+ idx
;
3292 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
3293 sob
.SOBufferEnable
= true;
3294 sob
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
,
3295 sob
.StreamOffsetWriteEnable
= false;
3296 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
3298 /* Size is in DWords - 1 */
3299 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
3304 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
3306 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3310 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
3311 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->base
.batch
);
3313 /* If the pipeline changed, we may need to re-allocate push constant
3316 cmd_buffer_alloc_push_constants(cmd_buffer
);
3320 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
3321 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
3322 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
3324 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
3325 * stall needs to be sent just prior to any 3DSTATE_VS,
3326 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
3327 * 3DSTATE_BINDING_TABLE_POINTER_VS,
3328 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
3329 * PIPE_CONTROL needs to be sent before any combination of VS
3330 * associated 3DSTATE."
3332 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3333 pc
.DepthStallEnable
= true;
3334 pc
.PostSyncOperation
= WriteImmediateData
;
3336 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
3341 /* Render targets live in the same binding table as fragment descriptors */
3342 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
3343 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
3345 /* We emit the binding tables and sampler tables first, then emit push
3346 * constants and then finally emit binding table and sampler table
3347 * pointers. It has to happen in this order, since emitting the binding
3348 * tables may change the push constants (in case of storage images). After
3349 * emitting push constants, on SKL+ we have to emit the corresponding
3350 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
3353 if (cmd_buffer
->state
.descriptors_dirty
) {
3354 dirty
= flush_descriptor_sets(cmd_buffer
,
3355 &cmd_buffer
->state
.gfx
.base
,
3357 ARRAY_SIZE(pipeline
->shaders
));
3360 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
3361 /* Because we're pushing UBOs, we have to push whenever either
3362 * descriptors or push constants is dirty.
3364 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
3365 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
3366 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
3370 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
3372 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
3373 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
3375 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
3376 ANV_CMD_DIRTY_PIPELINE
)) {
3377 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
3378 pipeline
->depth_clamp_enable
);
3381 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
3382 ANV_CMD_DIRTY_RENDER_TARGETS
))
3383 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
3385 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
3389 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
3390 struct anv_address addr
,
3391 uint32_t size
, uint32_t index
)
3393 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
3394 GENX(3DSTATE_VERTEX_BUFFERS
));
3396 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
3397 &(struct GENX(VERTEX_BUFFER_STATE
)) {
3398 .VertexBufferIndex
= index
,
3399 .AddressModifyEnable
= true,
3401 .MOCS
= addr
.bo
? anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
) : 0,
3402 .NullVertexBuffer
= size
== 0,
3404 .BufferStartingAddress
= addr
,
3407 .BufferStartingAddress
= addr
,
3408 .EndAddress
= anv_address_add(addr
, size
),
3412 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(cmd_buffer
,
3417 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
3418 struct anv_address addr
)
3420 emit_vertex_bo(cmd_buffer
, addr
, addr
.bo
? 8 : 0, ANV_SVGS_VB_INDEX
);
3424 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
3425 uint32_t base_vertex
, uint32_t base_instance
)
3427 if (base_vertex
== 0 && base_instance
== 0) {
3428 emit_base_vertex_instance_bo(cmd_buffer
, ANV_NULL_ADDRESS
);
3430 struct anv_state id_state
=
3431 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
3433 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
3434 ((uint32_t *)id_state
.map
)[1] = base_instance
;
3436 struct anv_address addr
= {
3437 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3438 .offset
= id_state
.offset
,
3441 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
3446 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
3448 struct anv_state state
=
3449 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
3451 ((uint32_t *)state
.map
)[0] = draw_index
;
3453 struct anv_address addr
= {
3454 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3455 .offset
= state
.offset
,
3458 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
3462 update_dirty_vbs_for_gen8_vb_flush(struct anv_cmd_buffer
*cmd_buffer
,
3463 uint32_t access_type
)
3465 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3466 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3468 uint64_t vb_used
= pipeline
->vb_used
;
3469 if (vs_prog_data
->uses_firstvertex
||
3470 vs_prog_data
->uses_baseinstance
)
3471 vb_used
|= 1ull << ANV_SVGS_VB_INDEX
;
3472 if (vs_prog_data
->uses_drawid
)
3473 vb_used
|= 1ull << ANV_DRAWID_VB_INDEX
;
3475 genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush
)(cmd_buffer
,
3476 access_type
== RANDOM
,
3481 VkCommandBuffer commandBuffer
,
3482 uint32_t vertexCount
,
3483 uint32_t instanceCount
,
3484 uint32_t firstVertex
,
3485 uint32_t firstInstance
)
3487 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3488 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3489 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3491 if (anv_batch_has_error(&cmd_buffer
->batch
))
3494 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3496 if (cmd_buffer
->state
.conditional_render_enabled
)
3497 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3499 if (vs_prog_data
->uses_firstvertex
||
3500 vs_prog_data
->uses_baseinstance
)
3501 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3502 if (vs_prog_data
->uses_drawid
)
3503 emit_draw_index(cmd_buffer
, 0);
3505 /* Emitting draw index or vertex index BOs may result in needing
3506 * additional VF cache flushes.
3508 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3510 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3511 * different views. We need to multiply instanceCount by the view count.
3513 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3515 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3516 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3517 prim
.VertexAccessType
= SEQUENTIAL
;
3518 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3519 prim
.VertexCountPerInstance
= vertexCount
;
3520 prim
.StartVertexLocation
= firstVertex
;
3521 prim
.InstanceCount
= instanceCount
;
3522 prim
.StartInstanceLocation
= firstInstance
;
3523 prim
.BaseVertexLocation
= 0;
3526 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3529 void genX(CmdDrawIndexed
)(
3530 VkCommandBuffer commandBuffer
,
3531 uint32_t indexCount
,
3532 uint32_t instanceCount
,
3533 uint32_t firstIndex
,
3534 int32_t vertexOffset
,
3535 uint32_t firstInstance
)
3537 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3538 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3539 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3541 if (anv_batch_has_error(&cmd_buffer
->batch
))
3544 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3546 if (cmd_buffer
->state
.conditional_render_enabled
)
3547 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3549 if (vs_prog_data
->uses_firstvertex
||
3550 vs_prog_data
->uses_baseinstance
)
3551 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
3552 if (vs_prog_data
->uses_drawid
)
3553 emit_draw_index(cmd_buffer
, 0);
3555 /* Emitting draw index or vertex index BOs may result in needing
3556 * additional VF cache flushes.
3558 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3560 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3561 * different views. We need to multiply instanceCount by the view count.
3563 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3565 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3566 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3567 prim
.VertexAccessType
= RANDOM
;
3568 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3569 prim
.VertexCountPerInstance
= indexCount
;
3570 prim
.StartVertexLocation
= firstIndex
;
3571 prim
.InstanceCount
= instanceCount
;
3572 prim
.StartInstanceLocation
= firstInstance
;
3573 prim
.BaseVertexLocation
= vertexOffset
;
3576 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
3579 /* Auto-Draw / Indirect Registers */
3580 #define GEN7_3DPRIM_END_OFFSET 0x2420
3581 #define GEN7_3DPRIM_START_VERTEX 0x2430
3582 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
3583 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
3584 #define GEN7_3DPRIM_START_INSTANCE 0x243C
3585 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
3587 void genX(CmdDrawIndirectByteCountEXT
)(
3588 VkCommandBuffer commandBuffer
,
3589 uint32_t instanceCount
,
3590 uint32_t firstInstance
,
3591 VkBuffer counterBuffer
,
3592 VkDeviceSize counterBufferOffset
,
3593 uint32_t counterOffset
,
3594 uint32_t vertexStride
)
3596 #if GEN_IS_HASWELL || GEN_GEN >= 8
3597 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3598 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
3599 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3600 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3602 /* firstVertex is always zero for this draw function */
3603 const uint32_t firstVertex
= 0;
3605 if (anv_batch_has_error(&cmd_buffer
->batch
))
3608 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3610 if (vs_prog_data
->uses_firstvertex
||
3611 vs_prog_data
->uses_baseinstance
)
3612 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3613 if (vs_prog_data
->uses_drawid
)
3614 emit_draw_index(cmd_buffer
, 0);
3616 /* Emitting draw index or vertex index BOs may result in needing
3617 * additional VF cache flushes.
3619 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3621 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3622 * different views. We need to multiply instanceCount by the view count.
3624 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3626 struct gen_mi_builder b
;
3627 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3628 struct gen_mi_value count
=
3629 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
3630 counterBufferOffset
));
3632 count
= gen_mi_isub(&b
, count
, gen_mi_imm(counterOffset
));
3633 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
3634 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
3636 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3637 gen_mi_imm(firstVertex
));
3638 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
3639 gen_mi_imm(instanceCount
));
3640 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3641 gen_mi_imm(firstInstance
));
3642 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3644 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3645 prim
.IndirectParameterEnable
= true;
3646 prim
.VertexAccessType
= SEQUENTIAL
;
3647 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3650 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3651 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3655 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
3656 struct anv_address addr
,
3659 struct gen_mi_builder b
;
3660 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3662 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
),
3663 gen_mi_mem32(anv_address_add(addr
, 0)));
3665 struct gen_mi_value instance_count
= gen_mi_mem32(anv_address_add(addr
, 4));
3666 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3667 if (view_count
> 1) {
3668 #if GEN_IS_HASWELL || GEN_GEN >= 8
3669 instance_count
= gen_mi_imul_imm(&b
, instance_count
, view_count
);
3671 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3672 "MI_MATH is not supported on Ivy Bridge");
3675 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
), instance_count
);
3677 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3678 gen_mi_mem32(anv_address_add(addr
, 8)));
3681 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
),
3682 gen_mi_mem32(anv_address_add(addr
, 12)));
3683 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3684 gen_mi_mem32(anv_address_add(addr
, 16)));
3686 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3687 gen_mi_mem32(anv_address_add(addr
, 12)));
3688 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3692 void genX(CmdDrawIndirect
)(
3693 VkCommandBuffer commandBuffer
,
3695 VkDeviceSize offset
,
3699 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3700 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3701 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3702 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3704 if (anv_batch_has_error(&cmd_buffer
->batch
))
3707 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3709 if (cmd_buffer
->state
.conditional_render_enabled
)
3710 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3712 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3713 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3715 if (vs_prog_data
->uses_firstvertex
||
3716 vs_prog_data
->uses_baseinstance
)
3717 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3718 if (vs_prog_data
->uses_drawid
)
3719 emit_draw_index(cmd_buffer
, i
);
3721 /* Emitting draw index or vertex index BOs may result in needing
3722 * additional VF cache flushes.
3724 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3726 load_indirect_parameters(cmd_buffer
, draw
, false);
3728 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3729 prim
.IndirectParameterEnable
= true;
3730 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3731 prim
.VertexAccessType
= SEQUENTIAL
;
3732 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3735 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3741 void genX(CmdDrawIndexedIndirect
)(
3742 VkCommandBuffer commandBuffer
,
3744 VkDeviceSize offset
,
3748 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3749 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3750 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3751 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3753 if (anv_batch_has_error(&cmd_buffer
->batch
))
3756 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3758 if (cmd_buffer
->state
.conditional_render_enabled
)
3759 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3761 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3762 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3764 /* TODO: We need to stomp base vertex to 0 somehow */
3765 if (vs_prog_data
->uses_firstvertex
||
3766 vs_prog_data
->uses_baseinstance
)
3767 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3768 if (vs_prog_data
->uses_drawid
)
3769 emit_draw_index(cmd_buffer
, i
);
3771 /* Emitting draw index or vertex index BOs may result in needing
3772 * additional VF cache flushes.
3774 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3776 load_indirect_parameters(cmd_buffer
, draw
, true);
3778 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3779 prim
.IndirectParameterEnable
= true;
3780 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3781 prim
.VertexAccessType
= RANDOM
;
3782 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3785 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
3791 #define TMP_DRAW_COUNT_REG 0x2670 /* MI_ALU_REG14 */
3794 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3795 struct anv_address count_address
,
3796 const bool conditional_render_enabled
)
3798 struct gen_mi_builder b
;
3799 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3801 if (conditional_render_enabled
) {
3802 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3803 gen_mi_store(&b
, gen_mi_reg64(TMP_DRAW_COUNT_REG
),
3804 gen_mi_mem32(count_address
));
3807 /* Upload the current draw count from the draw parameters buffer to
3808 * MI_PREDICATE_SRC0.
3810 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
3811 gen_mi_mem32(count_address
));
3813 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
+ 4), gen_mi_imm(0));
3818 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3819 uint32_t draw_index
)
3821 struct gen_mi_builder b
;
3822 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3824 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3825 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
), gen_mi_imm(draw_index
));
3827 if (draw_index
== 0) {
3828 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3829 mip
.LoadOperation
= LOAD_LOADINV
;
3830 mip
.CombineOperation
= COMBINE_SET
;
3831 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3834 /* While draw_index < draw_count the predicate's result will be
3835 * (draw_index == draw_count) ^ TRUE = TRUE
3836 * When draw_index == draw_count the result is
3837 * (TRUE) ^ TRUE = FALSE
3838 * After this all results will be:
3839 * (FALSE) ^ FALSE = FALSE
3841 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3842 mip
.LoadOperation
= LOAD_LOAD
;
3843 mip
.CombineOperation
= COMBINE_XOR
;
3844 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3849 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3851 emit_draw_count_predicate_with_conditional_render(
3852 struct anv_cmd_buffer
*cmd_buffer
,
3853 uint32_t draw_index
)
3855 struct gen_mi_builder b
;
3856 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3858 struct gen_mi_value pred
= gen_mi_ult(&b
, gen_mi_imm(draw_index
),
3859 gen_mi_reg64(TMP_DRAW_COUNT_REG
));
3860 pred
= gen_mi_iand(&b
, pred
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
));
3863 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_RESULT
), pred
);
3865 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3866 * so we emit MI_PREDICATE to set it.
3869 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), pred
);
3870 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3872 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3873 mip
.LoadOperation
= LOAD_LOADINV
;
3874 mip
.CombineOperation
= COMBINE_SET
;
3875 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3881 void genX(CmdDrawIndirectCount
)(
3882 VkCommandBuffer commandBuffer
,
3884 VkDeviceSize offset
,
3885 VkBuffer _countBuffer
,
3886 VkDeviceSize countBufferOffset
,
3887 uint32_t maxDrawCount
,
3890 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3891 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3892 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3893 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3894 struct anv_graphics_pipeline
*pipeline
= cmd_state
->gfx
.pipeline
;
3895 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3897 if (anv_batch_has_error(&cmd_buffer
->batch
))
3900 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3902 struct anv_address count_address
=
3903 anv_address_add(count_buffer
->address
, countBufferOffset
);
3905 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3906 cmd_state
->conditional_render_enabled
);
3908 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3909 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3911 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3912 if (cmd_state
->conditional_render_enabled
) {
3913 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3915 emit_draw_count_predicate(cmd_buffer
, i
);
3918 emit_draw_count_predicate(cmd_buffer
, i
);
3921 if (vs_prog_data
->uses_firstvertex
||
3922 vs_prog_data
->uses_baseinstance
)
3923 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3924 if (vs_prog_data
->uses_drawid
)
3925 emit_draw_index(cmd_buffer
, i
);
3927 /* Emitting draw index or vertex index BOs may result in needing
3928 * additional VF cache flushes.
3930 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3932 load_indirect_parameters(cmd_buffer
, draw
, false);
3934 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3935 prim
.IndirectParameterEnable
= true;
3936 prim
.PredicateEnable
= true;
3937 prim
.VertexAccessType
= SEQUENTIAL
;
3938 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3941 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3947 void genX(CmdDrawIndexedIndirectCount
)(
3948 VkCommandBuffer commandBuffer
,
3950 VkDeviceSize offset
,
3951 VkBuffer _countBuffer
,
3952 VkDeviceSize countBufferOffset
,
3953 uint32_t maxDrawCount
,
3956 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3957 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3958 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3959 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3960 struct anv_graphics_pipeline
*pipeline
= cmd_state
->gfx
.pipeline
;
3961 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3963 if (anv_batch_has_error(&cmd_buffer
->batch
))
3966 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3968 struct anv_address count_address
=
3969 anv_address_add(count_buffer
->address
, countBufferOffset
);
3971 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3972 cmd_state
->conditional_render_enabled
);
3974 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3975 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3977 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3978 if (cmd_state
->conditional_render_enabled
) {
3979 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3981 emit_draw_count_predicate(cmd_buffer
, i
);
3984 emit_draw_count_predicate(cmd_buffer
, i
);
3987 /* TODO: We need to stomp base vertex to 0 somehow */
3988 if (vs_prog_data
->uses_firstvertex
||
3989 vs_prog_data
->uses_baseinstance
)
3990 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3991 if (vs_prog_data
->uses_drawid
)
3992 emit_draw_index(cmd_buffer
, i
);
3994 /* Emitting draw index or vertex index BOs may result in needing
3995 * additional VF cache flushes.
3997 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3999 load_indirect_parameters(cmd_buffer
, draw
, true);
4001 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
4002 prim
.IndirectParameterEnable
= true;
4003 prim
.PredicateEnable
= true;
4004 prim
.VertexAccessType
= RANDOM
;
4005 prim
.PrimitiveTopologyType
= pipeline
->topology
;
4008 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
4014 void genX(CmdBeginTransformFeedbackEXT
)(
4015 VkCommandBuffer commandBuffer
,
4016 uint32_t firstCounterBuffer
,
4017 uint32_t counterBufferCount
,
4018 const VkBuffer
* pCounterBuffers
,
4019 const VkDeviceSize
* pCounterBufferOffsets
)
4021 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4023 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
4024 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
4025 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
4027 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
4029 * "Ssoftware must ensure that no HW stream output operations can be in
4030 * process or otherwise pending at the point that the MI_LOAD/STORE
4031 * commands are processed. This will likely require a pipeline flush."
4033 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4034 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4036 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
4037 /* If we have a counter buffer, this is a resume so we need to load the
4038 * value into the streamout offset register. Otherwise, this is a begin
4039 * and we need to reset it to zero.
4041 if (pCounterBuffers
&&
4042 idx
>= firstCounterBuffer
&&
4043 idx
- firstCounterBuffer
< counterBufferCount
&&
4044 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
4045 uint32_t cb_idx
= idx
- firstCounterBuffer
;
4046 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
4047 uint64_t offset
= pCounterBufferOffsets
?
4048 pCounterBufferOffsets
[cb_idx
] : 0;
4050 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4051 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
4052 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
4056 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
4057 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
4063 cmd_buffer
->state
.xfb_enabled
= true;
4064 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
4067 void genX(CmdEndTransformFeedbackEXT
)(
4068 VkCommandBuffer commandBuffer
,
4069 uint32_t firstCounterBuffer
,
4070 uint32_t counterBufferCount
,
4071 const VkBuffer
* pCounterBuffers
,
4072 const VkDeviceSize
* pCounterBufferOffsets
)
4074 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4076 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
4077 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
4078 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
4080 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
4082 * "Ssoftware must ensure that no HW stream output operations can be in
4083 * process or otherwise pending at the point that the MI_LOAD/STORE
4084 * commands are processed. This will likely require a pipeline flush."
4086 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4087 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4089 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
4090 unsigned idx
= firstCounterBuffer
+ cb_idx
;
4092 /* If we have a counter buffer, this is a resume so we need to load the
4093 * value into the streamout offset register. Otherwise, this is a begin
4094 * and we need to reset it to zero.
4096 if (pCounterBuffers
&&
4097 cb_idx
< counterBufferCount
&&
4098 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
4099 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
4100 uint64_t offset
= pCounterBufferOffsets
?
4101 pCounterBufferOffsets
[cb_idx
] : 0;
4103 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
4104 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
4106 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
4111 cmd_buffer
->state
.xfb_enabled
= false;
4112 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
4116 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
4118 struct anv_compute_pipeline
*pipeline
= cmd_buffer
->state
.compute
.pipeline
;
4120 assert(pipeline
->cs
);
4122 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->base
.l3_config
);
4124 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
4126 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
4127 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
4129 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4130 * the only bits that are changed are scoreboard related: Scoreboard
4131 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
4132 * these scoreboard related states, a MEDIA_STATE_FLUSH is
4135 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4136 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4138 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->base
.batch
);
4140 /* The workgroup size of the pipeline affects our push constant layout
4141 * so flag push constants as dirty if we change the pipeline.
4143 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4146 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
4147 cmd_buffer
->state
.compute
.pipeline_dirty
) {
4148 flush_descriptor_sets(cmd_buffer
,
4149 &cmd_buffer
->state
.compute
.base
,
4152 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
4153 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
4154 .BindingTablePointer
=
4155 cmd_buffer
->state
.binding_tables
[MESA_SHADER_COMPUTE
].offset
,
4156 .SamplerStatePointer
=
4157 cmd_buffer
->state
.samplers
[MESA_SHADER_COMPUTE
].offset
,
4159 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
4161 struct anv_state state
=
4162 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
4163 pipeline
->interface_descriptor_data
,
4164 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
4167 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4168 anv_batch_emit(&cmd_buffer
->batch
,
4169 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
4170 mid
.InterfaceDescriptorTotalLength
= size
;
4171 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
4175 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
4176 struct anv_state push_state
=
4177 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
4179 if (push_state
.alloc_size
) {
4180 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4181 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
4182 curbe
.CURBEDataStartAddress
= push_state
.offset
;
4186 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
4189 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
4191 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4197 verify_cmd_parser(const struct anv_device
*device
,
4198 int required_version
,
4199 const char *function
)
4201 if (device
->physical
->cmd_parser_version
< required_version
) {
4202 return vk_errorf(device
, device
->physical
,
4203 VK_ERROR_FEATURE_NOT_PRESENT
,
4204 "cmd parser version %d is required for %s",
4205 required_version
, function
);
4214 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
4215 uint32_t baseGroupX
,
4216 uint32_t baseGroupY
,
4217 uint32_t baseGroupZ
)
4219 if (anv_batch_has_error(&cmd_buffer
->batch
))
4222 struct anv_push_constants
*push
=
4223 &cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
4224 if (push
->cs
.base_work_group_id
[0] != baseGroupX
||
4225 push
->cs
.base_work_group_id
[1] != baseGroupY
||
4226 push
->cs
.base_work_group_id
[2] != baseGroupZ
) {
4227 push
->cs
.base_work_group_id
[0] = baseGroupX
;
4228 push
->cs
.base_work_group_id
[1] = baseGroupY
;
4229 push
->cs
.base_work_group_id
[2] = baseGroupZ
;
4231 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4235 void genX(CmdDispatch
)(
4236 VkCommandBuffer commandBuffer
,
4241 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
4244 void genX(CmdDispatchBase
)(
4245 VkCommandBuffer commandBuffer
,
4246 uint32_t baseGroupX
,
4247 uint32_t baseGroupY
,
4248 uint32_t baseGroupZ
,
4249 uint32_t groupCountX
,
4250 uint32_t groupCountY
,
4251 uint32_t groupCountZ
)
4253 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4254 struct anv_compute_pipeline
*pipeline
= cmd_buffer
->state
.compute
.pipeline
;
4255 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
4257 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
4258 baseGroupY
, baseGroupZ
);
4260 if (anv_batch_has_error(&cmd_buffer
->batch
))
4263 if (prog_data
->uses_num_work_groups
) {
4264 struct anv_state state
=
4265 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
4266 uint32_t *sizes
= state
.map
;
4267 sizes
[0] = groupCountX
;
4268 sizes
[1] = groupCountY
;
4269 sizes
[2] = groupCountZ
;
4270 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
4271 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4272 .offset
= state
.offset
,
4275 /* The num_workgroups buffer goes in the binding table */
4276 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4279 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
4281 if (cmd_buffer
->state
.conditional_render_enabled
)
4282 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
4284 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
4285 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
4286 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
4287 ggw
.ThreadDepthCounterMaximum
= 0;
4288 ggw
.ThreadHeightCounterMaximum
= 0;
4289 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
4290 ggw
.ThreadGroupIDXDimension
= groupCountX
;
4291 ggw
.ThreadGroupIDYDimension
= groupCountY
;
4292 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
4293 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
4294 ggw
.BottomExecutionMask
= 0xffffffff;
4297 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
4300 #define GPGPU_DISPATCHDIMX 0x2500
4301 #define GPGPU_DISPATCHDIMY 0x2504
4302 #define GPGPU_DISPATCHDIMZ 0x2508
4304 void genX(CmdDispatchIndirect
)(
4305 VkCommandBuffer commandBuffer
,
4307 VkDeviceSize offset
)
4309 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4310 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
4311 struct anv_compute_pipeline
*pipeline
= cmd_buffer
->state
.compute
.pipeline
;
4312 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
4313 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
4314 struct anv_batch
*batch
= &cmd_buffer
->batch
;
4316 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
4319 /* Linux 4.4 added command parser version 5 which allows the GPGPU
4320 * indirect dispatch registers to be written.
4322 if (verify_cmd_parser(cmd_buffer
->device
, 5,
4323 "vkCmdDispatchIndirect") != VK_SUCCESS
)
4327 if (prog_data
->uses_num_work_groups
) {
4328 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
4330 /* The num_workgroups buffer goes in the binding table */
4331 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4334 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
4336 struct gen_mi_builder b
;
4337 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4339 struct gen_mi_value size_x
= gen_mi_mem32(anv_address_add(addr
, 0));
4340 struct gen_mi_value size_y
= gen_mi_mem32(anv_address_add(addr
, 4));
4341 struct gen_mi_value size_z
= gen_mi_mem32(anv_address_add(addr
, 8));
4343 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMX
), size_x
);
4344 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMY
), size_y
);
4345 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMZ
), size_z
);
4348 /* predicate = (compute_dispatch_indirect_x_size == 0); */
4349 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), size_x
);
4350 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
4351 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4352 mip
.LoadOperation
= LOAD_LOAD
;
4353 mip
.CombineOperation
= COMBINE_SET
;
4354 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4357 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
4358 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_y
);
4359 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4360 mip
.LoadOperation
= LOAD_LOAD
;
4361 mip
.CombineOperation
= COMBINE_OR
;
4362 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4365 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
4366 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_z
);
4367 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4368 mip
.LoadOperation
= LOAD_LOAD
;
4369 mip
.CombineOperation
= COMBINE_OR
;
4370 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4373 /* predicate = !predicate; */
4374 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4375 mip
.LoadOperation
= LOAD_LOADINV
;
4376 mip
.CombineOperation
= COMBINE_OR
;
4377 mip
.CompareOperation
= COMPARE_FALSE
;
4381 if (cmd_buffer
->state
.conditional_render_enabled
) {
4382 /* predicate &= !(conditional_rendering_predicate == 0); */
4383 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
),
4384 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
4385 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4386 mip
.LoadOperation
= LOAD_LOADINV
;
4387 mip
.CombineOperation
= COMBINE_AND
;
4388 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4393 #else /* GEN_GEN > 7 */
4394 if (cmd_buffer
->state
.conditional_render_enabled
)
4395 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
4398 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
4399 ggw
.IndirectParameterEnable
= true;
4400 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
4401 cmd_buffer
->state
.conditional_render_enabled
;
4402 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
4403 ggw
.ThreadDepthCounterMaximum
= 0;
4404 ggw
.ThreadHeightCounterMaximum
= 0;
4405 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
4406 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
4407 ggw
.BottomExecutionMask
= 0xffffffff;
4410 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
4414 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
4417 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4419 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
4422 #if GEN_GEN >= 8 && GEN_GEN < 10
4423 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
4425 * Software must clear the COLOR_CALC_STATE Valid field in
4426 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
4427 * with Pipeline Select set to GPGPU.
4429 * The internal hardware docs recommend the same workaround for Gen9
4432 if (pipeline
== GPGPU
)
4433 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
4437 if (pipeline
== _3D
) {
4438 /* There is a mid-object preemption workaround which requires you to
4439 * re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D. However,
4440 * even without preemption, we have issues with geometry flickering when
4441 * GPGPU and 3D are back-to-back and this seems to fix it. We don't
4444 const uint32_t subslices
=
4445 MAX2(cmd_buffer
->device
->physical
->subslice_total
, 1);
4446 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
4447 vfe
.MaximumNumberofThreads
=
4448 devinfo
->max_cs_threads
* subslices
- 1;
4449 vfe
.NumberofURBEntries
= 2;
4450 vfe
.URBEntryAllocationSize
= 2;
4453 /* We just emitted a dummy MEDIA_VFE_STATE so now that packet is
4454 * invalid. Set the compute pipeline to dirty to force a re-emit of the
4455 * pipeline in case we get back-to-back dispatch calls with the same
4456 * pipeline and a PIPELINE_SELECT in between.
4458 cmd_buffer
->state
.compute
.pipeline_dirty
= true;
4462 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
4463 * PIPELINE_SELECT [DevBWR+]":
4467 * Software must ensure all the write caches are flushed through a
4468 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
4469 * command to invalidate read only caches prior to programming
4470 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
4472 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4473 pc
.RenderTargetCacheFlushEnable
= true;
4474 pc
.DepthCacheFlushEnable
= true;
4475 pc
.DCFlushEnable
= true;
4476 pc
.PostSyncOperation
= NoWrite
;
4477 pc
.CommandStreamerStallEnable
= true;
4479 pc
.TileCacheFlushEnable
= true;
4481 /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must be
4482 * set with any PIPE_CONTROL with Depth Flush Enable bit set.
4484 pc
.DepthStallEnable
= true;
4488 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4489 pc
.TextureCacheInvalidationEnable
= true;
4490 pc
.ConstantCacheInvalidationEnable
= true;
4491 pc
.StateCacheInvalidationEnable
= true;
4492 pc
.InstructionCacheInvalidateEnable
= true;
4493 pc
.PostSyncOperation
= NoWrite
;
4495 pc
.TileCacheFlushEnable
= true;
4499 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
4503 ps
.PipelineSelection
= pipeline
;
4507 if (devinfo
->is_geminilake
) {
4510 * "This chicken bit works around a hardware issue with barrier logic
4511 * encountered when switching between GPGPU and 3D pipelines. To
4512 * workaround the issue, this mode bit should be set after a pipeline
4516 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
4518 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
4519 : GLK_BARRIER_MODE_3D_HULL
,
4520 .GLKBarrierModeMask
= 1);
4521 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
4525 cmd_buffer
->state
.current_pipeline
= pipeline
;
4529 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
4531 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
4535 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
4537 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
4541 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
4546 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
4548 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
4549 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
4550 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
4551 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
4552 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
4553 * Depth Flush Bit set, followed by another pipelined depth stall
4554 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
4555 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
4556 * via a preceding MI_FLUSH)."
4558 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4559 pipe
.DepthStallEnable
= true;
4561 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4562 pipe
.DepthCacheFlushEnable
= true;
4564 pipe
.TileCacheFlushEnable
= true;
4567 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4568 pipe
.DepthStallEnable
= true;
4572 /* From the Skylake PRM, 3DSTATE_VERTEX_BUFFERS:
4574 * "The VF cache needs to be invalidated before binding and then using
4575 * Vertex Buffers that overlap with any previously bound Vertex Buffer
4576 * (at a 64B granularity) since the last invalidation. A VF cache
4577 * invalidate is performed by setting the "VF Cache Invalidation Enable"
4578 * bit in PIPE_CONTROL."
4580 * This is implemented by carefully tracking all vertex and index buffer
4581 * bindings and flushing if the cache ever ends up with a range in the cache
4582 * that would exceed 4 GiB. This is implemented in three parts:
4584 * 1. genX(cmd_buffer_set_binding_for_gen8_vb_flush)() which must be called
4585 * every time a 3DSTATE_VERTEX_BUFFER packet is emitted and informs the
4586 * tracking code of the new binding. If this new binding would cause
4587 * the cache to have a too-large range on the next draw call, a pipeline
4588 * stall and VF cache invalidate are added to pending_pipeline_bits.
4590 * 2. genX(cmd_buffer_apply_pipe_flushes)() resets the cache tracking to
4591 * empty whenever we emit a VF invalidate.
4593 * 3. genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush)() must be called
4594 * after every 3DPRIMITIVE and copies the bound range into the dirty
4595 * range for each used buffer. This has to be a separate step because
4596 * we don't always re-bind all buffers and so 1. can't know which
4597 * buffers are actually bound.
4600 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(struct anv_cmd_buffer
*cmd_buffer
,
4602 struct anv_address vb_address
,
4605 if (GEN_GEN
< 8 || GEN_GEN
> 9 ||
4606 !cmd_buffer
->device
->physical
->use_softpin
)
4609 struct anv_vb_cache_range
*bound
, *dirty
;
4610 if (vb_index
== -1) {
4611 bound
= &cmd_buffer
->state
.gfx
.ib_bound_range
;
4612 dirty
= &cmd_buffer
->state
.gfx
.ib_dirty_range
;
4614 assert(vb_index
>= 0);
4615 assert(vb_index
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_bound_ranges
));
4616 assert(vb_index
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
4617 bound
= &cmd_buffer
->state
.gfx
.vb_bound_ranges
[vb_index
];
4618 dirty
= &cmd_buffer
->state
.gfx
.vb_dirty_ranges
[vb_index
];
4627 assert(vb_address
.bo
&& (vb_address
.bo
->flags
& EXEC_OBJECT_PINNED
));
4628 bound
->start
= gen_48b_address(anv_address_physical(vb_address
));
4629 bound
->end
= bound
->start
+ vb_size
;
4630 assert(bound
->end
> bound
->start
); /* No overflow */
4632 /* Align everything to a cache line */
4633 bound
->start
&= ~(64ull - 1ull);
4634 bound
->end
= align_u64(bound
->end
, 64);
4636 /* Compute the dirty range */
4637 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4638 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4640 /* If our range is larger than 32 bits, we have to flush */
4641 assert(bound
->end
- bound
->start
<= (1ull << 32));
4642 if (dirty
->end
- dirty
->start
> (1ull << 32)) {
4643 cmd_buffer
->state
.pending_pipe_bits
|=
4644 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
4649 genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush
)(struct anv_cmd_buffer
*cmd_buffer
,
4650 uint32_t access_type
,
4653 if (GEN_GEN
< 8 || GEN_GEN
> 9 ||
4654 !cmd_buffer
->device
->physical
->use_softpin
)
4657 if (access_type
== RANDOM
) {
4658 /* We have an index buffer */
4659 struct anv_vb_cache_range
*bound
= &cmd_buffer
->state
.gfx
.ib_bound_range
;
4660 struct anv_vb_cache_range
*dirty
= &cmd_buffer
->state
.gfx
.ib_dirty_range
;
4662 if (bound
->end
> bound
->start
) {
4663 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4664 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4668 uint64_t mask
= vb_used
;
4670 int i
= u_bit_scan64(&mask
);
4672 assert(i
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_bound_ranges
));
4673 assert(i
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
4675 struct anv_vb_cache_range
*bound
, *dirty
;
4676 bound
= &cmd_buffer
->state
.gfx
.vb_bound_ranges
[i
];
4677 dirty
= &cmd_buffer
->state
.gfx
.vb_dirty_ranges
[i
];
4679 if (bound
->end
> bound
->start
) {
4680 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4681 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4687 * Update the pixel hashing modes that determine the balancing of PS threads
4688 * across subslices and slices.
4690 * \param width Width bound of the rendering area (already scaled down if \p
4691 * scale is greater than 1).
4692 * \param height Height bound of the rendering area (already scaled down if \p
4693 * scale is greater than 1).
4694 * \param scale The number of framebuffer samples that could potentially be
4695 * affected by an individual channel of the PS thread. This is
4696 * typically one for single-sampled rendering, but for operations
4697 * like CCS resolves and fast clears a single PS invocation may
4698 * update a huge number of pixels, in which case a finer
4699 * balancing is desirable in order to maximally utilize the
4700 * bandwidth available. UINT_MAX can be used as shorthand for
4701 * "finest hashing mode available".
4704 genX(cmd_buffer_emit_hashing_mode
)(struct anv_cmd_buffer
*cmd_buffer
,
4705 unsigned width
, unsigned height
,
4709 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4710 const unsigned slice_hashing
[] = {
4711 /* Because all Gen9 platforms with more than one slice require
4712 * three-way subslice hashing, a single "normal" 16x16 slice hashing
4713 * block is guaranteed to suffer from substantial imbalance, with one
4714 * subslice receiving twice as much work as the other two in the
4717 * The performance impact of that would be particularly severe when
4718 * three-way hashing is also in use for slice balancing (which is the
4719 * case for all Gen9 GT4 platforms), because one of the slices
4720 * receives one every three 16x16 blocks in either direction, which
4721 * is roughly the periodicity of the underlying subslice imbalance
4722 * pattern ("roughly" because in reality the hardware's
4723 * implementation of three-way hashing doesn't do exact modulo 3
4724 * arithmetic, which somewhat decreases the magnitude of this effect
4725 * in practice). This leads to a systematic subslice imbalance
4726 * within that slice regardless of the size of the primitive. The
4727 * 32x32 hashing mode guarantees that the subslice imbalance within a
4728 * single slice hashing block is minimal, largely eliminating this
4732 /* Finest slice hashing mode available. */
4735 const unsigned subslice_hashing
[] = {
4736 /* 16x16 would provide a slight cache locality benefit especially
4737 * visible in the sampler L1 cache efficiency of low-bandwidth
4738 * non-LLC platforms, but it comes at the cost of greater subslice
4739 * imbalance for primitives of dimensions approximately intermediate
4740 * between 16x4 and 16x16.
4743 /* Finest subslice hashing mode available. */
4746 /* Dimensions of the smallest hashing block of a given hashing mode. If
4747 * the rendering area is smaller than this there can't possibly be any
4748 * benefit from switching to this mode, so we optimize out the
4751 const unsigned min_size
[][2] = {
4755 const unsigned idx
= scale
> 1;
4757 if (cmd_buffer
->state
.current_hash_scale
!= scale
&&
4758 (width
> min_size
[idx
][0] || height
> min_size
[idx
][1])) {
4761 anv_pack_struct(>_mode
, GENX(GT_MODE
),
4762 .SliceHashing
= (devinfo
->num_slices
> 1 ? slice_hashing
[idx
] : 0),
4763 .SliceHashingMask
= (devinfo
->num_slices
> 1 ? -1 : 0),
4764 .SubsliceHashing
= subslice_hashing
[idx
],
4765 .SubsliceHashingMask
= -1);
4767 cmd_buffer
->state
.pending_pipe_bits
|=
4768 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
4769 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4771 emit_lri(&cmd_buffer
->batch
, GENX(GT_MODE_num
), gt_mode
);
4773 cmd_buffer
->state
.current_hash_scale
= scale
;
4779 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
4781 struct anv_device
*device
= cmd_buffer
->device
;
4782 const struct anv_image_view
*iview
=
4783 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
4784 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
4786 /* FIXME: Width and Height are wrong */
4788 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
4790 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
4791 device
->isl_dev
.ds
.size
/ 4);
4795 struct isl_depth_stencil_hiz_emit_info info
= { };
4798 info
.view
= &iview
->planes
[0].isl
;
4800 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
4801 uint32_t depth_plane
=
4802 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
4803 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
4805 info
.depth_surf
= &surface
->isl
;
4807 info
.depth_address
=
4808 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4809 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
4810 image
->planes
[depth_plane
].address
.bo
,
4811 image
->planes
[depth_plane
].address
.offset
+
4814 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
4817 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
4818 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
4819 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
4820 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
4823 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4824 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
4825 image
->planes
[depth_plane
].address
.bo
,
4826 image
->planes
[depth_plane
].address
.offset
+
4827 image
->planes
[depth_plane
].aux_surface
.offset
);
4829 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
4833 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4834 uint32_t stencil_plane
=
4835 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
4836 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
4838 info
.stencil_surf
= &surface
->isl
;
4840 info
.stencil_address
=
4841 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4842 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
4843 image
->planes
[stencil_plane
].address
.bo
,
4844 image
->planes
[stencil_plane
].address
.offset
+
4847 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
4850 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
4852 if (GEN_GEN
>= 12) {
4853 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
4854 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4856 /* GEN:BUG:1408224581
4858 * Workaround: Gen12LP Astep only An additional pipe control with
4859 * post-sync = store dword operation would be required.( w/a is to
4860 * have an additional pipe control after the stencil state whenever
4861 * the surface state bits of this state is changing).
4863 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4864 pc
.PostSyncOperation
= WriteImmediateData
;
4866 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
4869 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
4873 * This ANDs the view mask of the current subpass with the pending clear
4874 * views in the attachment to get the mask of views active in the subpass
4875 * that still need to be cleared.
4877 static inline uint32_t
4878 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
4879 const struct anv_attachment_state
*att_state
)
4881 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
4885 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
4886 const struct anv_attachment_state
*att_state
)
4888 if (!cmd_state
->subpass
->view_mask
)
4891 uint32_t pending_clear_mask
=
4892 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4894 return pending_clear_mask
& 1;
4898 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
4901 const uint32_t last_subpass_idx
=
4902 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
4903 const struct anv_subpass
*last_subpass
=
4904 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
4905 return last_subpass
== cmd_state
->subpass
;
4909 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
4910 uint32_t subpass_id
)
4912 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4913 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
4914 cmd_state
->subpass
= subpass
;
4916 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
4918 /* Our implementation of VK_KHR_multiview uses instancing to draw the
4919 * different views. If the client asks for instancing, we need to use the
4920 * Instance Data Step Rate to ensure that we repeat the client's
4921 * per-instance data once for each view. Since this bit is in
4922 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
4926 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
4928 /* It is possible to start a render pass with an old pipeline. Because the
4929 * render pass and subpass index are both baked into the pipeline, this is
4930 * highly unlikely. In order to do so, it requires that you have a render
4931 * pass with a single subpass and that you use that render pass twice
4932 * back-to-back and use the same pipeline at the start of the second render
4933 * pass as at the end of the first. In order to avoid unpredictable issues
4934 * with this edge case, we just dirty the pipeline at the start of every
4937 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
4939 /* Accumulate any subpass flushes that need to happen before the subpass */
4940 cmd_buffer
->state
.pending_pipe_bits
|=
4941 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
4943 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4944 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4946 bool is_multiview
= subpass
->view_mask
!= 0;
4948 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4949 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4950 if (a
== VK_ATTACHMENT_UNUSED
)
4953 assert(a
< cmd_state
->pass
->attachment_count
);
4954 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4956 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
4957 const struct anv_image
*image
= iview
->image
;
4959 /* A resolve is necessary before use as an input attachment if the clear
4960 * color or auxiliary buffer usage isn't supported by the sampler.
4962 const bool input_needs_resolve
=
4963 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
4964 att_state
->input_aux_usage
!= att_state
->aux_usage
;
4966 VkImageLayout target_layout
;
4967 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
4968 !input_needs_resolve
) {
4969 /* Layout transitions before the final only help to enable sampling
4970 * as an input attachment. If the input attachment supports sampling
4971 * using the auxiliary surface, we can skip such transitions by
4972 * making the target layout one that is CCS-aware.
4974 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
4976 target_layout
= subpass
->attachments
[i
].layout
;
4979 VkImageLayout target_stencil_layout
=
4980 subpass
->attachments
[i
].stencil_layout
;
4982 uint32_t base_layer
, layer_count
;
4983 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4985 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4986 iview
->planes
[0].isl
.base_level
);
4988 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4989 layer_count
= fb
->layers
;
4992 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4993 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4994 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4995 iview
->planes
[0].isl
.base_level
, 1,
4996 base_layer
, layer_count
,
4997 att_state
->current_layout
, target_layout
);
5000 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5001 transition_depth_buffer(cmd_buffer
, image
,
5002 att_state
->current_layout
, target_layout
);
5003 att_state
->aux_usage
=
5004 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
5005 VK_IMAGE_ASPECT_DEPTH_BIT
,
5006 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
5010 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5011 transition_stencil_buffer(cmd_buffer
, image
,
5012 iview
->planes
[0].isl
.base_level
, 1,
5013 base_layer
, layer_count
,
5014 att_state
->current_stencil_layout
,
5015 target_stencil_layout
);
5017 att_state
->current_layout
= target_layout
;
5018 att_state
->current_stencil_layout
= target_stencil_layout
;
5020 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
5021 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5023 /* Multi-planar images are not supported as attachments */
5024 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5025 assert(image
->n_planes
== 1);
5027 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
5028 uint32_t clear_layer_count
= fb
->layers
;
5030 if (att_state
->fast_clear
&&
5031 do_first_layer_clear(cmd_state
, att_state
)) {
5032 /* We only support fast-clears on the first layer */
5033 assert(iview
->planes
[0].isl
.base_level
== 0);
5034 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
5036 union isl_color_value clear_color
= {};
5037 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
5038 if (iview
->image
->samples
== 1) {
5039 anv_image_ccs_op(cmd_buffer
, image
,
5040 iview
->planes
[0].isl
.format
,
5041 VK_IMAGE_ASPECT_COLOR_BIT
,
5042 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
5046 anv_image_mcs_op(cmd_buffer
, image
,
5047 iview
->planes
[0].isl
.format
,
5048 VK_IMAGE_ASPECT_COLOR_BIT
,
5049 0, 1, ISL_AUX_OP_FAST_CLEAR
,
5054 clear_layer_count
--;
5056 att_state
->pending_clear_views
&= ~1;
5058 if (att_state
->clear_color_is_zero
) {
5059 /* This image has the auxiliary buffer enabled. We can mark the
5060 * subresource as not needing a resolve because the clear color
5061 * will match what's in every RENDER_SURFACE_STATE object when
5062 * it's being used for sampling.
5064 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
5065 VK_IMAGE_ASPECT_COLOR_BIT
,
5066 ANV_FAST_CLEAR_DEFAULT_VALUE
);
5068 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
5069 VK_IMAGE_ASPECT_COLOR_BIT
,
5070 ANV_FAST_CLEAR_ANY
);
5074 /* From the VkFramebufferCreateInfo spec:
5076 * "If the render pass uses multiview, then layers must be one and each
5077 * attachment requires a number of layers that is greater than the
5078 * maximum bit index set in the view mask in the subpasses in which it
5081 * So if multiview is active we ignore the number of layers in the
5082 * framebuffer and instead we honor the view mask from the subpass.
5085 assert(image
->n_planes
== 1);
5086 uint32_t pending_clear_mask
=
5087 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
5090 for_each_bit(layer_idx
, pending_clear_mask
) {
5092 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
5094 anv_image_clear_color(cmd_buffer
, image
,
5095 VK_IMAGE_ASPECT_COLOR_BIT
,
5096 att_state
->aux_usage
,
5097 iview
->planes
[0].isl
.format
,
5098 iview
->planes
[0].isl
.swizzle
,
5099 iview
->planes
[0].isl
.base_level
,
5102 vk_to_isl_color(att_state
->clear_value
.color
));
5105 att_state
->pending_clear_views
&= ~pending_clear_mask
;
5106 } else if (clear_layer_count
> 0) {
5107 assert(image
->n_planes
== 1);
5108 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5109 att_state
->aux_usage
,
5110 iview
->planes
[0].isl
.format
,
5111 iview
->planes
[0].isl
.swizzle
,
5112 iview
->planes
[0].isl
.base_level
,
5113 base_clear_layer
, clear_layer_count
,
5115 vk_to_isl_color(att_state
->clear_value
.color
));
5117 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
5118 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
5119 if (att_state
->fast_clear
&& !is_multiview
) {
5120 /* We currently only support HiZ for single-layer images */
5121 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5122 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
5123 assert(iview
->planes
[0].isl
.base_level
== 0);
5124 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
5125 assert(fb
->layers
== 1);
5128 anv_image_hiz_clear(cmd_buffer
, image
,
5129 att_state
->pending_clear_aspects
,
5130 iview
->planes
[0].isl
.base_level
,
5131 iview
->planes
[0].isl
.base_array_layer
,
5132 fb
->layers
, render_area
,
5133 att_state
->clear_value
.depthStencil
.stencil
);
5134 } else if (is_multiview
) {
5135 uint32_t pending_clear_mask
=
5136 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
5139 for_each_bit(layer_idx
, pending_clear_mask
) {
5141 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
5143 anv_image_clear_depth_stencil(cmd_buffer
, image
,
5144 att_state
->pending_clear_aspects
,
5145 att_state
->aux_usage
,
5146 iview
->planes
[0].isl
.base_level
,
5149 att_state
->clear_value
.depthStencil
.depth
,
5150 att_state
->clear_value
.depthStencil
.stencil
);
5153 att_state
->pending_clear_views
&= ~pending_clear_mask
;
5155 anv_image_clear_depth_stencil(cmd_buffer
, image
,
5156 att_state
->pending_clear_aspects
,
5157 att_state
->aux_usage
,
5158 iview
->planes
[0].isl
.base_level
,
5159 iview
->planes
[0].isl
.base_array_layer
,
5160 fb
->layers
, render_area
,
5161 att_state
->clear_value
.depthStencil
.depth
,
5162 att_state
->clear_value
.depthStencil
.stencil
);
5165 assert(att_state
->pending_clear_aspects
== 0);
5169 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
5170 image
->planes
[0].aux_usage
!= ISL_AUX_USAGE_NONE
&&
5171 iview
->planes
[0].isl
.base_level
== 0 &&
5172 iview
->planes
[0].isl
.base_array_layer
== 0) {
5173 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
5174 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
5175 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5176 false /* copy to ss */);
5179 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
5180 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
5181 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
5182 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5183 false /* copy to ss */);
5187 if (subpass
->attachments
[i
].usage
==
5188 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
5189 /* We assume that if we're starting a subpass, we're going to do some
5190 * rendering so we may end up with compressed data.
5192 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
5193 VK_IMAGE_ASPECT_COLOR_BIT
,
5194 att_state
->aux_usage
,
5195 iview
->planes
[0].isl
.base_level
,
5196 iview
->planes
[0].isl
.base_array_layer
,
5198 } else if (subpass
->attachments
[i
].usage
==
5199 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
5200 /* We may be writing depth or stencil so we need to mark the surface.
5201 * Unfortunately, there's no way to know at this point whether the
5202 * depth or stencil tests used will actually write to the surface.
5204 * Even though stencil may be plane 1, it always shares a base_level
5207 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
5208 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5209 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
5210 VK_IMAGE_ASPECT_DEPTH_BIT
,
5211 att_state
->aux_usage
,
5212 ds_view
->base_level
,
5213 ds_view
->base_array_layer
,
5216 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5217 /* Even though stencil may be plane 1, it always shares a
5218 * base_level with depth.
5220 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
5221 VK_IMAGE_ASPECT_STENCIL_BIT
,
5223 ds_view
->base_level
,
5224 ds_view
->base_array_layer
,
5229 /* If multiview is enabled, then we are only done clearing when we no
5230 * longer have pending layers to clear, or when we have processed the
5231 * last subpass that uses this attachment.
5233 if (!is_multiview
||
5234 att_state
->pending_clear_views
== 0 ||
5235 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
5236 att_state
->pending_clear_aspects
= 0;
5239 att_state
->pending_load_aspects
= 0;
5243 /* The PIPE_CONTROL command description says:
5245 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
5246 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
5247 * Target Cache Flush by enabling this bit. When render target flush
5248 * is set due to new association of BTI, PS Scoreboard Stall bit must
5249 * be set in this packet."
5251 cmd_buffer
->state
.pending_pipe_bits
|=
5252 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
|
5253 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
5257 /* GEN:BUG:14010455700
5259 * ISL will change some CHICKEN registers depending on the depth surface
5260 * format, along with emitting the depth and stencil packets. In that case,
5261 * we want to do a depth flush and stall, so the pipeline is not using these
5262 * settings while we change the registers.
5264 cmd_buffer
->state
.pending_pipe_bits
|=
5265 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
|
5266 ANV_PIPE_DEPTH_STALL_BIT
|
5267 ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
5268 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5271 cmd_buffer_emit_depth_stencil(cmd_buffer
);
5274 static enum blorp_filter
5275 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
5278 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
5279 return BLORP_FILTER_SAMPLE_0
;
5280 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
5281 return BLORP_FILTER_AVERAGE
;
5282 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
5283 return BLORP_FILTER_MIN_SAMPLE
;
5284 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
5285 return BLORP_FILTER_MAX_SAMPLE
;
5287 return BLORP_FILTER_NONE
;
5292 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
5294 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5295 struct anv_subpass
*subpass
= cmd_state
->subpass
;
5296 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
5297 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
5299 if (subpass
->has_color_resolve
) {
5300 /* We are about to do some MSAA resolves. We need to flush so that the
5301 * result of writes to the MSAA color attachments show up in the sampler
5302 * when we blit to the single-sampled resolve target.
5304 cmd_buffer
->state
.pending_pipe_bits
|=
5305 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
5306 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
5308 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
5309 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
5310 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
5312 if (dst_att
== VK_ATTACHMENT_UNUSED
)
5315 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
5316 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
5318 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
5319 /* From the Vulkan 1.0 spec:
5321 * If the first use of an attachment in a render pass is as a
5322 * resolve attachment, then the loadOp is effectively ignored
5323 * as the resolve is guaranteed to overwrite all pixels in the
5326 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
5329 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
5330 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
5332 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
5334 enum isl_aux_usage src_aux_usage
=
5335 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
5336 enum isl_aux_usage dst_aux_usage
=
5337 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
5339 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
5340 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
5342 anv_image_msaa_resolve(cmd_buffer
,
5343 src_iview
->image
, src_aux_usage
,
5344 src_iview
->planes
[0].isl
.base_level
,
5345 src_iview
->planes
[0].isl
.base_array_layer
,
5346 dst_iview
->image
, dst_aux_usage
,
5347 dst_iview
->planes
[0].isl
.base_level
,
5348 dst_iview
->planes
[0].isl
.base_array_layer
,
5349 VK_IMAGE_ASPECT_COLOR_BIT
,
5350 render_area
.offset
.x
, render_area
.offset
.y
,
5351 render_area
.offset
.x
, render_area
.offset
.y
,
5352 render_area
.extent
.width
,
5353 render_area
.extent
.height
,
5354 fb
->layers
, BLORP_FILTER_NONE
);
5358 if (subpass
->ds_resolve_attachment
) {
5359 /* We are about to do some MSAA resolves. We need to flush so that the
5360 * result of writes to the MSAA depth attachments show up in the sampler
5361 * when we blit to the single-sampled resolve target.
5363 cmd_buffer
->state
.pending_pipe_bits
|=
5364 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
5365 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
5367 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
5368 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
5370 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
5371 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
5373 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
5374 /* From the Vulkan 1.0 spec:
5376 * If the first use of an attachment in a render pass is as a
5377 * resolve attachment, then the loadOp is effectively ignored
5378 * as the resolve is guaranteed to overwrite all pixels in the
5381 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
5384 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
5385 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
5387 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
5389 struct anv_attachment_state
*src_state
=
5390 &cmd_state
->attachments
[src_att
];
5391 struct anv_attachment_state
*dst_state
=
5392 &cmd_state
->attachments
[dst_att
];
5394 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
5395 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
5397 /* MSAA resolves sample from the source attachment. Transition the
5398 * depth attachment first to get rid of any HiZ that we may not be
5401 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
5402 src_state
->current_layout
,
5403 VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
);
5404 src_state
->aux_usage
=
5405 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
5406 VK_IMAGE_ASPECT_DEPTH_BIT
,
5407 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
,
5408 VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
);
5409 src_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
;
5411 /* MSAA resolves write to the resolve attachment as if it were any
5412 * other transfer op. Transition the resolve attachment accordingly.
5414 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
5416 /* If our render area is the entire size of the image, we're going to
5417 * blow it all away so we can claim the initial layout is UNDEFINED
5418 * and we'll get a HiZ ambiguate instead of a resolve.
5420 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
5421 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
5422 render_area
.extent
.width
== dst_iview
->extent
.width
&&
5423 render_area
.extent
.height
== dst_iview
->extent
.height
)
5424 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
5426 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
5428 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
5429 dst_state
->aux_usage
=
5430 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
5431 VK_IMAGE_ASPECT_DEPTH_BIT
,
5432 VK_IMAGE_USAGE_TRANSFER_DST_BIT
,
5433 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
5434 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
5436 enum blorp_filter filter
=
5437 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
5439 anv_image_msaa_resolve(cmd_buffer
,
5440 src_iview
->image
, src_state
->aux_usage
,
5441 src_iview
->planes
[0].isl
.base_level
,
5442 src_iview
->planes
[0].isl
.base_array_layer
,
5443 dst_iview
->image
, dst_state
->aux_usage
,
5444 dst_iview
->planes
[0].isl
.base_level
,
5445 dst_iview
->planes
[0].isl
.base_array_layer
,
5446 VK_IMAGE_ASPECT_DEPTH_BIT
,
5447 render_area
.offset
.x
, render_area
.offset
.y
,
5448 render_area
.offset
.x
, render_area
.offset
.y
,
5449 render_area
.extent
.width
,
5450 render_area
.extent
.height
,
5451 fb
->layers
, filter
);
5454 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
5455 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
5457 src_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
;
5458 dst_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
5460 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
5461 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
5463 enum blorp_filter filter
=
5464 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
5466 anv_image_msaa_resolve(cmd_buffer
,
5467 src_iview
->image
, src_aux_usage
,
5468 src_iview
->planes
[0].isl
.base_level
,
5469 src_iview
->planes
[0].isl
.base_array_layer
,
5470 dst_iview
->image
, dst_aux_usage
,
5471 dst_iview
->planes
[0].isl
.base_level
,
5472 dst_iview
->planes
[0].isl
.base_array_layer
,
5473 VK_IMAGE_ASPECT_STENCIL_BIT
,
5474 render_area
.offset
.x
, render_area
.offset
.y
,
5475 render_area
.offset
.x
, render_area
.offset
.y
,
5476 render_area
.extent
.width
,
5477 render_area
.extent
.height
,
5478 fb
->layers
, filter
);
5483 /* On gen7, we have to store a texturable version of the stencil buffer in
5484 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
5485 * forth at strategic points. Stencil writes are only allowed in following
5488 * - VK_IMAGE_LAYOUT_GENERAL
5489 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
5490 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
5491 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
5492 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
5494 * For general, we have no nice opportunity to transition so we do the copy
5495 * to the shadow unconditionally at the end of the subpass. For transfer
5496 * destinations, we can update it as part of the transfer op. For the other
5497 * layouts, we delay the copy until a transition into some other layout.
5499 if (subpass
->depth_stencil_attachment
) {
5500 uint32_t a
= subpass
->depth_stencil_attachment
->attachment
;
5501 assert(a
!= VK_ATTACHMENT_UNUSED
);
5503 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5504 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;;
5505 const struct anv_image
*image
= iview
->image
;
5507 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5508 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
5509 VK_IMAGE_ASPECT_STENCIL_BIT
);
5511 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
5512 att_state
->current_stencil_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
5513 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
5514 anv_image_copy_to_shadow(cmd_buffer
, image
,
5515 VK_IMAGE_ASPECT_STENCIL_BIT
,
5516 iview
->planes
[plane
].isl
.base_level
, 1,
5517 iview
->planes
[plane
].isl
.base_array_layer
,
5522 #endif /* GEN_GEN == 7 */
5524 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5525 const uint32_t a
= subpass
->attachments
[i
].attachment
;
5526 if (a
== VK_ATTACHMENT_UNUSED
)
5529 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
5532 assert(a
< cmd_state
->pass
->attachment_count
);
5533 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5534 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
5535 const struct anv_image
*image
= iview
->image
;
5537 if ((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
5538 image
->vk_format
!= iview
->vk_format
) {
5539 enum anv_fast_clear_type fast_clear_type
=
5540 anv_layout_to_fast_clear_type(&cmd_buffer
->device
->info
,
5541 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5542 att_state
->current_layout
);
5544 /* If any clear color was used, flush it down the aux surfaces. If we
5545 * don't do it now using the view's format we might use the clear
5546 * color incorrectly in the following resolves (for example with an
5547 * SRGB view & a UNORM image).
5549 if (fast_clear_type
!= ANV_FAST_CLEAR_NONE
) {
5550 anv_perf_warn(cmd_buffer
->device
, iview
,
5551 "Doing a partial resolve to get rid of clear color at the "
5552 "end of a renderpass due to an image/view format mismatch");
5554 uint32_t base_layer
, layer_count
;
5555 if (image
->type
== VK_IMAGE_TYPE_3D
) {
5557 layer_count
= anv_minify(iview
->image
->extent
.depth
,
5558 iview
->planes
[0].isl
.base_level
);
5560 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
5561 layer_count
= fb
->layers
;
5564 for (uint32_t a
= 0; a
< layer_count
; a
++) {
5565 uint32_t array_layer
= base_layer
+ a
;
5566 if (image
->samples
== 1) {
5567 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
5568 iview
->planes
[0].isl
.format
,
5569 VK_IMAGE_ASPECT_COLOR_BIT
,
5570 iview
->planes
[0].isl
.base_level
,
5572 ISL_AUX_OP_PARTIAL_RESOLVE
,
5573 ANV_FAST_CLEAR_NONE
);
5575 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
5576 iview
->planes
[0].isl
.format
,
5577 VK_IMAGE_ASPECT_COLOR_BIT
,
5579 ISL_AUX_OP_PARTIAL_RESOLVE
,
5580 ANV_FAST_CLEAR_NONE
);
5586 /* Transition the image into the final layout for this render pass */
5587 VkImageLayout target_layout
=
5588 cmd_state
->pass
->attachments
[a
].final_layout
;
5589 VkImageLayout target_stencil_layout
=
5590 cmd_state
->pass
->attachments
[a
].stencil_final_layout
;
5592 uint32_t base_layer
, layer_count
;
5593 if (image
->type
== VK_IMAGE_TYPE_3D
) {
5595 layer_count
= anv_minify(iview
->image
->extent
.depth
,
5596 iview
->planes
[0].isl
.base_level
);
5598 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
5599 layer_count
= fb
->layers
;
5602 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
5603 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5604 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5605 iview
->planes
[0].isl
.base_level
, 1,
5606 base_layer
, layer_count
,
5607 att_state
->current_layout
, target_layout
);
5610 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5611 transition_depth_buffer(cmd_buffer
, image
,
5612 att_state
->current_layout
, target_layout
);
5615 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5616 transition_stencil_buffer(cmd_buffer
, image
,
5617 iview
->planes
[0].isl
.base_level
, 1,
5618 base_layer
, layer_count
,
5619 att_state
->current_stencil_layout
,
5620 target_stencil_layout
);
5624 /* Accumulate any subpass flushes that need to happen after the subpass.
5625 * Yes, they do get accumulated twice in the NextSubpass case but since
5626 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
5627 * ORing the bits in twice so it's harmless.
5629 cmd_buffer
->state
.pending_pipe_bits
|=
5630 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
5633 void genX(CmdBeginRenderPass
)(
5634 VkCommandBuffer commandBuffer
,
5635 const VkRenderPassBeginInfo
* pRenderPassBegin
,
5636 VkSubpassContents contents
)
5638 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5639 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
5640 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
5642 cmd_buffer
->state
.framebuffer
= framebuffer
;
5643 cmd_buffer
->state
.pass
= pass
;
5644 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
5646 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
5648 /* If we failed to setup the attachments we should not try to go further */
5649 if (result
!= VK_SUCCESS
) {
5650 assert(anv_batch_has_error(&cmd_buffer
->batch
));
5654 genX(flush_pipeline_select_3d
)(cmd_buffer
);
5656 cmd_buffer_begin_subpass(cmd_buffer
, 0);
5659 void genX(CmdBeginRenderPass2
)(
5660 VkCommandBuffer commandBuffer
,
5661 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
5662 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
5664 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
5665 pSubpassBeginInfo
->contents
);
5668 void genX(CmdNextSubpass
)(
5669 VkCommandBuffer commandBuffer
,
5670 VkSubpassContents contents
)
5672 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5674 if (anv_batch_has_error(&cmd_buffer
->batch
))
5677 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
5679 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
5680 cmd_buffer_end_subpass(cmd_buffer
);
5681 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
5684 void genX(CmdNextSubpass2
)(
5685 VkCommandBuffer commandBuffer
,
5686 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
5687 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5689 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
5692 void genX(CmdEndRenderPass
)(
5693 VkCommandBuffer commandBuffer
)
5695 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5697 if (anv_batch_has_error(&cmd_buffer
->batch
))
5700 cmd_buffer_end_subpass(cmd_buffer
);
5702 cmd_buffer
->state
.hiz_enabled
= false;
5705 anv_dump_add_attachments(cmd_buffer
);
5708 /* Remove references to render pass specific state. This enables us to
5709 * detect whether or not we're in a renderpass.
5711 cmd_buffer
->state
.framebuffer
= NULL
;
5712 cmd_buffer
->state
.pass
= NULL
;
5713 cmd_buffer
->state
.subpass
= NULL
;
5716 void genX(CmdEndRenderPass2
)(
5717 VkCommandBuffer commandBuffer
,
5718 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5720 genX(CmdEndRenderPass
)(commandBuffer
);
5724 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
5726 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5727 struct gen_mi_builder b
;
5728 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5730 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
5731 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
5732 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
5734 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
5735 mip
.LoadOperation
= LOAD_LOADINV
;
5736 mip
.CombineOperation
= COMBINE_SET
;
5737 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
5742 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5743 void genX(CmdBeginConditionalRenderingEXT
)(
5744 VkCommandBuffer commandBuffer
,
5745 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5747 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5748 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5749 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5750 struct anv_address value_address
=
5751 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
5753 const bool isInverted
= pConditionalRenderingBegin
->flags
&
5754 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
5756 cmd_state
->conditional_render_enabled
= true;
5758 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5760 struct gen_mi_builder b
;
5761 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5763 /* Section 19.4 of the Vulkan 1.1.85 spec says:
5765 * If the value of the predicate in buffer memory changes
5766 * while conditional rendering is active, the rendering commands
5767 * may be discarded in an implementation-dependent way.
5768 * Some implementations may latch the value of the predicate
5769 * upon beginning conditional rendering while others
5770 * may read it before every rendering command.
5772 * So it's perfectly fine to read a value from the buffer once.
5774 struct gen_mi_value value
= gen_mi_mem32(value_address
);
5776 /* Precompute predicate result, it is necessary to support secondary
5777 * command buffers since it is unknown if conditional rendering is
5778 * inverted when populating them.
5780 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
5781 isInverted
? gen_mi_uge(&b
, gen_mi_imm(0), value
) :
5782 gen_mi_ult(&b
, gen_mi_imm(0), value
));
5785 void genX(CmdEndConditionalRenderingEXT
)(
5786 VkCommandBuffer commandBuffer
)
5788 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5789 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5791 cmd_state
->conditional_render_enabled
= false;
5795 /* Set of stage bits for which are pipelined, i.e. they get queued by the
5796 * command streamer for later execution.
5798 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
5799 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
5800 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
5801 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
5802 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
5803 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
5804 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
5805 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
5806 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
5807 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
5808 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
5809 VK_PIPELINE_STAGE_TRANSFER_BIT | \
5810 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
5811 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
5812 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
5814 void genX(CmdSetEvent
)(
5815 VkCommandBuffer commandBuffer
,
5817 VkPipelineStageFlags stageMask
)
5819 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5820 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5822 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
5823 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5825 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5826 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5827 pc
.StallAtPixelScoreboard
= true;
5828 pc
.CommandStreamerStallEnable
= true;
5831 pc
.DestinationAddressType
= DAT_PPGTT
,
5832 pc
.PostSyncOperation
= WriteImmediateData
,
5833 pc
.Address
= (struct anv_address
) {
5834 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5837 pc
.ImmediateData
= VK_EVENT_SET
;
5841 void genX(CmdResetEvent
)(
5842 VkCommandBuffer commandBuffer
,
5844 VkPipelineStageFlags stageMask
)
5846 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5847 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5849 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
5850 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5852 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5853 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5854 pc
.StallAtPixelScoreboard
= true;
5855 pc
.CommandStreamerStallEnable
= true;
5858 pc
.DestinationAddressType
= DAT_PPGTT
;
5859 pc
.PostSyncOperation
= WriteImmediateData
;
5860 pc
.Address
= (struct anv_address
) {
5861 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5864 pc
.ImmediateData
= VK_EVENT_RESET
;
5868 void genX(CmdWaitEvents
)(
5869 VkCommandBuffer commandBuffer
,
5870 uint32_t eventCount
,
5871 const VkEvent
* pEvents
,
5872 VkPipelineStageFlags srcStageMask
,
5873 VkPipelineStageFlags destStageMask
,
5874 uint32_t memoryBarrierCount
,
5875 const VkMemoryBarrier
* pMemoryBarriers
,
5876 uint32_t bufferMemoryBarrierCount
,
5877 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5878 uint32_t imageMemoryBarrierCount
,
5879 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5882 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5884 for (uint32_t i
= 0; i
< eventCount
; i
++) {
5885 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
5887 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
5888 sem
.WaitMode
= PollingMode
,
5889 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
5890 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
5891 sem
.SemaphoreAddress
= (struct anv_address
) {
5892 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5898 anv_finishme("Implement events on gen7");
5901 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
5902 false, /* byRegion */
5903 memoryBarrierCount
, pMemoryBarriers
,
5904 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5905 imageMemoryBarrierCount
, pImageMemoryBarriers
);
5908 VkResult
genX(CmdSetPerformanceOverrideINTEL
)(
5909 VkCommandBuffer commandBuffer
,
5910 const VkPerformanceOverrideInfoINTEL
* pOverrideInfo
)
5912 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5914 switch (pOverrideInfo
->type
) {
5915 case VK_PERFORMANCE_OVERRIDE_TYPE_NULL_HARDWARE_INTEL
: {
5919 anv_pack_struct(&dw
, GENX(CS_DEBUG_MODE2
),
5920 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
5921 .MediaInstructionDisable
= pOverrideInfo
->enable
,
5922 ._3DRenderingInstructionDisableMask
= true,
5923 .MediaInstructionDisableMask
= true);
5924 emit_lri(&cmd_buffer
->batch
, GENX(CS_DEBUG_MODE2_num
), dw
);
5926 anv_pack_struct(&dw
, GENX(INSTPM
),
5927 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
5928 .MediaInstructionDisable
= pOverrideInfo
->enable
,
5929 ._3DRenderingInstructionDisableMask
= true,
5930 .MediaInstructionDisableMask
= true);
5931 emit_lri(&cmd_buffer
->batch
, GENX(INSTPM_num
), dw
);
5936 case VK_PERFORMANCE_OVERRIDE_TYPE_FLUSH_GPU_CACHES_INTEL
:
5937 if (pOverrideInfo
->enable
) {
5938 /* FLUSH ALL THE THINGS! As requested by the MDAPI team. */
5939 cmd_buffer
->state
.pending_pipe_bits
|=
5940 ANV_PIPE_FLUSH_BITS
|
5941 ANV_PIPE_INVALIDATE_BITS
;
5942 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5947 unreachable("Invalid override");
5953 VkResult
genX(CmdSetPerformanceStreamMarkerINTEL
)(
5954 VkCommandBuffer commandBuffer
,
5955 const VkPerformanceStreamMarkerInfoINTEL
* pMarkerInfo
)
5957 /* TODO: Waiting on the register to write, might depend on generation. */