2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
29 #include "genxml/gen_macros.h"
30 #include "genxml/genX_pack.h"
33 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
35 struct anv_device
*device
= cmd_buffer
->device
;
36 struct anv_bo
*scratch_bo
= NULL
;
38 cmd_buffer
->state
.scratch_size
=
39 anv_block_pool_size(&device
->scratch_block_pool
);
40 if (cmd_buffer
->state
.scratch_size
> 0)
41 scratch_bo
= &device
->scratch_block_pool
.bo
;
43 /* XXX: Do we need this on more than just BDW? */
45 /* Emit a render target cache flush.
47 * This isn't documented anywhere in the PRM. However, it seems to be
48 * necessary prior to changing the surface state base adress. Without
49 * this, we get GPU hangs when using multi-level command buffers which
50 * clear depth, reset state base address, and then go render stuff.
52 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
53 .RenderTargetCacheFlushEnable
= true);
56 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
),
57 .GeneralStateBaseAddress
= { scratch_bo
, 0 },
58 .GeneralStateMemoryObjectControlState
= GENX(MOCS
),
59 .GeneralStateBaseAddressModifyEnable
= true,
61 .SurfaceStateBaseAddress
= anv_cmd_buffer_surface_base_address(cmd_buffer
),
62 .SurfaceStateMemoryObjectControlState
= GENX(MOCS
),
63 .SurfaceStateBaseAddressModifyEnable
= true,
65 .DynamicStateBaseAddress
= { &device
->dynamic_state_block_pool
.bo
, 0 },
66 .DynamicStateMemoryObjectControlState
= GENX(MOCS
),
67 .DynamicStateBaseAddressModifyEnable
= true,
69 .IndirectObjectBaseAddress
= { NULL
, 0 },
70 .IndirectObjectMemoryObjectControlState
= GENX(MOCS
),
71 .IndirectObjectBaseAddressModifyEnable
= true,
73 .InstructionBaseAddress
= { &device
->instruction_block_pool
.bo
, 0 },
74 .InstructionMemoryObjectControlState
= GENX(MOCS
),
75 .InstructionBaseAddressModifyEnable
= true,
78 /* Broadwell requires that we specify a buffer size for a bunch of
79 * these fields. However, since we will be growing the BO's live, we
80 * just set them all to the maximum.
82 .GeneralStateBufferSize
= 0xfffff,
83 .GeneralStateBufferSizeModifyEnable
= true,
84 .DynamicStateBufferSize
= 0xfffff,
85 .DynamicStateBufferSizeModifyEnable
= true,
86 .IndirectObjectBufferSize
= 0xfffff,
87 .IndirectObjectBufferSizeModifyEnable
= true,
88 .InstructionBufferSize
= 0xfffff,
89 .InstructionBuffersizeModifyEnable
= true,
93 /* After re-setting the surface state base address, we have to do some
94 * cache flusing so that the sampler engine will pick up the new
95 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
96 * Shared Function > 3D Sampler > State > State Caching (page 96):
98 * Coherency with system memory in the state cache, like the texture
99 * cache is handled partially by software. It is expected that the
100 * command stream or shader will issue Cache Flush operation or
101 * Cache_Flush sampler message to ensure that the L1 cache remains
102 * coherent with system memory.
106 * Whenever the value of the Dynamic_State_Base_Addr,
107 * Surface_State_Base_Addr are altered, the L1 state cache must be
108 * invalidated to ensure the new surface or sampler state is fetched
109 * from system memory.
111 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
112 * which, according the PIPE_CONTROL instruction documentation in the
115 * Setting this bit is independent of any other bit in this packet.
116 * This bit controls the invalidation of the L1 and L2 state caches
117 * at the top of the pipe i.e. at the parsing time.
119 * Unfortunately, experimentation seems to indicate that state cache
120 * invalidation through a PIPE_CONTROL does nothing whatsoever in
121 * regards to surface state and binding tables. In stead, it seems that
122 * invalidating the texture cache is what is actually needed.
124 * XXX: As far as we have been able to determine through
125 * experimentation, shows that flush the texture cache appears to be
126 * sufficient. The theory here is that all of the sampling/rendering
127 * units cache the binding table in the texture cache. However, we have
128 * yet to be able to actually confirm this.
130 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
131 .TextureCacheInvalidationEnable
= true);
134 void genX(CmdPipelineBarrier
)(
135 VkCommandBuffer commandBuffer
,
136 VkPipelineStageFlags srcStageMask
,
137 VkPipelineStageFlags destStageMask
,
139 uint32_t memoryBarrierCount
,
140 const VkMemoryBarrier
* pMemoryBarriers
,
141 uint32_t bufferMemoryBarrierCount
,
142 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
143 uint32_t imageMemoryBarrierCount
,
144 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
146 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
149 /* XXX: Right now, we're really dumb and just flush whatever categories
150 * the app asks for. One of these days we may make this a bit better
151 * but right now that's all the hardware allows for in most areas.
153 VkAccessFlags src_flags
= 0;
154 VkAccessFlags dst_flags
= 0;
156 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
157 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
158 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
161 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
162 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
163 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
166 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
167 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
168 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
171 /* Mask out the Source access flags we care about */
172 const uint32_t src_mask
=
173 VK_ACCESS_SHADER_WRITE_BIT
|
174 VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
|
175 VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
|
176 VK_ACCESS_TRANSFER_WRITE_BIT
;
178 src_flags
= src_flags
& src_mask
;
180 /* Mask out the destination access flags we care about */
181 const uint32_t dst_mask
=
182 VK_ACCESS_INDIRECT_COMMAND_READ_BIT
|
183 VK_ACCESS_INDEX_READ_BIT
|
184 VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
|
185 VK_ACCESS_UNIFORM_READ_BIT
|
186 VK_ACCESS_SHADER_READ_BIT
|
187 VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
|
188 VK_ACCESS_TRANSFER_READ_BIT
;
190 dst_flags
= dst_flags
& dst_mask
;
192 /* The src flags represent how things were used previously. This is
193 * what we use for doing flushes.
195 struct GENX(PIPE_CONTROL
) flush_cmd
= {
196 GENX(PIPE_CONTROL_header
),
197 .PostSyncOperation
= NoWrite
,
200 for_each_bit(b
, src_flags
) {
201 switch ((VkAccessFlagBits
)(1 << b
)) {
202 case VK_ACCESS_SHADER_WRITE_BIT
:
203 flush_cmd
.DCFlushEnable
= true;
205 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
206 flush_cmd
.RenderTargetCacheFlushEnable
= true;
208 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
209 flush_cmd
.DepthCacheFlushEnable
= true;
211 case VK_ACCESS_TRANSFER_WRITE_BIT
:
212 flush_cmd
.RenderTargetCacheFlushEnable
= true;
213 flush_cmd
.DepthCacheFlushEnable
= true;
216 unreachable("should've masked this out by now");
220 /* If we end up doing two PIPE_CONTROLs, the first, flusing one also has to
221 * stall and wait for the flushing to finish, so we don't re-dirty the
222 * caches with in-flight rendering after the second PIPE_CONTROL
227 flush_cmd
.CommandStreamerStallEnable
= true;
229 if (src_flags
&& dst_flags
) {
230 dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
, GENX(PIPE_CONTROL_length
));
231 GENX(PIPE_CONTROL_pack
)(&cmd_buffer
->batch
, dw
, &flush_cmd
);
234 /* The dst flags represent how things will be used in the future. This
235 * is what we use for doing cache invalidations.
237 struct GENX(PIPE_CONTROL
) invalidate_cmd
= {
238 GENX(PIPE_CONTROL_header
),
239 .PostSyncOperation
= NoWrite
,
242 for_each_bit(b
, dst_flags
) {
243 switch ((VkAccessFlagBits
)(1 << b
)) {
244 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
245 case VK_ACCESS_INDEX_READ_BIT
:
246 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
247 invalidate_cmd
.VFCacheInvalidationEnable
= true;
249 case VK_ACCESS_UNIFORM_READ_BIT
:
250 invalidate_cmd
.ConstantCacheInvalidationEnable
= true;
252 case VK_ACCESS_SHADER_READ_BIT
:
253 invalidate_cmd
.TextureCacheInvalidationEnable
= true;
255 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
256 invalidate_cmd
.TextureCacheInvalidationEnable
= true;
258 case VK_ACCESS_TRANSFER_READ_BIT
:
259 invalidate_cmd
.TextureCacheInvalidationEnable
= true;
262 unreachable("should've masked this out by now");
267 dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
, GENX(PIPE_CONTROL_length
));
268 GENX(PIPE_CONTROL_pack
)(&cmd_buffer
->batch
, dw
, &invalidate_cmd
);
273 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
275 static const uint32_t push_constant_opcodes
[] = {
276 [MESA_SHADER_VERTEX
] = 21,
277 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
278 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
279 [MESA_SHADER_GEOMETRY
] = 22,
280 [MESA_SHADER_FRAGMENT
] = 23,
281 [MESA_SHADER_COMPUTE
] = 0,
284 VkShaderStageFlags flushed
= 0;
286 anv_foreach_stage(stage
, cmd_buffer
->state
.push_constants_dirty
) {
287 if (stage
== MESA_SHADER_COMPUTE
)
290 struct anv_state state
= anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
292 if (state
.offset
== 0) {
293 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
),
294 ._3DCommandSubOpcode
= push_constant_opcodes
[stage
]);
296 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
),
297 ._3DCommandSubOpcode
= push_constant_opcodes
[stage
],
300 .PointerToConstantBuffer2
= { &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, state
.offset
},
301 .ConstantBuffer2ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
303 .PointerToConstantBuffer0
= { .offset
= state
.offset
},
304 .ConstantBuffer0ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
309 flushed
|= mesa_to_vk_shader_stage(stage
);
312 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_ALL_GRAPHICS
;
318 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
320 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
323 uint32_t vb_emit
= cmd_buffer
->state
.vb_dirty
& pipeline
->vb_used
;
325 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
328 /* FIXME (jason): Currently, the config_l3 function causes problems on
329 * Haswell and prior if you have a kernel older than 4.4. In order to
330 * work, it requires a couple of registers be white-listed in the
331 * command parser and they weren't added until 4.4. What we should do
332 * is check the command parser version and make it a no-op if your
333 * command parser is either off or too old. Compute won't work 100%,
334 * but at least 3-D will. In the mean time, I'm going to make this
335 * gen8+ only so that we can get Haswell working again.
337 genX(cmd_buffer_config_l3
)(cmd_buffer
, false);
340 genX(flush_pipeline_select_3d
)(cmd_buffer
);
343 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
344 const uint32_t num_dwords
= 1 + num_buffers
* 4;
346 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
347 GENX(3DSTATE_VERTEX_BUFFERS
));
349 for_each_bit(vb
, vb_emit
) {
350 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
351 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
353 struct GENX(VERTEX_BUFFER_STATE
) state
= {
354 .VertexBufferIndex
= vb
,
357 .MemoryObjectControlState
= GENX(MOCS
),
359 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
360 .InstanceDataStepRate
= 1,
361 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
364 .AddressModifyEnable
= true,
365 .BufferPitch
= pipeline
->binding_stride
[vb
],
366 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
369 .BufferSize
= buffer
->size
- offset
371 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
375 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
380 cmd_buffer
->state
.vb_dirty
&= ~vb_emit
;
382 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
383 /* If somebody compiled a pipeline after starting a command buffer the
384 * scratch bo may have grown since we started this cmd buffer (and
385 * emitted STATE_BASE_ADDRESS). If we're binding that pipeline now,
386 * reemit STATE_BASE_ADDRESS so that we use the bigger scratch bo. */
387 if (cmd_buffer
->state
.scratch_size
< pipeline
->total_scratch
)
388 anv_cmd_buffer_emit_state_base_address(cmd_buffer
);
390 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
392 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
394 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
395 * the next 3DPRIMITIVE command after programming the
396 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
398 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
399 * pipeline setup, we need to dirty push constants.
401 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
405 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
406 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
407 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
409 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
410 * stall needs to be sent just prior to any 3DSTATE_VS,
411 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
412 * 3DSTATE_BINDING_TABLE_POINTER_VS,
413 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
414 * PIPE_CONTROL needs to be sent before any combination of VS
415 * associated 3DSTATE."
417 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
418 .DepthStallEnable
= true,
419 .PostSyncOperation
= WriteImmediateData
,
420 .Address
= { &cmd_buffer
->device
->workaround_bo
, 0 });
424 /* We emit the binding tables and sampler tables first, then emit push
425 * constants and then finally emit binding table and sampler table
426 * pointers. It has to happen in this order, since emitting the binding
427 * tables may change the push constants (in case of storage images). After
428 * emitting push constants, on SKL+ we have to emit the corresponding
429 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
432 if (cmd_buffer
->state
.descriptors_dirty
)
433 dirty
= gen7_cmd_buffer_flush_descriptor_sets(cmd_buffer
);
435 if (cmd_buffer
->state
.push_constants_dirty
) {
437 /* On Sky Lake and later, the binding table pointers commands are
438 * what actually flush the changes to push constant state so we need
439 * to dirty them so they get re-emitted below.
441 dirty
|= cmd_buffer_flush_push_constants(cmd_buffer
);
443 cmd_buffer_flush_push_constants(cmd_buffer
);
448 gen7_cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
450 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
451 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
453 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
454 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
456 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
460 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
461 struct anv_bo
*bo
, uint32_t offset
)
463 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
464 GENX(3DSTATE_VERTEX_BUFFERS
));
466 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
467 &(struct GENX(VERTEX_BUFFER_STATE
)) {
468 .VertexBufferIndex
= 32, /* Reserved for this */
469 .AddressModifyEnable
= true,
472 .MemoryObjectControlState
= GENX(MOCS
),
473 .BufferStartingAddress
= { bo
, offset
},
476 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
477 .BufferStartingAddress
= { bo
, offset
},
478 .EndAddress
= { bo
, offset
+ 8 },
484 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
485 uint32_t base_vertex
, uint32_t base_instance
)
487 struct anv_state id_state
=
488 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
490 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
491 ((uint32_t *)id_state
.map
)[1] = base_instance
;
493 if (!cmd_buffer
->device
->info
.has_llc
)
494 anv_state_clflush(id_state
);
496 emit_base_vertex_instance_bo(cmd_buffer
,
497 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, id_state
.offset
);
501 VkCommandBuffer commandBuffer
,
502 uint32_t vertexCount
,
503 uint32_t instanceCount
,
504 uint32_t firstVertex
,
505 uint32_t firstInstance
)
507 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
508 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
509 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
511 genX(cmd_buffer_flush_state
)(cmd_buffer
);
513 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
514 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
516 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
),
517 .VertexAccessType
= SEQUENTIAL
,
518 .PrimitiveTopologyType
= pipeline
->topology
,
519 .VertexCountPerInstance
= vertexCount
,
520 .StartVertexLocation
= firstVertex
,
521 .InstanceCount
= instanceCount
,
522 .StartInstanceLocation
= firstInstance
,
523 .BaseVertexLocation
= 0);
526 void genX(CmdDrawIndexed
)(
527 VkCommandBuffer commandBuffer
,
529 uint32_t instanceCount
,
531 int32_t vertexOffset
,
532 uint32_t firstInstance
)
534 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
535 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
536 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
538 genX(cmd_buffer_flush_state
)(cmd_buffer
);
540 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
541 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
543 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
),
544 .VertexAccessType
= RANDOM
,
545 .PrimitiveTopologyType
= pipeline
->topology
,
546 .VertexCountPerInstance
= indexCount
,
547 .StartVertexLocation
= firstIndex
,
548 .InstanceCount
= instanceCount
,
549 .StartInstanceLocation
= firstInstance
,
550 .BaseVertexLocation
= vertexOffset
);
553 /* Auto-Draw / Indirect Registers */
554 #define GEN7_3DPRIM_END_OFFSET 0x2420
555 #define GEN7_3DPRIM_START_VERTEX 0x2430
556 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
557 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
558 #define GEN7_3DPRIM_START_INSTANCE 0x243C
559 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
562 emit_lrm(struct anv_batch
*batch
,
563 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
565 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
),
566 .RegisterAddress
= reg
,
567 .MemoryAddress
= { bo
, offset
});
571 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
573 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
),
574 .RegisterOffset
= reg
,
578 void genX(CmdDrawIndirect
)(
579 VkCommandBuffer commandBuffer
,
585 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
586 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
587 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
588 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
589 struct anv_bo
*bo
= buffer
->bo
;
590 uint32_t bo_offset
= buffer
->offset
+ offset
;
592 genX(cmd_buffer_flush_state
)(cmd_buffer
);
594 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
595 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
597 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
598 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
599 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
600 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
601 emit_lri(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
603 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
),
604 .IndirectParameterEnable
= true,
605 .VertexAccessType
= SEQUENTIAL
,
606 .PrimitiveTopologyType
= pipeline
->topology
);
609 void genX(CmdDrawIndexedIndirect
)(
610 VkCommandBuffer commandBuffer
,
616 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
617 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
618 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
619 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
620 struct anv_bo
*bo
= buffer
->bo
;
621 uint32_t bo_offset
= buffer
->offset
+ offset
;
623 genX(cmd_buffer_flush_state
)(cmd_buffer
);
625 /* TODO: We need to stomp base vertex to 0 somehow */
626 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
627 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
629 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
630 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
631 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
632 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
633 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
635 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
),
636 .IndirectParameterEnable
= true,
637 .VertexAccessType
= RANDOM
,
638 .PrimitiveTopologyType
= pipeline
->topology
);
642 void genX(CmdDispatch
)(
643 VkCommandBuffer commandBuffer
,
648 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
649 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
650 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
652 if (prog_data
->uses_num_work_groups
) {
653 struct anv_state state
=
654 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
655 uint32_t *sizes
= state
.map
;
659 if (!cmd_buffer
->device
->info
.has_llc
)
660 anv_state_clflush(state
);
661 cmd_buffer
->state
.num_workgroups_offset
= state
.offset
;
662 cmd_buffer
->state
.num_workgroups_bo
=
663 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
;
666 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
668 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
),
669 .SIMDSize
= prog_data
->simd_size
/ 16,
670 .ThreadDepthCounterMaximum
= 0,
671 .ThreadHeightCounterMaximum
= 0,
672 .ThreadWidthCounterMaximum
= pipeline
->cs_thread_width_max
- 1,
673 .ThreadGroupIDXDimension
= x
,
674 .ThreadGroupIDYDimension
= y
,
675 .ThreadGroupIDZDimension
= z
,
676 .RightExecutionMask
= pipeline
->cs_right_mask
,
677 .BottomExecutionMask
= 0xffffffff);
679 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
));
682 #define GPGPU_DISPATCHDIMX 0x2500
683 #define GPGPU_DISPATCHDIMY 0x2504
684 #define GPGPU_DISPATCHDIMZ 0x2508
686 #define MI_PREDICATE_SRC0 0x2400
687 #define MI_PREDICATE_SRC1 0x2408
689 void genX(CmdDispatchIndirect
)(
690 VkCommandBuffer commandBuffer
,
694 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
695 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
696 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
697 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
698 struct anv_bo
*bo
= buffer
->bo
;
699 uint32_t bo_offset
= buffer
->offset
+ offset
;
700 struct anv_batch
*batch
= &cmd_buffer
->batch
;
702 if (prog_data
->uses_num_work_groups
) {
703 cmd_buffer
->state
.num_workgroups_offset
= bo_offset
;
704 cmd_buffer
->state
.num_workgroups_bo
= bo
;
707 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
709 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
710 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
711 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
714 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
715 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
716 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
717 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
719 /* Load compute_dispatch_indirect_x_size into SRC0 */
720 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
722 /* predicate = (compute_dispatch_indirect_x_size == 0); */
723 anv_batch_emit(batch
, GENX(MI_PREDICATE
),
724 .LoadOperation
= LOAD_LOAD
,
725 .CombineOperation
= COMBINE_SET
,
726 .CompareOperation
= COMPARE_SRCS_EQUAL
);
728 /* Load compute_dispatch_indirect_y_size into SRC0 */
729 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
731 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
732 anv_batch_emit(batch
, GENX(MI_PREDICATE
),
733 .LoadOperation
= LOAD_LOAD
,
734 .CombineOperation
= COMBINE_OR
,
735 .CompareOperation
= COMPARE_SRCS_EQUAL
);
737 /* Load compute_dispatch_indirect_z_size into SRC0 */
738 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
740 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
741 anv_batch_emit(batch
, GENX(MI_PREDICATE
),
742 .LoadOperation
= LOAD_LOAD
,
743 .CombineOperation
= COMBINE_OR
,
744 .CompareOperation
= COMPARE_SRCS_EQUAL
);
746 /* predicate = !predicate; */
747 #define COMPARE_FALSE 1
748 anv_batch_emit(batch
, GENX(MI_PREDICATE
),
749 .LoadOperation
= LOAD_LOADINV
,
750 .CombineOperation
= COMBINE_OR
,
751 .CompareOperation
= COMPARE_FALSE
);
754 anv_batch_emit(batch
, GENX(GPGPU_WALKER
),
755 .IndirectParameterEnable
= true,
756 .PredicateEnable
= GEN_GEN
<= 7,
757 .SIMDSize
= prog_data
->simd_size
/ 16,
758 .ThreadDepthCounterMaximum
= 0,
759 .ThreadHeightCounterMaximum
= 0,
760 .ThreadWidthCounterMaximum
= pipeline
->cs_thread_width_max
- 1,
761 .RightExecutionMask
= pipeline
->cs_right_mask
,
762 .BottomExecutionMask
= 0xffffffff);
764 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
));
768 flush_pipeline_before_pipeline_select(struct anv_cmd_buffer
*cmd_buffer
,
771 #if GEN_GEN >= 8 && GEN_GEN < 10
772 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
774 * Software must clear the COLOR_CALC_STATE Valid field in
775 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
776 * with Pipeline Select set to GPGPU.
778 * The internal hardware docs recommend the same workaround for Gen9
781 if (pipeline
== GPGPU
)
782 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
));
784 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
785 * PIPELINE_SELECT [DevBWR+]":
789 * Software must ensure all the write caches are flushed through a
790 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
791 * command to invalidate read only caches prior to programming
792 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
794 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
795 .RenderTargetCacheFlushEnable
= true,
796 .DepthCacheFlushEnable
= true,
797 .DCFlushEnable
= true,
798 .PostSyncOperation
= NoWrite
,
799 .CommandStreamerStallEnable
= true);
801 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
802 .TextureCacheInvalidationEnable
= true,
803 .ConstantCacheInvalidationEnable
= true,
804 .StateCacheInvalidationEnable
= true,
805 .InstructionCacheInvalidateEnable
= true,
806 .PostSyncOperation
= NoWrite
);
811 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
813 if (cmd_buffer
->state
.current_pipeline
!= _3D
) {
814 flush_pipeline_before_pipeline_select(cmd_buffer
, _3D
);
816 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
),
820 .PipelineSelection
= _3D
);
821 cmd_buffer
->state
.current_pipeline
= _3D
;
826 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
828 if (cmd_buffer
->state
.current_pipeline
!= GPGPU
) {
829 flush_pipeline_before_pipeline_select(cmd_buffer
, GPGPU
);
831 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
),
835 .PipelineSelection
= GPGPU
);
836 cmd_buffer
->state
.current_pipeline
= GPGPU
;
841 genX(cmd_buffer_alloc_null_surface_state
)(struct anv_cmd_buffer
*cmd_buffer
,
842 struct anv_framebuffer
*fb
)
844 struct anv_state state
=
845 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
847 struct GENX(RENDER_SURFACE_STATE
) null_ss
= {
848 .SurfaceType
= SURFTYPE_NULL
,
849 .SurfaceArray
= fb
->layers
> 0,
850 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
854 .TiledSurface
= true,
856 .Width
= fb
->width
- 1,
857 .Height
= fb
->height
- 1,
858 .Depth
= fb
->layers
- 1,
859 .RenderTargetViewExtent
= fb
->layers
- 1,
862 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
.map
, &null_ss
);
864 if (!cmd_buffer
->device
->info
.has_llc
)
865 anv_state_clflush(state
);
871 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
873 struct anv_device
*device
= cmd_buffer
->device
;
874 const struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
875 const struct anv_image_view
*iview
=
876 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
877 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
878 const struct anv_format
*anv_format
=
879 iview
? anv_format_for_vk_format(iview
->vk_format
) : NULL
;
880 const bool has_depth
= iview
&& anv_format
->has_depth
;
881 const bool has_stencil
= iview
&& anv_format
->has_stencil
;
883 /* FIXME: Implement the PMA stall W/A */
884 /* FIXME: Width and Height are wrong */
886 /* Emit 3DSTATE_DEPTH_BUFFER */
888 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
),
889 .SurfaceType
= SURFTYPE_2D
,
890 .DepthWriteEnable
= true,
891 .StencilWriteEnable
= has_stencil
,
892 .HierarchicalDepthBufferEnable
= false,
893 .SurfaceFormat
= isl_surf_get_depth_format(&device
->isl_dev
,
894 &image
->depth_surface
.isl
),
895 .SurfacePitch
= image
->depth_surface
.isl
.row_pitch
- 1,
896 .SurfaceBaseAddress
= {
898 .offset
= image
->offset
+ image
->depth_surface
.offset
,
900 .Height
= fb
->height
- 1,
901 .Width
= fb
->width
- 1,
904 .MinimumArrayElement
= 0,
905 .DepthBufferObjectControlState
= GENX(MOCS
),
907 .SurfaceQPitch
= isl_surf_get_array_pitch_el_rows(&image
->depth_surface
.isl
) >> 2,
909 .RenderTargetViewExtent
= 1 - 1);
911 /* Even when no depth buffer is present, the hardware requires that
912 * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
914 * If a null depth buffer is bound, the driver must instead bind depth as:
915 * 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
916 * 3DSTATE_DEPTH.Width = 1
917 * 3DSTATE_DEPTH.Height = 1
918 * 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
919 * 3DSTATE_DEPTH.SurfaceBaseAddress = 0
920 * 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
921 * 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
922 * 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
924 * The PRM is wrong, though. The width and height must be programmed to
925 * actual framebuffer's width and height, even when neither depth buffer
926 * nor stencil buffer is present. Also, D16_UNORM is not allowed to
927 * be combined with a stencil buffer so we use D32_FLOAT instead.
929 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
),
930 .SurfaceType
= SURFTYPE_2D
,
931 .SurfaceFormat
= D32_FLOAT
,
932 .Width
= fb
->width
- 1,
933 .Height
= fb
->height
- 1,
934 .StencilWriteEnable
= has_stencil
);
937 /* Emit 3DSTATE_STENCIL_BUFFER */
939 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
),
940 #if GEN_GEN >= 8 || GEN_IS_HASWELL
941 .StencilBufferEnable
= true,
943 .StencilBufferObjectControlState
= GENX(MOCS
),
945 /* Stencil buffers have strange pitch. The PRM says:
947 * The pitch must be set to 2x the value computed based on width,
948 * as the stencil buffer is stored with two rows interleaved.
950 .SurfacePitch
= 2 * image
->stencil_surface
.isl
.row_pitch
- 1,
953 .SurfaceQPitch
= isl_surf_get_array_pitch_el_rows(&image
->stencil_surface
.isl
) >> 2,
955 .SurfaceBaseAddress
= {
957 .offset
= image
->offset
+ image
->stencil_surface
.offset
,
960 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
));
963 /* Disable hierarchial depth buffers. */
964 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
));
966 /* Clear the clear params. */
967 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CLEAR_PARAMS
));
971 * @see anv_cmd_buffer_set_subpass()
974 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
975 struct anv_subpass
*subpass
)
977 cmd_buffer
->state
.subpass
= subpass
;
979 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
981 cmd_buffer_emit_depth_stencil(cmd_buffer
);
984 void genX(CmdBeginRenderPass
)(
985 VkCommandBuffer commandBuffer
,
986 const VkRenderPassBeginInfo
* pRenderPassBegin
,
987 VkSubpassContents contents
)
989 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
990 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
991 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
993 cmd_buffer
->state
.framebuffer
= framebuffer
;
994 cmd_buffer
->state
.pass
= pass
;
995 anv_cmd_state_setup_attachments(cmd_buffer
, pRenderPassBegin
);
997 genX(flush_pipeline_select_3d
)(cmd_buffer
);
999 const VkRect2D
*render_area
= &pRenderPassBegin
->renderArea
;
1001 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DRAWING_RECTANGLE
),
1002 .ClippedDrawingRectangleYMin
= MAX2(render_area
->offset
.y
, 0),
1003 .ClippedDrawingRectangleXMin
= MAX2(render_area
->offset
.x
, 0),
1004 .ClippedDrawingRectangleYMax
=
1005 render_area
->offset
.y
+ render_area
->extent
.height
- 1,
1006 .ClippedDrawingRectangleXMax
=
1007 render_area
->offset
.x
+ render_area
->extent
.width
- 1,
1008 .DrawingRectangleOriginY
= 0,
1009 .DrawingRectangleOriginX
= 0);
1011 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
1012 anv_cmd_buffer_clear_subpass(cmd_buffer
);
1015 void genX(CmdNextSubpass
)(
1016 VkCommandBuffer commandBuffer
,
1017 VkSubpassContents contents
)
1019 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1021 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1023 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
1024 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
1025 anv_cmd_buffer_clear_subpass(cmd_buffer
);
1028 void genX(CmdEndRenderPass
)(
1029 VkCommandBuffer commandBuffer
)
1031 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1033 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
1037 emit_ps_depth_count(struct anv_batch
*batch
,
1038 struct anv_bo
*bo
, uint32_t offset
)
1040 anv_batch_emit(batch
, GENX(PIPE_CONTROL
),
1041 .DestinationAddressType
= DAT_PPGTT
,
1042 .PostSyncOperation
= WritePSDepthCount
,
1043 .DepthStallEnable
= true,
1044 .Address
= { bo
, offset
});
1048 emit_query_availability(struct anv_batch
*batch
,
1049 struct anv_bo
*bo
, uint32_t offset
)
1051 anv_batch_emit(batch
, GENX(PIPE_CONTROL
),
1052 .DestinationAddressType
= DAT_PPGTT
,
1053 .PostSyncOperation
= WriteImmediateData
,
1054 .Address
= { bo
, offset
},
1055 .ImmediateData
= 1);
1058 void genX(CmdBeginQuery
)(
1059 VkCommandBuffer commandBuffer
,
1060 VkQueryPool queryPool
,
1062 VkQueryControlFlags flags
)
1064 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1065 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
1067 /* Workaround: When meta uses the pipeline with the VS disabled, it seems
1068 * that the pipelining of the depth write breaks. What we see is that
1069 * samples from the render pass clear leaks into the first query
1070 * immediately after the clear. Doing a pipecontrol with a post-sync
1071 * operation and DepthStallEnable seems to work around the issue.
1073 if (cmd_buffer
->state
.need_query_wa
) {
1074 cmd_buffer
->state
.need_query_wa
= false;
1075 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
1076 .DepthCacheFlushEnable
= true,
1077 .DepthStallEnable
= true);
1080 switch (pool
->type
) {
1081 case VK_QUERY_TYPE_OCCLUSION
:
1082 emit_ps_depth_count(&cmd_buffer
->batch
, &pool
->bo
,
1083 query
* sizeof(struct anv_query_pool_slot
));
1086 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
1092 void genX(CmdEndQuery
)(
1093 VkCommandBuffer commandBuffer
,
1094 VkQueryPool queryPool
,
1097 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1098 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
1100 switch (pool
->type
) {
1101 case VK_QUERY_TYPE_OCCLUSION
:
1102 emit_ps_depth_count(&cmd_buffer
->batch
, &pool
->bo
,
1103 query
* sizeof(struct anv_query_pool_slot
) + 8);
1105 emit_query_availability(&cmd_buffer
->batch
, &pool
->bo
,
1106 query
* sizeof(struct anv_query_pool_slot
) + 16);
1109 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
1115 #define TIMESTAMP 0x2358
1117 void genX(CmdWriteTimestamp
)(
1118 VkCommandBuffer commandBuffer
,
1119 VkPipelineStageFlagBits pipelineStage
,
1120 VkQueryPool queryPool
,
1123 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1124 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
1125 uint32_t offset
= query
* sizeof(struct anv_query_pool_slot
);
1127 assert(pool
->type
== VK_QUERY_TYPE_TIMESTAMP
);
1129 switch (pipelineStage
) {
1130 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
:
1131 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
),
1132 .RegisterAddress
= TIMESTAMP
,
1133 .MemoryAddress
= { &pool
->bo
, offset
});
1134 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
),
1135 .RegisterAddress
= TIMESTAMP
+ 4,
1136 .MemoryAddress
= { &pool
->bo
, offset
+ 4 });
1140 /* Everything else is bottom-of-pipe */
1141 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
1142 .DestinationAddressType
= DAT_PPGTT
,
1143 .PostSyncOperation
= WriteTimestamp
,
1144 .Address
= { &pool
->bo
, offset
});
1148 emit_query_availability(&cmd_buffer
->batch
, &pool
->bo
, query
+ 16);
1151 #if GEN_GEN > 7 || GEN_IS_HASWELL
1153 #define alu_opcode(v) __gen_uint((v), 20, 31)
1154 #define alu_operand1(v) __gen_uint((v), 10, 19)
1155 #define alu_operand2(v) __gen_uint((v), 0, 9)
1156 #define alu(opcode, operand1, operand2) \
1157 alu_opcode(opcode) | alu_operand1(operand1) | alu_operand2(operand2)
1159 #define OPCODE_NOOP 0x000
1160 #define OPCODE_LOAD 0x080
1161 #define OPCODE_LOADINV 0x480
1162 #define OPCODE_LOAD0 0x081
1163 #define OPCODE_LOAD1 0x481
1164 #define OPCODE_ADD 0x100
1165 #define OPCODE_SUB 0x101
1166 #define OPCODE_AND 0x102
1167 #define OPCODE_OR 0x103
1168 #define OPCODE_XOR 0x104
1169 #define OPCODE_STORE 0x180
1170 #define OPCODE_STOREINV 0x580
1172 #define OPERAND_R0 0x00
1173 #define OPERAND_R1 0x01
1174 #define OPERAND_R2 0x02
1175 #define OPERAND_R3 0x03
1176 #define OPERAND_R4 0x04
1177 #define OPERAND_SRCA 0x20
1178 #define OPERAND_SRCB 0x21
1179 #define OPERAND_ACCU 0x31
1180 #define OPERAND_ZF 0x32
1181 #define OPERAND_CF 0x33
1183 #define CS_GPR(n) (0x2600 + (n) * 8)
1186 emit_load_alu_reg_u64(struct anv_batch
*batch
, uint32_t reg
,
1187 struct anv_bo
*bo
, uint32_t offset
)
1189 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
),
1190 .RegisterAddress
= reg
,
1191 .MemoryAddress
= { bo
, offset
});
1192 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
),
1193 .RegisterAddress
= reg
+ 4,
1194 .MemoryAddress
= { bo
, offset
+ 4 });
1198 store_query_result(struct anv_batch
*batch
, uint32_t reg
,
1199 struct anv_bo
*bo
, uint32_t offset
, VkQueryResultFlags flags
)
1201 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
),
1202 .RegisterAddress
= reg
,
1203 .MemoryAddress
= { bo
, offset
});
1205 if (flags
& VK_QUERY_RESULT_64_BIT
)
1206 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
),
1207 .RegisterAddress
= reg
+ 4,
1208 .MemoryAddress
= { bo
, offset
+ 4 });
1211 void genX(CmdCopyQueryPoolResults
)(
1212 VkCommandBuffer commandBuffer
,
1213 VkQueryPool queryPool
,
1214 uint32_t firstQuery
,
1215 uint32_t queryCount
,
1216 VkBuffer destBuffer
,
1217 VkDeviceSize destOffset
,
1218 VkDeviceSize destStride
,
1219 VkQueryResultFlags flags
)
1221 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1222 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
1223 ANV_FROM_HANDLE(anv_buffer
, buffer
, destBuffer
);
1224 uint32_t slot_offset
, dst_offset
;
1226 if (flags
& VK_QUERY_RESULT_WAIT_BIT
)
1227 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
1228 .CommandStreamerStallEnable
= true,
1229 .StallAtPixelScoreboard
= true);
1231 dst_offset
= buffer
->offset
+ destOffset
;
1232 for (uint32_t i
= 0; i
< queryCount
; i
++) {
1234 slot_offset
= (firstQuery
+ i
) * sizeof(struct anv_query_pool_slot
);
1235 switch (pool
->type
) {
1236 case VK_QUERY_TYPE_OCCLUSION
:
1237 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
1238 CS_GPR(0), &pool
->bo
, slot_offset
);
1239 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
1240 CS_GPR(1), &pool
->bo
, slot_offset
+ 8);
1242 /* FIXME: We need to clamp the result for 32 bit. */
1244 uint32_t *dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
1245 dw
[1] = alu(OPCODE_LOAD
, OPERAND_SRCA
, OPERAND_R1
);
1246 dw
[2] = alu(OPCODE_LOAD
, OPERAND_SRCB
, OPERAND_R0
);
1247 dw
[3] = alu(OPCODE_SUB
, 0, 0);
1248 dw
[4] = alu(OPCODE_STORE
, OPERAND_R2
, OPERAND_ACCU
);
1251 case VK_QUERY_TYPE_TIMESTAMP
:
1252 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
1253 CS_GPR(2), &pool
->bo
, slot_offset
);
1257 unreachable("unhandled query type");
1260 store_query_result(&cmd_buffer
->batch
,
1261 CS_GPR(2), buffer
->bo
, dst_offset
, flags
);
1263 if (flags
& VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
) {
1264 emit_load_alu_reg_u64(&cmd_buffer
->batch
, CS_GPR(0),
1265 &pool
->bo
, slot_offset
+ 16);
1266 if (flags
& VK_QUERY_RESULT_64_BIT
)
1267 store_query_result(&cmd_buffer
->batch
,
1268 CS_GPR(0), buffer
->bo
, dst_offset
+ 8, flags
);
1270 store_query_result(&cmd_buffer
->batch
,
1271 CS_GPR(0), buffer
->bo
, dst_offset
+ 4, flags
);
1274 dst_offset
+= destStride
;