2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_aux_map.h"
33 #include "common/gen_l3_config.h"
34 #include "genxml/gen_macros.h"
35 #include "genxml/genX_pack.h"
37 /* We reserve GPR 14 and 15 for conditional rendering */
38 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
39 #define __gen_get_batch_dwords anv_batch_emit_dwords
40 #define __gen_address_offset anv_address_add
41 #include "common/gen_mi_builder.h"
43 static void genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
47 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
49 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
50 lri
.RegisterOffset
= reg
;
56 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
58 struct anv_device
*device
= cmd_buffer
->device
;
59 UNUSED
const struct gen_device_info
*devinfo
= &device
->info
;
60 uint32_t mocs
= device
->isl_dev
.mocs
.internal
;
62 /* If we are emitting a new state base address we probably need to re-emit
65 cmd_buffer
->state
.descriptors_dirty
|= ~0;
67 /* Emit a render target cache flush.
69 * This isn't documented anywhere in the PRM. However, it seems to be
70 * necessary prior to changing the surface state base adress. Without
71 * this, we get GPU hangs when using multi-level command buffers which
72 * clear depth, reset state base address, and then go render stuff.
74 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
75 pc
.DCFlushEnable
= true;
76 pc
.RenderTargetCacheFlushEnable
= true;
77 pc
.CommandStreamerStallEnable
= true;
79 pc
.TileCacheFlushEnable
= true;
82 /* GEN:BUG:1606662791:
84 * Software must program PIPE_CONTROL command with "HDC Pipeline
85 * Flush" prior to programming of the below two non-pipeline state :
86 * * STATE_BASE_ADDRESS
87 * * 3DSTATE_BINDING_TABLE_POOL_ALLOC
89 if (devinfo
->revision
== 0 /* A0 */)
90 pc
.HDCPipelineFlushEnable
= true;
95 /* GEN:BUG:1607854226:
97 * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
98 * mode by putting the pipeline temporarily in 3D mode.
100 uint32_t gen12_wa_pipeline
= cmd_buffer
->state
.current_pipeline
;
101 genX(flush_pipeline_select_3d
)(cmd_buffer
);
104 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
105 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
106 sba
.GeneralStateMOCS
= mocs
;
107 sba
.GeneralStateBaseAddressModifyEnable
= true;
109 sba
.StatelessDataPortAccessMOCS
= mocs
;
111 sba
.SurfaceStateBaseAddress
=
112 anv_cmd_buffer_surface_base_address(cmd_buffer
);
113 sba
.SurfaceStateMOCS
= mocs
;
114 sba
.SurfaceStateBaseAddressModifyEnable
= true;
116 sba
.DynamicStateBaseAddress
=
117 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
118 sba
.DynamicStateMOCS
= mocs
;
119 sba
.DynamicStateBaseAddressModifyEnable
= true;
121 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
122 sba
.IndirectObjectMOCS
= mocs
;
123 sba
.IndirectObjectBaseAddressModifyEnable
= true;
125 sba
.InstructionBaseAddress
=
126 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
127 sba
.InstructionMOCS
= mocs
;
128 sba
.InstructionBaseAddressModifyEnable
= true;
131 /* Broadwell requires that we specify a buffer size for a bunch of
132 * these fields. However, since we will be growing the BO's live, we
133 * just set them all to the maximum.
135 sba
.GeneralStateBufferSize
= 0xfffff;
136 sba
.IndirectObjectBufferSize
= 0xfffff;
137 if (device
->physical
->use_softpin
) {
138 /* With softpin, we use fixed addresses so we actually know how big
139 * our base addresses are.
141 sba
.DynamicStateBufferSize
= DYNAMIC_STATE_POOL_SIZE
/ 4096;
142 sba
.InstructionBufferSize
= INSTRUCTION_STATE_POOL_SIZE
/ 4096;
144 sba
.DynamicStateBufferSize
= 0xfffff;
145 sba
.InstructionBufferSize
= 0xfffff;
147 sba
.GeneralStateBufferSizeModifyEnable
= true;
148 sba
.IndirectObjectBufferSizeModifyEnable
= true;
149 sba
.DynamicStateBufferSizeModifyEnable
= true;
150 sba
.InstructionBuffersizeModifyEnable
= true;
152 /* On gen7, we have upper bounds instead. According to the docs,
153 * setting an upper bound of zero means that no bounds checking is
154 * performed so, in theory, we should be able to leave them zero.
155 * However, border color is broken and the GPU bounds-checks anyway.
156 * To avoid this and other potential problems, we may as well set it
159 sba
.GeneralStateAccessUpperBound
=
160 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
161 sba
.GeneralStateAccessUpperBoundModifyEnable
= true;
162 sba
.DynamicStateAccessUpperBound
=
163 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
164 sba
.DynamicStateAccessUpperBoundModifyEnable
= true;
165 sba
.InstructionAccessUpperBound
=
166 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
167 sba
.InstructionAccessUpperBoundModifyEnable
= true;
170 if (cmd_buffer
->device
->physical
->use_softpin
) {
171 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) {
172 .bo
= device
->surface_state_pool
.block_pool
.bo
,
175 sba
.BindlessSurfaceStateSize
= (1 << 20) - 1;
177 sba
.BindlessSurfaceStateBaseAddress
= ANV_NULL_ADDRESS
;
178 sba
.BindlessSurfaceStateSize
= 0;
180 sba
.BindlessSurfaceStateMOCS
= mocs
;
181 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
184 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
185 sba
.BindlessSamplerStateMOCS
= mocs
;
186 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
187 sba
.BindlessSamplerStateBufferSize
= 0;
192 /* GEN:BUG:1607854226:
194 * Put the pipeline back into its current mode.
196 if (gen12_wa_pipeline
!= UINT32_MAX
)
197 genX(flush_pipeline_select
)(cmd_buffer
, gen12_wa_pipeline
);
200 /* After re-setting the surface state base address, we have to do some
201 * cache flusing so that the sampler engine will pick up the new
202 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
203 * Shared Function > 3D Sampler > State > State Caching (page 96):
205 * Coherency with system memory in the state cache, like the texture
206 * cache is handled partially by software. It is expected that the
207 * command stream or shader will issue Cache Flush operation or
208 * Cache_Flush sampler message to ensure that the L1 cache remains
209 * coherent with system memory.
213 * Whenever the value of the Dynamic_State_Base_Addr,
214 * Surface_State_Base_Addr are altered, the L1 state cache must be
215 * invalidated to ensure the new surface or sampler state is fetched
216 * from system memory.
218 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
219 * which, according the PIPE_CONTROL instruction documentation in the
222 * Setting this bit is independent of any other bit in this packet.
223 * This bit controls the invalidation of the L1 and L2 state caches
224 * at the top of the pipe i.e. at the parsing time.
226 * Unfortunately, experimentation seems to indicate that state cache
227 * invalidation through a PIPE_CONTROL does nothing whatsoever in
228 * regards to surface state and binding tables. In stead, it seems that
229 * invalidating the texture cache is what is actually needed.
231 * XXX: As far as we have been able to determine through
232 * experimentation, shows that flush the texture cache appears to be
233 * sufficient. The theory here is that all of the sampling/rendering
234 * units cache the binding table in the texture cache. However, we have
235 * yet to be able to actually confirm this.
237 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
238 pc
.TextureCacheInvalidationEnable
= true;
239 pc
.ConstantCacheInvalidationEnable
= true;
240 pc
.StateCacheInvalidationEnable
= true;
245 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
246 struct anv_state state
, struct anv_address addr
)
248 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
251 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
252 state
.offset
+ isl_dev
->ss
.addr_offset
,
253 addr
.bo
, addr
.offset
, NULL
);
254 if (result
!= VK_SUCCESS
)
255 anv_batch_set_error(&cmd_buffer
->batch
, result
);
259 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
260 struct anv_surface_state state
)
262 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
264 assert(!anv_address_is_null(state
.address
));
265 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
267 if (!anv_address_is_null(state
.aux_address
)) {
269 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
270 &cmd_buffer
->pool
->alloc
,
271 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
272 state
.aux_address
.bo
,
273 state
.aux_address
.offset
,
275 if (result
!= VK_SUCCESS
)
276 anv_batch_set_error(&cmd_buffer
->batch
, result
);
279 if (!anv_address_is_null(state
.clear_address
)) {
281 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
282 &cmd_buffer
->pool
->alloc
,
284 isl_dev
->ss
.clear_color_state_offset
,
285 state
.clear_address
.bo
,
286 state
.clear_address
.offset
,
288 if (result
!= VK_SUCCESS
)
289 anv_batch_set_error(&cmd_buffer
->batch
, result
);
294 isl_color_value_requires_conversion(union isl_color_value color
,
295 const struct isl_surf
*surf
,
296 const struct isl_view
*view
)
298 if (surf
->format
== view
->format
&& isl_swizzle_is_identity(view
->swizzle
))
301 uint32_t surf_pack
[4] = { 0, 0, 0, 0 };
302 isl_color_value_pack(&color
, surf
->format
, surf_pack
);
304 uint32_t view_pack
[4] = { 0, 0, 0, 0 };
305 union isl_color_value swiz_color
=
306 isl_color_value_swizzle_inv(color
, view
->swizzle
);
307 isl_color_value_pack(&swiz_color
, view
->format
, view_pack
);
309 return memcmp(surf_pack
, view_pack
, sizeof(surf_pack
)) != 0;
313 anv_can_fast_clear_color_view(struct anv_device
* device
,
314 struct anv_image_view
*iview
,
315 VkImageLayout layout
,
316 union isl_color_value clear_color
,
318 VkRect2D render_area
)
320 if (iview
->planes
[0].isl
.base_array_layer
>=
321 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
322 iview
->planes
[0].isl
.base_level
))
325 /* Start by getting the fast clear type. We use the first subpass
326 * layout here because we don't want to fast-clear if the first subpass
327 * to use the attachment can't handle fast-clears.
329 enum anv_fast_clear_type fast_clear_type
=
330 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
331 VK_IMAGE_ASPECT_COLOR_BIT
,
333 switch (fast_clear_type
) {
334 case ANV_FAST_CLEAR_NONE
:
336 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
337 if (!isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
))
340 case ANV_FAST_CLEAR_ANY
:
344 /* Potentially, we could do partial fast-clears but doing so has crazy
345 * alignment restrictions. It's easier to just restrict to full size
346 * fast clears for now.
348 if (render_area
.offset
.x
!= 0 ||
349 render_area
.offset
.y
!= 0 ||
350 render_area
.extent
.width
!= iview
->extent
.width
||
351 render_area
.extent
.height
!= iview
->extent
.height
)
354 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
356 !isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
))
359 /* If the clear color is one that would require non-trivial format
360 * conversion on resolve, we don't bother with the fast clear. This
361 * shouldn't be common as most clear colors are 0/1 and the most common
362 * format re-interpretation is for sRGB.
364 if (isl_color_value_requires_conversion(clear_color
,
365 &iview
->image
->planes
[0].surface
.isl
,
366 &iview
->planes
[0].isl
)) {
367 anv_perf_warn(device
, iview
,
368 "Cannot fast-clear to colors which would require "
369 "format conversion on resolve");
373 /* We only allow fast clears to the first slice of an image (level 0,
374 * layer 0) and only for the entire slice. This guarantees us that, at
375 * any given time, there is only one clear color on any given image at
376 * any given time. At the time of our testing (Jan 17, 2018), there
377 * were no known applications which would benefit from fast-clearing
378 * more than just the first slice.
380 if (iview
->planes
[0].isl
.base_level
> 0 ||
381 iview
->planes
[0].isl
.base_array_layer
> 0) {
382 anv_perf_warn(device
, iview
->image
,
383 "Rendering with multi-lod or multi-layer framebuffer "
384 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
385 "baseArrayLayer > 0. Not fast clearing.");
389 if (num_layers
> 1) {
390 anv_perf_warn(device
, iview
->image
,
391 "Rendering to a multi-layer framebuffer with "
392 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
399 anv_can_hiz_clear_ds_view(struct anv_device
*device
,
400 struct anv_image_view
*iview
,
401 VkImageLayout layout
,
402 VkImageAspectFlags clear_aspects
,
403 float depth_clear_value
,
404 VkRect2D render_area
)
406 /* We don't do any HiZ or depth fast-clears on gen7 yet */
410 /* If we're just clearing stencil, we can always HiZ clear */
411 if (!(clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
414 /* We must have depth in order to have HiZ */
415 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
418 const enum isl_aux_usage clear_aux_usage
=
419 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
420 VK_IMAGE_ASPECT_DEPTH_BIT
,
421 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
423 if (!blorp_can_hiz_clear_depth(&device
->info
,
424 &iview
->image
->planes
[0].surface
.isl
,
426 iview
->planes
[0].isl
.base_level
,
427 iview
->planes
[0].isl
.base_array_layer
,
428 render_area
.offset
.x
,
429 render_area
.offset
.y
,
430 render_area
.offset
.x
+
431 render_area
.extent
.width
,
432 render_area
.offset
.y
+
433 render_area
.extent
.height
))
436 if (depth_clear_value
!= ANV_HZ_FC_VAL
)
439 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a fast-cleared
440 * portion of a HiZ buffer. Testing has revealed that Gen8 only supports
441 * returning 0.0f. Gens prior to gen8 do not support this feature at all.
443 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
))
446 /* If we got here, then we can fast clear */
450 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
454 anv_image_init_aux_tt(struct anv_cmd_buffer
*cmd_buffer
,
455 const struct anv_image
*image
,
456 VkImageAspectFlagBits aspect
,
457 uint32_t base_level
, uint32_t level_count
,
458 uint32_t base_layer
, uint32_t layer_count
)
460 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
462 uint64_t base_address
=
463 anv_address_physical(image
->planes
[plane
].address
);
465 const struct isl_surf
*isl_surf
= &image
->planes
[plane
].surface
.isl
;
466 uint64_t format_bits
= gen_aux_map_format_bits_for_isl_surf(isl_surf
);
468 /* We're about to live-update the AUX-TT. We really don't want anyone else
469 * trying to read it while we're doing this. We could probably get away
470 * with not having this stall in some cases if we were really careful but
471 * it's better to play it safe. Full stall the GPU.
473 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
474 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
476 struct gen_mi_builder b
;
477 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
479 for (uint32_t a
= 0; a
< layer_count
; a
++) {
480 const uint32_t layer
= base_layer
+ a
;
482 uint64_t start_offset_B
= UINT64_MAX
, end_offset_B
= 0;
483 for (uint32_t l
= 0; l
< level_count
; l
++) {
484 const uint32_t level
= base_level
+ l
;
486 uint32_t logical_array_layer
, logical_z_offset_px
;
487 if (image
->type
== VK_IMAGE_TYPE_3D
) {
488 logical_array_layer
= 0;
490 /* If the given miplevel does not have this layer, then any higher
491 * miplevels won't either because miplevels only get smaller the
494 assert(layer
< image
->extent
.depth
);
495 if (layer
>= anv_minify(image
->extent
.depth
, level
))
497 logical_z_offset_px
= layer
;
499 assert(layer
< image
->array_size
);
500 logical_array_layer
= layer
;
501 logical_z_offset_px
= 0;
504 uint32_t slice_start_offset_B
, slice_end_offset_B
;
505 isl_surf_get_image_range_B_tile(isl_surf
, level
,
508 &slice_start_offset_B
,
509 &slice_end_offset_B
);
511 start_offset_B
= MIN2(start_offset_B
, slice_start_offset_B
);
512 end_offset_B
= MAX2(end_offset_B
, slice_end_offset_B
);
515 /* Aux operates 64K at a time */
516 start_offset_B
= align_down_u64(start_offset_B
, 64 * 1024);
517 end_offset_B
= align_u64(end_offset_B
, 64 * 1024);
519 for (uint64_t offset
= start_offset_B
;
520 offset
< end_offset_B
; offset
+= 64 * 1024) {
521 uint64_t address
= base_address
+ offset
;
523 uint64_t aux_entry_addr64
, *aux_entry_map
;
524 aux_entry_map
= gen_aux_map_get_entry(cmd_buffer
->device
->aux_map_ctx
,
525 address
, &aux_entry_addr64
);
527 assert(cmd_buffer
->device
->physical
->use_softpin
);
528 struct anv_address aux_entry_address
= {
530 .offset
= aux_entry_addr64
,
533 const uint64_t old_aux_entry
= READ_ONCE(*aux_entry_map
);
534 uint64_t new_aux_entry
=
535 (old_aux_entry
& GEN_AUX_MAP_ADDRESS_MASK
) | format_bits
;
537 if (isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
))
538 new_aux_entry
|= GEN_AUX_MAP_ENTRY_VALID_BIT
;
540 gen_mi_store(&b
, gen_mi_mem64(aux_entry_address
),
541 gen_mi_imm(new_aux_entry
));
545 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
;
547 #endif /* GEN_GEN == 12 */
549 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
550 * the initial layout is undefined, the HiZ buffer and depth buffer will
551 * represent the same data at the end of this operation.
554 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
555 const struct anv_image
*image
,
556 uint32_t base_layer
, uint32_t layer_count
,
557 VkImageLayout initial_layout
,
558 VkImageLayout final_layout
)
560 uint32_t depth_plane
=
561 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
562 if (image
->planes
[depth_plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
566 if ((initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
567 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) &&
568 cmd_buffer
->device
->physical
->has_implicit_ccs
&&
569 cmd_buffer
->device
->info
.has_aux_map
) {
570 anv_image_init_aux_tt(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
575 const enum isl_aux_state initial_state
=
576 anv_layout_to_aux_state(&cmd_buffer
->device
->info
, image
,
577 VK_IMAGE_ASPECT_DEPTH_BIT
,
579 const enum isl_aux_state final_state
=
580 anv_layout_to_aux_state(&cmd_buffer
->device
->info
, image
,
581 VK_IMAGE_ASPECT_DEPTH_BIT
,
584 const bool initial_depth_valid
=
585 isl_aux_state_has_valid_primary(initial_state
);
586 const bool initial_hiz_valid
=
587 isl_aux_state_has_valid_aux(initial_state
);
588 const bool final_needs_depth
=
589 isl_aux_state_has_valid_primary(final_state
);
590 const bool final_needs_hiz
=
591 isl_aux_state_has_valid_aux(final_state
);
593 /* Getting into the pass-through state for Depth is tricky and involves
594 * both a resolve and an ambiguate. We don't handle that state right now
595 * as anv_layout_to_aux_state never returns it.
597 assert(final_state
!= ISL_AUX_STATE_PASS_THROUGH
);
599 if (final_needs_depth
&& !initial_depth_valid
) {
600 assert(initial_hiz_valid
);
601 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
602 0, base_layer
, layer_count
, ISL_AUX_OP_FULL_RESOLVE
);
603 } else if (final_needs_hiz
&& !initial_hiz_valid
) {
604 assert(initial_depth_valid
);
605 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
606 0, base_layer
, layer_count
, ISL_AUX_OP_AMBIGUATE
);
611 vk_image_layout_stencil_write_optimal(VkImageLayout layout
)
613 return layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
614 layout
== VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
||
615 layout
== VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
;
618 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
619 * the initial layout is undefined, the HiZ buffer and depth buffer will
620 * represent the same data at the end of this operation.
623 transition_stencil_buffer(struct anv_cmd_buffer
*cmd_buffer
,
624 const struct anv_image
*image
,
625 uint32_t base_level
, uint32_t level_count
,
626 uint32_t base_layer
, uint32_t layer_count
,
627 VkImageLayout initial_layout
,
628 VkImageLayout final_layout
)
631 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
632 VK_IMAGE_ASPECT_STENCIL_BIT
);
634 /* On gen7, we have to store a texturable version of the stencil buffer in
635 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
636 * forth at strategic points. Stencil writes are only allowed in following
639 * - VK_IMAGE_LAYOUT_GENERAL
640 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
641 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
642 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
643 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
645 * For general, we have no nice opportunity to transition so we do the copy
646 * to the shadow unconditionally at the end of the subpass. For transfer
647 * destinations, we can update it as part of the transfer op. For the other
648 * layouts, we delay the copy until a transition into some other layout.
650 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
651 vk_image_layout_stencil_write_optimal(initial_layout
) &&
652 !vk_image_layout_stencil_write_optimal(final_layout
)) {
653 anv_image_copy_to_shadow(cmd_buffer
, image
,
654 VK_IMAGE_ASPECT_STENCIL_BIT
,
655 base_level
, level_count
,
656 base_layer
, layer_count
);
658 #endif /* GEN_GEN == 7 */
661 #define MI_PREDICATE_SRC0 0x2400
662 #define MI_PREDICATE_SRC1 0x2408
663 #define MI_PREDICATE_RESULT 0x2418
666 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
667 const struct anv_image
*image
,
668 VkImageAspectFlagBits aspect
,
670 uint32_t base_layer
, uint32_t layer_count
,
673 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
675 /* We only have compression tracking for CCS_E */
676 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
679 for (uint32_t a
= 0; a
< layer_count
; a
++) {
680 uint32_t layer
= base_layer
+ a
;
681 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
682 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
685 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
691 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
692 const struct anv_image
*image
,
693 VkImageAspectFlagBits aspect
,
694 enum anv_fast_clear_type fast_clear
)
696 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
697 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
699 sdi
.ImmediateData
= fast_clear
;
702 /* Whenever we have fast-clear, we consider that slice to be compressed.
703 * This makes building predicates much easier.
705 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
706 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
709 /* This is only really practical on haswell and above because it requires
710 * MI math in order to get it correct.
712 #if GEN_GEN >= 8 || GEN_IS_HASWELL
714 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
715 const struct anv_image
*image
,
716 VkImageAspectFlagBits aspect
,
717 uint32_t level
, uint32_t array_layer
,
718 enum isl_aux_op resolve_op
,
719 enum anv_fast_clear_type fast_clear_supported
)
721 struct gen_mi_builder b
;
722 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
724 const struct gen_mi_value fast_clear_type
=
725 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
728 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
729 /* In this case, we're doing a full resolve which means we want the
730 * resolve to happen if any compression (including fast-clears) is
733 * In order to simplify the logic a bit, we make the assumption that,
734 * if the first slice has been fast-cleared, it is also marked as
735 * compressed. See also set_image_fast_clear_state.
737 const struct gen_mi_value compression_state
=
738 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer
->device
,
740 level
, array_layer
));
741 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
743 gen_mi_store(&b
, compression_state
, gen_mi_imm(0));
745 if (level
== 0 && array_layer
== 0) {
746 /* If the predicate is true, we want to write 0 to the fast clear type
747 * and, if it's false, leave it alone. We can do this by writing
749 * clear_type = clear_type & ~predicate;
751 struct gen_mi_value new_fast_clear_type
=
752 gen_mi_iand(&b
, fast_clear_type
,
753 gen_mi_inot(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
)));
754 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
756 } else if (level
== 0 && array_layer
== 0) {
757 /* In this case, we are doing a partial resolve to get rid of fast-clear
758 * colors. We don't care about the compression state but we do care
759 * about how much fast clear is allowed by the final layout.
761 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
762 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
764 /* We need to compute (fast_clear_supported < image->fast_clear) */
765 struct gen_mi_value pred
=
766 gen_mi_ult(&b
, gen_mi_imm(fast_clear_supported
), fast_clear_type
);
767 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
768 gen_mi_value_ref(&b
, pred
));
770 /* If the predicate is true, we want to write 0 to the fast clear type
771 * and, if it's false, leave it alone. We can do this by writing
773 * clear_type = clear_type & ~predicate;
775 struct gen_mi_value new_fast_clear_type
=
776 gen_mi_iand(&b
, fast_clear_type
, gen_mi_inot(&b
, pred
));
777 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
779 /* In this case, we're trying to do a partial resolve on a slice that
780 * doesn't have clear color. There's nothing to do.
782 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
786 /* Set src1 to 0 and use a != condition */
787 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
789 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
790 mip
.LoadOperation
= LOAD_LOADINV
;
791 mip
.CombineOperation
= COMBINE_SET
;
792 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
795 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
799 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
800 const struct anv_image
*image
,
801 VkImageAspectFlagBits aspect
,
802 uint32_t level
, uint32_t array_layer
,
803 enum isl_aux_op resolve_op
,
804 enum anv_fast_clear_type fast_clear_supported
)
806 struct gen_mi_builder b
;
807 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
809 struct gen_mi_value fast_clear_type_mem
=
810 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
813 /* This only works for partial resolves and only when the clear color is
814 * all or nothing. On the upside, this emits less command streamer code
815 * and works on Ivybridge and Bay Trail.
817 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
818 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
820 /* We don't support fast clears on anything other than the first slice. */
821 if (level
> 0 || array_layer
> 0)
824 /* On gen8, we don't have a concept of default clear colors because we
825 * can't sample from CCS surfaces. It's enough to just load the fast clear
826 * state into the predicate register.
828 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), fast_clear_type_mem
);
829 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
830 gen_mi_store(&b
, fast_clear_type_mem
, gen_mi_imm(0));
832 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
833 mip
.LoadOperation
= LOAD_LOADINV
;
834 mip
.CombineOperation
= COMBINE_SET
;
835 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
838 #endif /* GEN_GEN <= 8 */
841 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
842 const struct anv_image
*image
,
843 enum isl_format format
,
844 struct isl_swizzle swizzle
,
845 VkImageAspectFlagBits aspect
,
846 uint32_t level
, uint32_t array_layer
,
847 enum isl_aux_op resolve_op
,
848 enum anv_fast_clear_type fast_clear_supported
)
850 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
853 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
854 aspect
, level
, array_layer
,
855 resolve_op
, fast_clear_supported
);
856 #else /* GEN_GEN <= 8 */
857 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
858 aspect
, level
, array_layer
,
859 resolve_op
, fast_clear_supported
);
862 /* CCS_D only supports full resolves and BLORP will assert on us if we try
863 * to do a partial resolve on a CCS_D surface.
865 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
866 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_D
)
867 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
869 anv_image_ccs_op(cmd_buffer
, image
, format
, swizzle
, aspect
,
870 level
, array_layer
, 1, resolve_op
, NULL
, true);
874 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
875 const struct anv_image
*image
,
876 enum isl_format format
,
877 struct isl_swizzle swizzle
,
878 VkImageAspectFlagBits aspect
,
879 uint32_t array_layer
,
880 enum isl_aux_op resolve_op
,
881 enum anv_fast_clear_type fast_clear_supported
)
883 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
884 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
886 #if GEN_GEN >= 8 || GEN_IS_HASWELL
887 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
888 aspect
, 0, array_layer
,
889 resolve_op
, fast_clear_supported
);
891 anv_image_mcs_op(cmd_buffer
, image
, format
, swizzle
, aspect
,
892 array_layer
, 1, resolve_op
, NULL
, true);
894 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
899 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
900 const struct anv_image
*image
,
901 VkImageAspectFlagBits aspect
,
902 enum isl_aux_usage aux_usage
,
905 uint32_t layer_count
)
907 /* The aspect must be exactly one of the image aspects. */
908 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
910 /* The only compression types with more than just fast-clears are MCS,
911 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
912 * track the current fast-clear and compression state. This leaves us
913 * with just MCS and CCS_E.
915 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
916 aux_usage
!= ISL_AUX_USAGE_MCS
)
919 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
920 level
, base_layer
, layer_count
, true);
924 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
925 const struct anv_image
*image
,
926 VkImageAspectFlagBits aspect
)
928 assert(cmd_buffer
&& image
);
929 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
931 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
932 ANV_FAST_CLEAR_NONE
);
934 /* Initialize the struct fields that are accessed for fast-clears so that
935 * the HW restrictions on the field values are satisfied.
937 struct anv_address addr
=
938 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
941 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
942 const unsigned num_dwords
= GEN_GEN
>= 10 ?
943 isl_dev
->ss
.clear_color_state_size
/ 4 :
944 isl_dev
->ss
.clear_value_size
/ 4;
945 for (unsigned i
= 0; i
< num_dwords
; i
++) {
946 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
948 sdi
.Address
.offset
+= i
* 4;
949 sdi
.ImmediateData
= 0;
953 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
955 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
956 /* Pre-SKL, the dword containing the clear values also contains
957 * other fields, so we need to initialize those fields to match the
958 * values that would be in a color attachment.
960 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
961 ISL_CHANNEL_SELECT_GREEN
<< 22 |
962 ISL_CHANNEL_SELECT_BLUE
<< 19 |
963 ISL_CHANNEL_SELECT_ALPHA
<< 16;
964 } else if (GEN_GEN
== 7) {
965 /* On IVB, the dword containing the clear values also contains
966 * other fields that must be zero or can be zero.
968 sdi
.ImmediateData
= 0;
974 /* Copy the fast-clear value dword(s) between a surface state object and an
975 * image's fast clear state buffer.
978 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
979 struct anv_state surface_state
,
980 const struct anv_image
*image
,
981 VkImageAspectFlagBits aspect
,
982 bool copy_from_surface_state
)
984 assert(cmd_buffer
&& image
);
985 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
987 struct anv_address ss_clear_addr
= {
988 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
989 .offset
= surface_state
.offset
+
990 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
992 const struct anv_address entry_addr
=
993 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
994 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
997 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
998 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
999 * in-flight when they are issued even if the memory touched is not
1000 * currently active for rendering. The weird bit is that it is not the
1001 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
1002 * rendering hangs such that the next stalling command after the
1003 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
1005 * It is unclear exactly why this hang occurs. Both MI commands come with
1006 * warnings about the 3D pipeline but that doesn't seem to fully explain
1007 * it. My (Jason's) best theory is that it has something to do with the
1008 * fact that we're using a GPU state register as our temporary and that
1009 * something with reading/writing it is causing problems.
1011 * In order to work around this issue, we emit a PIPE_CONTROL with the
1012 * command streamer stall bit set.
1014 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
1015 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1018 struct gen_mi_builder b
;
1019 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
1021 if (copy_from_surface_state
) {
1022 gen_mi_memcpy(&b
, entry_addr
, ss_clear_addr
, copy_size
);
1024 gen_mi_memcpy(&b
, ss_clear_addr
, entry_addr
, copy_size
);
1026 /* Updating a surface state object may require that the state cache be
1027 * invalidated. From the SKL PRM, Shared Functions -> State -> State
1030 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
1031 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
1032 * modified [...], the L1 state cache must be invalidated to ensure
1033 * the new surface or sampler state is fetched from system memory.
1035 * In testing, SKL doesn't actually seem to need this, but HSW does.
1037 cmd_buffer
->state
.pending_pipe_bits
|=
1038 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1043 * @brief Transitions a color buffer from one layout to another.
1045 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
1048 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
1049 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
1050 * this represents the maximum layers to transition at each
1051 * specified miplevel.
1054 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
1055 const struct anv_image
*image
,
1056 VkImageAspectFlagBits aspect
,
1057 const uint32_t base_level
, uint32_t level_count
,
1058 uint32_t base_layer
, uint32_t layer_count
,
1059 VkImageLayout initial_layout
,
1060 VkImageLayout final_layout
)
1062 struct anv_device
*device
= cmd_buffer
->device
;
1063 const struct gen_device_info
*devinfo
= &device
->info
;
1064 /* Validate the inputs. */
1066 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
1067 /* These values aren't supported for simplicity's sake. */
1068 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
1069 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
1070 /* Ensure the subresource range is valid. */
1071 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
1072 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
1073 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
1074 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
1075 assert(last_level_num
<= image
->levels
);
1076 /* The spec disallows these final layouts. */
1077 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
1078 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
1080 /* No work is necessary if the layout stays the same or if this subresource
1081 * range lacks auxiliary data.
1083 if (initial_layout
== final_layout
)
1086 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
1088 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
1089 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
1090 /* This surface is a linear compressed image with a tiled shadow surface
1091 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
1092 * we need to ensure the shadow copy is up-to-date.
1094 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1095 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
1096 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
1097 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
1099 anv_image_copy_to_shadow(cmd_buffer
, image
,
1100 VK_IMAGE_ASPECT_COLOR_BIT
,
1101 base_level
, level_count
,
1102 base_layer
, layer_count
);
1105 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
1108 assert(image
->planes
[plane
].surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
1110 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
1111 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
1113 if (device
->physical
->has_implicit_ccs
&& devinfo
->has_aux_map
) {
1114 anv_image_init_aux_tt(cmd_buffer
, image
, aspect
,
1115 base_level
, level_count
,
1116 base_layer
, layer_count
);
1119 assert(!(device
->physical
->has_implicit_ccs
&& devinfo
->has_aux_map
));
1122 /* A subresource in the undefined layout may have been aliased and
1123 * populated with any arrangement of bits. Therefore, we must initialize
1124 * the related aux buffer and clear buffer entry with desirable values.
1125 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
1126 * images with VK_IMAGE_TILING_OPTIMAL.
1128 * Initialize the relevant clear buffer entries.
1130 if (base_level
== 0 && base_layer
== 0)
1131 init_fast_clear_color(cmd_buffer
, image
, aspect
);
1133 /* Initialize the aux buffers to enable correct rendering. In order to
1134 * ensure that things such as storage images work correctly, aux buffers
1135 * need to be initialized to valid data.
1137 * Having an aux buffer with invalid data is a problem for two reasons:
1139 * 1) Having an invalid value in the buffer can confuse the hardware.
1140 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1141 * invalid and leads to the hardware doing strange things. It
1142 * doesn't hang as far as we can tell but rendering corruption can
1145 * 2) If this transition is into the GENERAL layout and we then use the
1146 * image as a storage image, then we must have the aux buffer in the
1147 * pass-through state so that, if we then go to texture from the
1148 * image, we get the results of our storage image writes and not the
1149 * fast clear color or other random data.
1151 * For CCS both of the problems above are real demonstrable issues. In
1152 * that case, the only thing we can do is to perform an ambiguate to
1153 * transition the aux surface into the pass-through state.
1155 * For MCS, (2) is never an issue because we don't support multisampled
1156 * storage images. In theory, issue (1) is a problem with MCS but we've
1157 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1158 * theory, be interpreted as something but we don't know that all bit
1159 * patterns are actually valid. For 2x and 8x, you could easily end up
1160 * with the MCS referring to an invalid plane because not all bits of
1161 * the MCS value are actually used. Even though we've never seen issues
1162 * in the wild, it's best to play it safe and initialize the MCS. We
1163 * can use a fast-clear for MCS because we only ever touch from render
1164 * and texture (no image load store).
1166 if (image
->samples
== 1) {
1167 for (uint32_t l
= 0; l
< level_count
; l
++) {
1168 const uint32_t level
= base_level
+ l
;
1170 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1171 if (base_layer
>= aux_layers
)
1172 break; /* We will only get fewer layers as level increases */
1173 uint32_t level_layer_count
=
1174 MIN2(layer_count
, aux_layers
- base_layer
);
1176 anv_image_ccs_op(cmd_buffer
, image
,
1177 image
->planes
[plane
].surface
.isl
.format
,
1178 ISL_SWIZZLE_IDENTITY
,
1179 aspect
, level
, base_layer
, level_layer_count
,
1180 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1182 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1183 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1184 level
, base_layer
, level_layer_count
,
1189 if (image
->samples
== 4 || image
->samples
== 16) {
1190 anv_perf_warn(cmd_buffer
->device
, image
,
1191 "Doing a potentially unnecessary fast-clear to "
1192 "define an MCS buffer.");
1195 assert(base_level
== 0 && level_count
== 1);
1196 anv_image_mcs_op(cmd_buffer
, image
,
1197 image
->planes
[plane
].surface
.isl
.format
,
1198 ISL_SWIZZLE_IDENTITY
,
1199 aspect
, base_layer
, layer_count
,
1200 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1205 const enum isl_aux_usage initial_aux_usage
=
1206 anv_layout_to_aux_usage(devinfo
, image
, aspect
, 0, initial_layout
);
1207 const enum isl_aux_usage final_aux_usage
=
1208 anv_layout_to_aux_usage(devinfo
, image
, aspect
, 0, final_layout
);
1210 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1211 * We can handle transitions between CCS_D/E to and from NONE. What we
1212 * don't yet handle is switching between CCS_E and CCS_D within a given
1213 * image. Doing so in a performant way requires more detailed aux state
1214 * tracking such as what is done in i965. For now, just assume that we
1215 * only have one type of compression.
1217 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1218 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1219 initial_aux_usage
== final_aux_usage
);
1221 /* If initial aux usage is NONE, there is nothing to resolve */
1222 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1225 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1227 /* If the initial layout supports more fast clear than the final layout
1228 * then we need at least a partial resolve.
1230 const enum anv_fast_clear_type initial_fast_clear
=
1231 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1232 const enum anv_fast_clear_type final_fast_clear
=
1233 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1234 if (final_fast_clear
< initial_fast_clear
)
1235 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1237 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1238 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1239 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1241 if (resolve_op
== ISL_AUX_OP_NONE
)
1244 /* Perform a resolve to synchronize data between the main and aux buffer.
1245 * Before we begin, we must satisfy the cache flushing requirement specified
1246 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1248 * Any transition from any value in {Clear, Render, Resolve} to a
1249 * different value in {Clear, Render, Resolve} requires end of pipe
1252 * We perform a flush of the write cache before and after the clear and
1253 * resolve operations to meet this requirement.
1255 * Unlike other drawing, fast clear operations are not properly
1256 * synchronized. The first PIPE_CONTROL here likely ensures that the
1257 * contents of the previous render or clear hit the render target before we
1258 * resolve and the second likely ensures that the resolve is complete before
1259 * we do any more rendering or clearing.
1261 cmd_buffer
->state
.pending_pipe_bits
|=
1262 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
1264 for (uint32_t l
= 0; l
< level_count
; l
++) {
1265 uint32_t level
= base_level
+ l
;
1267 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1268 if (base_layer
>= aux_layers
)
1269 break; /* We will only get fewer layers as level increases */
1270 uint32_t level_layer_count
=
1271 MIN2(layer_count
, aux_layers
- base_layer
);
1273 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1274 uint32_t array_layer
= base_layer
+ a
;
1275 if (image
->samples
== 1) {
1276 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1277 image
->planes
[plane
].surface
.isl
.format
,
1278 ISL_SWIZZLE_IDENTITY
,
1279 aspect
, level
, array_layer
, resolve_op
,
1282 /* We only support fast-clear on the first layer so partial
1283 * resolves should not be used on other layers as they will use
1284 * the clear color stored in memory that is only valid for layer0.
1286 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1290 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1291 image
->planes
[plane
].surface
.isl
.format
,
1292 ISL_SWIZZLE_IDENTITY
,
1293 aspect
, array_layer
, resolve_op
,
1299 cmd_buffer
->state
.pending_pipe_bits
|=
1300 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
1304 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1305 const struct anv_render_pass
*pass
,
1306 const struct anv_framebuffer
*framebuffer
,
1307 const VkRenderPassBeginInfo
*begin
)
1309 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1311 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1313 if (pass
->attachment_count
> 0) {
1314 state
->attachments
= vk_zalloc(&cmd_buffer
->pool
->alloc
,
1315 pass
->attachment_count
*
1316 sizeof(state
->attachments
[0]),
1317 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1318 if (state
->attachments
== NULL
) {
1319 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1320 return anv_batch_set_error(&cmd_buffer
->batch
,
1321 VK_ERROR_OUT_OF_HOST_MEMORY
);
1324 state
->attachments
= NULL
;
1327 const VkRenderPassAttachmentBeginInfoKHR
*attach_begin
=
1328 vk_find_struct_const(begin
, RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR
);
1329 if (begin
&& !attach_begin
)
1330 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1332 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1333 if (attach_begin
&& attach_begin
->attachmentCount
!= 0) {
1334 assert(attach_begin
->attachmentCount
== pass
->attachment_count
);
1335 ANV_FROM_HANDLE(anv_image_view
, iview
, attach_begin
->pAttachments
[i
]);
1336 state
->attachments
[i
].image_view
= iview
;
1337 } else if (framebuffer
&& i
< framebuffer
->attachment_count
) {
1338 state
->attachments
[i
].image_view
= framebuffer
->attachments
[i
];
1340 state
->attachments
[i
].image_view
= NULL
;
1345 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1346 const struct anv_render_pass_attachment
*pass_att
= &pass
->attachments
[i
];
1347 struct anv_attachment_state
*att_state
= &state
->attachments
[i
];
1348 VkImageAspectFlags att_aspects
= vk_format_aspects(pass_att
->format
);
1349 VkImageAspectFlags clear_aspects
= 0;
1350 VkImageAspectFlags load_aspects
= 0;
1352 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1353 /* color attachment */
1354 if (pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1355 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1356 } else if (pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1357 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1360 /* depthstencil attachment */
1361 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1362 if (pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1363 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1364 } else if (pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1365 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1368 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1369 if (pass_att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1370 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1371 } else if (pass_att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1372 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1377 att_state
->current_layout
= pass_att
->initial_layout
;
1378 att_state
->current_stencil_layout
= pass_att
->stencil_initial_layout
;
1379 att_state
->pending_clear_aspects
= clear_aspects
;
1380 att_state
->pending_load_aspects
= load_aspects
;
1382 att_state
->clear_value
= begin
->pClearValues
[i
];
1384 struct anv_image_view
*iview
= state
->attachments
[i
].image_view
;
1385 anv_assert(iview
->vk_format
== pass_att
->format
);
1387 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1388 att_state
->pending_clear_views
= (1 << num_layers
) - 1;
1390 /* This will be initialized after the first subpass transition. */
1391 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
1393 att_state
->fast_clear
= false;
1394 if (clear_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1395 assert(clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1396 att_state
->fast_clear
=
1397 anv_can_fast_clear_color_view(cmd_buffer
->device
, iview
,
1398 pass_att
->first_subpass_layout
,
1399 vk_to_isl_color(att_state
->clear_value
.color
),
1400 framebuffer
->layers
,
1402 } else if (clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
1403 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
1404 att_state
->fast_clear
=
1405 anv_can_hiz_clear_ds_view(cmd_buffer
->device
, iview
,
1406 pass_att
->first_subpass_layout
,
1408 att_state
->clear_value
.depthStencil
.depth
,
1418 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1421 genX(cmd_buffer_alloc_att_surf_states
)(struct anv_cmd_buffer
*cmd_buffer
,
1422 const struct anv_render_pass
*pass
,
1423 const struct anv_subpass
*subpass
)
1425 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1426 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1428 /* Reserve one for the NULL state. */
1429 unsigned num_states
= 1;
1430 for (uint32_t i
= 0; i
< subpass
->attachment_count
; i
++) {
1431 uint32_t att
= subpass
->attachments
[i
].attachment
;
1432 if (att
== VK_ATTACHMENT_UNUSED
)
1435 assert(att
< pass
->attachment_count
);
1436 if (!vk_format_is_color(pass
->attachments
[att
].format
))
1439 const VkImageUsageFlagBits att_usage
= subpass
->attachments
[i
].usage
;
1440 assert(util_bitcount(att_usage
) == 1);
1442 if (att_usage
== VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
||
1443 att_usage
== VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)
1447 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1448 state
->attachment_states
=
1449 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1450 num_states
* ss_stride
, isl_dev
->ss
.align
);
1451 if (state
->attachment_states
.map
== NULL
) {
1452 return anv_batch_set_error(&cmd_buffer
->batch
,
1453 VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1456 struct anv_state next_state
= state
->attachment_states
;
1457 next_state
.alloc_size
= isl_dev
->ss
.size
;
1459 state
->null_surface_state
= next_state
;
1460 next_state
.offset
+= ss_stride
;
1461 next_state
.map
+= ss_stride
;
1463 for (uint32_t i
= 0; i
< subpass
->attachment_count
; i
++) {
1464 uint32_t att
= subpass
->attachments
[i
].attachment
;
1465 if (att
== VK_ATTACHMENT_UNUSED
)
1468 assert(att
< pass
->attachment_count
);
1469 if (!vk_format_is_color(pass
->attachments
[att
].format
))
1472 const VkImageUsageFlagBits att_usage
= subpass
->attachments
[i
].usage
;
1473 assert(util_bitcount(att_usage
) == 1);
1475 if (att_usage
== VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
)
1476 state
->attachments
[att
].color
.state
= next_state
;
1477 else if (att_usage
== VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)
1478 state
->attachments
[att
].input
.state
= next_state
;
1482 state
->attachments
[att
].color
.state
= next_state
;
1483 next_state
.offset
+= ss_stride
;
1484 next_state
.map
+= ss_stride
;
1487 assert(next_state
.offset
== state
->attachment_states
.offset
+
1488 state
->attachment_states
.alloc_size
);
1494 genX(BeginCommandBuffer
)(
1495 VkCommandBuffer commandBuffer
,
1496 const VkCommandBufferBeginInfo
* pBeginInfo
)
1498 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1500 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1501 * command buffer's state. Otherwise, we must *reset* its state. In both
1502 * cases we reset it.
1504 * From the Vulkan 1.0 spec:
1506 * If a command buffer is in the executable state and the command buffer
1507 * was allocated from a command pool with the
1508 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1509 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1510 * as if vkResetCommandBuffer had been called with
1511 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1512 * the command buffer in the recording state.
1514 anv_cmd_buffer_reset(cmd_buffer
);
1516 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1518 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1519 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1521 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1523 /* We sometimes store vertex data in the dynamic state buffer for blorp
1524 * operations and our dynamic state stream may re-use data from previous
1525 * command buffers. In order to prevent stale cache data, we flush the VF
1526 * cache. We could do this on every blorp call but that's not really
1527 * needed as all of the data will get written by the CPU prior to the GPU
1528 * executing anything. The chances are fairly high that they will use
1529 * blorp at least once per primary command buffer so it shouldn't be
1532 * There is also a workaround on gen8 which requires us to invalidate the
1533 * VF cache occasionally. It's easier if we can assume we start with a
1534 * fresh cache (See also genX(cmd_buffer_set_binding_for_gen8_vb_flush).)
1536 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1538 /* Re-emit the aux table register in every command buffer. This way we're
1539 * ensured that we have the table even if this command buffer doesn't
1540 * initialize any images.
1542 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
;
1544 /* We send an "Indirect State Pointers Disable" packet at
1545 * EndCommandBuffer, so all push contant packets are ignored during a
1546 * context restore. Documentation says after that command, we need to
1547 * emit push constants again before any rendering operation. So we
1548 * flag them dirty here to make sure they get emitted.
1550 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1552 VkResult result
= VK_SUCCESS
;
1553 if (cmd_buffer
->usage_flags
&
1554 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1555 assert(pBeginInfo
->pInheritanceInfo
);
1556 ANV_FROM_HANDLE(anv_render_pass
, pass
,
1557 pBeginInfo
->pInheritanceInfo
->renderPass
);
1558 struct anv_subpass
*subpass
=
1559 &pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1560 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
,
1561 pBeginInfo
->pInheritanceInfo
->framebuffer
);
1563 cmd_buffer
->state
.pass
= pass
;
1564 cmd_buffer
->state
.subpass
= subpass
;
1566 /* This is optional in the inheritance info. */
1567 cmd_buffer
->state
.framebuffer
= framebuffer
;
1569 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
,
1571 if (result
!= VK_SUCCESS
)
1574 result
= genX(cmd_buffer_alloc_att_surf_states
)(cmd_buffer
, pass
,
1576 if (result
!= VK_SUCCESS
)
1579 /* Record that HiZ is enabled if we can. */
1580 if (cmd_buffer
->state
.framebuffer
) {
1581 const struct anv_image_view
* const iview
=
1582 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1585 VkImageLayout layout
=
1586 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1588 enum isl_aux_usage aux_usage
=
1589 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1590 VK_IMAGE_ASPECT_DEPTH_BIT
,
1591 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
1594 cmd_buffer
->state
.hiz_enabled
= isl_aux_usage_has_hiz(aux_usage
);
1598 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1601 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1602 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1603 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1604 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1606 /* If secondary buffer supports conditional rendering
1607 * we should emit commands as if conditional rendering is enabled.
1609 cmd_buffer
->state
.conditional_render_enabled
=
1610 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1617 /* From the PRM, Volume 2a:
1619 * "Indirect State Pointers Disable
1621 * At the completion of the post-sync operation associated with this pipe
1622 * control packet, the indirect state pointers in the hardware are
1623 * considered invalid; the indirect pointers are not saved in the context.
1624 * If any new indirect state commands are executed in the command stream
1625 * while the pipe control is pending, the new indirect state commands are
1628 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1629 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1630 * commands are only considered as Indirect State Pointers. Once ISP is
1631 * issued in a context, SW must initialize by programming push constant
1632 * commands for all the shaders (at least to zero length) before attempting
1633 * any rendering operation for the same context."
1635 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1636 * even though they point to a BO that has been already unreferenced at
1637 * the end of the previous batch buffer. This has been fine so far since
1638 * we are protected by these scratch page (every address not covered by
1639 * a BO should be pointing to the scratch page). But on CNL, it is
1640 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1643 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1644 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1645 * context restore, so the mentioned hang doesn't happen. However,
1646 * software must program push constant commands for all stages prior to
1647 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1649 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1650 * constants have been loaded into the EUs prior to disable the push constants
1651 * so that it doesn't hang a previous 3DPRIMITIVE.
1654 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1656 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1657 pc
.StallAtPixelScoreboard
= true;
1658 pc
.CommandStreamerStallEnable
= true;
1660 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1661 pc
.IndirectStatePointersDisable
= true;
1662 pc
.CommandStreamerStallEnable
= true;
1667 genX(EndCommandBuffer
)(
1668 VkCommandBuffer commandBuffer
)
1670 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1672 if (anv_batch_has_error(&cmd_buffer
->batch
))
1673 return cmd_buffer
->batch
.status
;
1675 /* We want every command buffer to start with the PMA fix in a known state,
1676 * so we disable it at the end of the command buffer.
1678 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1680 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1682 emit_isp_disable(cmd_buffer
);
1684 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1690 genX(CmdExecuteCommands
)(
1691 VkCommandBuffer commandBuffer
,
1692 uint32_t commandBufferCount
,
1693 const VkCommandBuffer
* pCmdBuffers
)
1695 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1697 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1699 if (anv_batch_has_error(&primary
->batch
))
1702 /* The secondary command buffers will assume that the PMA fix is disabled
1703 * when they begin executing. Make sure this is true.
1705 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1707 /* The secondary command buffer doesn't know which textures etc. have been
1708 * flushed prior to their execution. Apply those flushes now.
1710 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1712 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1713 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1715 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1716 assert(!anv_batch_has_error(&secondary
->batch
));
1718 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1719 if (secondary
->state
.conditional_render_enabled
) {
1720 if (!primary
->state
.conditional_render_enabled
) {
1721 /* Secondary buffer is constructed as if it will be executed
1722 * with conditional rendering, we should satisfy this dependency
1723 * regardless of conditional rendering being enabled in primary.
1725 struct gen_mi_builder b
;
1726 gen_mi_builder_init(&b
, &primary
->batch
);
1727 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
1728 gen_mi_imm(UINT64_MAX
));
1733 if (secondary
->usage_flags
&
1734 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1735 /* If we're continuing a render pass from the primary, we need to
1736 * copy the surface states for the current subpass into the storage
1737 * we allocated for them in BeginCommandBuffer.
1739 struct anv_bo
*ss_bo
=
1740 primary
->device
->surface_state_pool
.block_pool
.bo
;
1741 struct anv_state src_state
= primary
->state
.attachment_states
;
1742 struct anv_state dst_state
= secondary
->state
.attachment_states
;
1743 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1745 genX(cmd_buffer_so_memcpy
)(primary
,
1746 (struct anv_address
) {
1748 .offset
= dst_state
.offset
,
1750 (struct anv_address
) {
1752 .offset
= src_state
.offset
,
1754 src_state
.alloc_size
);
1757 anv_cmd_buffer_add_secondary(primary
, secondary
);
1760 /* The secondary isn't counted in our VF cache tracking so we need to
1761 * invalidate the whole thing.
1763 if (GEN_GEN
>= 8 && GEN_GEN
<= 9) {
1764 primary
->state
.pending_pipe_bits
|=
1765 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1768 /* The secondary may have selected a different pipeline (3D or compute) and
1769 * may have changed the current L3$ configuration. Reset our tracking
1770 * variables to invalid values to ensure that we re-emit these in the case
1771 * where we do any draws or compute dispatches from the primary after the
1772 * secondary has returned.
1774 primary
->state
.current_pipeline
= UINT32_MAX
;
1775 primary
->state
.current_l3_config
= NULL
;
1776 primary
->state
.current_hash_scale
= 0;
1778 /* Each of the secondary command buffers will use its own state base
1779 * address. We need to re-emit state base address for the primary after
1780 * all of the secondaries are done.
1782 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1785 genX(cmd_buffer_emit_state_base_address
)(primary
);
1788 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1789 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1790 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1793 * Program the hardware to use the specified L3 configuration.
1796 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1797 const struct gen_l3_config
*cfg
)
1800 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1803 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1804 intel_logd("L3 config transition: ");
1805 gen_dump_l3_config(cfg
, stderr
);
1808 UNUSED
const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1810 /* According to the hardware docs, the L3 partitioning can only be changed
1811 * while the pipeline is completely drained and the caches are flushed,
1812 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1814 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1815 pc
.DCFlushEnable
= true;
1816 pc
.PostSyncOperation
= NoWrite
;
1817 pc
.CommandStreamerStallEnable
= true;
1820 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1821 * invalidation of the relevant caches. Note that because RO invalidation
1822 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1823 * command is processed by the CS) we cannot combine it with the previous
1824 * stalling flush as the hardware documentation suggests, because that
1825 * would cause the CS to stall on previous rendering *after* RO
1826 * invalidation and wouldn't prevent the RO caches from being polluted by
1827 * concurrent rendering before the stall completes. This intentionally
1828 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1829 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1830 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1831 * already guarantee that there is no concurrent GPGPU kernel execution
1832 * (see SKL HSD 2132585).
1834 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1835 pc
.TextureCacheInvalidationEnable
= true;
1836 pc
.ConstantCacheInvalidationEnable
= true;
1837 pc
.InstructionCacheInvalidateEnable
= true;
1838 pc
.StateCacheInvalidationEnable
= true;
1839 pc
.PostSyncOperation
= NoWrite
;
1842 /* Now send a third stalling flush to make sure that invalidation is
1843 * complete when the L3 configuration registers are modified.
1845 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1846 pc
.DCFlushEnable
= true;
1847 pc
.PostSyncOperation
= NoWrite
;
1848 pc
.CommandStreamerStallEnable
= true;
1853 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1856 #define L3_ALLOCATION_REG GENX(L3ALLOC)
1857 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
1859 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
1860 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
1864 anv_pack_struct(&l3cr
, L3_ALLOCATION_REG
,
1866 .SLMEnable
= has_slm
,
1869 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1870 * in L3CNTLREG register. The default setting of the bit is not the
1871 * desirable behavior.
1873 .ErrorDetectionBehaviorControl
= true,
1874 .UseFullWays
= true,
1876 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1877 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1878 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1879 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1881 /* Set up the L3 partitioning. */
1882 emit_lri(&cmd_buffer
->batch
, L3_ALLOCATION_REG_num
, l3cr
);
1886 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1887 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1888 cfg
->n
[GEN_L3P_ALL
];
1889 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1890 cfg
->n
[GEN_L3P_ALL
];
1891 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1892 cfg
->n
[GEN_L3P_ALL
];
1894 assert(!cfg
->n
[GEN_L3P_ALL
]);
1896 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1897 * the matching space on the remaining banks has to be allocated to a
1898 * client (URB for all validated configurations) set to the
1899 * lower-bandwidth 2-bank address hashing mode.
1901 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1902 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1903 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1905 /* Minimum number of ways that can be allocated to the URB. */
1906 const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1907 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1909 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1910 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1911 .ConvertDC_UC
= !has_dc
,
1912 .ConvertIS_UC
= !has_is
,
1913 .ConvertC_UC
= !has_c
,
1914 .ConvertT_UC
= !has_t
);
1916 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1917 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1918 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1920 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1921 .SLMEnable
= has_slm
,
1922 .URBLowBandwidth
= urb_low_bw
,
1923 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1925 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1927 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1928 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1930 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1931 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1932 .ISLowBandwidth
= 0,
1933 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1935 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1936 .TLowBandwidth
= 0);
1938 /* Set up the L3 partitioning. */
1939 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1940 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1941 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1944 if (cmd_buffer
->device
->physical
->cmd_parser_version
>= 4) {
1945 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1946 * them disabled to avoid crashing the system hard.
1948 uint32_t scratch1
, chicken3
;
1949 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1950 .L3AtomicDisable
= !has_dc
);
1951 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1952 .L3AtomicDisableMask
= true,
1953 .L3AtomicDisable
= !has_dc
);
1954 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1955 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1961 cmd_buffer
->state
.current_l3_config
= cfg
;
1965 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1967 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1968 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1970 if (cmd_buffer
->device
->physical
->always_flush_cache
)
1971 bits
|= ANV_PIPE_FLUSH_BITS
| ANV_PIPE_INVALIDATE_BITS
;
1974 * From Sandybridge PRM, volume 2, "1.7.2 End-of-Pipe Synchronization":
1976 * Write synchronization is a special case of end-of-pipe
1977 * synchronization that requires that the render cache and/or depth
1978 * related caches are flushed to memory, where the data will become
1979 * globally visible. This type of synchronization is required prior to
1980 * SW (CPU) actually reading the result data from memory, or initiating
1981 * an operation that will use as a read surface (such as a texture
1982 * surface) a previous render target and/or depth/stencil buffer
1985 * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
1987 * Exercising the write cache flush bits (Render Target Cache Flush
1988 * Enable, Depth Cache Flush Enable, DC Flush) in PIPE_CONTROL only
1989 * ensures the write caches are flushed and doesn't guarantee the data
1990 * is globally visible.
1992 * SW can track the completion of the end-of-pipe-synchronization by
1993 * using "Notify Enable" and "PostSync Operation - Write Immediate
1994 * Data" in the PIPE_CONTROL command.
1996 * In other words, flushes are pipelined while invalidations are handled
1997 * immediately. Therefore, if we're flushing anything then we need to
1998 * schedule an end-of-pipe sync before any invalidations can happen.
2000 if (bits
& ANV_PIPE_FLUSH_BITS
)
2001 bits
|= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2004 /* HSD 1209978178: docs say that before programming the aux table:
2006 * "Driver must ensure that the engine is IDLE but ensure it doesn't
2007 * add extra flushes in the case it knows that the engine is already
2010 if (GEN_GEN
== 12 && (bits
& ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
))
2011 bits
|= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2013 /* If we're going to do an invalidate and we have a pending end-of-pipe
2014 * sync that has yet to be resolved, we do the end-of-pipe sync now.
2016 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
2017 (bits
& ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
)) {
2018 bits
|= ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
2019 bits
&= ~ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2022 if (GEN_GEN
>= 12 &&
2023 ((bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
) ||
2024 (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
))) {
2025 /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
2028 * Unified Cache (Tile Cache Disabled):
2030 * When the Color and Depth (Z) streams are enabled to be cached in
2031 * the DC space of L2, Software must use "Render Target Cache Flush
2032 * Enable" and "Depth Cache Flush Enable" along with "Tile Cache
2033 * Flush" for getting the color and depth (Z) write data to be
2034 * globally observable. In this mode of operation it is not required
2035 * to set "CS Stall" upon setting "Tile Cache Flush" bit.
2037 bits
|= ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
2040 /* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which
2041 * invalidates the instruction cache
2043 if (GEN_GEN
== 12 && (bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
))
2044 bits
|= ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
2046 if ((GEN_GEN
>= 8 && GEN_GEN
<= 9) &&
2047 (bits
& ANV_PIPE_CS_STALL_BIT
) &&
2048 (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
)) {
2049 /* If we are doing a VF cache invalidate AND a CS stall (it must be
2050 * both) then we can reset our vertex cache tracking.
2052 memset(cmd_buffer
->state
.gfx
.vb_dirty_ranges
, 0,
2053 sizeof(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
2054 memset(&cmd_buffer
->state
.gfx
.ib_dirty_range
, 0,
2055 sizeof(cmd_buffer
->state
.gfx
.ib_dirty_range
));
2058 /* Project: SKL / Argument: LRI Post Sync Operation [23]
2060 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
2061 * programmed prior to programming a PIPECONTROL command with "LRI
2062 * Post Sync Operation" in GPGPU mode of operation (i.e when
2063 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
2065 * The same text exists a few rows below for Post Sync Op.
2067 * On Gen12 this is GEN:BUG:1607156449.
2069 if (bits
& ANV_PIPE_POST_SYNC_BIT
) {
2070 if ((GEN_GEN
== 9 || (GEN_GEN
== 12 && devinfo
->revision
== 0 /* A0 */)) &&
2071 cmd_buffer
->state
.current_pipeline
== GPGPU
)
2072 bits
|= ANV_PIPE_CS_STALL_BIT
;
2073 bits
&= ~ANV_PIPE_POST_SYNC_BIT
;
2076 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
|
2077 ANV_PIPE_END_OF_PIPE_SYNC_BIT
)) {
2078 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2080 pipe
.TileCacheFlushEnable
= bits
& ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
2082 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2083 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2084 pipe
.RenderTargetCacheFlushEnable
=
2085 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2087 /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
2088 * be set with any PIPE_CONTROL with Depth Flush Enable bit set.
2091 pipe
.DepthStallEnable
=
2092 pipe
.DepthCacheFlushEnable
|| (bits
& ANV_PIPE_DEPTH_STALL_BIT
);
2094 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
2097 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
2098 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
2100 /* From Sandybridge PRM, volume 2, "1.7.3.1 Writing a Value to Memory":
2102 * "The most common action to perform upon reaching a
2103 * synchronization point is to write a value out to memory. An
2104 * immediate value (included with the synchronization command) may
2108 * From Broadwell PRM, volume 7, "End-of-Pipe Synchronization":
2110 * "In case the data flushed out by the render engine is to be
2111 * read back in to the render engine in coherent manner, then the
2112 * render engine has to wait for the fence completion before
2113 * accessing the flushed data. This can be achieved by following
2114 * means on various products: PIPE_CONTROL command with CS Stall
2115 * and the required write caches flushed with Post-Sync-Operation
2116 * as Write Immediate Data.
2119 * - Workload-1 (3D/GPGPU/MEDIA)
2120 * - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write
2121 * Immediate Data, Required Write Cache Flush bits set)
2122 * - Workload-2 (Can use the data produce or output by
2125 if (bits
& ANV_PIPE_END_OF_PIPE_SYNC_BIT
) {
2126 pipe
.CommandStreamerStallEnable
= true;
2127 pipe
.PostSyncOperation
= WriteImmediateData
;
2128 pipe
.Address
= (struct anv_address
) {
2129 .bo
= cmd_buffer
->device
->workaround_bo
,
2135 * According to the Broadwell documentation, any PIPE_CONTROL with the
2136 * "Command Streamer Stall" bit set must also have another bit set,
2137 * with five different options:
2139 * - Render Target Cache Flush
2140 * - Depth Cache Flush
2141 * - Stall at Pixel Scoreboard
2142 * - Post-Sync Operation
2146 * I chose "Stall at Pixel Scoreboard" since that's what we use in
2147 * mesa and it seems to work fine. The choice is fairly arbitrary.
2149 if (pipe
.CommandStreamerStallEnable
&&
2150 !pipe
.RenderTargetCacheFlushEnable
&&
2151 !pipe
.DepthCacheFlushEnable
&&
2152 !pipe
.StallAtPixelScoreboard
&&
2153 !pipe
.PostSyncOperation
&&
2154 !pipe
.DepthStallEnable
&&
2155 !pipe
.DCFlushEnable
)
2156 pipe
.StallAtPixelScoreboard
= true;
2159 /* If a render target flush was emitted, then we can toggle off the bit
2160 * saying that render target writes are ongoing.
2162 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
2163 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
2165 if (GEN_IS_HASWELL
) {
2166 /* Haswell needs addition work-arounds:
2168 * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
2171 * PIPE_CONTROL command with the CS Stall and the required write
2172 * caches flushed with Post-SyncOperation as Write Immediate Data
2173 * followed by eight dummy MI_STORE_DATA_IMM (write to scratch
2178 * - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write
2179 * Immediate Data, Required Write Cache Flush bits set)
2180 * - MI_STORE_DATA_IMM (8 times) (Dummy data, Scratch Address)
2181 * - Workload-2 (Can use the data produce or output by
2184 * Unfortunately, both the PRMs and the internal docs are a bit
2185 * out-of-date in this regard. What the windows driver does (and
2186 * this appears to actually work) is to emit a register read from the
2187 * memory address written by the pipe control above.
2189 * What register we load into doesn't matter. We choose an indirect
2190 * rendering register because we know it always exists and it's one
2191 * of the first registers the command parser allows us to write. If
2192 * you don't have command parser support in your kernel (pre-4.2),
2193 * this will get turned into MI_NOOP and you won't get the
2194 * workaround. Unfortunately, there's just not much we can do in
2195 * that case. This register is perfectly safe to write since we
2196 * always re-load all of the indirect draw registers right before
2197 * 3DPRIMITIVE when needed anyway.
2199 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2200 lrm
.RegisterAddress
= 0x243C; /* GEN7_3DPRIM_START_INSTANCE */
2201 lrm
.MemoryAddress
= (struct anv_address
) {
2202 .bo
= cmd_buffer
->device
->workaround_bo
,
2208 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
|
2209 ANV_PIPE_END_OF_PIPE_SYNC_BIT
);
2212 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
2213 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
2215 * "If the VF Cache Invalidation Enable is set to a 1 in a
2216 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
2217 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
2218 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
2221 * This appears to hang Broadwell, so we restrict it to just gen9.
2223 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
2224 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
2226 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2227 pipe
.StateCacheInvalidationEnable
=
2228 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
2229 pipe
.ConstantCacheInvalidationEnable
=
2230 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2231 pipe
.VFCacheInvalidationEnable
=
2232 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2233 pipe
.TextureCacheInvalidationEnable
=
2234 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2235 pipe
.InstructionCacheInvalidateEnable
=
2236 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
2238 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
2240 * "When VF Cache Invalidate is set “Post Sync Operation” must be
2241 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
2242 * “Write Timestamp”.
2244 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
2245 pipe
.PostSyncOperation
= WriteImmediateData
;
2247 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
2252 if ((bits
& ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
) &&
2253 cmd_buffer
->device
->info
.has_aux_map
) {
2254 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
2255 lri
.RegisterOffset
= GENX(GFX_CCS_AUX_INV_num
);
2261 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
2264 cmd_buffer
->state
.pending_pipe_bits
= bits
;
2267 void genX(CmdPipelineBarrier
)(
2268 VkCommandBuffer commandBuffer
,
2269 VkPipelineStageFlags srcStageMask
,
2270 VkPipelineStageFlags destStageMask
,
2272 uint32_t memoryBarrierCount
,
2273 const VkMemoryBarrier
* pMemoryBarriers
,
2274 uint32_t bufferMemoryBarrierCount
,
2275 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
2276 uint32_t imageMemoryBarrierCount
,
2277 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
2279 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2281 /* XXX: Right now, we're really dumb and just flush whatever categories
2282 * the app asks for. One of these days we may make this a bit better
2283 * but right now that's all the hardware allows for in most areas.
2285 VkAccessFlags src_flags
= 0;
2286 VkAccessFlags dst_flags
= 0;
2288 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
2289 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
2290 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
2293 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
2294 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
2295 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
2298 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
2299 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
2300 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
2301 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
2302 const VkImageSubresourceRange
*range
=
2303 &pImageMemoryBarriers
[i
].subresourceRange
;
2305 uint32_t base_layer
, layer_count
;
2306 if (image
->type
== VK_IMAGE_TYPE_3D
) {
2308 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
2310 base_layer
= range
->baseArrayLayer
;
2311 layer_count
= anv_get_layerCount(image
, range
);
2314 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
2315 transition_depth_buffer(cmd_buffer
, image
,
2316 base_layer
, layer_count
,
2317 pImageMemoryBarriers
[i
].oldLayout
,
2318 pImageMemoryBarriers
[i
].newLayout
);
2321 if (range
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
2322 transition_stencil_buffer(cmd_buffer
, image
,
2323 range
->baseMipLevel
,
2324 anv_get_levelCount(image
, range
),
2325 base_layer
, layer_count
,
2326 pImageMemoryBarriers
[i
].oldLayout
,
2327 pImageMemoryBarriers
[i
].newLayout
);
2330 if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
2331 VkImageAspectFlags color_aspects
=
2332 anv_image_expand_aspects(image
, range
->aspectMask
);
2333 uint32_t aspect_bit
;
2334 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
2335 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
2336 range
->baseMipLevel
,
2337 anv_get_levelCount(image
, range
),
2338 base_layer
, layer_count
,
2339 pImageMemoryBarriers
[i
].oldLayout
,
2340 pImageMemoryBarriers
[i
].newLayout
);
2345 cmd_buffer
->state
.pending_pipe_bits
|=
2346 anv_pipe_flush_bits_for_access_flags(src_flags
) |
2347 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
2351 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
2353 VkShaderStageFlags stages
=
2354 cmd_buffer
->state
.gfx
.pipeline
->active_stages
;
2356 /* In order to avoid thrash, we assume that vertex and fragment stages
2357 * always exist. In the rare case where one is missing *and* the other
2358 * uses push concstants, this may be suboptimal. However, avoiding stalls
2359 * seems more important.
2361 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
2363 if (stages
== cmd_buffer
->state
.push_constant_stages
)
2367 const unsigned push_constant_kb
= 32;
2368 #elif GEN_IS_HASWELL
2369 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
2371 const unsigned push_constant_kb
= 16;
2374 const unsigned num_stages
=
2375 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
2376 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
2378 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
2379 * units of 2KB. Incidentally, these are the same platforms that have
2380 * 32KB worth of push constant space.
2382 if (push_constant_kb
== 32)
2383 size_per_stage
&= ~1u;
2385 uint32_t kb_used
= 0;
2386 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
2387 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
2388 anv_batch_emit(&cmd_buffer
->batch
,
2389 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
2390 alloc
._3DCommandSubOpcode
= 18 + i
;
2391 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
2392 alloc
.ConstantBufferSize
= push_size
;
2394 kb_used
+= push_size
;
2397 anv_batch_emit(&cmd_buffer
->batch
,
2398 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
2399 alloc
.ConstantBufferOffset
= kb_used
;
2400 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
2403 cmd_buffer
->state
.push_constant_stages
= stages
;
2405 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
2407 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
2408 * the next 3DPRIMITIVE command after programming the
2409 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
2411 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
2412 * pipeline setup, we need to dirty push constants.
2414 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
2417 static struct anv_address
2418 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
2419 struct anv_descriptor_set
*set
)
2422 /* This is a normal descriptor set */
2423 return (struct anv_address
) {
2424 .bo
= set
->pool
->bo
,
2425 .offset
= set
->desc_mem
.offset
,
2428 /* This is a push descriptor set. We have to flag it as used on the GPU
2429 * so that the next time we push descriptors, we grab a new memory.
2431 struct anv_push_descriptor_set
*push_set
=
2432 (struct anv_push_descriptor_set
*)set
;
2433 push_set
->set_used_on_gpu
= true;
2435 return (struct anv_address
) {
2436 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2437 .offset
= set
->desc_mem
.offset
,
2443 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2444 struct anv_cmd_pipeline_state
*pipe_state
,
2445 struct anv_shader_bin
*shader
,
2446 struct anv_state
*bt_state
)
2448 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2449 uint32_t state_offset
;
2451 struct anv_pipeline_bind_map
*map
= &shader
->bind_map
;
2452 if (map
->surface_count
== 0) {
2453 *bt_state
= (struct anv_state
) { 0, };
2457 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2460 uint32_t *bt_map
= bt_state
->map
;
2462 if (bt_state
->map
== NULL
)
2463 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2465 /* We only need to emit relocs if we're not using softpin. If we are using
2466 * softpin then we always keep all user-allocated memory objects resident.
2468 const bool need_client_mem_relocs
=
2469 !cmd_buffer
->device
->physical
->use_softpin
;
2471 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2472 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2474 struct anv_state surface_state
;
2476 switch (binding
->set
) {
2477 case ANV_DESCRIPTOR_SET_NULL
:
2481 case ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
:
2482 /* Color attachment binding */
2483 assert(shader
->stage
== MESA_SHADER_FRAGMENT
);
2484 if (binding
->index
< subpass
->color_count
) {
2485 const unsigned att
=
2486 subpass
->color_attachments
[binding
->index
].attachment
;
2488 /* From the Vulkan 1.0.46 spec:
2490 * "If any color or depth/stencil attachments are
2491 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2494 if (att
== VK_ATTACHMENT_UNUSED
) {
2495 surface_state
= cmd_buffer
->state
.null_surface_state
;
2497 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2500 surface_state
= cmd_buffer
->state
.null_surface_state
;
2503 assert(surface_state
.map
);
2504 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2507 case ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
: {
2508 struct anv_state surface_state
=
2509 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2511 struct anv_address constant_data
= {
2512 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2513 .offset
= shader
->constant_data
.offset
,
2515 unsigned constant_data_size
= shader
->constant_data_size
;
2517 const enum isl_format format
=
2518 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2519 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2520 surface_state
, format
,
2521 constant_data
, constant_data_size
, 1);
2523 assert(surface_state
.map
);
2524 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2525 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2529 case ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
: {
2530 /* This is always the first binding for compute shaders */
2531 assert(shader
->stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2533 struct anv_state surface_state
=
2534 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2536 const enum isl_format format
=
2537 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2538 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2540 cmd_buffer
->state
.compute
.num_workgroups
,
2543 assert(surface_state
.map
);
2544 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2545 if (need_client_mem_relocs
) {
2546 add_surface_reloc(cmd_buffer
, surface_state
,
2547 cmd_buffer
->state
.compute
.num_workgroups
);
2552 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2553 /* This is a descriptor set buffer so the set index is actually
2554 * given by binding->binding. (Yes, that's confusing.)
2556 struct anv_descriptor_set
*set
=
2557 pipe_state
->descriptors
[binding
->index
];
2558 assert(set
->desc_mem
.alloc_size
);
2559 assert(set
->desc_surface_state
.alloc_size
);
2560 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2561 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2562 anv_descriptor_set_address(cmd_buffer
, set
));
2567 assert(binding
->set
< MAX_SETS
);
2568 const struct anv_descriptor
*desc
=
2569 &pipe_state
->descriptors
[binding
->set
]->descriptors
[binding
->index
];
2571 switch (desc
->type
) {
2572 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2573 /* Nothing for us to do here */
2576 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2577 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2578 if (desc
->image_view
) {
2579 struct anv_surface_state sstate
=
2580 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2581 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2582 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2583 surface_state
= sstate
.state
;
2584 assert(surface_state
.alloc_size
);
2585 if (need_client_mem_relocs
)
2586 add_surface_state_relocs(cmd_buffer
, sstate
);
2588 surface_state
= cmd_buffer
->device
->null_surface_state
;
2592 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2593 assert(shader
->stage
== MESA_SHADER_FRAGMENT
);
2594 assert(desc
->image_view
!= NULL
);
2595 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2596 /* For depth and stencil input attachments, we treat it like any
2597 * old texture that a user may have bound.
2599 assert(desc
->image_view
->n_planes
== 1);
2600 struct anv_surface_state sstate
=
2601 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2602 desc
->image_view
->planes
[0].general_sampler_surface_state
:
2603 desc
->image_view
->planes
[0].optimal_sampler_surface_state
;
2604 surface_state
= sstate
.state
;
2605 assert(surface_state
.alloc_size
);
2606 if (need_client_mem_relocs
)
2607 add_surface_state_relocs(cmd_buffer
, sstate
);
2609 /* For color input attachments, we create the surface state at
2610 * vkBeginRenderPass time so that we can include aux and clear
2611 * color information.
2613 assert(binding
->input_attachment_index
< subpass
->input_count
);
2614 const unsigned subpass_att
= binding
->input_attachment_index
;
2615 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2616 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2620 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2621 if (desc
->image_view
) {
2622 struct anv_surface_state sstate
= (binding
->write_only
)
2623 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2624 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2625 surface_state
= sstate
.state
;
2626 assert(surface_state
.alloc_size
);
2627 if (need_client_mem_relocs
)
2628 add_surface_state_relocs(cmd_buffer
, sstate
);
2630 surface_state
= cmd_buffer
->device
->null_surface_state
;
2635 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2636 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2637 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2638 if (desc
->buffer_view
) {
2639 surface_state
= desc
->buffer_view
->surface_state
;
2640 assert(surface_state
.alloc_size
);
2641 if (need_client_mem_relocs
) {
2642 add_surface_reloc(cmd_buffer
, surface_state
,
2643 desc
->buffer_view
->address
);
2646 surface_state
= cmd_buffer
->device
->null_surface_state
;
2650 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2651 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2653 /* Compute the offset within the buffer */
2654 struct anv_push_constants
*push
=
2655 &cmd_buffer
->state
.push_constants
[shader
->stage
];
2657 uint32_t dynamic_offset
=
2658 push
->dynamic_offsets
[binding
->dynamic_offset_index
];
2659 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2660 /* Clamp to the buffer size */
2661 offset
= MIN2(offset
, desc
->buffer
->size
);
2662 /* Clamp the range to the buffer size */
2663 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2665 /* Align the range for consistency */
2666 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
)
2667 range
= align_u32(range
, ANV_UBO_BOUNDS_CHECK_ALIGNMENT
);
2669 struct anv_address address
=
2670 anv_address_add(desc
->buffer
->address
, offset
);
2673 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2674 enum isl_format format
=
2675 anv_isl_format_for_descriptor_type(desc
->type
);
2677 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2678 format
, address
, range
, 1);
2679 if (need_client_mem_relocs
)
2680 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2682 surface_state
= cmd_buffer
->device
->null_surface_state
;
2687 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2688 if (desc
->buffer_view
) {
2689 surface_state
= (binding
->write_only
)
2690 ? desc
->buffer_view
->writeonly_storage_surface_state
2691 : desc
->buffer_view
->storage_surface_state
;
2692 assert(surface_state
.alloc_size
);
2693 if (need_client_mem_relocs
) {
2694 add_surface_reloc(cmd_buffer
, surface_state
,
2695 desc
->buffer_view
->address
);
2698 surface_state
= cmd_buffer
->device
->null_surface_state
;
2703 assert(!"Invalid descriptor type");
2706 assert(surface_state
.map
);
2707 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2717 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2718 struct anv_cmd_pipeline_state
*pipe_state
,
2719 struct anv_shader_bin
*shader
,
2720 struct anv_state
*state
)
2722 struct anv_pipeline_bind_map
*map
= &shader
->bind_map
;
2723 if (map
->sampler_count
== 0) {
2724 *state
= (struct anv_state
) { 0, };
2728 uint32_t size
= map
->sampler_count
* 16;
2729 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2731 if (state
->map
== NULL
)
2732 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2734 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2735 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2736 const struct anv_descriptor
*desc
=
2737 &pipe_state
->descriptors
[binding
->set
]->descriptors
[binding
->index
];
2739 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2740 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2743 struct anv_sampler
*sampler
= desc
->sampler
;
2745 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2746 * happens to be zero.
2748 if (sampler
== NULL
)
2751 memcpy(state
->map
+ (s
* 16),
2752 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2759 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
,
2760 struct anv_cmd_pipeline_state
*pipe_state
,
2761 struct anv_shader_bin
**shaders
,
2762 uint32_t num_shaders
)
2764 const VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
;
2765 VkShaderStageFlags flushed
= 0;
2767 VkResult result
= VK_SUCCESS
;
2768 for (uint32_t i
= 0; i
< num_shaders
; i
++) {
2772 gl_shader_stage stage
= shaders
[i
]->stage
;
2773 VkShaderStageFlags vk_stage
= mesa_to_vk_shader_stage(stage
);
2774 if ((vk_stage
& dirty
) == 0)
2777 result
= emit_samplers(cmd_buffer
, pipe_state
, shaders
[i
],
2778 &cmd_buffer
->state
.samplers
[stage
]);
2779 if (result
!= VK_SUCCESS
)
2781 result
= emit_binding_table(cmd_buffer
, pipe_state
, shaders
[i
],
2782 &cmd_buffer
->state
.binding_tables
[stage
]);
2783 if (result
!= VK_SUCCESS
)
2786 flushed
|= vk_stage
;
2789 if (result
!= VK_SUCCESS
) {
2790 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2792 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2793 if (result
!= VK_SUCCESS
)
2796 /* Re-emit state base addresses so we get the new surface state base
2797 * address before we start emitting binding tables etc.
2799 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2801 /* Re-emit all active binding tables */
2804 for (uint32_t i
= 0; i
< num_shaders
; i
++) {
2808 gl_shader_stage stage
= shaders
[i
]->stage
;
2810 result
= emit_samplers(cmd_buffer
, pipe_state
, shaders
[i
],
2811 &cmd_buffer
->state
.samplers
[stage
]);
2812 if (result
!= VK_SUCCESS
) {
2813 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2816 result
= emit_binding_table(cmd_buffer
, pipe_state
, shaders
[i
],
2817 &cmd_buffer
->state
.binding_tables
[stage
]);
2818 if (result
!= VK_SUCCESS
) {
2819 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2823 flushed
|= mesa_to_vk_shader_stage(stage
);
2827 cmd_buffer
->state
.descriptors_dirty
&= ~flushed
;
2833 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2836 static const uint32_t sampler_state_opcodes
[] = {
2837 [MESA_SHADER_VERTEX
] = 43,
2838 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2839 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2840 [MESA_SHADER_GEOMETRY
] = 46,
2841 [MESA_SHADER_FRAGMENT
] = 47,
2842 [MESA_SHADER_COMPUTE
] = 0,
2845 static const uint32_t binding_table_opcodes
[] = {
2846 [MESA_SHADER_VERTEX
] = 38,
2847 [MESA_SHADER_TESS_CTRL
] = 39,
2848 [MESA_SHADER_TESS_EVAL
] = 40,
2849 [MESA_SHADER_GEOMETRY
] = 41,
2850 [MESA_SHADER_FRAGMENT
] = 42,
2851 [MESA_SHADER_COMPUTE
] = 0,
2854 anv_foreach_stage(s
, stages
) {
2855 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2856 assert(binding_table_opcodes
[s
] > 0);
2858 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2859 anv_batch_emit(&cmd_buffer
->batch
,
2860 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2861 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2862 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2866 /* Always emit binding table pointers if we're asked to, since on SKL
2867 * this is what flushes push constants. */
2868 anv_batch_emit(&cmd_buffer
->batch
,
2869 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2870 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2871 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2876 static struct anv_address
2877 get_push_range_address(struct anv_cmd_buffer
*cmd_buffer
,
2878 gl_shader_stage stage
,
2879 const struct anv_push_range
*range
)
2881 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2882 switch (range
->set
) {
2883 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2884 /* This is a descriptor set buffer so the set index is
2885 * actually given by binding->binding. (Yes, that's
2888 struct anv_descriptor_set
*set
=
2889 gfx_state
->base
.descriptors
[range
->index
];
2890 return anv_descriptor_set_address(cmd_buffer
, set
);
2893 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
: {
2894 struct anv_state state
=
2895 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2896 return (struct anv_address
) {
2897 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2898 .offset
= state
.offset
,
2903 assert(range
->set
< MAX_SETS
);
2904 struct anv_descriptor_set
*set
=
2905 gfx_state
->base
.descriptors
[range
->set
];
2906 const struct anv_descriptor
*desc
=
2907 &set
->descriptors
[range
->index
];
2909 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2910 if (desc
->buffer_view
)
2911 return desc
->buffer_view
->address
;
2913 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2915 struct anv_push_constants
*push
=
2916 &cmd_buffer
->state
.push_constants
[stage
];
2917 uint32_t dynamic_offset
=
2918 push
->dynamic_offsets
[range
->dynamic_offset_index
];
2919 return anv_address_add(desc
->buffer
->address
,
2920 desc
->offset
+ dynamic_offset
);
2924 /* For NULL UBOs, we just return an address in the workaround BO. We do
2925 * writes to it for workarounds but always at the bottom. The higher
2926 * bytes should be all zeros.
2928 assert(range
->length
* 32 <= 2048);
2929 return (struct anv_address
) {
2930 .bo
= cmd_buffer
->device
->workaround_bo
,
2938 /** Returns the size in bytes of the bound buffer
2940 * The range is relative to the start of the buffer, not the start of the
2941 * range. The returned range may be smaller than
2943 * (range->start + range->length) * 32;
2946 get_push_range_bound_size(struct anv_cmd_buffer
*cmd_buffer
,
2947 gl_shader_stage stage
,
2948 const struct anv_push_range
*range
)
2950 assert(stage
!= MESA_SHADER_COMPUTE
);
2951 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2952 switch (range
->set
) {
2953 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2954 struct anv_descriptor_set
*set
=
2955 gfx_state
->base
.descriptors
[range
->index
];
2956 assert(range
->start
* 32 < set
->desc_mem
.alloc_size
);
2957 assert((range
->start
+ range
->length
) * 32 <= set
->desc_mem
.alloc_size
);
2958 return set
->desc_mem
.alloc_size
;
2961 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
:
2962 return (range
->start
+ range
->length
) * 32;
2965 assert(range
->set
< MAX_SETS
);
2966 struct anv_descriptor_set
*set
=
2967 gfx_state
->base
.descriptors
[range
->set
];
2968 const struct anv_descriptor
*desc
=
2969 &set
->descriptors
[range
->index
];
2971 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2972 if (!desc
->buffer_view
)
2975 if (range
->start
* 32 > desc
->buffer_view
->range
)
2978 return desc
->buffer_view
->range
;
2983 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2984 /* Compute the offset within the buffer */
2985 struct anv_push_constants
*push
=
2986 &cmd_buffer
->state
.push_constants
[stage
];
2987 uint32_t dynamic_offset
=
2988 push
->dynamic_offsets
[range
->dynamic_offset_index
];
2989 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2990 /* Clamp to the buffer size */
2991 offset
= MIN2(offset
, desc
->buffer
->size
);
2992 /* Clamp the range to the buffer size */
2993 uint32_t bound_range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2995 /* Align the range for consistency */
2996 bound_range
= align_u32(bound_range
, ANV_UBO_BOUNDS_CHECK_ALIGNMENT
);
3005 cmd_buffer_emit_push_constant(struct anv_cmd_buffer
*cmd_buffer
,
3006 gl_shader_stage stage
,
3007 struct anv_address
*buffers
,
3008 unsigned buffer_count
)
3010 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
3011 const struct anv_graphics_pipeline
*pipeline
= gfx_state
->pipeline
;
3013 static const uint32_t push_constant_opcodes
[] = {
3014 [MESA_SHADER_VERTEX
] = 21,
3015 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3016 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3017 [MESA_SHADER_GEOMETRY
] = 22,
3018 [MESA_SHADER_FRAGMENT
] = 23,
3019 [MESA_SHADER_COMPUTE
] = 0,
3022 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
3023 assert(push_constant_opcodes
[stage
] > 0);
3025 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
3026 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3028 if (anv_pipeline_has_stage(pipeline
, stage
)) {
3029 const struct anv_pipeline_bind_map
*bind_map
=
3030 &pipeline
->shaders
[stage
]->bind_map
;
3033 c
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
;
3036 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3037 /* The Skylake PRM contains the following restriction:
3039 * "The driver must ensure The following case does not occur
3040 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3041 * buffer 3 read length equal to zero committed followed by a
3042 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3045 * To avoid this, we program the buffers in the highest slots.
3046 * This way, slot 0 is only used if slot 3 is also used.
3048 assert(buffer_count
<= 4);
3049 const unsigned shift
= 4 - buffer_count
;
3050 for (unsigned i
= 0; i
< buffer_count
; i
++) {
3051 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3053 /* At this point we only have non-empty ranges */
3054 assert(range
->length
> 0);
3056 /* For Ivy Bridge, make sure we only set the first range (actual
3059 assert((GEN_GEN
>= 8 || GEN_IS_HASWELL
) || i
== 0);
3061 c
.ConstantBody
.ReadLength
[i
+ shift
] = range
->length
;
3062 c
.ConstantBody
.Buffer
[i
+ shift
] =
3063 anv_address_add(buffers
[i
], range
->start
* 32);
3066 /* For Ivy Bridge, push constants are relative to dynamic state
3067 * base address and we only ever push actual push constants.
3069 if (bind_map
->push_ranges
[0].length
> 0) {
3070 assert(buffer_count
== 1);
3071 assert(bind_map
->push_ranges
[0].set
==
3072 ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
);
3073 assert(buffers
[0].bo
==
3074 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
);
3075 c
.ConstantBody
.ReadLength
[0] = bind_map
->push_ranges
[0].length
;
3076 c
.ConstantBody
.Buffer
[0].bo
= NULL
;
3077 c
.ConstantBody
.Buffer
[0].offset
= buffers
[0].offset
;
3079 assert(bind_map
->push_ranges
[1].length
== 0);
3080 assert(bind_map
->push_ranges
[2].length
== 0);
3081 assert(bind_map
->push_ranges
[3].length
== 0);
3089 cmd_buffer_emit_push_constant_all(struct anv_cmd_buffer
*cmd_buffer
,
3090 uint32_t shader_mask
,
3091 struct anv_address
*buffers
,
3092 uint32_t buffer_count
)
3094 if (buffer_count
== 0) {
3095 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_ALL
), c
) {
3096 c
.ShaderUpdateEnable
= shader_mask
;
3097 c
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
;
3102 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
3103 const struct anv_graphics_pipeline
*pipeline
= gfx_state
->pipeline
;
3105 static const uint32_t push_constant_opcodes
[] = {
3106 [MESA_SHADER_VERTEX
] = 21,
3107 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3108 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3109 [MESA_SHADER_GEOMETRY
] = 22,
3110 [MESA_SHADER_FRAGMENT
] = 23,
3111 [MESA_SHADER_COMPUTE
] = 0,
3114 gl_shader_stage stage
= vk_to_mesa_shader_stage(shader_mask
);
3115 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
3116 assert(push_constant_opcodes
[stage
] > 0);
3118 const struct anv_pipeline_bind_map
*bind_map
=
3119 &pipeline
->shaders
[stage
]->bind_map
;
3122 const uint32_t buffer_mask
= (1 << buffer_count
) - 1;
3123 const uint32_t num_dwords
= 2 + 2 * buffer_count
;
3125 dw
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
3126 GENX(3DSTATE_CONSTANT_ALL
),
3127 .ShaderUpdateEnable
= shader_mask
,
3128 .PointerBufferMask
= buffer_mask
,
3129 .MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
);
3131 for (int i
= 0; i
< buffer_count
; i
++) {
3132 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3133 GENX(3DSTATE_CONSTANT_ALL_DATA_pack
)(
3134 &cmd_buffer
->batch
, dw
+ 2 + i
* 2,
3135 &(struct GENX(3DSTATE_CONSTANT_ALL_DATA
)) {
3136 .PointerToConstantBuffer
=
3137 anv_address_add(buffers
[i
], range
->start
* 32),
3138 .ConstantBufferReadLength
= range
->length
,
3145 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
3146 VkShaderStageFlags dirty_stages
)
3148 VkShaderStageFlags flushed
= 0;
3149 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
3150 const struct anv_graphics_pipeline
*pipeline
= gfx_state
->pipeline
;
3153 uint32_t nobuffer_stages
= 0;
3156 anv_foreach_stage(stage
, dirty_stages
) {
3157 unsigned buffer_count
= 0;
3158 flushed
|= mesa_to_vk_shader_stage(stage
);
3159 UNUSED
uint32_t max_push_range
= 0;
3161 struct anv_address buffers
[4] = {};
3162 if (anv_pipeline_has_stage(pipeline
, stage
)) {
3163 const struct anv_pipeline_bind_map
*bind_map
=
3164 &pipeline
->shaders
[stage
]->bind_map
;
3165 struct anv_push_constants
*push
=
3166 &cmd_buffer
->state
.push_constants
[stage
];
3168 if (cmd_buffer
->device
->robust_buffer_access
) {
3169 push
->push_reg_mask
= 0;
3170 /* Start of the current range in the shader, relative to the start
3171 * of push constants in the shader.
3173 unsigned range_start_reg
= 0;
3174 for (unsigned i
= 0; i
< 4; i
++) {
3175 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3176 if (range
->length
== 0)
3179 unsigned bound_size
=
3180 get_push_range_bound_size(cmd_buffer
, stage
, range
);
3181 if (bound_size
>= range
->start
* 32) {
3182 unsigned bound_regs
=
3183 MIN2(DIV_ROUND_UP(bound_size
, 32) - range
->start
,
3185 assert(range_start_reg
+ bound_regs
<= 64);
3186 push
->push_reg_mask
|= BITFIELD64_RANGE(range_start_reg
,
3190 cmd_buffer
->state
.push_constants_dirty
|=
3191 mesa_to_vk_shader_stage(stage
);
3193 range_start_reg
+= range
->length
;
3197 /* We have to gather buffer addresses as a second step because the
3198 * loop above puts data into the push constant area and the call to
3199 * get_push_range_address is what locks our push constants and copies
3200 * them into the actual GPU buffer. If we did the two loops at the
3201 * same time, we'd risk only having some of the sizes in the push
3202 * constant buffer when we did the copy.
3204 for (unsigned i
= 0; i
< 4; i
++) {
3205 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3206 if (range
->length
== 0)
3209 buffers
[i
] = get_push_range_address(cmd_buffer
, stage
, range
);
3210 max_push_range
= MAX2(max_push_range
, range
->length
);
3214 /* We have at most 4 buffers but they should be tightly packed */
3215 for (unsigned i
= buffer_count
; i
< 4; i
++)
3216 assert(bind_map
->push_ranges
[i
].length
== 0);
3220 /* If this stage doesn't have any push constants, emit it later in a
3221 * single CONSTANT_ALL packet.
3223 if (buffer_count
== 0) {
3224 nobuffer_stages
|= 1 << stage
;
3228 /* The Constant Buffer Read Length field from 3DSTATE_CONSTANT_ALL
3229 * contains only 5 bits, so we can only use it for buffers smaller than
3232 if (max_push_range
< 32) {
3233 cmd_buffer_emit_push_constant_all(cmd_buffer
, 1 << stage
,
3234 buffers
, buffer_count
);
3239 cmd_buffer_emit_push_constant(cmd_buffer
, stage
, buffers
, buffer_count
);
3243 if (nobuffer_stages
)
3244 cmd_buffer_emit_push_constant_all(cmd_buffer
, nobuffer_stages
, NULL
, 0);
3247 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
3251 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3253 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3256 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
3258 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->base
.l3_config
);
3260 genX(cmd_buffer_emit_hashing_mode
)(cmd_buffer
, UINT_MAX
, UINT_MAX
, 1);
3262 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3264 /* Apply any pending pipeline flushes we may have. We want to apply them
3265 * now because, if any of those flushes are for things like push constants,
3266 * the GPU will read the state at weird times.
3268 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3270 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
3271 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
3272 vb_emit
|= pipeline
->vb_used
;
3275 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
3276 const uint32_t num_dwords
= 1 + num_buffers
* 4;
3278 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
3279 GENX(3DSTATE_VERTEX_BUFFERS
));
3281 for_each_bit(vb
, vb_emit
) {
3282 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
3283 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
3285 struct GENX(VERTEX_BUFFER_STATE
) state
;
3287 state
= (struct GENX(VERTEX_BUFFER_STATE
)) {
3288 .VertexBufferIndex
= vb
,
3290 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
3292 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
3293 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
3296 .AddressModifyEnable
= true,
3297 .BufferPitch
= pipeline
->vb
[vb
].stride
,
3298 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
3299 .NullVertexBuffer
= offset
>= buffer
->size
,
3302 .BufferSize
= buffer
->size
- offset
3304 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
3308 state
= (struct GENX(VERTEX_BUFFER_STATE
)) {
3309 .VertexBufferIndex
= vb
,
3310 .NullVertexBuffer
= true,
3314 #if GEN_GEN >= 8 && GEN_GEN <= 9
3315 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(cmd_buffer
, vb
,
3316 state
.BufferStartingAddress
,
3320 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
3325 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
3328 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
3329 /* We don't need any per-buffer dirty tracking because you're not
3330 * allowed to bind different XFB buffers while XFB is enabled.
3332 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3333 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
3334 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3336 sob
.SOBufferIndex
= idx
;
3338 sob
._3DCommandOpcode
= 0;
3339 sob
._3DCommandSubOpcode
= SO_BUFFER_INDEX_0_CMD
+ idx
;
3342 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
3343 sob
.SOBufferEnable
= true;
3344 sob
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
,
3345 sob
.StreamOffsetWriteEnable
= false;
3346 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
3348 /* Size is in DWords - 1 */
3349 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
3354 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
3356 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3360 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
3361 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->base
.batch
);
3363 /* If the pipeline changed, we may need to re-allocate push constant
3366 cmd_buffer_alloc_push_constants(cmd_buffer
);
3370 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
3371 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
3372 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
3374 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
3375 * stall needs to be sent just prior to any 3DSTATE_VS,
3376 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
3377 * 3DSTATE_BINDING_TABLE_POINTER_VS,
3378 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
3379 * PIPE_CONTROL needs to be sent before any combination of VS
3380 * associated 3DSTATE."
3382 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3383 pc
.DepthStallEnable
= true;
3384 pc
.PostSyncOperation
= WriteImmediateData
;
3386 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
3391 /* Render targets live in the same binding table as fragment descriptors */
3392 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
3393 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
3395 /* We emit the binding tables and sampler tables first, then emit push
3396 * constants and then finally emit binding table and sampler table
3397 * pointers. It has to happen in this order, since emitting the binding
3398 * tables may change the push constants (in case of storage images). After
3399 * emitting push constants, on SKL+ we have to emit the corresponding
3400 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
3403 if (cmd_buffer
->state
.descriptors_dirty
) {
3404 dirty
= flush_descriptor_sets(cmd_buffer
,
3405 &cmd_buffer
->state
.gfx
.base
,
3407 ARRAY_SIZE(pipeline
->shaders
));
3410 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
3411 /* Because we're pushing UBOs, we have to push whenever either
3412 * descriptors or push constants is dirty.
3414 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
3415 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
3416 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
3420 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
3422 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
3423 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
3425 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
3426 ANV_CMD_DIRTY_PIPELINE
)) {
3427 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
3428 pipeline
->depth_clamp_enable
);
3431 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
3432 ANV_CMD_DIRTY_RENDER_TARGETS
))
3433 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
3435 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
3439 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
3440 struct anv_address addr
,
3441 uint32_t size
, uint32_t index
)
3443 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
3444 GENX(3DSTATE_VERTEX_BUFFERS
));
3446 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
3447 &(struct GENX(VERTEX_BUFFER_STATE
)) {
3448 .VertexBufferIndex
= index
,
3449 .AddressModifyEnable
= true,
3451 .MOCS
= addr
.bo
? anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
) : 0,
3452 .NullVertexBuffer
= size
== 0,
3454 .BufferStartingAddress
= addr
,
3457 .BufferStartingAddress
= addr
,
3458 .EndAddress
= anv_address_add(addr
, size
),
3462 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(cmd_buffer
,
3467 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
3468 struct anv_address addr
)
3470 emit_vertex_bo(cmd_buffer
, addr
, addr
.bo
? 8 : 0, ANV_SVGS_VB_INDEX
);
3474 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
3475 uint32_t base_vertex
, uint32_t base_instance
)
3477 if (base_vertex
== 0 && base_instance
== 0) {
3478 emit_base_vertex_instance_bo(cmd_buffer
, ANV_NULL_ADDRESS
);
3480 struct anv_state id_state
=
3481 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
3483 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
3484 ((uint32_t *)id_state
.map
)[1] = base_instance
;
3486 struct anv_address addr
= {
3487 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3488 .offset
= id_state
.offset
,
3491 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
3496 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
3498 struct anv_state state
=
3499 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
3501 ((uint32_t *)state
.map
)[0] = draw_index
;
3503 struct anv_address addr
= {
3504 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3505 .offset
= state
.offset
,
3508 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
3512 update_dirty_vbs_for_gen8_vb_flush(struct anv_cmd_buffer
*cmd_buffer
,
3513 uint32_t access_type
)
3515 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3516 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3518 uint64_t vb_used
= pipeline
->vb_used
;
3519 if (vs_prog_data
->uses_firstvertex
||
3520 vs_prog_data
->uses_baseinstance
)
3521 vb_used
|= 1ull << ANV_SVGS_VB_INDEX
;
3522 if (vs_prog_data
->uses_drawid
)
3523 vb_used
|= 1ull << ANV_DRAWID_VB_INDEX
;
3525 genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush
)(cmd_buffer
,
3526 access_type
== RANDOM
,
3531 VkCommandBuffer commandBuffer
,
3532 uint32_t vertexCount
,
3533 uint32_t instanceCount
,
3534 uint32_t firstVertex
,
3535 uint32_t firstInstance
)
3537 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3538 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3539 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3541 if (anv_batch_has_error(&cmd_buffer
->batch
))
3544 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3546 if (cmd_buffer
->state
.conditional_render_enabled
)
3547 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3549 if (vs_prog_data
->uses_firstvertex
||
3550 vs_prog_data
->uses_baseinstance
)
3551 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3552 if (vs_prog_data
->uses_drawid
)
3553 emit_draw_index(cmd_buffer
, 0);
3555 /* Emitting draw index or vertex index BOs may result in needing
3556 * additional VF cache flushes.
3558 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3560 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3561 * different views. We need to multiply instanceCount by the view count.
3563 if (!pipeline
->use_primitive_replication
)
3564 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3566 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3567 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3568 prim
.VertexAccessType
= SEQUENTIAL
;
3569 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3570 prim
.VertexCountPerInstance
= vertexCount
;
3571 prim
.StartVertexLocation
= firstVertex
;
3572 prim
.InstanceCount
= instanceCount
;
3573 prim
.StartInstanceLocation
= firstInstance
;
3574 prim
.BaseVertexLocation
= 0;
3577 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3580 void genX(CmdDrawIndexed
)(
3581 VkCommandBuffer commandBuffer
,
3582 uint32_t indexCount
,
3583 uint32_t instanceCount
,
3584 uint32_t firstIndex
,
3585 int32_t vertexOffset
,
3586 uint32_t firstInstance
)
3588 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3589 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3590 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3592 if (anv_batch_has_error(&cmd_buffer
->batch
))
3595 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3597 if (cmd_buffer
->state
.conditional_render_enabled
)
3598 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3600 if (vs_prog_data
->uses_firstvertex
||
3601 vs_prog_data
->uses_baseinstance
)
3602 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
3603 if (vs_prog_data
->uses_drawid
)
3604 emit_draw_index(cmd_buffer
, 0);
3606 /* Emitting draw index or vertex index BOs may result in needing
3607 * additional VF cache flushes.
3609 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3611 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3612 * different views. We need to multiply instanceCount by the view count.
3614 if (!pipeline
->use_primitive_replication
)
3615 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3617 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3618 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3619 prim
.VertexAccessType
= RANDOM
;
3620 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3621 prim
.VertexCountPerInstance
= indexCount
;
3622 prim
.StartVertexLocation
= firstIndex
;
3623 prim
.InstanceCount
= instanceCount
;
3624 prim
.StartInstanceLocation
= firstInstance
;
3625 prim
.BaseVertexLocation
= vertexOffset
;
3628 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
3631 /* Auto-Draw / Indirect Registers */
3632 #define GEN7_3DPRIM_END_OFFSET 0x2420
3633 #define GEN7_3DPRIM_START_VERTEX 0x2430
3634 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
3635 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
3636 #define GEN7_3DPRIM_START_INSTANCE 0x243C
3637 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
3639 void genX(CmdDrawIndirectByteCountEXT
)(
3640 VkCommandBuffer commandBuffer
,
3641 uint32_t instanceCount
,
3642 uint32_t firstInstance
,
3643 VkBuffer counterBuffer
,
3644 VkDeviceSize counterBufferOffset
,
3645 uint32_t counterOffset
,
3646 uint32_t vertexStride
)
3648 #if GEN_IS_HASWELL || GEN_GEN >= 8
3649 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3650 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
3651 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3652 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3654 /* firstVertex is always zero for this draw function */
3655 const uint32_t firstVertex
= 0;
3657 if (anv_batch_has_error(&cmd_buffer
->batch
))
3660 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3662 if (vs_prog_data
->uses_firstvertex
||
3663 vs_prog_data
->uses_baseinstance
)
3664 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3665 if (vs_prog_data
->uses_drawid
)
3666 emit_draw_index(cmd_buffer
, 0);
3668 /* Emitting draw index or vertex index BOs may result in needing
3669 * additional VF cache flushes.
3671 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3673 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3674 * different views. We need to multiply instanceCount by the view count.
3676 if (!pipeline
->use_primitive_replication
)
3677 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3679 struct gen_mi_builder b
;
3680 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3681 struct gen_mi_value count
=
3682 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
3683 counterBufferOffset
));
3685 count
= gen_mi_isub(&b
, count
, gen_mi_imm(counterOffset
));
3686 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
3687 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
3689 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3690 gen_mi_imm(firstVertex
));
3691 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
3692 gen_mi_imm(instanceCount
));
3693 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3694 gen_mi_imm(firstInstance
));
3695 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3697 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3698 prim
.IndirectParameterEnable
= true;
3699 prim
.VertexAccessType
= SEQUENTIAL
;
3700 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3703 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3704 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3708 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
3709 struct anv_address addr
,
3712 struct gen_mi_builder b
;
3713 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3715 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
),
3716 gen_mi_mem32(anv_address_add(addr
, 0)));
3718 struct gen_mi_value instance_count
= gen_mi_mem32(anv_address_add(addr
, 4));
3719 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3720 if (view_count
> 1) {
3721 #if GEN_IS_HASWELL || GEN_GEN >= 8
3722 instance_count
= gen_mi_imul_imm(&b
, instance_count
, view_count
);
3724 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3725 "MI_MATH is not supported on Ivy Bridge");
3728 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
), instance_count
);
3730 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3731 gen_mi_mem32(anv_address_add(addr
, 8)));
3734 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
),
3735 gen_mi_mem32(anv_address_add(addr
, 12)));
3736 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3737 gen_mi_mem32(anv_address_add(addr
, 16)));
3739 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3740 gen_mi_mem32(anv_address_add(addr
, 12)));
3741 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3745 void genX(CmdDrawIndirect
)(
3746 VkCommandBuffer commandBuffer
,
3748 VkDeviceSize offset
,
3752 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3753 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3754 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3755 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3757 if (anv_batch_has_error(&cmd_buffer
->batch
))
3760 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3762 if (cmd_buffer
->state
.conditional_render_enabled
)
3763 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3765 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3766 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3768 if (vs_prog_data
->uses_firstvertex
||
3769 vs_prog_data
->uses_baseinstance
)
3770 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3771 if (vs_prog_data
->uses_drawid
)
3772 emit_draw_index(cmd_buffer
, i
);
3774 /* Emitting draw index or vertex index BOs may result in needing
3775 * additional VF cache flushes.
3777 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3779 load_indirect_parameters(cmd_buffer
, draw
, false);
3781 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3782 prim
.IndirectParameterEnable
= true;
3783 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3784 prim
.VertexAccessType
= SEQUENTIAL
;
3785 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3788 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3794 void genX(CmdDrawIndexedIndirect
)(
3795 VkCommandBuffer commandBuffer
,
3797 VkDeviceSize offset
,
3801 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3802 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3803 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3804 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3806 if (anv_batch_has_error(&cmd_buffer
->batch
))
3809 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3811 if (cmd_buffer
->state
.conditional_render_enabled
)
3812 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3814 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3815 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3817 /* TODO: We need to stomp base vertex to 0 somehow */
3818 if (vs_prog_data
->uses_firstvertex
||
3819 vs_prog_data
->uses_baseinstance
)
3820 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3821 if (vs_prog_data
->uses_drawid
)
3822 emit_draw_index(cmd_buffer
, i
);
3824 /* Emitting draw index or vertex index BOs may result in needing
3825 * additional VF cache flushes.
3827 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3829 load_indirect_parameters(cmd_buffer
, draw
, true);
3831 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3832 prim
.IndirectParameterEnable
= true;
3833 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3834 prim
.VertexAccessType
= RANDOM
;
3835 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3838 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
3844 #define TMP_DRAW_COUNT_REG 0x2670 /* MI_ALU_REG14 */
3847 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3848 struct anv_address count_address
,
3849 const bool conditional_render_enabled
)
3851 struct gen_mi_builder b
;
3852 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3854 if (conditional_render_enabled
) {
3855 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3856 gen_mi_store(&b
, gen_mi_reg64(TMP_DRAW_COUNT_REG
),
3857 gen_mi_mem32(count_address
));
3860 /* Upload the current draw count from the draw parameters buffer to
3861 * MI_PREDICATE_SRC0.
3863 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
3864 gen_mi_mem32(count_address
));
3866 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
+ 4), gen_mi_imm(0));
3871 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3872 uint32_t draw_index
)
3874 struct gen_mi_builder b
;
3875 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3877 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3878 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
), gen_mi_imm(draw_index
));
3880 if (draw_index
== 0) {
3881 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3882 mip
.LoadOperation
= LOAD_LOADINV
;
3883 mip
.CombineOperation
= COMBINE_SET
;
3884 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3887 /* While draw_index < draw_count the predicate's result will be
3888 * (draw_index == draw_count) ^ TRUE = TRUE
3889 * When draw_index == draw_count the result is
3890 * (TRUE) ^ TRUE = FALSE
3891 * After this all results will be:
3892 * (FALSE) ^ FALSE = FALSE
3894 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3895 mip
.LoadOperation
= LOAD_LOAD
;
3896 mip
.CombineOperation
= COMBINE_XOR
;
3897 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3902 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3904 emit_draw_count_predicate_with_conditional_render(
3905 struct anv_cmd_buffer
*cmd_buffer
,
3906 uint32_t draw_index
)
3908 struct gen_mi_builder b
;
3909 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3911 struct gen_mi_value pred
= gen_mi_ult(&b
, gen_mi_imm(draw_index
),
3912 gen_mi_reg64(TMP_DRAW_COUNT_REG
));
3913 pred
= gen_mi_iand(&b
, pred
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
));
3916 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_RESULT
), pred
);
3918 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3919 * so we emit MI_PREDICATE to set it.
3922 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), pred
);
3923 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3925 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3926 mip
.LoadOperation
= LOAD_LOADINV
;
3927 mip
.CombineOperation
= COMBINE_SET
;
3928 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3934 void genX(CmdDrawIndirectCount
)(
3935 VkCommandBuffer commandBuffer
,
3937 VkDeviceSize offset
,
3938 VkBuffer _countBuffer
,
3939 VkDeviceSize countBufferOffset
,
3940 uint32_t maxDrawCount
,
3943 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3944 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3945 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3946 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3947 struct anv_graphics_pipeline
*pipeline
= cmd_state
->gfx
.pipeline
;
3948 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3950 if (anv_batch_has_error(&cmd_buffer
->batch
))
3953 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3955 struct anv_address count_address
=
3956 anv_address_add(count_buffer
->address
, countBufferOffset
);
3958 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3959 cmd_state
->conditional_render_enabled
);
3961 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3962 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3964 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3965 if (cmd_state
->conditional_render_enabled
) {
3966 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3968 emit_draw_count_predicate(cmd_buffer
, i
);
3971 emit_draw_count_predicate(cmd_buffer
, i
);
3974 if (vs_prog_data
->uses_firstvertex
||
3975 vs_prog_data
->uses_baseinstance
)
3976 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3977 if (vs_prog_data
->uses_drawid
)
3978 emit_draw_index(cmd_buffer
, i
);
3980 /* Emitting draw index or vertex index BOs may result in needing
3981 * additional VF cache flushes.
3983 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3985 load_indirect_parameters(cmd_buffer
, draw
, false);
3987 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3988 prim
.IndirectParameterEnable
= true;
3989 prim
.PredicateEnable
= true;
3990 prim
.VertexAccessType
= SEQUENTIAL
;
3991 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3994 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
4000 void genX(CmdDrawIndexedIndirectCount
)(
4001 VkCommandBuffer commandBuffer
,
4003 VkDeviceSize offset
,
4004 VkBuffer _countBuffer
,
4005 VkDeviceSize countBufferOffset
,
4006 uint32_t maxDrawCount
,
4009 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4010 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
4011 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
4012 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4013 struct anv_graphics_pipeline
*pipeline
= cmd_state
->gfx
.pipeline
;
4014 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
4016 if (anv_batch_has_error(&cmd_buffer
->batch
))
4019 genX(cmd_buffer_flush_state
)(cmd_buffer
);
4021 struct anv_address count_address
=
4022 anv_address_add(count_buffer
->address
, countBufferOffset
);
4024 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
4025 cmd_state
->conditional_render_enabled
);
4027 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
4028 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
4030 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4031 if (cmd_state
->conditional_render_enabled
) {
4032 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
4034 emit_draw_count_predicate(cmd_buffer
, i
);
4037 emit_draw_count_predicate(cmd_buffer
, i
);
4040 /* TODO: We need to stomp base vertex to 0 somehow */
4041 if (vs_prog_data
->uses_firstvertex
||
4042 vs_prog_data
->uses_baseinstance
)
4043 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
4044 if (vs_prog_data
->uses_drawid
)
4045 emit_draw_index(cmd_buffer
, i
);
4047 /* Emitting draw index or vertex index BOs may result in needing
4048 * additional VF cache flushes.
4050 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4052 load_indirect_parameters(cmd_buffer
, draw
, true);
4054 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
4055 prim
.IndirectParameterEnable
= true;
4056 prim
.PredicateEnable
= true;
4057 prim
.VertexAccessType
= RANDOM
;
4058 prim
.PrimitiveTopologyType
= pipeline
->topology
;
4061 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
4067 void genX(CmdBeginTransformFeedbackEXT
)(
4068 VkCommandBuffer commandBuffer
,
4069 uint32_t firstCounterBuffer
,
4070 uint32_t counterBufferCount
,
4071 const VkBuffer
* pCounterBuffers
,
4072 const VkDeviceSize
* pCounterBufferOffsets
)
4074 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4076 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
4077 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
4078 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
4080 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
4082 * "Ssoftware must ensure that no HW stream output operations can be in
4083 * process or otherwise pending at the point that the MI_LOAD/STORE
4084 * commands are processed. This will likely require a pipeline flush."
4086 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4087 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4089 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
4090 /* If we have a counter buffer, this is a resume so we need to load the
4091 * value into the streamout offset register. Otherwise, this is a begin
4092 * and we need to reset it to zero.
4094 if (pCounterBuffers
&&
4095 idx
>= firstCounterBuffer
&&
4096 idx
- firstCounterBuffer
< counterBufferCount
&&
4097 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
4098 uint32_t cb_idx
= idx
- firstCounterBuffer
;
4099 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
4100 uint64_t offset
= pCounterBufferOffsets
?
4101 pCounterBufferOffsets
[cb_idx
] : 0;
4103 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4104 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
4105 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
4109 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
4110 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
4116 cmd_buffer
->state
.xfb_enabled
= true;
4117 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
4120 void genX(CmdEndTransformFeedbackEXT
)(
4121 VkCommandBuffer commandBuffer
,
4122 uint32_t firstCounterBuffer
,
4123 uint32_t counterBufferCount
,
4124 const VkBuffer
* pCounterBuffers
,
4125 const VkDeviceSize
* pCounterBufferOffsets
)
4127 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4129 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
4130 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
4131 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
4133 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
4135 * "Ssoftware must ensure that no HW stream output operations can be in
4136 * process or otherwise pending at the point that the MI_LOAD/STORE
4137 * commands are processed. This will likely require a pipeline flush."
4139 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4140 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4142 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
4143 unsigned idx
= firstCounterBuffer
+ cb_idx
;
4145 /* If we have a counter buffer, this is a resume so we need to load the
4146 * value into the streamout offset register. Otherwise, this is a begin
4147 * and we need to reset it to zero.
4149 if (pCounterBuffers
&&
4150 cb_idx
< counterBufferCount
&&
4151 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
4152 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
4153 uint64_t offset
= pCounterBufferOffsets
?
4154 pCounterBufferOffsets
[cb_idx
] : 0;
4156 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
4157 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
4159 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
4164 cmd_buffer
->state
.xfb_enabled
= false;
4165 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
4169 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
4171 struct anv_compute_pipeline
*pipeline
= cmd_buffer
->state
.compute
.pipeline
;
4173 assert(pipeline
->cs
);
4175 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->base
.l3_config
);
4177 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
4179 /* Apply any pending pipeline flushes we may have. We want to apply them
4180 * now because, if any of those flushes are for things like push constants,
4181 * the GPU will read the state at weird times.
4183 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4185 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
4186 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
4188 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4189 * the only bits that are changed are scoreboard related: Scoreboard
4190 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
4191 * these scoreboard related states, a MEDIA_STATE_FLUSH is
4194 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4195 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4197 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->base
.batch
);
4199 /* The workgroup size of the pipeline affects our push constant layout
4200 * so flag push constants as dirty if we change the pipeline.
4202 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4205 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
4206 cmd_buffer
->state
.compute
.pipeline_dirty
) {
4207 flush_descriptor_sets(cmd_buffer
,
4208 &cmd_buffer
->state
.compute
.base
,
4211 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
4212 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
4213 .BindingTablePointer
=
4214 cmd_buffer
->state
.binding_tables
[MESA_SHADER_COMPUTE
].offset
,
4215 .SamplerStatePointer
=
4216 cmd_buffer
->state
.samplers
[MESA_SHADER_COMPUTE
].offset
,
4218 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
4220 struct anv_state state
=
4221 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
4222 pipeline
->interface_descriptor_data
,
4223 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
4226 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4227 anv_batch_emit(&cmd_buffer
->batch
,
4228 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
4229 mid
.InterfaceDescriptorTotalLength
= size
;
4230 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
4234 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
4235 struct anv_state push_state
=
4236 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
4238 if (push_state
.alloc_size
) {
4239 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4240 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
4241 curbe
.CURBEDataStartAddress
= push_state
.offset
;
4245 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
4248 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
4250 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4256 verify_cmd_parser(const struct anv_device
*device
,
4257 int required_version
,
4258 const char *function
)
4260 if (device
->physical
->cmd_parser_version
< required_version
) {
4261 return vk_errorf(device
, device
->physical
,
4262 VK_ERROR_FEATURE_NOT_PRESENT
,
4263 "cmd parser version %d is required for %s",
4264 required_version
, function
);
4273 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
4274 uint32_t baseGroupX
,
4275 uint32_t baseGroupY
,
4276 uint32_t baseGroupZ
)
4278 if (anv_batch_has_error(&cmd_buffer
->batch
))
4281 struct anv_push_constants
*push
=
4282 &cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
4283 if (push
->cs
.base_work_group_id
[0] != baseGroupX
||
4284 push
->cs
.base_work_group_id
[1] != baseGroupY
||
4285 push
->cs
.base_work_group_id
[2] != baseGroupZ
) {
4286 push
->cs
.base_work_group_id
[0] = baseGroupX
;
4287 push
->cs
.base_work_group_id
[1] = baseGroupY
;
4288 push
->cs
.base_work_group_id
[2] = baseGroupZ
;
4290 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4294 void genX(CmdDispatch
)(
4295 VkCommandBuffer commandBuffer
,
4300 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
4303 void genX(CmdDispatchBase
)(
4304 VkCommandBuffer commandBuffer
,
4305 uint32_t baseGroupX
,
4306 uint32_t baseGroupY
,
4307 uint32_t baseGroupZ
,
4308 uint32_t groupCountX
,
4309 uint32_t groupCountY
,
4310 uint32_t groupCountZ
)
4312 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4313 struct anv_compute_pipeline
*pipeline
= cmd_buffer
->state
.compute
.pipeline
;
4314 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
4316 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
4317 baseGroupY
, baseGroupZ
);
4319 if (anv_batch_has_error(&cmd_buffer
->batch
))
4322 if (prog_data
->uses_num_work_groups
) {
4323 struct anv_state state
=
4324 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
4325 uint32_t *sizes
= state
.map
;
4326 sizes
[0] = groupCountX
;
4327 sizes
[1] = groupCountY
;
4328 sizes
[2] = groupCountZ
;
4329 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
4330 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4331 .offset
= state
.offset
,
4334 /* The num_workgroups buffer goes in the binding table */
4335 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4338 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
4340 if (cmd_buffer
->state
.conditional_render_enabled
)
4341 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
4343 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
4344 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
4345 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
4346 ggw
.ThreadDepthCounterMaximum
= 0;
4347 ggw
.ThreadHeightCounterMaximum
= 0;
4348 ggw
.ThreadWidthCounterMaximum
= anv_cs_threads(pipeline
) - 1;
4349 ggw
.ThreadGroupIDXDimension
= groupCountX
;
4350 ggw
.ThreadGroupIDYDimension
= groupCountY
;
4351 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
4352 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
4353 ggw
.BottomExecutionMask
= 0xffffffff;
4356 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
4359 #define GPGPU_DISPATCHDIMX 0x2500
4360 #define GPGPU_DISPATCHDIMY 0x2504
4361 #define GPGPU_DISPATCHDIMZ 0x2508
4363 void genX(CmdDispatchIndirect
)(
4364 VkCommandBuffer commandBuffer
,
4366 VkDeviceSize offset
)
4368 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4369 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
4370 struct anv_compute_pipeline
*pipeline
= cmd_buffer
->state
.compute
.pipeline
;
4371 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
4372 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
4373 struct anv_batch
*batch
= &cmd_buffer
->batch
;
4375 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
4378 /* Linux 4.4 added command parser version 5 which allows the GPGPU
4379 * indirect dispatch registers to be written.
4381 if (verify_cmd_parser(cmd_buffer
->device
, 5,
4382 "vkCmdDispatchIndirect") != VK_SUCCESS
)
4386 if (prog_data
->uses_num_work_groups
) {
4387 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
4389 /* The num_workgroups buffer goes in the binding table */
4390 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4393 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
4395 struct gen_mi_builder b
;
4396 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4398 struct gen_mi_value size_x
= gen_mi_mem32(anv_address_add(addr
, 0));
4399 struct gen_mi_value size_y
= gen_mi_mem32(anv_address_add(addr
, 4));
4400 struct gen_mi_value size_z
= gen_mi_mem32(anv_address_add(addr
, 8));
4402 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMX
), size_x
);
4403 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMY
), size_y
);
4404 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMZ
), size_z
);
4407 /* predicate = (compute_dispatch_indirect_x_size == 0); */
4408 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), size_x
);
4409 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
4410 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4411 mip
.LoadOperation
= LOAD_LOAD
;
4412 mip
.CombineOperation
= COMBINE_SET
;
4413 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4416 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
4417 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_y
);
4418 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4419 mip
.LoadOperation
= LOAD_LOAD
;
4420 mip
.CombineOperation
= COMBINE_OR
;
4421 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4424 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
4425 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_z
);
4426 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4427 mip
.LoadOperation
= LOAD_LOAD
;
4428 mip
.CombineOperation
= COMBINE_OR
;
4429 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4432 /* predicate = !predicate; */
4433 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4434 mip
.LoadOperation
= LOAD_LOADINV
;
4435 mip
.CombineOperation
= COMBINE_OR
;
4436 mip
.CompareOperation
= COMPARE_FALSE
;
4440 if (cmd_buffer
->state
.conditional_render_enabled
) {
4441 /* predicate &= !(conditional_rendering_predicate == 0); */
4442 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
),
4443 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
4444 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4445 mip
.LoadOperation
= LOAD_LOADINV
;
4446 mip
.CombineOperation
= COMBINE_AND
;
4447 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4452 #else /* GEN_GEN > 7 */
4453 if (cmd_buffer
->state
.conditional_render_enabled
)
4454 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
4457 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
4458 ggw
.IndirectParameterEnable
= true;
4459 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
4460 cmd_buffer
->state
.conditional_render_enabled
;
4461 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
4462 ggw
.ThreadDepthCounterMaximum
= 0;
4463 ggw
.ThreadHeightCounterMaximum
= 0;
4464 ggw
.ThreadWidthCounterMaximum
= anv_cs_threads(pipeline
) - 1;
4465 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
4466 ggw
.BottomExecutionMask
= 0xffffffff;
4469 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
4473 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
4476 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4478 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
4481 #if GEN_GEN >= 8 && GEN_GEN < 10
4482 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
4484 * Software must clear the COLOR_CALC_STATE Valid field in
4485 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
4486 * with Pipeline Select set to GPGPU.
4488 * The internal hardware docs recommend the same workaround for Gen9
4491 if (pipeline
== GPGPU
)
4492 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
4496 if (pipeline
== _3D
) {
4497 /* There is a mid-object preemption workaround which requires you to
4498 * re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D. However,
4499 * even without preemption, we have issues with geometry flickering when
4500 * GPGPU and 3D are back-to-back and this seems to fix it. We don't
4503 const uint32_t subslices
=
4504 MAX2(cmd_buffer
->device
->physical
->subslice_total
, 1);
4505 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
4506 vfe
.MaximumNumberofThreads
=
4507 devinfo
->max_cs_threads
* subslices
- 1;
4508 vfe
.NumberofURBEntries
= 2;
4509 vfe
.URBEntryAllocationSize
= 2;
4512 /* We just emitted a dummy MEDIA_VFE_STATE so now that packet is
4513 * invalid. Set the compute pipeline to dirty to force a re-emit of the
4514 * pipeline in case we get back-to-back dispatch calls with the same
4515 * pipeline and a PIPELINE_SELECT in between.
4517 cmd_buffer
->state
.compute
.pipeline_dirty
= true;
4521 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
4522 * PIPELINE_SELECT [DevBWR+]":
4526 * Software must ensure all the write caches are flushed through a
4527 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
4528 * command to invalidate read only caches prior to programming
4529 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
4531 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4532 pc
.RenderTargetCacheFlushEnable
= true;
4533 pc
.DepthCacheFlushEnable
= true;
4534 pc
.DCFlushEnable
= true;
4535 pc
.PostSyncOperation
= NoWrite
;
4536 pc
.CommandStreamerStallEnable
= true;
4538 pc
.TileCacheFlushEnable
= true;
4540 /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must be
4541 * set with any PIPE_CONTROL with Depth Flush Enable bit set.
4543 pc
.DepthStallEnable
= true;
4547 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4548 pc
.TextureCacheInvalidationEnable
= true;
4549 pc
.ConstantCacheInvalidationEnable
= true;
4550 pc
.StateCacheInvalidationEnable
= true;
4551 pc
.InstructionCacheInvalidateEnable
= true;
4552 pc
.PostSyncOperation
= NoWrite
;
4554 pc
.TileCacheFlushEnable
= true;
4558 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
4562 ps
.PipelineSelection
= pipeline
;
4566 if (devinfo
->is_geminilake
) {
4569 * "This chicken bit works around a hardware issue with barrier logic
4570 * encountered when switching between GPGPU and 3D pipelines. To
4571 * workaround the issue, this mode bit should be set after a pipeline
4575 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
4577 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
4578 : GLK_BARRIER_MODE_3D_HULL
,
4579 .GLKBarrierModeMask
= 1);
4580 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
4584 cmd_buffer
->state
.current_pipeline
= pipeline
;
4588 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
4590 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
4594 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
4596 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
4600 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
4605 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
4607 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
4608 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
4609 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
4610 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
4611 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
4612 * Depth Flush Bit set, followed by another pipelined depth stall
4613 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
4614 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
4615 * via a preceding MI_FLUSH)."
4617 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4618 pipe
.DepthStallEnable
= true;
4620 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4621 pipe
.DepthCacheFlushEnable
= true;
4623 pipe
.TileCacheFlushEnable
= true;
4626 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4627 pipe
.DepthStallEnable
= true;
4631 /* From the Skylake PRM, 3DSTATE_VERTEX_BUFFERS:
4633 * "The VF cache needs to be invalidated before binding and then using
4634 * Vertex Buffers that overlap with any previously bound Vertex Buffer
4635 * (at a 64B granularity) since the last invalidation. A VF cache
4636 * invalidate is performed by setting the "VF Cache Invalidation Enable"
4637 * bit in PIPE_CONTROL."
4639 * This is implemented by carefully tracking all vertex and index buffer
4640 * bindings and flushing if the cache ever ends up with a range in the cache
4641 * that would exceed 4 GiB. This is implemented in three parts:
4643 * 1. genX(cmd_buffer_set_binding_for_gen8_vb_flush)() which must be called
4644 * every time a 3DSTATE_VERTEX_BUFFER packet is emitted and informs the
4645 * tracking code of the new binding. If this new binding would cause
4646 * the cache to have a too-large range on the next draw call, a pipeline
4647 * stall and VF cache invalidate are added to pending_pipeline_bits.
4649 * 2. genX(cmd_buffer_apply_pipe_flushes)() resets the cache tracking to
4650 * empty whenever we emit a VF invalidate.
4652 * 3. genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush)() must be called
4653 * after every 3DPRIMITIVE and copies the bound range into the dirty
4654 * range for each used buffer. This has to be a separate step because
4655 * we don't always re-bind all buffers and so 1. can't know which
4656 * buffers are actually bound.
4659 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(struct anv_cmd_buffer
*cmd_buffer
,
4661 struct anv_address vb_address
,
4664 if (GEN_GEN
< 8 || GEN_GEN
> 9 ||
4665 !cmd_buffer
->device
->physical
->use_softpin
)
4668 struct anv_vb_cache_range
*bound
, *dirty
;
4669 if (vb_index
== -1) {
4670 bound
= &cmd_buffer
->state
.gfx
.ib_bound_range
;
4671 dirty
= &cmd_buffer
->state
.gfx
.ib_dirty_range
;
4673 assert(vb_index
>= 0);
4674 assert(vb_index
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_bound_ranges
));
4675 assert(vb_index
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
4676 bound
= &cmd_buffer
->state
.gfx
.vb_bound_ranges
[vb_index
];
4677 dirty
= &cmd_buffer
->state
.gfx
.vb_dirty_ranges
[vb_index
];
4686 assert(vb_address
.bo
&& (vb_address
.bo
->flags
& EXEC_OBJECT_PINNED
));
4687 bound
->start
= gen_48b_address(anv_address_physical(vb_address
));
4688 bound
->end
= bound
->start
+ vb_size
;
4689 assert(bound
->end
> bound
->start
); /* No overflow */
4691 /* Align everything to a cache line */
4692 bound
->start
&= ~(64ull - 1ull);
4693 bound
->end
= align_u64(bound
->end
, 64);
4695 /* Compute the dirty range */
4696 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4697 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4699 /* If our range is larger than 32 bits, we have to flush */
4700 assert(bound
->end
- bound
->start
<= (1ull << 32));
4701 if (dirty
->end
- dirty
->start
> (1ull << 32)) {
4702 cmd_buffer
->state
.pending_pipe_bits
|=
4703 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
4708 genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush
)(struct anv_cmd_buffer
*cmd_buffer
,
4709 uint32_t access_type
,
4712 if (GEN_GEN
< 8 || GEN_GEN
> 9 ||
4713 !cmd_buffer
->device
->physical
->use_softpin
)
4716 if (access_type
== RANDOM
) {
4717 /* We have an index buffer */
4718 struct anv_vb_cache_range
*bound
= &cmd_buffer
->state
.gfx
.ib_bound_range
;
4719 struct anv_vb_cache_range
*dirty
= &cmd_buffer
->state
.gfx
.ib_dirty_range
;
4721 if (bound
->end
> bound
->start
) {
4722 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4723 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4727 uint64_t mask
= vb_used
;
4729 int i
= u_bit_scan64(&mask
);
4731 assert(i
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_bound_ranges
));
4732 assert(i
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
4734 struct anv_vb_cache_range
*bound
, *dirty
;
4735 bound
= &cmd_buffer
->state
.gfx
.vb_bound_ranges
[i
];
4736 dirty
= &cmd_buffer
->state
.gfx
.vb_dirty_ranges
[i
];
4738 if (bound
->end
> bound
->start
) {
4739 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4740 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4746 * Update the pixel hashing modes that determine the balancing of PS threads
4747 * across subslices and slices.
4749 * \param width Width bound of the rendering area (already scaled down if \p
4750 * scale is greater than 1).
4751 * \param height Height bound of the rendering area (already scaled down if \p
4752 * scale is greater than 1).
4753 * \param scale The number of framebuffer samples that could potentially be
4754 * affected by an individual channel of the PS thread. This is
4755 * typically one for single-sampled rendering, but for operations
4756 * like CCS resolves and fast clears a single PS invocation may
4757 * update a huge number of pixels, in which case a finer
4758 * balancing is desirable in order to maximally utilize the
4759 * bandwidth available. UINT_MAX can be used as shorthand for
4760 * "finest hashing mode available".
4763 genX(cmd_buffer_emit_hashing_mode
)(struct anv_cmd_buffer
*cmd_buffer
,
4764 unsigned width
, unsigned height
,
4768 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4769 const unsigned slice_hashing
[] = {
4770 /* Because all Gen9 platforms with more than one slice require
4771 * three-way subslice hashing, a single "normal" 16x16 slice hashing
4772 * block is guaranteed to suffer from substantial imbalance, with one
4773 * subslice receiving twice as much work as the other two in the
4776 * The performance impact of that would be particularly severe when
4777 * three-way hashing is also in use for slice balancing (which is the
4778 * case for all Gen9 GT4 platforms), because one of the slices
4779 * receives one every three 16x16 blocks in either direction, which
4780 * is roughly the periodicity of the underlying subslice imbalance
4781 * pattern ("roughly" because in reality the hardware's
4782 * implementation of three-way hashing doesn't do exact modulo 3
4783 * arithmetic, which somewhat decreases the magnitude of this effect
4784 * in practice). This leads to a systematic subslice imbalance
4785 * within that slice regardless of the size of the primitive. The
4786 * 32x32 hashing mode guarantees that the subslice imbalance within a
4787 * single slice hashing block is minimal, largely eliminating this
4791 /* Finest slice hashing mode available. */
4794 const unsigned subslice_hashing
[] = {
4795 /* 16x16 would provide a slight cache locality benefit especially
4796 * visible in the sampler L1 cache efficiency of low-bandwidth
4797 * non-LLC platforms, but it comes at the cost of greater subslice
4798 * imbalance for primitives of dimensions approximately intermediate
4799 * between 16x4 and 16x16.
4802 /* Finest subslice hashing mode available. */
4805 /* Dimensions of the smallest hashing block of a given hashing mode. If
4806 * the rendering area is smaller than this there can't possibly be any
4807 * benefit from switching to this mode, so we optimize out the
4810 const unsigned min_size
[][2] = {
4814 const unsigned idx
= scale
> 1;
4816 if (cmd_buffer
->state
.current_hash_scale
!= scale
&&
4817 (width
> min_size
[idx
][0] || height
> min_size
[idx
][1])) {
4820 anv_pack_struct(>_mode
, GENX(GT_MODE
),
4821 .SliceHashing
= (devinfo
->num_slices
> 1 ? slice_hashing
[idx
] : 0),
4822 .SliceHashingMask
= (devinfo
->num_slices
> 1 ? -1 : 0),
4823 .SubsliceHashing
= subslice_hashing
[idx
],
4824 .SubsliceHashingMask
= -1);
4826 cmd_buffer
->state
.pending_pipe_bits
|=
4827 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
4828 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4830 emit_lri(&cmd_buffer
->batch
, GENX(GT_MODE_num
), gt_mode
);
4832 cmd_buffer
->state
.current_hash_scale
= scale
;
4838 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
4840 struct anv_device
*device
= cmd_buffer
->device
;
4841 const struct anv_image_view
*iview
=
4842 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
4843 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
4845 /* FIXME: Width and Height are wrong */
4847 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
4849 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
4850 device
->isl_dev
.ds
.size
/ 4);
4854 struct isl_depth_stencil_hiz_emit_info info
= { };
4857 info
.view
= &iview
->planes
[0].isl
;
4859 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
4860 uint32_t depth_plane
=
4861 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
4862 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
4864 info
.depth_surf
= &surface
->isl
;
4866 info
.depth_address
=
4867 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4868 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
4869 image
->planes
[depth_plane
].address
.bo
,
4870 image
->planes
[depth_plane
].address
.offset
+
4873 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
4876 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
4877 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
4878 if (info
.hiz_usage
!= ISL_AUX_USAGE_NONE
) {
4879 assert(isl_aux_usage_has_hiz(info
.hiz_usage
));
4880 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
4883 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4884 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
4885 image
->planes
[depth_plane
].address
.bo
,
4886 image
->planes
[depth_plane
].address
.offset
+
4887 image
->planes
[depth_plane
].aux_surface
.offset
);
4889 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
4893 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4894 uint32_t stencil_plane
=
4895 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
4896 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
4898 info
.stencil_surf
= &surface
->isl
;
4900 info
.stencil_address
=
4901 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4902 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
4903 image
->planes
[stencil_plane
].address
.bo
,
4904 image
->planes
[stencil_plane
].address
.offset
+
4907 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
4910 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
4912 if (GEN_GEN
>= 12) {
4913 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
4914 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4916 /* GEN:BUG:1408224581
4918 * Workaround: Gen12LP Astep only An additional pipe control with
4919 * post-sync = store dword operation would be required.( w/a is to
4920 * have an additional pipe control after the stencil state whenever
4921 * the surface state bits of this state is changing).
4923 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4924 pc
.PostSyncOperation
= WriteImmediateData
;
4926 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
4929 cmd_buffer
->state
.hiz_enabled
= isl_aux_usage_has_hiz(info
.hiz_usage
);
4933 * This ANDs the view mask of the current subpass with the pending clear
4934 * views in the attachment to get the mask of views active in the subpass
4935 * that still need to be cleared.
4937 static inline uint32_t
4938 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
4939 const struct anv_attachment_state
*att_state
)
4941 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
4945 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
4946 const struct anv_attachment_state
*att_state
)
4948 if (!cmd_state
->subpass
->view_mask
)
4951 uint32_t pending_clear_mask
=
4952 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4954 return pending_clear_mask
& 1;
4958 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
4961 const uint32_t last_subpass_idx
=
4962 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
4963 const struct anv_subpass
*last_subpass
=
4964 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
4965 return last_subpass
== cmd_state
->subpass
;
4969 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
4970 uint32_t subpass_id
)
4972 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4973 struct anv_render_pass
*pass
= cmd_state
->pass
;
4974 struct anv_subpass
*subpass
= &pass
->subpasses
[subpass_id
];
4975 cmd_state
->subpass
= subpass
;
4977 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
4979 /* Our implementation of VK_KHR_multiview uses instancing to draw the
4980 * different views. If the client asks for instancing, we need to use the
4981 * Instance Data Step Rate to ensure that we repeat the client's
4982 * per-instance data once for each view. Since this bit is in
4983 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
4987 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
4989 /* It is possible to start a render pass with an old pipeline. Because the
4990 * render pass and subpass index are both baked into the pipeline, this is
4991 * highly unlikely. In order to do so, it requires that you have a render
4992 * pass with a single subpass and that you use that render pass twice
4993 * back-to-back and use the same pipeline at the start of the second render
4994 * pass as at the end of the first. In order to avoid unpredictable issues
4995 * with this edge case, we just dirty the pipeline at the start of every
4998 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
5000 /* Accumulate any subpass flushes that need to happen before the subpass */
5001 cmd_buffer
->state
.pending_pipe_bits
|=
5002 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
5004 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
5005 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
5007 bool is_multiview
= subpass
->view_mask
!= 0;
5009 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5010 const uint32_t a
= subpass
->attachments
[i
].attachment
;
5011 if (a
== VK_ATTACHMENT_UNUSED
)
5014 assert(a
< cmd_state
->pass
->attachment_count
);
5015 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5017 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
5018 const struct anv_image
*image
= iview
->image
;
5020 VkImageLayout target_layout
= subpass
->attachments
[i
].layout
;
5021 VkImageLayout target_stencil_layout
=
5022 subpass
->attachments
[i
].stencil_layout
;
5024 uint32_t base_layer
, layer_count
;
5025 if (image
->type
== VK_IMAGE_TYPE_3D
) {
5027 layer_count
= anv_minify(iview
->image
->extent
.depth
,
5028 iview
->planes
[0].isl
.base_level
);
5030 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
5031 layer_count
= fb
->layers
;
5034 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
5035 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5036 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5037 iview
->planes
[0].isl
.base_level
, 1,
5038 base_layer
, layer_count
,
5039 att_state
->current_layout
, target_layout
);
5040 att_state
->aux_usage
=
5041 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
5042 VK_IMAGE_ASPECT_COLOR_BIT
,
5043 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
,
5047 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5048 transition_depth_buffer(cmd_buffer
, image
,
5049 base_layer
, layer_count
,
5050 att_state
->current_layout
, target_layout
);
5051 att_state
->aux_usage
=
5052 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
5053 VK_IMAGE_ASPECT_DEPTH_BIT
,
5054 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
5058 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5059 transition_stencil_buffer(cmd_buffer
, image
,
5060 iview
->planes
[0].isl
.base_level
, 1,
5061 base_layer
, layer_count
,
5062 att_state
->current_stencil_layout
,
5063 target_stencil_layout
);
5065 att_state
->current_layout
= target_layout
;
5066 att_state
->current_stencil_layout
= target_stencil_layout
;
5068 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
5069 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5071 /* Multi-planar images are not supported as attachments */
5072 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5073 assert(image
->n_planes
== 1);
5075 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
5076 uint32_t clear_layer_count
= fb
->layers
;
5078 if (att_state
->fast_clear
&&
5079 do_first_layer_clear(cmd_state
, att_state
)) {
5080 /* We only support fast-clears on the first layer */
5081 assert(iview
->planes
[0].isl
.base_level
== 0);
5082 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
5084 union isl_color_value clear_color
= {};
5085 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
5086 if (iview
->image
->samples
== 1) {
5087 anv_image_ccs_op(cmd_buffer
, image
,
5088 iview
->planes
[0].isl
.format
,
5089 iview
->planes
[0].isl
.swizzle
,
5090 VK_IMAGE_ASPECT_COLOR_BIT
,
5091 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
5095 anv_image_mcs_op(cmd_buffer
, image
,
5096 iview
->planes
[0].isl
.format
,
5097 iview
->planes
[0].isl
.swizzle
,
5098 VK_IMAGE_ASPECT_COLOR_BIT
,
5099 0, 1, ISL_AUX_OP_FAST_CLEAR
,
5104 clear_layer_count
--;
5106 att_state
->pending_clear_views
&= ~1;
5108 if (isl_color_value_is_zero(clear_color
,
5109 iview
->planes
[0].isl
.format
)) {
5110 /* This image has the auxiliary buffer enabled. We can mark the
5111 * subresource as not needing a resolve because the clear color
5112 * will match what's in every RENDER_SURFACE_STATE object when
5113 * it's being used for sampling.
5115 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
5116 VK_IMAGE_ASPECT_COLOR_BIT
,
5117 ANV_FAST_CLEAR_DEFAULT_VALUE
);
5119 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
5120 VK_IMAGE_ASPECT_COLOR_BIT
,
5121 ANV_FAST_CLEAR_ANY
);
5125 /* From the VkFramebufferCreateInfo spec:
5127 * "If the render pass uses multiview, then layers must be one and each
5128 * attachment requires a number of layers that is greater than the
5129 * maximum bit index set in the view mask in the subpasses in which it
5132 * So if multiview is active we ignore the number of layers in the
5133 * framebuffer and instead we honor the view mask from the subpass.
5136 assert(image
->n_planes
== 1);
5137 uint32_t pending_clear_mask
=
5138 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
5141 for_each_bit(layer_idx
, pending_clear_mask
) {
5143 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
5145 anv_image_clear_color(cmd_buffer
, image
,
5146 VK_IMAGE_ASPECT_COLOR_BIT
,
5147 att_state
->aux_usage
,
5148 iview
->planes
[0].isl
.format
,
5149 iview
->planes
[0].isl
.swizzle
,
5150 iview
->planes
[0].isl
.base_level
,
5153 vk_to_isl_color(att_state
->clear_value
.color
));
5156 att_state
->pending_clear_views
&= ~pending_clear_mask
;
5157 } else if (clear_layer_count
> 0) {
5158 assert(image
->n_planes
== 1);
5159 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5160 att_state
->aux_usage
,
5161 iview
->planes
[0].isl
.format
,
5162 iview
->planes
[0].isl
.swizzle
,
5163 iview
->planes
[0].isl
.base_level
,
5164 base_clear_layer
, clear_layer_count
,
5166 vk_to_isl_color(att_state
->clear_value
.color
));
5168 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
5169 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
5170 if (att_state
->fast_clear
&& !is_multiview
) {
5171 /* We currently only support HiZ for single-LOD images */
5172 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5173 assert(isl_aux_usage_has_hiz(iview
->image
->planes
[0].aux_usage
));
5174 assert(iview
->planes
[0].isl
.base_level
== 0);
5177 anv_image_hiz_clear(cmd_buffer
, image
,
5178 att_state
->pending_clear_aspects
,
5179 iview
->planes
[0].isl
.base_level
,
5180 iview
->planes
[0].isl
.base_array_layer
,
5181 fb
->layers
, render_area
,
5182 att_state
->clear_value
.depthStencil
.stencil
);
5183 } else if (is_multiview
) {
5184 uint32_t pending_clear_mask
=
5185 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
5188 for_each_bit(layer_idx
, pending_clear_mask
) {
5190 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
5192 anv_image_clear_depth_stencil(cmd_buffer
, image
,
5193 att_state
->pending_clear_aspects
,
5194 att_state
->aux_usage
,
5195 iview
->planes
[0].isl
.base_level
,
5198 att_state
->clear_value
.depthStencil
.depth
,
5199 att_state
->clear_value
.depthStencil
.stencil
);
5202 att_state
->pending_clear_views
&= ~pending_clear_mask
;
5204 anv_image_clear_depth_stencil(cmd_buffer
, image
,
5205 att_state
->pending_clear_aspects
,
5206 att_state
->aux_usage
,
5207 iview
->planes
[0].isl
.base_level
,
5208 iview
->planes
[0].isl
.base_array_layer
,
5209 fb
->layers
, render_area
,
5210 att_state
->clear_value
.depthStencil
.depth
,
5211 att_state
->clear_value
.depthStencil
.stencil
);
5214 assert(att_state
->pending_clear_aspects
== 0);
5217 /* If multiview is enabled, then we are only done clearing when we no
5218 * longer have pending layers to clear, or when we have processed the
5219 * last subpass that uses this attachment.
5221 if (!is_multiview
||
5222 att_state
->pending_clear_views
== 0 ||
5223 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
5224 att_state
->pending_clear_aspects
= 0;
5227 att_state
->pending_load_aspects
= 0;
5230 /* We've transitioned all our images possibly fast clearing them. Now we
5231 * can fill out the surface states that we will use as render targets
5232 * during actual subpass rendering.
5234 VkResult result
= genX(cmd_buffer_alloc_att_surf_states
)(cmd_buffer
,
5236 if (result
!= VK_SUCCESS
)
5239 isl_null_fill_state(&cmd_buffer
->device
->isl_dev
,
5240 cmd_state
->null_surface_state
.map
,
5241 isl_extent3d(fb
->width
, fb
->height
, fb
->layers
));
5243 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5244 const uint32_t att
= subpass
->attachments
[i
].attachment
;
5245 if (att
== VK_ATTACHMENT_UNUSED
)
5248 assert(att
< cmd_state
->pass
->attachment_count
);
5249 struct anv_render_pass_attachment
*pass_att
= &pass
->attachments
[att
];
5250 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
5251 struct anv_image_view
*iview
= att_state
->image_view
;
5253 if (!vk_format_is_color(pass_att
->format
))
5256 const VkImageUsageFlagBits att_usage
= subpass
->attachments
[i
].usage
;
5257 assert(util_bitcount(att_usage
) == 1);
5259 struct anv_surface_state
*surface_state
;
5260 isl_surf_usage_flags_t isl_surf_usage
;
5261 enum isl_aux_usage isl_aux_usage
;
5262 if (att_usage
== VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
5263 surface_state
= &att_state
->color
;
5264 isl_surf_usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
5265 isl_aux_usage
= att_state
->aux_usage
;
5266 } else if (att_usage
== VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
) {
5267 surface_state
= &att_state
->input
;
5268 isl_surf_usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
5270 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
5271 VK_IMAGE_ASPECT_COLOR_BIT
,
5272 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
,
5273 att_state
->current_layout
);
5278 /* We had better have a surface state when we get here */
5279 assert(surface_state
->state
.map
);
5281 union isl_color_value clear_color
= { .u32
= { 0, } };
5282 if (pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
&&
5283 att_state
->fast_clear
)
5284 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
5286 anv_image_fill_surface_state(cmd_buffer
->device
,
5288 VK_IMAGE_ASPECT_COLOR_BIT
,
5289 &iview
->planes
[0].isl
,
5297 add_surface_state_relocs(cmd_buffer
, *surface_state
);
5300 pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
&&
5301 iview
->image
->planes
[0].aux_usage
!= ISL_AUX_USAGE_NONE
&&
5302 iview
->planes
[0].isl
.base_level
== 0 &&
5303 iview
->planes
[0].isl
.base_array_layer
== 0) {
5304 genX(copy_fast_clear_dwords
)(cmd_buffer
, surface_state
->state
,
5306 VK_IMAGE_ASPECT_COLOR_BIT
,
5307 false /* copy to ss */);
5312 /* The PIPE_CONTROL command description says:
5314 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
5315 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
5316 * Target Cache Flush by enabling this bit. When render target flush
5317 * is set due to new association of BTI, PS Scoreboard Stall bit must
5318 * be set in this packet."
5320 cmd_buffer
->state
.pending_pipe_bits
|=
5321 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
|
5322 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
5326 /* GEN:BUG:14010455700
5328 * ISL will change some CHICKEN registers depending on the depth surface
5329 * format, along with emitting the depth and stencil packets. In that case,
5330 * we want to do a depth flush and stall, so the pipeline is not using these
5331 * settings while we change the registers.
5333 cmd_buffer
->state
.pending_pipe_bits
|=
5334 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
|
5335 ANV_PIPE_DEPTH_STALL_BIT
|
5336 ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
5337 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5340 cmd_buffer_emit_depth_stencil(cmd_buffer
);
5343 static enum blorp_filter
5344 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
5347 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
5348 return BLORP_FILTER_SAMPLE_0
;
5349 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
5350 return BLORP_FILTER_AVERAGE
;
5351 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
5352 return BLORP_FILTER_MIN_SAMPLE
;
5353 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
5354 return BLORP_FILTER_MAX_SAMPLE
;
5356 return BLORP_FILTER_NONE
;
5361 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
5363 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5364 struct anv_subpass
*subpass
= cmd_state
->subpass
;
5365 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
5366 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
5368 /* We are done with the previous subpass and all rendering directly to that
5369 * subpass is now complete. Zero out all the surface states so we don't
5370 * accidentally use them between now and the next subpass.
5372 for (uint32_t i
= 0; i
< cmd_state
->pass
->attachment_count
; ++i
) {
5373 memset(&cmd_state
->attachments
[i
].color
, 0,
5374 sizeof(cmd_state
->attachments
[i
].color
));
5375 memset(&cmd_state
->attachments
[i
].input
, 0,
5376 sizeof(cmd_state
->attachments
[i
].input
));
5378 cmd_state
->null_surface_state
= ANV_STATE_NULL
;
5379 cmd_state
->attachment_states
= ANV_STATE_NULL
;
5381 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5382 const uint32_t a
= subpass
->attachments
[i
].attachment
;
5383 if (a
== VK_ATTACHMENT_UNUSED
)
5386 assert(a
< cmd_state
->pass
->attachment_count
);
5387 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5388 struct anv_image_view
*iview
= att_state
->image_view
;
5390 assert(util_bitcount(subpass
->attachments
[i
].usage
) == 1);
5391 if (subpass
->attachments
[i
].usage
==
5392 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
5393 /* We assume that if we're ending a subpass, we did do some rendering
5394 * so we may end up with compressed data.
5396 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
5397 VK_IMAGE_ASPECT_COLOR_BIT
,
5398 att_state
->aux_usage
,
5399 iview
->planes
[0].isl
.base_level
,
5400 iview
->planes
[0].isl
.base_array_layer
,
5402 } else if (subpass
->attachments
[i
].usage
==
5403 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
5404 /* We may be writing depth or stencil so we need to mark the surface.
5405 * Unfortunately, there's no way to know at this point whether the
5406 * depth or stencil tests used will actually write to the surface.
5408 * Even though stencil may be plane 1, it always shares a base_level
5411 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
5412 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5413 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
5414 VK_IMAGE_ASPECT_DEPTH_BIT
,
5415 att_state
->aux_usage
,
5416 ds_view
->base_level
,
5417 ds_view
->base_array_layer
,
5420 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5421 /* Even though stencil may be plane 1, it always shares a
5422 * base_level with depth.
5424 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
5425 VK_IMAGE_ASPECT_STENCIL_BIT
,
5427 ds_view
->base_level
,
5428 ds_view
->base_array_layer
,
5434 if (subpass
->has_color_resolve
) {
5435 /* We are about to do some MSAA resolves. We need to flush so that the
5436 * result of writes to the MSAA color attachments show up in the sampler
5437 * when we blit to the single-sampled resolve target.
5439 cmd_buffer
->state
.pending_pipe_bits
|=
5440 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
5441 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
5443 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
5444 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
5445 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
5447 if (dst_att
== VK_ATTACHMENT_UNUSED
)
5450 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
5451 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
5453 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
5454 /* From the Vulkan 1.0 spec:
5456 * If the first use of an attachment in a render pass is as a
5457 * resolve attachment, then the loadOp is effectively ignored
5458 * as the resolve is guaranteed to overwrite all pixels in the
5461 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
5464 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
5465 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
5467 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
5469 enum isl_aux_usage src_aux_usage
=
5470 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
5471 enum isl_aux_usage dst_aux_usage
=
5472 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
5474 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
5475 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
5477 anv_image_msaa_resolve(cmd_buffer
,
5478 src_iview
->image
, src_aux_usage
,
5479 src_iview
->planes
[0].isl
.base_level
,
5480 src_iview
->planes
[0].isl
.base_array_layer
,
5481 dst_iview
->image
, dst_aux_usage
,
5482 dst_iview
->planes
[0].isl
.base_level
,
5483 dst_iview
->planes
[0].isl
.base_array_layer
,
5484 VK_IMAGE_ASPECT_COLOR_BIT
,
5485 render_area
.offset
.x
, render_area
.offset
.y
,
5486 render_area
.offset
.x
, render_area
.offset
.y
,
5487 render_area
.extent
.width
,
5488 render_area
.extent
.height
,
5489 fb
->layers
, BLORP_FILTER_NONE
);
5493 if (subpass
->ds_resolve_attachment
) {
5494 /* We are about to do some MSAA resolves. We need to flush so that the
5495 * result of writes to the MSAA depth attachments show up in the sampler
5496 * when we blit to the single-sampled resolve target.
5498 cmd_buffer
->state
.pending_pipe_bits
|=
5499 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
5500 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
5502 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
5503 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
5505 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
5506 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
5508 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
5509 /* From the Vulkan 1.0 spec:
5511 * If the first use of an attachment in a render pass is as a
5512 * resolve attachment, then the loadOp is effectively ignored
5513 * as the resolve is guaranteed to overwrite all pixels in the
5516 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
5519 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
5520 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
5522 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
5524 struct anv_attachment_state
*src_state
=
5525 &cmd_state
->attachments
[src_att
];
5526 struct anv_attachment_state
*dst_state
=
5527 &cmd_state
->attachments
[dst_att
];
5529 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
5530 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
5532 /* MSAA resolves sample from the source attachment. Transition the
5533 * depth attachment first to get rid of any HiZ that we may not be
5536 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
5537 src_iview
->planes
[0].isl
.base_array_layer
,
5539 src_state
->current_layout
,
5540 VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
);
5541 src_state
->aux_usage
=
5542 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
5543 VK_IMAGE_ASPECT_DEPTH_BIT
,
5544 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
,
5545 VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
);
5546 src_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
;
5548 /* MSAA resolves write to the resolve attachment as if it were any
5549 * other transfer op. Transition the resolve attachment accordingly.
5551 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
5553 /* If our render area is the entire size of the image, we're going to
5554 * blow it all away so we can claim the initial layout is UNDEFINED
5555 * and we'll get a HiZ ambiguate instead of a resolve.
5557 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
5558 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
5559 render_area
.extent
.width
== dst_iview
->extent
.width
&&
5560 render_area
.extent
.height
== dst_iview
->extent
.height
)
5561 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
5563 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
5564 dst_iview
->planes
[0].isl
.base_array_layer
,
5567 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
5568 dst_state
->aux_usage
=
5569 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
5570 VK_IMAGE_ASPECT_DEPTH_BIT
,
5571 VK_IMAGE_USAGE_TRANSFER_DST_BIT
,
5572 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
5573 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
5575 enum blorp_filter filter
=
5576 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
5578 anv_image_msaa_resolve(cmd_buffer
,
5579 src_iview
->image
, src_state
->aux_usage
,
5580 src_iview
->planes
[0].isl
.base_level
,
5581 src_iview
->planes
[0].isl
.base_array_layer
,
5582 dst_iview
->image
, dst_state
->aux_usage
,
5583 dst_iview
->planes
[0].isl
.base_level
,
5584 dst_iview
->planes
[0].isl
.base_array_layer
,
5585 VK_IMAGE_ASPECT_DEPTH_BIT
,
5586 render_area
.offset
.x
, render_area
.offset
.y
,
5587 render_area
.offset
.x
, render_area
.offset
.y
,
5588 render_area
.extent
.width
,
5589 render_area
.extent
.height
,
5590 fb
->layers
, filter
);
5593 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
5594 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
5596 src_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
;
5597 dst_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
5599 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
5600 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
5602 enum blorp_filter filter
=
5603 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
5605 anv_image_msaa_resolve(cmd_buffer
,
5606 src_iview
->image
, src_aux_usage
,
5607 src_iview
->planes
[0].isl
.base_level
,
5608 src_iview
->planes
[0].isl
.base_array_layer
,
5609 dst_iview
->image
, dst_aux_usage
,
5610 dst_iview
->planes
[0].isl
.base_level
,
5611 dst_iview
->planes
[0].isl
.base_array_layer
,
5612 VK_IMAGE_ASPECT_STENCIL_BIT
,
5613 render_area
.offset
.x
, render_area
.offset
.y
,
5614 render_area
.offset
.x
, render_area
.offset
.y
,
5615 render_area
.extent
.width
,
5616 render_area
.extent
.height
,
5617 fb
->layers
, filter
);
5622 /* On gen7, we have to store a texturable version of the stencil buffer in
5623 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
5624 * forth at strategic points. Stencil writes are only allowed in following
5627 * - VK_IMAGE_LAYOUT_GENERAL
5628 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
5629 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
5630 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
5631 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
5633 * For general, we have no nice opportunity to transition so we do the copy
5634 * to the shadow unconditionally at the end of the subpass. For transfer
5635 * destinations, we can update it as part of the transfer op. For the other
5636 * layouts, we delay the copy until a transition into some other layout.
5638 if (subpass
->depth_stencil_attachment
) {
5639 uint32_t a
= subpass
->depth_stencil_attachment
->attachment
;
5640 assert(a
!= VK_ATTACHMENT_UNUSED
);
5642 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5643 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;;
5644 const struct anv_image
*image
= iview
->image
;
5646 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5647 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
5648 VK_IMAGE_ASPECT_STENCIL_BIT
);
5650 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
5651 att_state
->current_stencil_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
5652 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
5653 anv_image_copy_to_shadow(cmd_buffer
, image
,
5654 VK_IMAGE_ASPECT_STENCIL_BIT
,
5655 iview
->planes
[plane
].isl
.base_level
, 1,
5656 iview
->planes
[plane
].isl
.base_array_layer
,
5661 #endif /* GEN_GEN == 7 */
5663 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5664 const uint32_t a
= subpass
->attachments
[i
].attachment
;
5665 if (a
== VK_ATTACHMENT_UNUSED
)
5668 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
5671 assert(a
< cmd_state
->pass
->attachment_count
);
5672 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5673 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
5674 const struct anv_image
*image
= iview
->image
;
5676 /* Transition the image into the final layout for this render pass */
5677 VkImageLayout target_layout
=
5678 cmd_state
->pass
->attachments
[a
].final_layout
;
5679 VkImageLayout target_stencil_layout
=
5680 cmd_state
->pass
->attachments
[a
].stencil_final_layout
;
5682 uint32_t base_layer
, layer_count
;
5683 if (image
->type
== VK_IMAGE_TYPE_3D
) {
5685 layer_count
= anv_minify(iview
->image
->extent
.depth
,
5686 iview
->planes
[0].isl
.base_level
);
5688 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
5689 layer_count
= fb
->layers
;
5692 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
5693 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5694 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5695 iview
->planes
[0].isl
.base_level
, 1,
5696 base_layer
, layer_count
,
5697 att_state
->current_layout
, target_layout
);
5700 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5701 transition_depth_buffer(cmd_buffer
, image
,
5702 base_layer
, layer_count
,
5703 att_state
->current_layout
, target_layout
);
5706 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5707 transition_stencil_buffer(cmd_buffer
, image
,
5708 iview
->planes
[0].isl
.base_level
, 1,
5709 base_layer
, layer_count
,
5710 att_state
->current_stencil_layout
,
5711 target_stencil_layout
);
5715 /* Accumulate any subpass flushes that need to happen after the subpass.
5716 * Yes, they do get accumulated twice in the NextSubpass case but since
5717 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
5718 * ORing the bits in twice so it's harmless.
5720 cmd_buffer
->state
.pending_pipe_bits
|=
5721 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
5724 void genX(CmdBeginRenderPass
)(
5725 VkCommandBuffer commandBuffer
,
5726 const VkRenderPassBeginInfo
* pRenderPassBegin
,
5727 VkSubpassContents contents
)
5729 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5730 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
5731 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
5734 cmd_buffer
->state
.framebuffer
= framebuffer
;
5735 cmd_buffer
->state
.pass
= pass
;
5736 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
5738 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
,
5741 if (result
!= VK_SUCCESS
) {
5742 assert(anv_batch_has_error(&cmd_buffer
->batch
));
5746 genX(flush_pipeline_select_3d
)(cmd_buffer
);
5748 cmd_buffer_begin_subpass(cmd_buffer
, 0);
5751 void genX(CmdBeginRenderPass2
)(
5752 VkCommandBuffer commandBuffer
,
5753 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
5754 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
5756 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
5757 pSubpassBeginInfo
->contents
);
5760 void genX(CmdNextSubpass
)(
5761 VkCommandBuffer commandBuffer
,
5762 VkSubpassContents contents
)
5764 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5766 if (anv_batch_has_error(&cmd_buffer
->batch
))
5769 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
5771 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
5772 cmd_buffer_end_subpass(cmd_buffer
);
5773 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
5776 void genX(CmdNextSubpass2
)(
5777 VkCommandBuffer commandBuffer
,
5778 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
5779 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5781 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
5784 void genX(CmdEndRenderPass
)(
5785 VkCommandBuffer commandBuffer
)
5787 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5789 if (anv_batch_has_error(&cmd_buffer
->batch
))
5792 cmd_buffer_end_subpass(cmd_buffer
);
5794 cmd_buffer
->state
.hiz_enabled
= false;
5797 anv_dump_add_attachments(cmd_buffer
);
5800 /* Remove references to render pass specific state. This enables us to
5801 * detect whether or not we're in a renderpass.
5803 cmd_buffer
->state
.framebuffer
= NULL
;
5804 cmd_buffer
->state
.pass
= NULL
;
5805 cmd_buffer
->state
.subpass
= NULL
;
5808 void genX(CmdEndRenderPass2
)(
5809 VkCommandBuffer commandBuffer
,
5810 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5812 genX(CmdEndRenderPass
)(commandBuffer
);
5816 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
5818 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5819 struct gen_mi_builder b
;
5820 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5822 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
5823 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
5824 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
5826 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
5827 mip
.LoadOperation
= LOAD_LOADINV
;
5828 mip
.CombineOperation
= COMBINE_SET
;
5829 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
5834 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5835 void genX(CmdBeginConditionalRenderingEXT
)(
5836 VkCommandBuffer commandBuffer
,
5837 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5839 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5840 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5841 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5842 struct anv_address value_address
=
5843 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
5845 const bool isInverted
= pConditionalRenderingBegin
->flags
&
5846 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
5848 cmd_state
->conditional_render_enabled
= true;
5850 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5852 struct gen_mi_builder b
;
5853 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5855 /* Section 19.4 of the Vulkan 1.1.85 spec says:
5857 * If the value of the predicate in buffer memory changes
5858 * while conditional rendering is active, the rendering commands
5859 * may be discarded in an implementation-dependent way.
5860 * Some implementations may latch the value of the predicate
5861 * upon beginning conditional rendering while others
5862 * may read it before every rendering command.
5864 * So it's perfectly fine to read a value from the buffer once.
5866 struct gen_mi_value value
= gen_mi_mem32(value_address
);
5868 /* Precompute predicate result, it is necessary to support secondary
5869 * command buffers since it is unknown if conditional rendering is
5870 * inverted when populating them.
5872 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
5873 isInverted
? gen_mi_uge(&b
, gen_mi_imm(0), value
) :
5874 gen_mi_ult(&b
, gen_mi_imm(0), value
));
5877 void genX(CmdEndConditionalRenderingEXT
)(
5878 VkCommandBuffer commandBuffer
)
5880 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5881 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5883 cmd_state
->conditional_render_enabled
= false;
5887 /* Set of stage bits for which are pipelined, i.e. they get queued by the
5888 * command streamer for later execution.
5890 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
5891 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
5892 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
5893 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
5894 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
5895 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
5896 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
5897 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
5898 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
5899 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
5900 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
5901 VK_PIPELINE_STAGE_TRANSFER_BIT | \
5902 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
5903 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
5904 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
5906 void genX(CmdSetEvent
)(
5907 VkCommandBuffer commandBuffer
,
5909 VkPipelineStageFlags stageMask
)
5911 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5912 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5914 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
5915 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5917 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5918 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5919 pc
.StallAtPixelScoreboard
= true;
5920 pc
.CommandStreamerStallEnable
= true;
5923 pc
.DestinationAddressType
= DAT_PPGTT
,
5924 pc
.PostSyncOperation
= WriteImmediateData
,
5925 pc
.Address
= (struct anv_address
) {
5926 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5929 pc
.ImmediateData
= VK_EVENT_SET
;
5933 void genX(CmdResetEvent
)(
5934 VkCommandBuffer commandBuffer
,
5936 VkPipelineStageFlags stageMask
)
5938 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5939 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5941 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
5942 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5944 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5945 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5946 pc
.StallAtPixelScoreboard
= true;
5947 pc
.CommandStreamerStallEnable
= true;
5950 pc
.DestinationAddressType
= DAT_PPGTT
;
5951 pc
.PostSyncOperation
= WriteImmediateData
;
5952 pc
.Address
= (struct anv_address
) {
5953 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5956 pc
.ImmediateData
= VK_EVENT_RESET
;
5960 void genX(CmdWaitEvents
)(
5961 VkCommandBuffer commandBuffer
,
5962 uint32_t eventCount
,
5963 const VkEvent
* pEvents
,
5964 VkPipelineStageFlags srcStageMask
,
5965 VkPipelineStageFlags destStageMask
,
5966 uint32_t memoryBarrierCount
,
5967 const VkMemoryBarrier
* pMemoryBarriers
,
5968 uint32_t bufferMemoryBarrierCount
,
5969 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5970 uint32_t imageMemoryBarrierCount
,
5971 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5974 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5976 for (uint32_t i
= 0; i
< eventCount
; i
++) {
5977 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
5979 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
5980 sem
.WaitMode
= PollingMode
,
5981 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
5982 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
5983 sem
.SemaphoreAddress
= (struct anv_address
) {
5984 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5990 anv_finishme("Implement events on gen7");
5993 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
5994 false, /* byRegion */
5995 memoryBarrierCount
, pMemoryBarriers
,
5996 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5997 imageMemoryBarrierCount
, pImageMemoryBarriers
);
6000 VkResult
genX(CmdSetPerformanceOverrideINTEL
)(
6001 VkCommandBuffer commandBuffer
,
6002 const VkPerformanceOverrideInfoINTEL
* pOverrideInfo
)
6004 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6006 switch (pOverrideInfo
->type
) {
6007 case VK_PERFORMANCE_OVERRIDE_TYPE_NULL_HARDWARE_INTEL
: {
6011 anv_pack_struct(&dw
, GENX(CS_DEBUG_MODE2
),
6012 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
6013 .MediaInstructionDisable
= pOverrideInfo
->enable
,
6014 ._3DRenderingInstructionDisableMask
= true,
6015 .MediaInstructionDisableMask
= true);
6016 emit_lri(&cmd_buffer
->batch
, GENX(CS_DEBUG_MODE2_num
), dw
);
6018 anv_pack_struct(&dw
, GENX(INSTPM
),
6019 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
6020 .MediaInstructionDisable
= pOverrideInfo
->enable
,
6021 ._3DRenderingInstructionDisableMask
= true,
6022 .MediaInstructionDisableMask
= true);
6023 emit_lri(&cmd_buffer
->batch
, GENX(INSTPM_num
), dw
);
6028 case VK_PERFORMANCE_OVERRIDE_TYPE_FLUSH_GPU_CACHES_INTEL
:
6029 if (pOverrideInfo
->enable
) {
6030 /* FLUSH ALL THE THINGS! As requested by the MDAPI team. */
6031 cmd_buffer
->state
.pending_pipe_bits
|=
6032 ANV_PIPE_FLUSH_BITS
|
6033 ANV_PIPE_INVALIDATE_BITS
;
6034 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
6039 unreachable("Invalid override");
6045 VkResult
genX(CmdSetPerformanceStreamMarkerINTEL
)(
6046 VkCommandBuffer commandBuffer
,
6047 const VkPerformanceStreamMarkerInfoINTEL
* pMarkerInfo
)
6049 /* TODO: Waiting on the register to write, might depend on generation. */