2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_aux_map.h"
33 #include "common/gen_l3_config.h"
34 #include "genxml/gen_macros.h"
35 #include "genxml/genX_pack.h"
38 * - GPR 14 for secondary command buffer returns
39 * - GPR 15 for conditional rendering
41 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
42 #define __gen_get_batch_dwords anv_batch_emit_dwords
43 #define __gen_address_offset anv_address_add
44 #include "common/gen_mi_builder.h"
46 static void genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
50 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
52 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
53 lri
.RegisterOffset
= reg
;
59 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
61 struct anv_device
*device
= cmd_buffer
->device
;
62 UNUSED
const struct gen_device_info
*devinfo
= &device
->info
;
63 uint32_t mocs
= device
->isl_dev
.mocs
.internal
;
65 /* If we are emitting a new state base address we probably need to re-emit
68 cmd_buffer
->state
.descriptors_dirty
|= ~0;
70 /* Emit a render target cache flush.
72 * This isn't documented anywhere in the PRM. However, it seems to be
73 * necessary prior to changing the surface state base adress. Without
74 * this, we get GPU hangs when using multi-level command buffers which
75 * clear depth, reset state base address, and then go render stuff.
77 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
78 pc
.DCFlushEnable
= true;
79 pc
.RenderTargetCacheFlushEnable
= true;
80 pc
.CommandStreamerStallEnable
= true;
82 pc
.TileCacheFlushEnable
= true;
85 /* GEN:BUG:1606662791:
87 * Software must program PIPE_CONTROL command with "HDC Pipeline
88 * Flush" prior to programming of the below two non-pipeline state :
89 * * STATE_BASE_ADDRESS
90 * * 3DSTATE_BINDING_TABLE_POOL_ALLOC
92 if (devinfo
->revision
== 0 /* A0 */)
93 pc
.HDCPipelineFlushEnable
= true;
98 /* GEN:BUG:1607854226:
100 * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
101 * mode by putting the pipeline temporarily in 3D mode.
103 uint32_t gen12_wa_pipeline
= cmd_buffer
->state
.current_pipeline
;
104 genX(flush_pipeline_select_3d
)(cmd_buffer
);
107 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
108 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
109 sba
.GeneralStateMOCS
= mocs
;
110 sba
.GeneralStateBaseAddressModifyEnable
= true;
112 sba
.StatelessDataPortAccessMOCS
= mocs
;
114 sba
.SurfaceStateBaseAddress
=
115 anv_cmd_buffer_surface_base_address(cmd_buffer
);
116 sba
.SurfaceStateMOCS
= mocs
;
117 sba
.SurfaceStateBaseAddressModifyEnable
= true;
119 sba
.DynamicStateBaseAddress
=
120 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
121 sba
.DynamicStateMOCS
= mocs
;
122 sba
.DynamicStateBaseAddressModifyEnable
= true;
124 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
125 sba
.IndirectObjectMOCS
= mocs
;
126 sba
.IndirectObjectBaseAddressModifyEnable
= true;
128 sba
.InstructionBaseAddress
=
129 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
130 sba
.InstructionMOCS
= mocs
;
131 sba
.InstructionBaseAddressModifyEnable
= true;
134 /* Broadwell requires that we specify a buffer size for a bunch of
135 * these fields. However, since we will be growing the BO's live, we
136 * just set them all to the maximum.
138 sba
.GeneralStateBufferSize
= 0xfffff;
139 sba
.IndirectObjectBufferSize
= 0xfffff;
140 if (device
->physical
->use_softpin
) {
141 /* With softpin, we use fixed addresses so we actually know how big
142 * our base addresses are.
144 sba
.DynamicStateBufferSize
= DYNAMIC_STATE_POOL_SIZE
/ 4096;
145 sba
.InstructionBufferSize
= INSTRUCTION_STATE_POOL_SIZE
/ 4096;
147 sba
.DynamicStateBufferSize
= 0xfffff;
148 sba
.InstructionBufferSize
= 0xfffff;
150 sba
.GeneralStateBufferSizeModifyEnable
= true;
151 sba
.IndirectObjectBufferSizeModifyEnable
= true;
152 sba
.DynamicStateBufferSizeModifyEnable
= true;
153 sba
.InstructionBuffersizeModifyEnable
= true;
155 /* On gen7, we have upper bounds instead. According to the docs,
156 * setting an upper bound of zero means that no bounds checking is
157 * performed so, in theory, we should be able to leave them zero.
158 * However, border color is broken and the GPU bounds-checks anyway.
159 * To avoid this and other potential problems, we may as well set it
162 sba
.GeneralStateAccessUpperBound
=
163 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
164 sba
.GeneralStateAccessUpperBoundModifyEnable
= true;
165 sba
.DynamicStateAccessUpperBound
=
166 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
167 sba
.DynamicStateAccessUpperBoundModifyEnable
= true;
168 sba
.InstructionAccessUpperBound
=
169 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
170 sba
.InstructionAccessUpperBoundModifyEnable
= true;
173 if (cmd_buffer
->device
->physical
->use_softpin
) {
174 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) {
175 .bo
= device
->surface_state_pool
.block_pool
.bo
,
178 sba
.BindlessSurfaceStateSize
= (1 << 20) - 1;
180 sba
.BindlessSurfaceStateBaseAddress
= ANV_NULL_ADDRESS
;
181 sba
.BindlessSurfaceStateSize
= 0;
183 sba
.BindlessSurfaceStateMOCS
= mocs
;
184 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
187 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
188 sba
.BindlessSamplerStateMOCS
= mocs
;
189 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
190 sba
.BindlessSamplerStateBufferSize
= 0;
195 /* GEN:BUG:1607854226:
197 * Put the pipeline back into its current mode.
199 if (gen12_wa_pipeline
!= UINT32_MAX
)
200 genX(flush_pipeline_select
)(cmd_buffer
, gen12_wa_pipeline
);
203 /* After re-setting the surface state base address, we have to do some
204 * cache flusing so that the sampler engine will pick up the new
205 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
206 * Shared Function > 3D Sampler > State > State Caching (page 96):
208 * Coherency with system memory in the state cache, like the texture
209 * cache is handled partially by software. It is expected that the
210 * command stream or shader will issue Cache Flush operation or
211 * Cache_Flush sampler message to ensure that the L1 cache remains
212 * coherent with system memory.
216 * Whenever the value of the Dynamic_State_Base_Addr,
217 * Surface_State_Base_Addr are altered, the L1 state cache must be
218 * invalidated to ensure the new surface or sampler state is fetched
219 * from system memory.
221 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
222 * which, according the PIPE_CONTROL instruction documentation in the
225 * Setting this bit is independent of any other bit in this packet.
226 * This bit controls the invalidation of the L1 and L2 state caches
227 * at the top of the pipe i.e. at the parsing time.
229 * Unfortunately, experimentation seems to indicate that state cache
230 * invalidation through a PIPE_CONTROL does nothing whatsoever in
231 * regards to surface state and binding tables. In stead, it seems that
232 * invalidating the texture cache is what is actually needed.
234 * XXX: As far as we have been able to determine through
235 * experimentation, shows that flush the texture cache appears to be
236 * sufficient. The theory here is that all of the sampling/rendering
237 * units cache the binding table in the texture cache. However, we have
238 * yet to be able to actually confirm this.
240 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
241 pc
.TextureCacheInvalidationEnable
= true;
242 pc
.ConstantCacheInvalidationEnable
= true;
243 pc
.StateCacheInvalidationEnable
= true;
248 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
249 struct anv_state state
, struct anv_address addr
)
251 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
254 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
255 state
.offset
+ isl_dev
->ss
.addr_offset
,
256 addr
.bo
, addr
.offset
, NULL
);
257 if (result
!= VK_SUCCESS
)
258 anv_batch_set_error(&cmd_buffer
->batch
, result
);
262 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
263 struct anv_surface_state state
)
265 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
267 assert(!anv_address_is_null(state
.address
));
268 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
270 if (!anv_address_is_null(state
.aux_address
)) {
272 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
273 &cmd_buffer
->pool
->alloc
,
274 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
275 state
.aux_address
.bo
,
276 state
.aux_address
.offset
,
278 if (result
!= VK_SUCCESS
)
279 anv_batch_set_error(&cmd_buffer
->batch
, result
);
282 if (!anv_address_is_null(state
.clear_address
)) {
284 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
285 &cmd_buffer
->pool
->alloc
,
287 isl_dev
->ss
.clear_color_state_offset
,
288 state
.clear_address
.bo
,
289 state
.clear_address
.offset
,
291 if (result
!= VK_SUCCESS
)
292 anv_batch_set_error(&cmd_buffer
->batch
, result
);
297 isl_color_value_requires_conversion(union isl_color_value color
,
298 const struct isl_surf
*surf
,
299 const struct isl_view
*view
)
301 if (surf
->format
== view
->format
&& isl_swizzle_is_identity(view
->swizzle
))
304 uint32_t surf_pack
[4] = { 0, 0, 0, 0 };
305 isl_color_value_pack(&color
, surf
->format
, surf_pack
);
307 uint32_t view_pack
[4] = { 0, 0, 0, 0 };
308 union isl_color_value swiz_color
=
309 isl_color_value_swizzle_inv(color
, view
->swizzle
);
310 isl_color_value_pack(&swiz_color
, view
->format
, view_pack
);
312 return memcmp(surf_pack
, view_pack
, sizeof(surf_pack
)) != 0;
316 anv_can_fast_clear_color_view(struct anv_device
* device
,
317 struct anv_image_view
*iview
,
318 VkImageLayout layout
,
319 union isl_color_value clear_color
,
321 VkRect2D render_area
)
323 if (iview
->planes
[0].isl
.base_array_layer
>=
324 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
325 iview
->planes
[0].isl
.base_level
))
328 /* Start by getting the fast clear type. We use the first subpass
329 * layout here because we don't want to fast-clear if the first subpass
330 * to use the attachment can't handle fast-clears.
332 enum anv_fast_clear_type fast_clear_type
=
333 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
334 VK_IMAGE_ASPECT_COLOR_BIT
,
336 switch (fast_clear_type
) {
337 case ANV_FAST_CLEAR_NONE
:
339 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
340 if (!isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
))
343 case ANV_FAST_CLEAR_ANY
:
347 /* Potentially, we could do partial fast-clears but doing so has crazy
348 * alignment restrictions. It's easier to just restrict to full size
349 * fast clears for now.
351 if (render_area
.offset
.x
!= 0 ||
352 render_area
.offset
.y
!= 0 ||
353 render_area
.extent
.width
!= iview
->extent
.width
||
354 render_area
.extent
.height
!= iview
->extent
.height
)
357 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
359 !isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
))
362 /* If the clear color is one that would require non-trivial format
363 * conversion on resolve, we don't bother with the fast clear. This
364 * shouldn't be common as most clear colors are 0/1 and the most common
365 * format re-interpretation is for sRGB.
367 if (isl_color_value_requires_conversion(clear_color
,
368 &iview
->image
->planes
[0].surface
.isl
,
369 &iview
->planes
[0].isl
)) {
370 anv_perf_warn(device
, iview
,
371 "Cannot fast-clear to colors which would require "
372 "format conversion on resolve");
376 /* We only allow fast clears to the first slice of an image (level 0,
377 * layer 0) and only for the entire slice. This guarantees us that, at
378 * any given time, there is only one clear color on any given image at
379 * any given time. At the time of our testing (Jan 17, 2018), there
380 * were no known applications which would benefit from fast-clearing
381 * more than just the first slice.
383 if (iview
->planes
[0].isl
.base_level
> 0 ||
384 iview
->planes
[0].isl
.base_array_layer
> 0) {
385 anv_perf_warn(device
, iview
->image
,
386 "Rendering with multi-lod or multi-layer framebuffer "
387 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
388 "baseArrayLayer > 0. Not fast clearing.");
392 if (num_layers
> 1) {
393 anv_perf_warn(device
, iview
->image
,
394 "Rendering to a multi-layer framebuffer with "
395 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
402 anv_can_hiz_clear_ds_view(struct anv_device
*device
,
403 struct anv_image_view
*iview
,
404 VkImageLayout layout
,
405 VkImageAspectFlags clear_aspects
,
406 float depth_clear_value
,
407 VkRect2D render_area
)
409 /* We don't do any HiZ or depth fast-clears on gen7 yet */
413 /* If we're just clearing stencil, we can always HiZ clear */
414 if (!(clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
417 /* We must have depth in order to have HiZ */
418 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
421 const enum isl_aux_usage clear_aux_usage
=
422 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
423 VK_IMAGE_ASPECT_DEPTH_BIT
,
424 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
426 if (!blorp_can_hiz_clear_depth(&device
->info
,
427 &iview
->image
->planes
[0].surface
.isl
,
429 iview
->planes
[0].isl
.base_level
,
430 iview
->planes
[0].isl
.base_array_layer
,
431 render_area
.offset
.x
,
432 render_area
.offset
.y
,
433 render_area
.offset
.x
+
434 render_area
.extent
.width
,
435 render_area
.offset
.y
+
436 render_area
.extent
.height
))
439 if (depth_clear_value
!= ANV_HZ_FC_VAL
)
442 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a fast-cleared
443 * portion of a HiZ buffer. Testing has revealed that Gen8 only supports
444 * returning 0.0f. Gens prior to gen8 do not support this feature at all.
446 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
))
449 /* If we got here, then we can fast clear */
453 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
457 anv_image_init_aux_tt(struct anv_cmd_buffer
*cmd_buffer
,
458 const struct anv_image
*image
,
459 VkImageAspectFlagBits aspect
,
460 uint32_t base_level
, uint32_t level_count
,
461 uint32_t base_layer
, uint32_t layer_count
)
463 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
465 uint64_t base_address
=
466 anv_address_physical(image
->planes
[plane
].address
);
468 const struct isl_surf
*isl_surf
= &image
->planes
[plane
].surface
.isl
;
469 uint64_t format_bits
= gen_aux_map_format_bits_for_isl_surf(isl_surf
);
471 /* We're about to live-update the AUX-TT. We really don't want anyone else
472 * trying to read it while we're doing this. We could probably get away
473 * with not having this stall in some cases if we were really careful but
474 * it's better to play it safe. Full stall the GPU.
476 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
477 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
479 struct gen_mi_builder b
;
480 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
482 for (uint32_t a
= 0; a
< layer_count
; a
++) {
483 const uint32_t layer
= base_layer
+ a
;
485 uint64_t start_offset_B
= UINT64_MAX
, end_offset_B
= 0;
486 for (uint32_t l
= 0; l
< level_count
; l
++) {
487 const uint32_t level
= base_level
+ l
;
489 uint32_t logical_array_layer
, logical_z_offset_px
;
490 if (image
->type
== VK_IMAGE_TYPE_3D
) {
491 logical_array_layer
= 0;
493 /* If the given miplevel does not have this layer, then any higher
494 * miplevels won't either because miplevels only get smaller the
497 assert(layer
< image
->extent
.depth
);
498 if (layer
>= anv_minify(image
->extent
.depth
, level
))
500 logical_z_offset_px
= layer
;
502 assert(layer
< image
->array_size
);
503 logical_array_layer
= layer
;
504 logical_z_offset_px
= 0;
507 uint32_t slice_start_offset_B
, slice_end_offset_B
;
508 isl_surf_get_image_range_B_tile(isl_surf
, level
,
511 &slice_start_offset_B
,
512 &slice_end_offset_B
);
514 start_offset_B
= MIN2(start_offset_B
, slice_start_offset_B
);
515 end_offset_B
= MAX2(end_offset_B
, slice_end_offset_B
);
518 /* Aux operates 64K at a time */
519 start_offset_B
= align_down_u64(start_offset_B
, 64 * 1024);
520 end_offset_B
= align_u64(end_offset_B
, 64 * 1024);
522 for (uint64_t offset
= start_offset_B
;
523 offset
< end_offset_B
; offset
+= 64 * 1024) {
524 uint64_t address
= base_address
+ offset
;
526 uint64_t aux_entry_addr64
, *aux_entry_map
;
527 aux_entry_map
= gen_aux_map_get_entry(cmd_buffer
->device
->aux_map_ctx
,
528 address
, &aux_entry_addr64
);
530 assert(cmd_buffer
->device
->physical
->use_softpin
);
531 struct anv_address aux_entry_address
= {
533 .offset
= aux_entry_addr64
,
536 const uint64_t old_aux_entry
= READ_ONCE(*aux_entry_map
);
537 uint64_t new_aux_entry
=
538 (old_aux_entry
& GEN_AUX_MAP_ADDRESS_MASK
) | format_bits
;
540 if (isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
))
541 new_aux_entry
|= GEN_AUX_MAP_ENTRY_VALID_BIT
;
543 gen_mi_store(&b
, gen_mi_mem64(aux_entry_address
),
544 gen_mi_imm(new_aux_entry
));
548 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
;
550 #endif /* GEN_GEN == 12 */
552 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
553 * the initial layout is undefined, the HiZ buffer and depth buffer will
554 * represent the same data at the end of this operation.
557 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
558 const struct anv_image
*image
,
559 uint32_t base_layer
, uint32_t layer_count
,
560 VkImageLayout initial_layout
,
561 VkImageLayout final_layout
)
563 uint32_t depth_plane
=
564 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
565 if (image
->planes
[depth_plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
569 if ((initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
570 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) &&
571 cmd_buffer
->device
->physical
->has_implicit_ccs
&&
572 cmd_buffer
->device
->info
.has_aux_map
) {
573 anv_image_init_aux_tt(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
578 const enum isl_aux_state initial_state
=
579 anv_layout_to_aux_state(&cmd_buffer
->device
->info
, image
,
580 VK_IMAGE_ASPECT_DEPTH_BIT
,
582 const enum isl_aux_state final_state
=
583 anv_layout_to_aux_state(&cmd_buffer
->device
->info
, image
,
584 VK_IMAGE_ASPECT_DEPTH_BIT
,
587 const bool initial_depth_valid
=
588 isl_aux_state_has_valid_primary(initial_state
);
589 const bool initial_hiz_valid
=
590 isl_aux_state_has_valid_aux(initial_state
);
591 const bool final_needs_depth
=
592 isl_aux_state_has_valid_primary(final_state
);
593 const bool final_needs_hiz
=
594 isl_aux_state_has_valid_aux(final_state
);
596 /* Getting into the pass-through state for Depth is tricky and involves
597 * both a resolve and an ambiguate. We don't handle that state right now
598 * as anv_layout_to_aux_state never returns it.
600 assert(final_state
!= ISL_AUX_STATE_PASS_THROUGH
);
602 if (final_needs_depth
&& !initial_depth_valid
) {
603 assert(initial_hiz_valid
);
604 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
605 0, base_layer
, layer_count
, ISL_AUX_OP_FULL_RESOLVE
);
606 } else if (final_needs_hiz
&& !initial_hiz_valid
) {
607 assert(initial_depth_valid
);
608 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
609 0, base_layer
, layer_count
, ISL_AUX_OP_AMBIGUATE
);
614 vk_image_layout_stencil_write_optimal(VkImageLayout layout
)
616 return layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
617 layout
== VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
||
618 layout
== VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
;
621 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
622 * the initial layout is undefined, the HiZ buffer and depth buffer will
623 * represent the same data at the end of this operation.
626 transition_stencil_buffer(struct anv_cmd_buffer
*cmd_buffer
,
627 const struct anv_image
*image
,
628 uint32_t base_level
, uint32_t level_count
,
629 uint32_t base_layer
, uint32_t layer_count
,
630 VkImageLayout initial_layout
,
631 VkImageLayout final_layout
)
634 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
635 VK_IMAGE_ASPECT_STENCIL_BIT
);
637 /* On gen7, we have to store a texturable version of the stencil buffer in
638 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
639 * forth at strategic points. Stencil writes are only allowed in following
642 * - VK_IMAGE_LAYOUT_GENERAL
643 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
644 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
645 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
646 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
648 * For general, we have no nice opportunity to transition so we do the copy
649 * to the shadow unconditionally at the end of the subpass. For transfer
650 * destinations, we can update it as part of the transfer op. For the other
651 * layouts, we delay the copy until a transition into some other layout.
653 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
654 vk_image_layout_stencil_write_optimal(initial_layout
) &&
655 !vk_image_layout_stencil_write_optimal(final_layout
)) {
656 anv_image_copy_to_shadow(cmd_buffer
, image
,
657 VK_IMAGE_ASPECT_STENCIL_BIT
,
658 base_level
, level_count
,
659 base_layer
, layer_count
);
661 #endif /* GEN_GEN == 7 */
664 #define MI_PREDICATE_SRC0 0x2400
665 #define MI_PREDICATE_SRC1 0x2408
666 #define MI_PREDICATE_RESULT 0x2418
669 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
670 const struct anv_image
*image
,
671 VkImageAspectFlagBits aspect
,
673 uint32_t base_layer
, uint32_t layer_count
,
676 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
678 /* We only have compression tracking for CCS_E */
679 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
682 for (uint32_t a
= 0; a
< layer_count
; a
++) {
683 uint32_t layer
= base_layer
+ a
;
684 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
685 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
688 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
694 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
695 const struct anv_image
*image
,
696 VkImageAspectFlagBits aspect
,
697 enum anv_fast_clear_type fast_clear
)
699 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
700 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
702 sdi
.ImmediateData
= fast_clear
;
705 /* Whenever we have fast-clear, we consider that slice to be compressed.
706 * This makes building predicates much easier.
708 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
709 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
712 /* This is only really practical on haswell and above because it requires
713 * MI math in order to get it correct.
715 #if GEN_GEN >= 8 || GEN_IS_HASWELL
717 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
718 const struct anv_image
*image
,
719 VkImageAspectFlagBits aspect
,
720 uint32_t level
, uint32_t array_layer
,
721 enum isl_aux_op resolve_op
,
722 enum anv_fast_clear_type fast_clear_supported
)
724 struct gen_mi_builder b
;
725 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
727 const struct gen_mi_value fast_clear_type
=
728 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
731 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
732 /* In this case, we're doing a full resolve which means we want the
733 * resolve to happen if any compression (including fast-clears) is
736 * In order to simplify the logic a bit, we make the assumption that,
737 * if the first slice has been fast-cleared, it is also marked as
738 * compressed. See also set_image_fast_clear_state.
740 const struct gen_mi_value compression_state
=
741 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer
->device
,
743 level
, array_layer
));
744 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
746 gen_mi_store(&b
, compression_state
, gen_mi_imm(0));
748 if (level
== 0 && array_layer
== 0) {
749 /* If the predicate is true, we want to write 0 to the fast clear type
750 * and, if it's false, leave it alone. We can do this by writing
752 * clear_type = clear_type & ~predicate;
754 struct gen_mi_value new_fast_clear_type
=
755 gen_mi_iand(&b
, fast_clear_type
,
756 gen_mi_inot(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
)));
757 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
759 } else if (level
== 0 && array_layer
== 0) {
760 /* In this case, we are doing a partial resolve to get rid of fast-clear
761 * colors. We don't care about the compression state but we do care
762 * about how much fast clear is allowed by the final layout.
764 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
765 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
767 /* We need to compute (fast_clear_supported < image->fast_clear) */
768 struct gen_mi_value pred
=
769 gen_mi_ult(&b
, gen_mi_imm(fast_clear_supported
), fast_clear_type
);
770 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
771 gen_mi_value_ref(&b
, pred
));
773 /* If the predicate is true, we want to write 0 to the fast clear type
774 * and, if it's false, leave it alone. We can do this by writing
776 * clear_type = clear_type & ~predicate;
778 struct gen_mi_value new_fast_clear_type
=
779 gen_mi_iand(&b
, fast_clear_type
, gen_mi_inot(&b
, pred
));
780 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
782 /* In this case, we're trying to do a partial resolve on a slice that
783 * doesn't have clear color. There's nothing to do.
785 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
789 /* Set src1 to 0 and use a != condition */
790 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
792 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
793 mip
.LoadOperation
= LOAD_LOADINV
;
794 mip
.CombineOperation
= COMBINE_SET
;
795 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
798 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
802 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
803 const struct anv_image
*image
,
804 VkImageAspectFlagBits aspect
,
805 uint32_t level
, uint32_t array_layer
,
806 enum isl_aux_op resolve_op
,
807 enum anv_fast_clear_type fast_clear_supported
)
809 struct gen_mi_builder b
;
810 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
812 struct gen_mi_value fast_clear_type_mem
=
813 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
816 /* This only works for partial resolves and only when the clear color is
817 * all or nothing. On the upside, this emits less command streamer code
818 * and works on Ivybridge and Bay Trail.
820 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
821 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
823 /* We don't support fast clears on anything other than the first slice. */
824 if (level
> 0 || array_layer
> 0)
827 /* On gen8, we don't have a concept of default clear colors because we
828 * can't sample from CCS surfaces. It's enough to just load the fast clear
829 * state into the predicate register.
831 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), fast_clear_type_mem
);
832 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
833 gen_mi_store(&b
, fast_clear_type_mem
, gen_mi_imm(0));
835 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
836 mip
.LoadOperation
= LOAD_LOADINV
;
837 mip
.CombineOperation
= COMBINE_SET
;
838 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
841 #endif /* GEN_GEN <= 8 */
844 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
845 const struct anv_image
*image
,
846 enum isl_format format
,
847 struct isl_swizzle swizzle
,
848 VkImageAspectFlagBits aspect
,
849 uint32_t level
, uint32_t array_layer
,
850 enum isl_aux_op resolve_op
,
851 enum anv_fast_clear_type fast_clear_supported
)
853 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
856 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
857 aspect
, level
, array_layer
,
858 resolve_op
, fast_clear_supported
);
859 #else /* GEN_GEN <= 8 */
860 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
861 aspect
, level
, array_layer
,
862 resolve_op
, fast_clear_supported
);
865 /* CCS_D only supports full resolves and BLORP will assert on us if we try
866 * to do a partial resolve on a CCS_D surface.
868 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
869 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_D
)
870 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
872 anv_image_ccs_op(cmd_buffer
, image
, format
, swizzle
, aspect
,
873 level
, array_layer
, 1, resolve_op
, NULL
, true);
877 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
878 const struct anv_image
*image
,
879 enum isl_format format
,
880 struct isl_swizzle swizzle
,
881 VkImageAspectFlagBits aspect
,
882 uint32_t array_layer
,
883 enum isl_aux_op resolve_op
,
884 enum anv_fast_clear_type fast_clear_supported
)
886 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
887 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
889 #if GEN_GEN >= 8 || GEN_IS_HASWELL
890 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
891 aspect
, 0, array_layer
,
892 resolve_op
, fast_clear_supported
);
894 anv_image_mcs_op(cmd_buffer
, image
, format
, swizzle
, aspect
,
895 array_layer
, 1, resolve_op
, NULL
, true);
897 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
902 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
903 const struct anv_image
*image
,
904 VkImageAspectFlagBits aspect
,
905 enum isl_aux_usage aux_usage
,
908 uint32_t layer_count
)
910 /* The aspect must be exactly one of the image aspects. */
911 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
913 /* The only compression types with more than just fast-clears are MCS,
914 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
915 * track the current fast-clear and compression state. This leaves us
916 * with just MCS and CCS_E.
918 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
919 aux_usage
!= ISL_AUX_USAGE_MCS
)
922 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
923 level
, base_layer
, layer_count
, true);
927 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
928 const struct anv_image
*image
,
929 VkImageAspectFlagBits aspect
)
931 assert(cmd_buffer
&& image
);
932 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
934 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
935 ANV_FAST_CLEAR_NONE
);
937 /* Initialize the struct fields that are accessed for fast-clears so that
938 * the HW restrictions on the field values are satisfied.
940 struct anv_address addr
=
941 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
944 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
945 const unsigned num_dwords
= GEN_GEN
>= 10 ?
946 isl_dev
->ss
.clear_color_state_size
/ 4 :
947 isl_dev
->ss
.clear_value_size
/ 4;
948 for (unsigned i
= 0; i
< num_dwords
; i
++) {
949 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
951 sdi
.Address
.offset
+= i
* 4;
952 sdi
.ImmediateData
= 0;
956 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
958 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
959 /* Pre-SKL, the dword containing the clear values also contains
960 * other fields, so we need to initialize those fields to match the
961 * values that would be in a color attachment.
963 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
964 ISL_CHANNEL_SELECT_GREEN
<< 22 |
965 ISL_CHANNEL_SELECT_BLUE
<< 19 |
966 ISL_CHANNEL_SELECT_ALPHA
<< 16;
967 } else if (GEN_GEN
== 7) {
968 /* On IVB, the dword containing the clear values also contains
969 * other fields that must be zero or can be zero.
971 sdi
.ImmediateData
= 0;
977 /* Copy the fast-clear value dword(s) between a surface state object and an
978 * image's fast clear state buffer.
981 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
982 struct anv_state surface_state
,
983 const struct anv_image
*image
,
984 VkImageAspectFlagBits aspect
,
985 bool copy_from_surface_state
)
987 assert(cmd_buffer
&& image
);
988 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
990 struct anv_address ss_clear_addr
= {
991 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
992 .offset
= surface_state
.offset
+
993 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
995 const struct anv_address entry_addr
=
996 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
997 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
1000 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
1001 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
1002 * in-flight when they are issued even if the memory touched is not
1003 * currently active for rendering. The weird bit is that it is not the
1004 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
1005 * rendering hangs such that the next stalling command after the
1006 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
1008 * It is unclear exactly why this hang occurs. Both MI commands come with
1009 * warnings about the 3D pipeline but that doesn't seem to fully explain
1010 * it. My (Jason's) best theory is that it has something to do with the
1011 * fact that we're using a GPU state register as our temporary and that
1012 * something with reading/writing it is causing problems.
1014 * In order to work around this issue, we emit a PIPE_CONTROL with the
1015 * command streamer stall bit set.
1017 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
1018 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1021 struct gen_mi_builder b
;
1022 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
1024 if (copy_from_surface_state
) {
1025 gen_mi_memcpy(&b
, entry_addr
, ss_clear_addr
, copy_size
);
1027 gen_mi_memcpy(&b
, ss_clear_addr
, entry_addr
, copy_size
);
1029 /* Updating a surface state object may require that the state cache be
1030 * invalidated. From the SKL PRM, Shared Functions -> State -> State
1033 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
1034 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
1035 * modified [...], the L1 state cache must be invalidated to ensure
1036 * the new surface or sampler state is fetched from system memory.
1038 * In testing, SKL doesn't actually seem to need this, but HSW does.
1040 cmd_buffer
->state
.pending_pipe_bits
|=
1041 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1046 * @brief Transitions a color buffer from one layout to another.
1048 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
1051 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
1052 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
1053 * this represents the maximum layers to transition at each
1054 * specified miplevel.
1057 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
1058 const struct anv_image
*image
,
1059 VkImageAspectFlagBits aspect
,
1060 const uint32_t base_level
, uint32_t level_count
,
1061 uint32_t base_layer
, uint32_t layer_count
,
1062 VkImageLayout initial_layout
,
1063 VkImageLayout final_layout
)
1065 struct anv_device
*device
= cmd_buffer
->device
;
1066 const struct gen_device_info
*devinfo
= &device
->info
;
1067 /* Validate the inputs. */
1069 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
1070 /* These values aren't supported for simplicity's sake. */
1071 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
1072 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
1073 /* Ensure the subresource range is valid. */
1074 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
1075 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
1076 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
1077 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
1078 assert(last_level_num
<= image
->levels
);
1079 /* The spec disallows these final layouts. */
1080 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
1081 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
1083 /* No work is necessary if the layout stays the same or if this subresource
1084 * range lacks auxiliary data.
1086 if (initial_layout
== final_layout
)
1089 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
1091 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
1092 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
1093 /* This surface is a linear compressed image with a tiled shadow surface
1094 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
1095 * we need to ensure the shadow copy is up-to-date.
1097 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1098 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
1099 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
1100 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
1102 anv_image_copy_to_shadow(cmd_buffer
, image
,
1103 VK_IMAGE_ASPECT_COLOR_BIT
,
1104 base_level
, level_count
,
1105 base_layer
, layer_count
);
1108 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
1111 assert(image
->planes
[plane
].surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
1113 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
1114 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
1116 if (device
->physical
->has_implicit_ccs
&& devinfo
->has_aux_map
) {
1117 anv_image_init_aux_tt(cmd_buffer
, image
, aspect
,
1118 base_level
, level_count
,
1119 base_layer
, layer_count
);
1122 assert(!(device
->physical
->has_implicit_ccs
&& devinfo
->has_aux_map
));
1125 /* A subresource in the undefined layout may have been aliased and
1126 * populated with any arrangement of bits. Therefore, we must initialize
1127 * the related aux buffer and clear buffer entry with desirable values.
1128 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
1129 * images with VK_IMAGE_TILING_OPTIMAL.
1131 * Initialize the relevant clear buffer entries.
1133 if (base_level
== 0 && base_layer
== 0)
1134 init_fast_clear_color(cmd_buffer
, image
, aspect
);
1136 /* Initialize the aux buffers to enable correct rendering. In order to
1137 * ensure that things such as storage images work correctly, aux buffers
1138 * need to be initialized to valid data.
1140 * Having an aux buffer with invalid data is a problem for two reasons:
1142 * 1) Having an invalid value in the buffer can confuse the hardware.
1143 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1144 * invalid and leads to the hardware doing strange things. It
1145 * doesn't hang as far as we can tell but rendering corruption can
1148 * 2) If this transition is into the GENERAL layout and we then use the
1149 * image as a storage image, then we must have the aux buffer in the
1150 * pass-through state so that, if we then go to texture from the
1151 * image, we get the results of our storage image writes and not the
1152 * fast clear color or other random data.
1154 * For CCS both of the problems above are real demonstrable issues. In
1155 * that case, the only thing we can do is to perform an ambiguate to
1156 * transition the aux surface into the pass-through state.
1158 * For MCS, (2) is never an issue because we don't support multisampled
1159 * storage images. In theory, issue (1) is a problem with MCS but we've
1160 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1161 * theory, be interpreted as something but we don't know that all bit
1162 * patterns are actually valid. For 2x and 8x, you could easily end up
1163 * with the MCS referring to an invalid plane because not all bits of
1164 * the MCS value are actually used. Even though we've never seen issues
1165 * in the wild, it's best to play it safe and initialize the MCS. We
1166 * can use a fast-clear for MCS because we only ever touch from render
1167 * and texture (no image load store).
1169 if (image
->samples
== 1) {
1170 for (uint32_t l
= 0; l
< level_count
; l
++) {
1171 const uint32_t level
= base_level
+ l
;
1173 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1174 if (base_layer
>= aux_layers
)
1175 break; /* We will only get fewer layers as level increases */
1176 uint32_t level_layer_count
=
1177 MIN2(layer_count
, aux_layers
- base_layer
);
1179 anv_image_ccs_op(cmd_buffer
, image
,
1180 image
->planes
[plane
].surface
.isl
.format
,
1181 ISL_SWIZZLE_IDENTITY
,
1182 aspect
, level
, base_layer
, level_layer_count
,
1183 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1185 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1186 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1187 level
, base_layer
, level_layer_count
,
1192 if (image
->samples
== 4 || image
->samples
== 16) {
1193 anv_perf_warn(cmd_buffer
->device
, image
,
1194 "Doing a potentially unnecessary fast-clear to "
1195 "define an MCS buffer.");
1198 assert(base_level
== 0 && level_count
== 1);
1199 anv_image_mcs_op(cmd_buffer
, image
,
1200 image
->planes
[plane
].surface
.isl
.format
,
1201 ISL_SWIZZLE_IDENTITY
,
1202 aspect
, base_layer
, layer_count
,
1203 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1208 const enum isl_aux_usage initial_aux_usage
=
1209 anv_layout_to_aux_usage(devinfo
, image
, aspect
, 0, initial_layout
);
1210 const enum isl_aux_usage final_aux_usage
=
1211 anv_layout_to_aux_usage(devinfo
, image
, aspect
, 0, final_layout
);
1213 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1214 * We can handle transitions between CCS_D/E to and from NONE. What we
1215 * don't yet handle is switching between CCS_E and CCS_D within a given
1216 * image. Doing so in a performant way requires more detailed aux state
1217 * tracking such as what is done in i965. For now, just assume that we
1218 * only have one type of compression.
1220 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1221 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1222 initial_aux_usage
== final_aux_usage
);
1224 /* If initial aux usage is NONE, there is nothing to resolve */
1225 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1228 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1230 /* If the initial layout supports more fast clear than the final layout
1231 * then we need at least a partial resolve.
1233 const enum anv_fast_clear_type initial_fast_clear
=
1234 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1235 const enum anv_fast_clear_type final_fast_clear
=
1236 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1237 if (final_fast_clear
< initial_fast_clear
)
1238 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1240 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1241 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1242 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1244 if (resolve_op
== ISL_AUX_OP_NONE
)
1247 /* Perform a resolve to synchronize data between the main and aux buffer.
1248 * Before we begin, we must satisfy the cache flushing requirement specified
1249 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1251 * Any transition from any value in {Clear, Render, Resolve} to a
1252 * different value in {Clear, Render, Resolve} requires end of pipe
1255 * We perform a flush of the write cache before and after the clear and
1256 * resolve operations to meet this requirement.
1258 * Unlike other drawing, fast clear operations are not properly
1259 * synchronized. The first PIPE_CONTROL here likely ensures that the
1260 * contents of the previous render or clear hit the render target before we
1261 * resolve and the second likely ensures that the resolve is complete before
1262 * we do any more rendering or clearing.
1264 cmd_buffer
->state
.pending_pipe_bits
|=
1265 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
1267 for (uint32_t l
= 0; l
< level_count
; l
++) {
1268 uint32_t level
= base_level
+ l
;
1270 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1271 if (base_layer
>= aux_layers
)
1272 break; /* We will only get fewer layers as level increases */
1273 uint32_t level_layer_count
=
1274 MIN2(layer_count
, aux_layers
- base_layer
);
1276 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1277 uint32_t array_layer
= base_layer
+ a
;
1278 if (image
->samples
== 1) {
1279 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1280 image
->planes
[plane
].surface
.isl
.format
,
1281 ISL_SWIZZLE_IDENTITY
,
1282 aspect
, level
, array_layer
, resolve_op
,
1285 /* We only support fast-clear on the first layer so partial
1286 * resolves should not be used on other layers as they will use
1287 * the clear color stored in memory that is only valid for layer0.
1289 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1293 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1294 image
->planes
[plane
].surface
.isl
.format
,
1295 ISL_SWIZZLE_IDENTITY
,
1296 aspect
, array_layer
, resolve_op
,
1302 cmd_buffer
->state
.pending_pipe_bits
|=
1303 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
1307 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1308 const struct anv_render_pass
*pass
,
1309 const struct anv_framebuffer
*framebuffer
,
1310 const VkRenderPassBeginInfo
*begin
)
1312 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1314 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1316 if (pass
->attachment_count
> 0) {
1317 state
->attachments
= vk_zalloc(&cmd_buffer
->pool
->alloc
,
1318 pass
->attachment_count
*
1319 sizeof(state
->attachments
[0]),
1320 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1321 if (state
->attachments
== NULL
) {
1322 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1323 return anv_batch_set_error(&cmd_buffer
->batch
,
1324 VK_ERROR_OUT_OF_HOST_MEMORY
);
1327 state
->attachments
= NULL
;
1330 const VkRenderPassAttachmentBeginInfoKHR
*attach_begin
=
1331 vk_find_struct_const(begin
, RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR
);
1332 if (begin
&& !attach_begin
)
1333 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1335 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1336 if (attach_begin
&& attach_begin
->attachmentCount
!= 0) {
1337 assert(attach_begin
->attachmentCount
== pass
->attachment_count
);
1338 ANV_FROM_HANDLE(anv_image_view
, iview
, attach_begin
->pAttachments
[i
]);
1339 state
->attachments
[i
].image_view
= iview
;
1340 } else if (framebuffer
&& i
< framebuffer
->attachment_count
) {
1341 state
->attachments
[i
].image_view
= framebuffer
->attachments
[i
];
1343 state
->attachments
[i
].image_view
= NULL
;
1348 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1349 const struct anv_render_pass_attachment
*pass_att
= &pass
->attachments
[i
];
1350 struct anv_attachment_state
*att_state
= &state
->attachments
[i
];
1351 VkImageAspectFlags att_aspects
= vk_format_aspects(pass_att
->format
);
1352 VkImageAspectFlags clear_aspects
= 0;
1353 VkImageAspectFlags load_aspects
= 0;
1355 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1356 /* color attachment */
1357 if (pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1358 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1359 } else if (pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1360 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1363 /* depthstencil attachment */
1364 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1365 if (pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1366 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1367 } else if (pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1368 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1371 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1372 if (pass_att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1373 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1374 } else if (pass_att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1375 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1380 att_state
->current_layout
= pass_att
->initial_layout
;
1381 att_state
->current_stencil_layout
= pass_att
->stencil_initial_layout
;
1382 att_state
->pending_clear_aspects
= clear_aspects
;
1383 att_state
->pending_load_aspects
= load_aspects
;
1385 att_state
->clear_value
= begin
->pClearValues
[i
];
1387 struct anv_image_view
*iview
= state
->attachments
[i
].image_view
;
1388 anv_assert(iview
->vk_format
== pass_att
->format
);
1390 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1391 att_state
->pending_clear_views
= (1 << num_layers
) - 1;
1393 /* This will be initialized after the first subpass transition. */
1394 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
1396 att_state
->fast_clear
= false;
1397 if (clear_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1398 assert(clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1399 att_state
->fast_clear
=
1400 anv_can_fast_clear_color_view(cmd_buffer
->device
, iview
,
1401 pass_att
->first_subpass_layout
,
1402 vk_to_isl_color(att_state
->clear_value
.color
),
1403 framebuffer
->layers
,
1405 } else if (clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
1406 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
1407 att_state
->fast_clear
=
1408 anv_can_hiz_clear_ds_view(cmd_buffer
->device
, iview
,
1409 pass_att
->first_subpass_layout
,
1411 att_state
->clear_value
.depthStencil
.depth
,
1421 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1424 genX(cmd_buffer_alloc_att_surf_states
)(struct anv_cmd_buffer
*cmd_buffer
,
1425 const struct anv_render_pass
*pass
,
1426 const struct anv_subpass
*subpass
)
1428 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1429 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1431 /* Reserve one for the NULL state. */
1432 unsigned num_states
= 1;
1433 for (uint32_t i
= 0; i
< subpass
->attachment_count
; i
++) {
1434 uint32_t att
= subpass
->attachments
[i
].attachment
;
1435 if (att
== VK_ATTACHMENT_UNUSED
)
1438 assert(att
< pass
->attachment_count
);
1439 if (!vk_format_is_color(pass
->attachments
[att
].format
))
1442 const VkImageUsageFlagBits att_usage
= subpass
->attachments
[i
].usage
;
1443 assert(util_bitcount(att_usage
) == 1);
1445 if (att_usage
== VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
||
1446 att_usage
== VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)
1450 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1451 state
->attachment_states
=
1452 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1453 num_states
* ss_stride
, isl_dev
->ss
.align
);
1454 if (state
->attachment_states
.map
== NULL
) {
1455 return anv_batch_set_error(&cmd_buffer
->batch
,
1456 VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1459 struct anv_state next_state
= state
->attachment_states
;
1460 next_state
.alloc_size
= isl_dev
->ss
.size
;
1462 state
->null_surface_state
= next_state
;
1463 next_state
.offset
+= ss_stride
;
1464 next_state
.map
+= ss_stride
;
1466 for (uint32_t i
= 0; i
< subpass
->attachment_count
; i
++) {
1467 uint32_t att
= subpass
->attachments
[i
].attachment
;
1468 if (att
== VK_ATTACHMENT_UNUSED
)
1471 assert(att
< pass
->attachment_count
);
1472 if (!vk_format_is_color(pass
->attachments
[att
].format
))
1475 const VkImageUsageFlagBits att_usage
= subpass
->attachments
[i
].usage
;
1476 assert(util_bitcount(att_usage
) == 1);
1478 if (att_usage
== VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
)
1479 state
->attachments
[att
].color
.state
= next_state
;
1480 else if (att_usage
== VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)
1481 state
->attachments
[att
].input
.state
= next_state
;
1485 state
->attachments
[att
].color
.state
= next_state
;
1486 next_state
.offset
+= ss_stride
;
1487 next_state
.map
+= ss_stride
;
1490 assert(next_state
.offset
== state
->attachment_states
.offset
+
1491 state
->attachment_states
.alloc_size
);
1497 genX(BeginCommandBuffer
)(
1498 VkCommandBuffer commandBuffer
,
1499 const VkCommandBufferBeginInfo
* pBeginInfo
)
1501 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1503 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1504 * command buffer's state. Otherwise, we must *reset* its state. In both
1505 * cases we reset it.
1507 * From the Vulkan 1.0 spec:
1509 * If a command buffer is in the executable state and the command buffer
1510 * was allocated from a command pool with the
1511 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1512 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1513 * as if vkResetCommandBuffer had been called with
1514 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1515 * the command buffer in the recording state.
1517 anv_cmd_buffer_reset(cmd_buffer
);
1519 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1521 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1522 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1524 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1526 /* We sometimes store vertex data in the dynamic state buffer for blorp
1527 * operations and our dynamic state stream may re-use data from previous
1528 * command buffers. In order to prevent stale cache data, we flush the VF
1529 * cache. We could do this on every blorp call but that's not really
1530 * needed as all of the data will get written by the CPU prior to the GPU
1531 * executing anything. The chances are fairly high that they will use
1532 * blorp at least once per primary command buffer so it shouldn't be
1535 * There is also a workaround on gen8 which requires us to invalidate the
1536 * VF cache occasionally. It's easier if we can assume we start with a
1537 * fresh cache (See also genX(cmd_buffer_set_binding_for_gen8_vb_flush).)
1539 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1541 /* Re-emit the aux table register in every command buffer. This way we're
1542 * ensured that we have the table even if this command buffer doesn't
1543 * initialize any images.
1545 if (cmd_buffer
->device
->info
.has_aux_map
)
1546 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
;
1548 /* We send an "Indirect State Pointers Disable" packet at
1549 * EndCommandBuffer, so all push contant packets are ignored during a
1550 * context restore. Documentation says after that command, we need to
1551 * emit push constants again before any rendering operation. So we
1552 * flag them dirty here to make sure they get emitted.
1554 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1556 VkResult result
= VK_SUCCESS
;
1557 if (cmd_buffer
->usage_flags
&
1558 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1559 assert(pBeginInfo
->pInheritanceInfo
);
1560 ANV_FROM_HANDLE(anv_render_pass
, pass
,
1561 pBeginInfo
->pInheritanceInfo
->renderPass
);
1562 struct anv_subpass
*subpass
=
1563 &pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1564 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
,
1565 pBeginInfo
->pInheritanceInfo
->framebuffer
);
1567 cmd_buffer
->state
.pass
= pass
;
1568 cmd_buffer
->state
.subpass
= subpass
;
1570 /* This is optional in the inheritance info. */
1571 cmd_buffer
->state
.framebuffer
= framebuffer
;
1573 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
,
1575 if (result
!= VK_SUCCESS
)
1578 result
= genX(cmd_buffer_alloc_att_surf_states
)(cmd_buffer
, pass
,
1580 if (result
!= VK_SUCCESS
)
1583 /* Record that HiZ is enabled if we can. */
1584 if (cmd_buffer
->state
.framebuffer
) {
1585 const struct anv_image_view
* const iview
=
1586 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1589 VkImageLayout layout
=
1590 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1592 enum isl_aux_usage aux_usage
=
1593 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1594 VK_IMAGE_ASPECT_DEPTH_BIT
,
1595 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
1598 cmd_buffer
->state
.hiz_enabled
= isl_aux_usage_has_hiz(aux_usage
);
1602 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1605 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1606 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1607 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1608 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1610 /* If secondary buffer supports conditional rendering
1611 * we should emit commands as if conditional rendering is enabled.
1613 cmd_buffer
->state
.conditional_render_enabled
=
1614 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1621 /* From the PRM, Volume 2a:
1623 * "Indirect State Pointers Disable
1625 * At the completion of the post-sync operation associated with this pipe
1626 * control packet, the indirect state pointers in the hardware are
1627 * considered invalid; the indirect pointers are not saved in the context.
1628 * If any new indirect state commands are executed in the command stream
1629 * while the pipe control is pending, the new indirect state commands are
1632 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1633 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1634 * commands are only considered as Indirect State Pointers. Once ISP is
1635 * issued in a context, SW must initialize by programming push constant
1636 * commands for all the shaders (at least to zero length) before attempting
1637 * any rendering operation for the same context."
1639 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1640 * even though they point to a BO that has been already unreferenced at
1641 * the end of the previous batch buffer. This has been fine so far since
1642 * we are protected by these scratch page (every address not covered by
1643 * a BO should be pointing to the scratch page). But on CNL, it is
1644 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1647 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1648 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1649 * context restore, so the mentioned hang doesn't happen. However,
1650 * software must program push constant commands for all stages prior to
1651 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1653 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1654 * constants have been loaded into the EUs prior to disable the push constants
1655 * so that it doesn't hang a previous 3DPRIMITIVE.
1658 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1660 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1661 pc
.StallAtPixelScoreboard
= true;
1662 pc
.CommandStreamerStallEnable
= true;
1664 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1665 pc
.IndirectStatePointersDisable
= true;
1666 pc
.CommandStreamerStallEnable
= true;
1671 genX(EndCommandBuffer
)(
1672 VkCommandBuffer commandBuffer
)
1674 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1676 if (anv_batch_has_error(&cmd_buffer
->batch
))
1677 return cmd_buffer
->batch
.status
;
1679 /* We want every command buffer to start with the PMA fix in a known state,
1680 * so we disable it at the end of the command buffer.
1682 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1684 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1686 emit_isp_disable(cmd_buffer
);
1688 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1694 genX(CmdExecuteCommands
)(
1695 VkCommandBuffer commandBuffer
,
1696 uint32_t commandBufferCount
,
1697 const VkCommandBuffer
* pCmdBuffers
)
1699 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1701 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1703 if (anv_batch_has_error(&primary
->batch
))
1706 /* The secondary command buffers will assume that the PMA fix is disabled
1707 * when they begin executing. Make sure this is true.
1709 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1711 /* The secondary command buffer doesn't know which textures etc. have been
1712 * flushed prior to their execution. Apply those flushes now.
1714 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1716 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1717 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1719 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1720 assert(!anv_batch_has_error(&secondary
->batch
));
1722 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1723 if (secondary
->state
.conditional_render_enabled
) {
1724 if (!primary
->state
.conditional_render_enabled
) {
1725 /* Secondary buffer is constructed as if it will be executed
1726 * with conditional rendering, we should satisfy this dependency
1727 * regardless of conditional rendering being enabled in primary.
1729 struct gen_mi_builder b
;
1730 gen_mi_builder_init(&b
, &primary
->batch
);
1731 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
1732 gen_mi_imm(UINT64_MAX
));
1737 if (secondary
->usage_flags
&
1738 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1739 /* If we're continuing a render pass from the primary, we need to
1740 * copy the surface states for the current subpass into the storage
1741 * we allocated for them in BeginCommandBuffer.
1743 struct anv_bo
*ss_bo
=
1744 primary
->device
->surface_state_pool
.block_pool
.bo
;
1745 struct anv_state src_state
= primary
->state
.attachment_states
;
1746 struct anv_state dst_state
= secondary
->state
.attachment_states
;
1747 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1749 genX(cmd_buffer_so_memcpy
)(primary
,
1750 (struct anv_address
) {
1752 .offset
= dst_state
.offset
,
1754 (struct anv_address
) {
1756 .offset
= src_state
.offset
,
1758 src_state
.alloc_size
);
1761 anv_cmd_buffer_add_secondary(primary
, secondary
);
1763 assert(secondary
->perf_query_pool
== NULL
|| primary
->perf_query_pool
== NULL
||
1764 secondary
->perf_query_pool
== primary
->perf_query_pool
);
1765 if (secondary
->perf_query_pool
)
1766 primary
->perf_query_pool
= secondary
->perf_query_pool
;
1769 /* The secondary isn't counted in our VF cache tracking so we need to
1770 * invalidate the whole thing.
1772 if (GEN_GEN
>= 8 && GEN_GEN
<= 9) {
1773 primary
->state
.pending_pipe_bits
|=
1774 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1777 /* The secondary may have selected a different pipeline (3D or compute) and
1778 * may have changed the current L3$ configuration. Reset our tracking
1779 * variables to invalid values to ensure that we re-emit these in the case
1780 * where we do any draws or compute dispatches from the primary after the
1781 * secondary has returned.
1783 primary
->state
.current_pipeline
= UINT32_MAX
;
1784 primary
->state
.current_l3_config
= NULL
;
1785 primary
->state
.current_hash_scale
= 0;
1787 /* Each of the secondary command buffers will use its own state base
1788 * address. We need to re-emit state base address for the primary after
1789 * all of the secondaries are done.
1791 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1794 genX(cmd_buffer_emit_state_base_address
)(primary
);
1797 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1798 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1799 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1802 * Program the hardware to use the specified L3 configuration.
1805 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1806 const struct gen_l3_config
*cfg
)
1808 assert(cfg
|| GEN_GEN
>= 12);
1809 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1812 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1813 intel_logd("L3 config transition: ");
1814 gen_dump_l3_config(cfg
, stderr
);
1817 UNUSED
const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1819 /* According to the hardware docs, the L3 partitioning can only be changed
1820 * while the pipeline is completely drained and the caches are flushed,
1821 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1823 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1824 pc
.DCFlushEnable
= true;
1825 pc
.PostSyncOperation
= NoWrite
;
1826 pc
.CommandStreamerStallEnable
= true;
1829 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1830 * invalidation of the relevant caches. Note that because RO invalidation
1831 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1832 * command is processed by the CS) we cannot combine it with the previous
1833 * stalling flush as the hardware documentation suggests, because that
1834 * would cause the CS to stall on previous rendering *after* RO
1835 * invalidation and wouldn't prevent the RO caches from being polluted by
1836 * concurrent rendering before the stall completes. This intentionally
1837 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1838 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1839 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1840 * already guarantee that there is no concurrent GPGPU kernel execution
1841 * (see SKL HSD 2132585).
1843 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1844 pc
.TextureCacheInvalidationEnable
= true;
1845 pc
.ConstantCacheInvalidationEnable
= true;
1846 pc
.InstructionCacheInvalidateEnable
= true;
1847 pc
.StateCacheInvalidationEnable
= true;
1848 pc
.PostSyncOperation
= NoWrite
;
1851 /* Now send a third stalling flush to make sure that invalidation is
1852 * complete when the L3 configuration registers are modified.
1854 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1855 pc
.DCFlushEnable
= true;
1856 pc
.PostSyncOperation
= NoWrite
;
1857 pc
.CommandStreamerStallEnable
= true;
1862 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1865 #define L3_ALLOCATION_REG GENX(L3ALLOC)
1866 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
1868 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
1869 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
1873 anv_pack_struct(&l3cr
, L3_ALLOCATION_REG
,
1875 .SLMEnable
= has_slm
,
1878 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1879 * in L3CNTLREG register. The default setting of the bit is not the
1880 * desirable behavior.
1882 .ErrorDetectionBehaviorControl
= true,
1883 .UseFullWays
= true,
1885 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1886 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1887 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1888 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1890 /* Set up the L3 partitioning. */
1891 emit_lri(&cmd_buffer
->batch
, L3_ALLOCATION_REG_num
, l3cr
);
1895 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1896 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1897 cfg
->n
[GEN_L3P_ALL
];
1898 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1899 cfg
->n
[GEN_L3P_ALL
];
1900 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1901 cfg
->n
[GEN_L3P_ALL
];
1903 assert(!cfg
->n
[GEN_L3P_ALL
]);
1905 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1906 * the matching space on the remaining banks has to be allocated to a
1907 * client (URB for all validated configurations) set to the
1908 * lower-bandwidth 2-bank address hashing mode.
1910 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1911 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1912 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1914 /* Minimum number of ways that can be allocated to the URB. */
1915 const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1916 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1918 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1919 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1920 .ConvertDC_UC
= !has_dc
,
1921 .ConvertIS_UC
= !has_is
,
1922 .ConvertC_UC
= !has_c
,
1923 .ConvertT_UC
= !has_t
);
1925 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1926 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1927 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1929 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1930 .SLMEnable
= has_slm
,
1931 .URBLowBandwidth
= urb_low_bw
,
1932 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1934 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1936 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1937 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1939 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1940 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1941 .ISLowBandwidth
= 0,
1942 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1944 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1945 .TLowBandwidth
= 0);
1947 /* Set up the L3 partitioning. */
1948 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1949 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1950 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1953 if (cmd_buffer
->device
->physical
->cmd_parser_version
>= 4) {
1954 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1955 * them disabled to avoid crashing the system hard.
1957 uint32_t scratch1
, chicken3
;
1958 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1959 .L3AtomicDisable
= !has_dc
);
1960 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1961 .L3AtomicDisableMask
= true,
1962 .L3AtomicDisable
= !has_dc
);
1963 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1964 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1970 cmd_buffer
->state
.current_l3_config
= cfg
;
1974 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1976 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1977 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1979 if (cmd_buffer
->device
->physical
->always_flush_cache
)
1980 bits
|= ANV_PIPE_FLUSH_BITS
| ANV_PIPE_INVALIDATE_BITS
;
1983 * From Sandybridge PRM, volume 2, "1.7.2 End-of-Pipe Synchronization":
1985 * Write synchronization is a special case of end-of-pipe
1986 * synchronization that requires that the render cache and/or depth
1987 * related caches are flushed to memory, where the data will become
1988 * globally visible. This type of synchronization is required prior to
1989 * SW (CPU) actually reading the result data from memory, or initiating
1990 * an operation that will use as a read surface (such as a texture
1991 * surface) a previous render target and/or depth/stencil buffer
1994 * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
1996 * Exercising the write cache flush bits (Render Target Cache Flush
1997 * Enable, Depth Cache Flush Enable, DC Flush) in PIPE_CONTROL only
1998 * ensures the write caches are flushed and doesn't guarantee the data
1999 * is globally visible.
2001 * SW can track the completion of the end-of-pipe-synchronization by
2002 * using "Notify Enable" and "PostSync Operation - Write Immediate
2003 * Data" in the PIPE_CONTROL command.
2005 * In other words, flushes are pipelined while invalidations are handled
2006 * immediately. Therefore, if we're flushing anything then we need to
2007 * schedule an end-of-pipe sync before any invalidations can happen.
2009 if (bits
& ANV_PIPE_FLUSH_BITS
)
2010 bits
|= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2013 /* HSD 1209978178: docs say that before programming the aux table:
2015 * "Driver must ensure that the engine is IDLE but ensure it doesn't
2016 * add extra flushes in the case it knows that the engine is already
2019 if (GEN_GEN
== 12 && (bits
& ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
))
2020 bits
|= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2022 /* If we're going to do an invalidate and we have a pending end-of-pipe
2023 * sync that has yet to be resolved, we do the end-of-pipe sync now.
2025 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
2026 (bits
& ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
)) {
2027 bits
|= ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
2028 bits
&= ~ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2031 if (GEN_GEN
>= 12 &&
2032 ((bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
) ||
2033 (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
))) {
2034 /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
2037 * Unified Cache (Tile Cache Disabled):
2039 * When the Color and Depth (Z) streams are enabled to be cached in
2040 * the DC space of L2, Software must use "Render Target Cache Flush
2041 * Enable" and "Depth Cache Flush Enable" along with "Tile Cache
2042 * Flush" for getting the color and depth (Z) write data to be
2043 * globally observable. In this mode of operation it is not required
2044 * to set "CS Stall" upon setting "Tile Cache Flush" bit.
2046 bits
|= ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
2049 /* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which
2050 * invalidates the instruction cache
2052 if (GEN_GEN
== 12 && (bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
))
2053 bits
|= ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
2055 if ((GEN_GEN
>= 8 && GEN_GEN
<= 9) &&
2056 (bits
& ANV_PIPE_CS_STALL_BIT
) &&
2057 (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
)) {
2058 /* If we are doing a VF cache invalidate AND a CS stall (it must be
2059 * both) then we can reset our vertex cache tracking.
2061 memset(cmd_buffer
->state
.gfx
.vb_dirty_ranges
, 0,
2062 sizeof(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
2063 memset(&cmd_buffer
->state
.gfx
.ib_dirty_range
, 0,
2064 sizeof(cmd_buffer
->state
.gfx
.ib_dirty_range
));
2067 /* Project: SKL / Argument: LRI Post Sync Operation [23]
2069 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
2070 * programmed prior to programming a PIPECONTROL command with "LRI
2071 * Post Sync Operation" in GPGPU mode of operation (i.e when
2072 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
2074 * The same text exists a few rows below for Post Sync Op.
2076 * On Gen12 this is GEN:BUG:1607156449.
2078 if (bits
& ANV_PIPE_POST_SYNC_BIT
) {
2079 if ((GEN_GEN
== 9 || (GEN_GEN
== 12 && devinfo
->revision
== 0 /* A0 */)) &&
2080 cmd_buffer
->state
.current_pipeline
== GPGPU
)
2081 bits
|= ANV_PIPE_CS_STALL_BIT
;
2082 bits
&= ~ANV_PIPE_POST_SYNC_BIT
;
2085 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
|
2086 ANV_PIPE_END_OF_PIPE_SYNC_BIT
)) {
2087 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2089 pipe
.TileCacheFlushEnable
= bits
& ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
2091 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2092 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2093 pipe
.RenderTargetCacheFlushEnable
=
2094 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2096 /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
2097 * be set with any PIPE_CONTROL with Depth Flush Enable bit set.
2100 pipe
.DepthStallEnable
=
2101 pipe
.DepthCacheFlushEnable
|| (bits
& ANV_PIPE_DEPTH_STALL_BIT
);
2103 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
2106 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
2107 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
2109 /* From Sandybridge PRM, volume 2, "1.7.3.1 Writing a Value to Memory":
2111 * "The most common action to perform upon reaching a
2112 * synchronization point is to write a value out to memory. An
2113 * immediate value (included with the synchronization command) may
2117 * From Broadwell PRM, volume 7, "End-of-Pipe Synchronization":
2119 * "In case the data flushed out by the render engine is to be
2120 * read back in to the render engine in coherent manner, then the
2121 * render engine has to wait for the fence completion before
2122 * accessing the flushed data. This can be achieved by following
2123 * means on various products: PIPE_CONTROL command with CS Stall
2124 * and the required write caches flushed with Post-Sync-Operation
2125 * as Write Immediate Data.
2128 * - Workload-1 (3D/GPGPU/MEDIA)
2129 * - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write
2130 * Immediate Data, Required Write Cache Flush bits set)
2131 * - Workload-2 (Can use the data produce or output by
2134 if (bits
& ANV_PIPE_END_OF_PIPE_SYNC_BIT
) {
2135 pipe
.CommandStreamerStallEnable
= true;
2136 pipe
.PostSyncOperation
= WriteImmediateData
;
2137 pipe
.Address
= cmd_buffer
->device
->workaround_address
;
2141 * According to the Broadwell documentation, any PIPE_CONTROL with the
2142 * "Command Streamer Stall" bit set must also have another bit set,
2143 * with five different options:
2145 * - Render Target Cache Flush
2146 * - Depth Cache Flush
2147 * - Stall at Pixel Scoreboard
2148 * - Post-Sync Operation
2152 * I chose "Stall at Pixel Scoreboard" since that's what we use in
2153 * mesa and it seems to work fine. The choice is fairly arbitrary.
2155 if (pipe
.CommandStreamerStallEnable
&&
2156 !pipe
.RenderTargetCacheFlushEnable
&&
2157 !pipe
.DepthCacheFlushEnable
&&
2158 !pipe
.StallAtPixelScoreboard
&&
2159 !pipe
.PostSyncOperation
&&
2160 !pipe
.DepthStallEnable
&&
2161 !pipe
.DCFlushEnable
)
2162 pipe
.StallAtPixelScoreboard
= true;
2165 /* If a render target flush was emitted, then we can toggle off the bit
2166 * saying that render target writes are ongoing.
2168 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
2169 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
2171 if (GEN_IS_HASWELL
) {
2172 /* Haswell needs addition work-arounds:
2174 * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
2177 * PIPE_CONTROL command with the CS Stall and the required write
2178 * caches flushed with Post-SyncOperation as Write Immediate Data
2179 * followed by eight dummy MI_STORE_DATA_IMM (write to scratch
2184 * - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write
2185 * Immediate Data, Required Write Cache Flush bits set)
2186 * - MI_STORE_DATA_IMM (8 times) (Dummy data, Scratch Address)
2187 * - Workload-2 (Can use the data produce or output by
2190 * Unfortunately, both the PRMs and the internal docs are a bit
2191 * out-of-date in this regard. What the windows driver does (and
2192 * this appears to actually work) is to emit a register read from the
2193 * memory address written by the pipe control above.
2195 * What register we load into doesn't matter. We choose an indirect
2196 * rendering register because we know it always exists and it's one
2197 * of the first registers the command parser allows us to write. If
2198 * you don't have command parser support in your kernel (pre-4.2),
2199 * this will get turned into MI_NOOP and you won't get the
2200 * workaround. Unfortunately, there's just not much we can do in
2201 * that case. This register is perfectly safe to write since we
2202 * always re-load all of the indirect draw registers right before
2203 * 3DPRIMITIVE when needed anyway.
2205 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2206 lrm
.RegisterAddress
= 0x243C; /* GEN7_3DPRIM_START_INSTANCE */
2207 lrm
.MemoryAddress
= cmd_buffer
->device
->workaround_address
;
2211 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
|
2212 ANV_PIPE_END_OF_PIPE_SYNC_BIT
);
2215 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
2216 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
2218 * "If the VF Cache Invalidation Enable is set to a 1 in a
2219 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
2220 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
2221 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
2224 * This appears to hang Broadwell, so we restrict it to just gen9.
2226 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
2227 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
2229 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2230 pipe
.StateCacheInvalidationEnable
=
2231 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
2232 pipe
.ConstantCacheInvalidationEnable
=
2233 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2234 pipe
.VFCacheInvalidationEnable
=
2235 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2236 pipe
.TextureCacheInvalidationEnable
=
2237 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2238 pipe
.InstructionCacheInvalidateEnable
=
2239 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
2241 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
2243 * "When VF Cache Invalidate is set “Post Sync Operation” must be
2244 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
2245 * “Write Timestamp”.
2247 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
2248 pipe
.PostSyncOperation
= WriteImmediateData
;
2249 pipe
.Address
= cmd_buffer
->device
->workaround_address
;
2254 if ((bits
& ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
) &&
2255 cmd_buffer
->device
->info
.has_aux_map
) {
2256 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
2257 lri
.RegisterOffset
= GENX(GFX_CCS_AUX_INV_num
);
2263 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
2266 cmd_buffer
->state
.pending_pipe_bits
= bits
;
2269 void genX(CmdPipelineBarrier
)(
2270 VkCommandBuffer commandBuffer
,
2271 VkPipelineStageFlags srcStageMask
,
2272 VkPipelineStageFlags destStageMask
,
2274 uint32_t memoryBarrierCount
,
2275 const VkMemoryBarrier
* pMemoryBarriers
,
2276 uint32_t bufferMemoryBarrierCount
,
2277 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
2278 uint32_t imageMemoryBarrierCount
,
2279 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
2281 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2283 /* XXX: Right now, we're really dumb and just flush whatever categories
2284 * the app asks for. One of these days we may make this a bit better
2285 * but right now that's all the hardware allows for in most areas.
2287 VkAccessFlags src_flags
= 0;
2288 VkAccessFlags dst_flags
= 0;
2290 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
2291 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
2292 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
2295 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
2296 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
2297 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
2300 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
2301 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
2302 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
2303 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
2304 const VkImageSubresourceRange
*range
=
2305 &pImageMemoryBarriers
[i
].subresourceRange
;
2307 uint32_t base_layer
, layer_count
;
2308 if (image
->type
== VK_IMAGE_TYPE_3D
) {
2310 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
2312 base_layer
= range
->baseArrayLayer
;
2313 layer_count
= anv_get_layerCount(image
, range
);
2316 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
2317 transition_depth_buffer(cmd_buffer
, image
,
2318 base_layer
, layer_count
,
2319 pImageMemoryBarriers
[i
].oldLayout
,
2320 pImageMemoryBarriers
[i
].newLayout
);
2323 if (range
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
2324 transition_stencil_buffer(cmd_buffer
, image
,
2325 range
->baseMipLevel
,
2326 anv_get_levelCount(image
, range
),
2327 base_layer
, layer_count
,
2328 pImageMemoryBarriers
[i
].oldLayout
,
2329 pImageMemoryBarriers
[i
].newLayout
);
2332 if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
2333 VkImageAspectFlags color_aspects
=
2334 anv_image_expand_aspects(image
, range
->aspectMask
);
2335 uint32_t aspect_bit
;
2336 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
2337 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
2338 range
->baseMipLevel
,
2339 anv_get_levelCount(image
, range
),
2340 base_layer
, layer_count
,
2341 pImageMemoryBarriers
[i
].oldLayout
,
2342 pImageMemoryBarriers
[i
].newLayout
);
2347 cmd_buffer
->state
.pending_pipe_bits
|=
2348 anv_pipe_flush_bits_for_access_flags(src_flags
) |
2349 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
2353 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
2355 VkShaderStageFlags stages
=
2356 cmd_buffer
->state
.gfx
.pipeline
->active_stages
;
2358 /* In order to avoid thrash, we assume that vertex and fragment stages
2359 * always exist. In the rare case where one is missing *and* the other
2360 * uses push concstants, this may be suboptimal. However, avoiding stalls
2361 * seems more important.
2363 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
2365 if (stages
== cmd_buffer
->state
.push_constant_stages
)
2369 const unsigned push_constant_kb
= 32;
2370 #elif GEN_IS_HASWELL
2371 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
2373 const unsigned push_constant_kb
= 16;
2376 const unsigned num_stages
=
2377 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
2378 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
2380 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
2381 * units of 2KB. Incidentally, these are the same platforms that have
2382 * 32KB worth of push constant space.
2384 if (push_constant_kb
== 32)
2385 size_per_stage
&= ~1u;
2387 uint32_t kb_used
= 0;
2388 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
2389 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
2390 anv_batch_emit(&cmd_buffer
->batch
,
2391 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
2392 alloc
._3DCommandSubOpcode
= 18 + i
;
2393 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
2394 alloc
.ConstantBufferSize
= push_size
;
2396 kb_used
+= push_size
;
2399 anv_batch_emit(&cmd_buffer
->batch
,
2400 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
2401 alloc
.ConstantBufferOffset
= kb_used
;
2402 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
2405 cmd_buffer
->state
.push_constant_stages
= stages
;
2407 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
2409 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
2410 * the next 3DPRIMITIVE command after programming the
2411 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
2413 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
2414 * pipeline setup, we need to dirty push constants.
2416 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
2419 static struct anv_address
2420 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
2421 struct anv_descriptor_set
*set
)
2424 /* This is a normal descriptor set */
2425 return (struct anv_address
) {
2426 .bo
= set
->pool
->bo
,
2427 .offset
= set
->desc_mem
.offset
,
2430 /* This is a push descriptor set. We have to flag it as used on the GPU
2431 * so that the next time we push descriptors, we grab a new memory.
2433 struct anv_push_descriptor_set
*push_set
=
2434 (struct anv_push_descriptor_set
*)set
;
2435 push_set
->set_used_on_gpu
= true;
2437 return (struct anv_address
) {
2438 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2439 .offset
= set
->desc_mem
.offset
,
2445 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2446 struct anv_cmd_pipeline_state
*pipe_state
,
2447 struct anv_shader_bin
*shader
,
2448 struct anv_state
*bt_state
)
2450 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2451 uint32_t state_offset
;
2453 struct anv_pipeline_bind_map
*map
= &shader
->bind_map
;
2454 if (map
->surface_count
== 0) {
2455 *bt_state
= (struct anv_state
) { 0, };
2459 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2462 uint32_t *bt_map
= bt_state
->map
;
2464 if (bt_state
->map
== NULL
)
2465 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2467 /* We only need to emit relocs if we're not using softpin. If we are using
2468 * softpin then we always keep all user-allocated memory objects resident.
2470 const bool need_client_mem_relocs
=
2471 !cmd_buffer
->device
->physical
->use_softpin
;
2473 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2474 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2476 struct anv_state surface_state
;
2478 switch (binding
->set
) {
2479 case ANV_DESCRIPTOR_SET_NULL
:
2483 case ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
:
2484 /* Color attachment binding */
2485 assert(shader
->stage
== MESA_SHADER_FRAGMENT
);
2486 if (binding
->index
< subpass
->color_count
) {
2487 const unsigned att
=
2488 subpass
->color_attachments
[binding
->index
].attachment
;
2490 /* From the Vulkan 1.0.46 spec:
2492 * "If any color or depth/stencil attachments are
2493 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2496 if (att
== VK_ATTACHMENT_UNUSED
) {
2497 surface_state
= cmd_buffer
->state
.null_surface_state
;
2499 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2502 surface_state
= cmd_buffer
->state
.null_surface_state
;
2505 assert(surface_state
.map
);
2506 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2509 case ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
: {
2510 struct anv_state surface_state
=
2511 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2513 struct anv_address constant_data
= {
2514 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2515 .offset
= shader
->constant_data
.offset
,
2517 unsigned constant_data_size
= shader
->constant_data_size
;
2519 const enum isl_format format
=
2520 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2521 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2522 surface_state
, format
,
2523 constant_data
, constant_data_size
, 1);
2525 assert(surface_state
.map
);
2526 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2527 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2531 case ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
: {
2532 /* This is always the first binding for compute shaders */
2533 assert(shader
->stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2535 struct anv_state surface_state
=
2536 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2538 const enum isl_format format
=
2539 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2540 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2542 cmd_buffer
->state
.compute
.num_workgroups
,
2545 assert(surface_state
.map
);
2546 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2547 if (need_client_mem_relocs
) {
2548 add_surface_reloc(cmd_buffer
, surface_state
,
2549 cmd_buffer
->state
.compute
.num_workgroups
);
2554 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2555 /* This is a descriptor set buffer so the set index is actually
2556 * given by binding->binding. (Yes, that's confusing.)
2558 struct anv_descriptor_set
*set
=
2559 pipe_state
->descriptors
[binding
->index
];
2560 assert(set
->desc_mem
.alloc_size
);
2561 assert(set
->desc_surface_state
.alloc_size
);
2562 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2563 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2564 anv_descriptor_set_address(cmd_buffer
, set
));
2569 assert(binding
->set
< MAX_SETS
);
2570 const struct anv_descriptor
*desc
=
2571 &pipe_state
->descriptors
[binding
->set
]->descriptors
[binding
->index
];
2573 switch (desc
->type
) {
2574 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2575 /* Nothing for us to do here */
2578 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2579 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2580 if (desc
->image_view
) {
2581 struct anv_surface_state sstate
=
2582 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2583 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2584 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2585 surface_state
= sstate
.state
;
2586 assert(surface_state
.alloc_size
);
2587 if (need_client_mem_relocs
)
2588 add_surface_state_relocs(cmd_buffer
, sstate
);
2590 surface_state
= cmd_buffer
->device
->null_surface_state
;
2594 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2595 assert(shader
->stage
== MESA_SHADER_FRAGMENT
);
2596 assert(desc
->image_view
!= NULL
);
2597 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2598 /* For depth and stencil input attachments, we treat it like any
2599 * old texture that a user may have bound.
2601 assert(desc
->image_view
->n_planes
== 1);
2602 struct anv_surface_state sstate
=
2603 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2604 desc
->image_view
->planes
[0].general_sampler_surface_state
:
2605 desc
->image_view
->planes
[0].optimal_sampler_surface_state
;
2606 surface_state
= sstate
.state
;
2607 assert(surface_state
.alloc_size
);
2608 if (need_client_mem_relocs
)
2609 add_surface_state_relocs(cmd_buffer
, sstate
);
2611 /* For color input attachments, we create the surface state at
2612 * vkBeginRenderPass time so that we can include aux and clear
2613 * color information.
2615 assert(binding
->input_attachment_index
< subpass
->input_count
);
2616 const unsigned subpass_att
= binding
->input_attachment_index
;
2617 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2618 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2622 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2623 if (desc
->image_view
) {
2624 struct anv_surface_state sstate
= (binding
->write_only
)
2625 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2626 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2627 surface_state
= sstate
.state
;
2628 assert(surface_state
.alloc_size
);
2629 if (need_client_mem_relocs
)
2630 add_surface_state_relocs(cmd_buffer
, sstate
);
2632 surface_state
= cmd_buffer
->device
->null_surface_state
;
2637 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2638 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2639 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2640 if (desc
->buffer_view
) {
2641 surface_state
= desc
->buffer_view
->surface_state
;
2642 assert(surface_state
.alloc_size
);
2643 if (need_client_mem_relocs
) {
2644 add_surface_reloc(cmd_buffer
, surface_state
,
2645 desc
->buffer_view
->address
);
2648 surface_state
= cmd_buffer
->device
->null_surface_state
;
2652 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2653 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2655 /* Compute the offset within the buffer */
2656 struct anv_push_constants
*push
=
2657 &cmd_buffer
->state
.push_constants
[shader
->stage
];
2659 uint32_t dynamic_offset
=
2660 push
->dynamic_offsets
[binding
->dynamic_offset_index
];
2661 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2662 /* Clamp to the buffer size */
2663 offset
= MIN2(offset
, desc
->buffer
->size
);
2664 /* Clamp the range to the buffer size */
2665 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2667 /* Align the range for consistency */
2668 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
)
2669 range
= align_u32(range
, ANV_UBO_ALIGNMENT
);
2671 struct anv_address address
=
2672 anv_address_add(desc
->buffer
->address
, offset
);
2675 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2676 enum isl_format format
=
2677 anv_isl_format_for_descriptor_type(desc
->type
);
2679 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2680 format
, address
, range
, 1);
2681 if (need_client_mem_relocs
)
2682 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2684 surface_state
= cmd_buffer
->device
->null_surface_state
;
2689 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2690 if (desc
->buffer_view
) {
2691 surface_state
= (binding
->write_only
)
2692 ? desc
->buffer_view
->writeonly_storage_surface_state
2693 : desc
->buffer_view
->storage_surface_state
;
2694 assert(surface_state
.alloc_size
);
2695 if (need_client_mem_relocs
) {
2696 add_surface_reloc(cmd_buffer
, surface_state
,
2697 desc
->buffer_view
->address
);
2700 surface_state
= cmd_buffer
->device
->null_surface_state
;
2705 assert(!"Invalid descriptor type");
2708 assert(surface_state
.map
);
2709 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2719 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2720 struct anv_cmd_pipeline_state
*pipe_state
,
2721 struct anv_shader_bin
*shader
,
2722 struct anv_state
*state
)
2724 struct anv_pipeline_bind_map
*map
= &shader
->bind_map
;
2725 if (map
->sampler_count
== 0) {
2726 *state
= (struct anv_state
) { 0, };
2730 uint32_t size
= map
->sampler_count
* 16;
2731 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2733 if (state
->map
== NULL
)
2734 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2736 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2737 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2738 const struct anv_descriptor
*desc
=
2739 &pipe_state
->descriptors
[binding
->set
]->descriptors
[binding
->index
];
2741 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2742 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2745 struct anv_sampler
*sampler
= desc
->sampler
;
2747 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2748 * happens to be zero.
2750 if (sampler
== NULL
)
2753 memcpy(state
->map
+ (s
* 16),
2754 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2761 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
,
2762 struct anv_cmd_pipeline_state
*pipe_state
,
2763 struct anv_shader_bin
**shaders
,
2764 uint32_t num_shaders
)
2766 const VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
;
2767 VkShaderStageFlags flushed
= 0;
2769 VkResult result
= VK_SUCCESS
;
2770 for (uint32_t i
= 0; i
< num_shaders
; i
++) {
2774 gl_shader_stage stage
= shaders
[i
]->stage
;
2775 VkShaderStageFlags vk_stage
= mesa_to_vk_shader_stage(stage
);
2776 if ((vk_stage
& dirty
) == 0)
2779 result
= emit_samplers(cmd_buffer
, pipe_state
, shaders
[i
],
2780 &cmd_buffer
->state
.samplers
[stage
]);
2781 if (result
!= VK_SUCCESS
)
2783 result
= emit_binding_table(cmd_buffer
, pipe_state
, shaders
[i
],
2784 &cmd_buffer
->state
.binding_tables
[stage
]);
2785 if (result
!= VK_SUCCESS
)
2788 flushed
|= vk_stage
;
2791 if (result
!= VK_SUCCESS
) {
2792 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2794 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2795 if (result
!= VK_SUCCESS
)
2798 /* Re-emit state base addresses so we get the new surface state base
2799 * address before we start emitting binding tables etc.
2801 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2803 /* Re-emit all active binding tables */
2806 for (uint32_t i
= 0; i
< num_shaders
; i
++) {
2810 gl_shader_stage stage
= shaders
[i
]->stage
;
2812 result
= emit_samplers(cmd_buffer
, pipe_state
, shaders
[i
],
2813 &cmd_buffer
->state
.samplers
[stage
]);
2814 if (result
!= VK_SUCCESS
) {
2815 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2818 result
= emit_binding_table(cmd_buffer
, pipe_state
, shaders
[i
],
2819 &cmd_buffer
->state
.binding_tables
[stage
]);
2820 if (result
!= VK_SUCCESS
) {
2821 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2825 flushed
|= mesa_to_vk_shader_stage(stage
);
2829 cmd_buffer
->state
.descriptors_dirty
&= ~flushed
;
2835 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2838 static const uint32_t sampler_state_opcodes
[] = {
2839 [MESA_SHADER_VERTEX
] = 43,
2840 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2841 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2842 [MESA_SHADER_GEOMETRY
] = 46,
2843 [MESA_SHADER_FRAGMENT
] = 47,
2844 [MESA_SHADER_COMPUTE
] = 0,
2847 static const uint32_t binding_table_opcodes
[] = {
2848 [MESA_SHADER_VERTEX
] = 38,
2849 [MESA_SHADER_TESS_CTRL
] = 39,
2850 [MESA_SHADER_TESS_EVAL
] = 40,
2851 [MESA_SHADER_GEOMETRY
] = 41,
2852 [MESA_SHADER_FRAGMENT
] = 42,
2853 [MESA_SHADER_COMPUTE
] = 0,
2856 anv_foreach_stage(s
, stages
) {
2857 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2858 assert(binding_table_opcodes
[s
] > 0);
2860 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2861 anv_batch_emit(&cmd_buffer
->batch
,
2862 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2863 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2864 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2868 /* Always emit binding table pointers if we're asked to, since on SKL
2869 * this is what flushes push constants. */
2870 anv_batch_emit(&cmd_buffer
->batch
,
2871 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2872 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2873 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2878 static struct anv_address
2879 get_push_range_address(struct anv_cmd_buffer
*cmd_buffer
,
2880 gl_shader_stage stage
,
2881 const struct anv_push_range
*range
)
2883 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2884 switch (range
->set
) {
2885 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2886 /* This is a descriptor set buffer so the set index is
2887 * actually given by binding->binding. (Yes, that's
2890 struct anv_descriptor_set
*set
=
2891 gfx_state
->base
.descriptors
[range
->index
];
2892 return anv_descriptor_set_address(cmd_buffer
, set
);
2895 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
: {
2896 struct anv_state state
=
2897 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2898 return (struct anv_address
) {
2899 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2900 .offset
= state
.offset
,
2905 assert(range
->set
< MAX_SETS
);
2906 struct anv_descriptor_set
*set
=
2907 gfx_state
->base
.descriptors
[range
->set
];
2908 const struct anv_descriptor
*desc
=
2909 &set
->descriptors
[range
->index
];
2911 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2912 if (desc
->buffer_view
)
2913 return desc
->buffer_view
->address
;
2915 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2917 struct anv_push_constants
*push
=
2918 &cmd_buffer
->state
.push_constants
[stage
];
2919 uint32_t dynamic_offset
=
2920 push
->dynamic_offsets
[range
->dynamic_offset_index
];
2921 return anv_address_add(desc
->buffer
->address
,
2922 desc
->offset
+ dynamic_offset
);
2926 /* For NULL UBOs, we just return an address in the workaround BO. We do
2927 * writes to it for workarounds but always at the bottom. The higher
2928 * bytes should be all zeros.
2930 assert(range
->length
* 32 <= 2048);
2931 return (struct anv_address
) {
2932 .bo
= cmd_buffer
->device
->workaround_bo
,
2940 /** Returns the size in bytes of the bound buffer
2942 * The range is relative to the start of the buffer, not the start of the
2943 * range. The returned range may be smaller than
2945 * (range->start + range->length) * 32;
2948 get_push_range_bound_size(struct anv_cmd_buffer
*cmd_buffer
,
2949 gl_shader_stage stage
,
2950 const struct anv_push_range
*range
)
2952 assert(stage
!= MESA_SHADER_COMPUTE
);
2953 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2954 switch (range
->set
) {
2955 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2956 struct anv_descriptor_set
*set
=
2957 gfx_state
->base
.descriptors
[range
->index
];
2958 assert(range
->start
* 32 < set
->desc_mem
.alloc_size
);
2959 assert((range
->start
+ range
->length
) * 32 <= set
->desc_mem
.alloc_size
);
2960 return set
->desc_mem
.alloc_size
;
2963 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
:
2964 return (range
->start
+ range
->length
) * 32;
2967 assert(range
->set
< MAX_SETS
);
2968 struct anv_descriptor_set
*set
=
2969 gfx_state
->base
.descriptors
[range
->set
];
2970 const struct anv_descriptor
*desc
=
2971 &set
->descriptors
[range
->index
];
2973 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2974 if (!desc
->buffer_view
)
2977 if (range
->start
* 32 > desc
->buffer_view
->range
)
2980 return desc
->buffer_view
->range
;
2985 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2986 /* Compute the offset within the buffer */
2987 struct anv_push_constants
*push
=
2988 &cmd_buffer
->state
.push_constants
[stage
];
2989 uint32_t dynamic_offset
=
2990 push
->dynamic_offsets
[range
->dynamic_offset_index
];
2991 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2992 /* Clamp to the buffer size */
2993 offset
= MIN2(offset
, desc
->buffer
->size
);
2994 /* Clamp the range to the buffer size */
2995 uint32_t bound_range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2997 /* Align the range for consistency */
2998 bound_range
= align_u32(bound_range
, ANV_UBO_ALIGNMENT
);
3007 cmd_buffer_emit_push_constant(struct anv_cmd_buffer
*cmd_buffer
,
3008 gl_shader_stage stage
,
3009 struct anv_address
*buffers
,
3010 unsigned buffer_count
)
3012 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
3013 const struct anv_graphics_pipeline
*pipeline
= gfx_state
->pipeline
;
3015 static const uint32_t push_constant_opcodes
[] = {
3016 [MESA_SHADER_VERTEX
] = 21,
3017 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3018 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3019 [MESA_SHADER_GEOMETRY
] = 22,
3020 [MESA_SHADER_FRAGMENT
] = 23,
3021 [MESA_SHADER_COMPUTE
] = 0,
3024 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
3025 assert(push_constant_opcodes
[stage
] > 0);
3027 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
3028 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3030 if (anv_pipeline_has_stage(pipeline
, stage
)) {
3031 const struct anv_pipeline_bind_map
*bind_map
=
3032 &pipeline
->shaders
[stage
]->bind_map
;
3035 /* This field exists since Gen8. However, the Broadwell PRM says:
3037 * "Constant Buffer Object Control State must be always programmed
3040 * This restriction does not exist on any newer platforms.
3042 * We only have one MOCS field for the whole packet, not one per
3043 * buffer. We could go out of our way here to walk over all of the
3044 * buffers and see if any of them are used externally and use the
3045 * external MOCS. However, the notion that someone would use the
3046 * same bit of memory for both scanout and a UBO is nuts. Let's not
3047 * bother and assume it's all internal.
3049 c
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
;
3052 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3053 /* The Skylake PRM contains the following restriction:
3055 * "The driver must ensure The following case does not occur
3056 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3057 * buffer 3 read length equal to zero committed followed by a
3058 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3061 * To avoid this, we program the buffers in the highest slots.
3062 * This way, slot 0 is only used if slot 3 is also used.
3064 assert(buffer_count
<= 4);
3065 const unsigned shift
= 4 - buffer_count
;
3066 for (unsigned i
= 0; i
< buffer_count
; i
++) {
3067 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3069 /* At this point we only have non-empty ranges */
3070 assert(range
->length
> 0);
3072 /* For Ivy Bridge, make sure we only set the first range (actual
3075 assert((GEN_GEN
>= 8 || GEN_IS_HASWELL
) || i
== 0);
3077 c
.ConstantBody
.ReadLength
[i
+ shift
] = range
->length
;
3078 c
.ConstantBody
.Buffer
[i
+ shift
] =
3079 anv_address_add(buffers
[i
], range
->start
* 32);
3082 /* For Ivy Bridge, push constants are relative to dynamic state
3083 * base address and we only ever push actual push constants.
3085 if (bind_map
->push_ranges
[0].length
> 0) {
3086 assert(buffer_count
== 1);
3087 assert(bind_map
->push_ranges
[0].set
==
3088 ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
);
3089 assert(buffers
[0].bo
==
3090 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
);
3091 c
.ConstantBody
.ReadLength
[0] = bind_map
->push_ranges
[0].length
;
3092 c
.ConstantBody
.Buffer
[0].bo
= NULL
;
3093 c
.ConstantBody
.Buffer
[0].offset
= buffers
[0].offset
;
3095 assert(bind_map
->push_ranges
[1].length
== 0);
3096 assert(bind_map
->push_ranges
[2].length
== 0);
3097 assert(bind_map
->push_ranges
[3].length
== 0);
3105 cmd_buffer_emit_push_constant_all(struct anv_cmd_buffer
*cmd_buffer
,
3106 uint32_t shader_mask
,
3107 struct anv_address
*buffers
,
3108 uint32_t buffer_count
)
3110 if (buffer_count
== 0) {
3111 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_ALL
), c
) {
3112 c
.ShaderUpdateEnable
= shader_mask
;
3113 c
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
;
3118 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
3119 const struct anv_graphics_pipeline
*pipeline
= gfx_state
->pipeline
;
3121 static const uint32_t push_constant_opcodes
[] = {
3122 [MESA_SHADER_VERTEX
] = 21,
3123 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3124 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3125 [MESA_SHADER_GEOMETRY
] = 22,
3126 [MESA_SHADER_FRAGMENT
] = 23,
3127 [MESA_SHADER_COMPUTE
] = 0,
3130 gl_shader_stage stage
= vk_to_mesa_shader_stage(shader_mask
);
3131 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
3132 assert(push_constant_opcodes
[stage
] > 0);
3134 const struct anv_pipeline_bind_map
*bind_map
=
3135 &pipeline
->shaders
[stage
]->bind_map
;
3138 const uint32_t buffer_mask
= (1 << buffer_count
) - 1;
3139 const uint32_t num_dwords
= 2 + 2 * buffer_count
;
3141 dw
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
3142 GENX(3DSTATE_CONSTANT_ALL
),
3143 .ShaderUpdateEnable
= shader_mask
,
3144 .PointerBufferMask
= buffer_mask
,
3145 .MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
);
3147 for (int i
= 0; i
< buffer_count
; i
++) {
3148 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3149 GENX(3DSTATE_CONSTANT_ALL_DATA_pack
)(
3150 &cmd_buffer
->batch
, dw
+ 2 + i
* 2,
3151 &(struct GENX(3DSTATE_CONSTANT_ALL_DATA
)) {
3152 .PointerToConstantBuffer
=
3153 anv_address_add(buffers
[i
], range
->start
* 32),
3154 .ConstantBufferReadLength
= range
->length
,
3161 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
3162 VkShaderStageFlags dirty_stages
)
3164 VkShaderStageFlags flushed
= 0;
3165 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
3166 const struct anv_graphics_pipeline
*pipeline
= gfx_state
->pipeline
;
3169 uint32_t nobuffer_stages
= 0;
3172 anv_foreach_stage(stage
, dirty_stages
) {
3173 unsigned buffer_count
= 0;
3174 flushed
|= mesa_to_vk_shader_stage(stage
);
3175 UNUSED
uint32_t max_push_range
= 0;
3177 struct anv_address buffers
[4] = {};
3178 if (anv_pipeline_has_stage(pipeline
, stage
)) {
3179 const struct anv_pipeline_bind_map
*bind_map
=
3180 &pipeline
->shaders
[stage
]->bind_map
;
3181 struct anv_push_constants
*push
=
3182 &cmd_buffer
->state
.push_constants
[stage
];
3184 if (cmd_buffer
->device
->robust_buffer_access
) {
3185 push
->push_reg_mask
= 0;
3186 /* Start of the current range in the shader, relative to the start
3187 * of push constants in the shader.
3189 unsigned range_start_reg
= 0;
3190 for (unsigned i
= 0; i
< 4; i
++) {
3191 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3192 if (range
->length
== 0)
3195 unsigned bound_size
=
3196 get_push_range_bound_size(cmd_buffer
, stage
, range
);
3197 if (bound_size
>= range
->start
* 32) {
3198 unsigned bound_regs
=
3199 MIN2(DIV_ROUND_UP(bound_size
, 32) - range
->start
,
3201 assert(range_start_reg
+ bound_regs
<= 64);
3202 push
->push_reg_mask
|= BITFIELD64_RANGE(range_start_reg
,
3206 cmd_buffer
->state
.push_constants_dirty
|=
3207 mesa_to_vk_shader_stage(stage
);
3209 range_start_reg
+= range
->length
;
3213 /* We have to gather buffer addresses as a second step because the
3214 * loop above puts data into the push constant area and the call to
3215 * get_push_range_address is what locks our push constants and copies
3216 * them into the actual GPU buffer. If we did the two loops at the
3217 * same time, we'd risk only having some of the sizes in the push
3218 * constant buffer when we did the copy.
3220 for (unsigned i
= 0; i
< 4; i
++) {
3221 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3222 if (range
->length
== 0)
3225 buffers
[i
] = get_push_range_address(cmd_buffer
, stage
, range
);
3226 max_push_range
= MAX2(max_push_range
, range
->length
);
3230 /* We have at most 4 buffers but they should be tightly packed */
3231 for (unsigned i
= buffer_count
; i
< 4; i
++)
3232 assert(bind_map
->push_ranges
[i
].length
== 0);
3236 /* If this stage doesn't have any push constants, emit it later in a
3237 * single CONSTANT_ALL packet.
3239 if (buffer_count
== 0) {
3240 nobuffer_stages
|= 1 << stage
;
3244 /* The Constant Buffer Read Length field from 3DSTATE_CONSTANT_ALL
3245 * contains only 5 bits, so we can only use it for buffers smaller than
3248 if (max_push_range
< 32) {
3249 cmd_buffer_emit_push_constant_all(cmd_buffer
, 1 << stage
,
3250 buffers
, buffer_count
);
3255 cmd_buffer_emit_push_constant(cmd_buffer
, stage
, buffers
, buffer_count
);
3259 if (nobuffer_stages
)
3260 cmd_buffer_emit_push_constant_all(cmd_buffer
, nobuffer_stages
, NULL
, 0);
3263 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
3267 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3269 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3272 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
3274 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->base
.l3_config
);
3276 genX(cmd_buffer_emit_hashing_mode
)(cmd_buffer
, UINT_MAX
, UINT_MAX
, 1);
3278 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3280 /* Apply any pending pipeline flushes we may have. We want to apply them
3281 * now because, if any of those flushes are for things like push constants,
3282 * the GPU will read the state at weird times.
3284 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3286 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
3287 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
3288 vb_emit
|= pipeline
->vb_used
;
3291 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
3292 const uint32_t num_dwords
= 1 + num_buffers
* 4;
3294 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
3295 GENX(3DSTATE_VERTEX_BUFFERS
));
3297 for_each_bit(vb
, vb_emit
) {
3298 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
3299 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
3301 struct GENX(VERTEX_BUFFER_STATE
) state
;
3303 state
= (struct GENX(VERTEX_BUFFER_STATE
)) {
3304 .VertexBufferIndex
= vb
,
3306 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
3308 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
3309 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
3312 .AddressModifyEnable
= true,
3313 .BufferPitch
= pipeline
->vb
[vb
].stride
,
3314 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
3315 .NullVertexBuffer
= offset
>= buffer
->size
,
3318 .BufferSize
= buffer
->size
- offset
3320 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
3324 state
= (struct GENX(VERTEX_BUFFER_STATE
)) {
3325 .VertexBufferIndex
= vb
,
3326 .NullVertexBuffer
= true,
3330 #if GEN_GEN >= 8 && GEN_GEN <= 9
3331 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(cmd_buffer
, vb
,
3332 state
.BufferStartingAddress
,
3336 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
3341 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
3344 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
3345 /* We don't need any per-buffer dirty tracking because you're not
3346 * allowed to bind different XFB buffers while XFB is enabled.
3348 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3349 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
3350 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3352 sob
.SOBufferIndex
= idx
;
3354 sob
._3DCommandOpcode
= 0;
3355 sob
._3DCommandSubOpcode
= SO_BUFFER_INDEX_0_CMD
+ idx
;
3358 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
3359 sob
.SOBufferEnable
= true;
3360 sob
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
,
3361 sob
.StreamOffsetWriteEnable
= false;
3362 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
3364 /* Size is in DWords - 1 */
3365 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
3370 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
3372 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3376 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
3377 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->base
.batch
);
3379 /* If the pipeline changed, we may need to re-allocate push constant
3382 cmd_buffer_alloc_push_constants(cmd_buffer
);
3386 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
3387 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
3388 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
3390 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
3391 * stall needs to be sent just prior to any 3DSTATE_VS,
3392 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
3393 * 3DSTATE_BINDING_TABLE_POINTER_VS,
3394 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
3395 * PIPE_CONTROL needs to be sent before any combination of VS
3396 * associated 3DSTATE."
3398 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3399 pc
.DepthStallEnable
= true;
3400 pc
.PostSyncOperation
= WriteImmediateData
;
3401 pc
.Address
= cmd_buffer
->device
->workaround_address
;
3406 /* Render targets live in the same binding table as fragment descriptors */
3407 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
3408 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
3410 /* We emit the binding tables and sampler tables first, then emit push
3411 * constants and then finally emit binding table and sampler table
3412 * pointers. It has to happen in this order, since emitting the binding
3413 * tables may change the push constants (in case of storage images). After
3414 * emitting push constants, on SKL+ we have to emit the corresponding
3415 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
3418 if (cmd_buffer
->state
.descriptors_dirty
) {
3419 dirty
= flush_descriptor_sets(cmd_buffer
,
3420 &cmd_buffer
->state
.gfx
.base
,
3422 ARRAY_SIZE(pipeline
->shaders
));
3425 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
3426 /* Because we're pushing UBOs, we have to push whenever either
3427 * descriptors or push constants is dirty.
3429 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
3430 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
3431 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
3435 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
3437 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
3438 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
3440 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
3441 ANV_CMD_DIRTY_PIPELINE
)) {
3442 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
3443 pipeline
->depth_clamp_enable
);
3446 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
3447 ANV_CMD_DIRTY_RENDER_TARGETS
))
3448 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
3450 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
3454 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
3455 struct anv_address addr
,
3456 uint32_t size
, uint32_t index
)
3458 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
3459 GENX(3DSTATE_VERTEX_BUFFERS
));
3461 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
3462 &(struct GENX(VERTEX_BUFFER_STATE
)) {
3463 .VertexBufferIndex
= index
,
3464 .AddressModifyEnable
= true,
3466 .MOCS
= addr
.bo
? anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
) : 0,
3467 .NullVertexBuffer
= size
== 0,
3469 .BufferStartingAddress
= addr
,
3472 .BufferStartingAddress
= addr
,
3473 .EndAddress
= anv_address_add(addr
, size
),
3477 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(cmd_buffer
,
3482 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
3483 struct anv_address addr
)
3485 emit_vertex_bo(cmd_buffer
, addr
, addr
.bo
? 8 : 0, ANV_SVGS_VB_INDEX
);
3489 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
3490 uint32_t base_vertex
, uint32_t base_instance
)
3492 if (base_vertex
== 0 && base_instance
== 0) {
3493 emit_base_vertex_instance_bo(cmd_buffer
, ANV_NULL_ADDRESS
);
3495 struct anv_state id_state
=
3496 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
3498 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
3499 ((uint32_t *)id_state
.map
)[1] = base_instance
;
3501 struct anv_address addr
= {
3502 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3503 .offset
= id_state
.offset
,
3506 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
3511 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
3513 struct anv_state state
=
3514 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
3516 ((uint32_t *)state
.map
)[0] = draw_index
;
3518 struct anv_address addr
= {
3519 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3520 .offset
= state
.offset
,
3523 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
3527 update_dirty_vbs_for_gen8_vb_flush(struct anv_cmd_buffer
*cmd_buffer
,
3528 uint32_t access_type
)
3530 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3531 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3533 uint64_t vb_used
= pipeline
->vb_used
;
3534 if (vs_prog_data
->uses_firstvertex
||
3535 vs_prog_data
->uses_baseinstance
)
3536 vb_used
|= 1ull << ANV_SVGS_VB_INDEX
;
3537 if (vs_prog_data
->uses_drawid
)
3538 vb_used
|= 1ull << ANV_DRAWID_VB_INDEX
;
3540 genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush
)(cmd_buffer
,
3541 access_type
== RANDOM
,
3546 VkCommandBuffer commandBuffer
,
3547 uint32_t vertexCount
,
3548 uint32_t instanceCount
,
3549 uint32_t firstVertex
,
3550 uint32_t firstInstance
)
3552 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3553 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3554 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3556 if (anv_batch_has_error(&cmd_buffer
->batch
))
3559 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3561 if (cmd_buffer
->state
.conditional_render_enabled
)
3562 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3564 if (vs_prog_data
->uses_firstvertex
||
3565 vs_prog_data
->uses_baseinstance
)
3566 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3567 if (vs_prog_data
->uses_drawid
)
3568 emit_draw_index(cmd_buffer
, 0);
3570 /* Emitting draw index or vertex index BOs may result in needing
3571 * additional VF cache flushes.
3573 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3575 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3576 * different views. We need to multiply instanceCount by the view count.
3578 if (!pipeline
->use_primitive_replication
)
3579 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3581 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3582 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3583 prim
.VertexAccessType
= SEQUENTIAL
;
3584 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3585 prim
.VertexCountPerInstance
= vertexCount
;
3586 prim
.StartVertexLocation
= firstVertex
;
3587 prim
.InstanceCount
= instanceCount
;
3588 prim
.StartInstanceLocation
= firstInstance
;
3589 prim
.BaseVertexLocation
= 0;
3592 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3595 void genX(CmdDrawIndexed
)(
3596 VkCommandBuffer commandBuffer
,
3597 uint32_t indexCount
,
3598 uint32_t instanceCount
,
3599 uint32_t firstIndex
,
3600 int32_t vertexOffset
,
3601 uint32_t firstInstance
)
3603 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3604 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3605 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3607 if (anv_batch_has_error(&cmd_buffer
->batch
))
3610 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3612 if (cmd_buffer
->state
.conditional_render_enabled
)
3613 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3615 if (vs_prog_data
->uses_firstvertex
||
3616 vs_prog_data
->uses_baseinstance
)
3617 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
3618 if (vs_prog_data
->uses_drawid
)
3619 emit_draw_index(cmd_buffer
, 0);
3621 /* Emitting draw index or vertex index BOs may result in needing
3622 * additional VF cache flushes.
3624 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3626 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3627 * different views. We need to multiply instanceCount by the view count.
3629 if (!pipeline
->use_primitive_replication
)
3630 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3632 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3633 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3634 prim
.VertexAccessType
= RANDOM
;
3635 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3636 prim
.VertexCountPerInstance
= indexCount
;
3637 prim
.StartVertexLocation
= firstIndex
;
3638 prim
.InstanceCount
= instanceCount
;
3639 prim
.StartInstanceLocation
= firstInstance
;
3640 prim
.BaseVertexLocation
= vertexOffset
;
3643 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
3646 /* Auto-Draw / Indirect Registers */
3647 #define GEN7_3DPRIM_END_OFFSET 0x2420
3648 #define GEN7_3DPRIM_START_VERTEX 0x2430
3649 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
3650 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
3651 #define GEN7_3DPRIM_START_INSTANCE 0x243C
3652 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
3654 void genX(CmdDrawIndirectByteCountEXT
)(
3655 VkCommandBuffer commandBuffer
,
3656 uint32_t instanceCount
,
3657 uint32_t firstInstance
,
3658 VkBuffer counterBuffer
,
3659 VkDeviceSize counterBufferOffset
,
3660 uint32_t counterOffset
,
3661 uint32_t vertexStride
)
3663 #if GEN_IS_HASWELL || GEN_GEN >= 8
3664 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3665 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
3666 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3667 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3669 /* firstVertex is always zero for this draw function */
3670 const uint32_t firstVertex
= 0;
3672 if (anv_batch_has_error(&cmd_buffer
->batch
))
3675 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3677 if (vs_prog_data
->uses_firstvertex
||
3678 vs_prog_data
->uses_baseinstance
)
3679 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3680 if (vs_prog_data
->uses_drawid
)
3681 emit_draw_index(cmd_buffer
, 0);
3683 /* Emitting draw index or vertex index BOs may result in needing
3684 * additional VF cache flushes.
3686 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3688 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3689 * different views. We need to multiply instanceCount by the view count.
3691 if (!pipeline
->use_primitive_replication
)
3692 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3694 struct gen_mi_builder b
;
3695 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3696 struct gen_mi_value count
=
3697 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
3698 counterBufferOffset
));
3700 count
= gen_mi_isub(&b
, count
, gen_mi_imm(counterOffset
));
3701 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
3702 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
3704 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3705 gen_mi_imm(firstVertex
));
3706 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
3707 gen_mi_imm(instanceCount
));
3708 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3709 gen_mi_imm(firstInstance
));
3710 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3712 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3713 prim
.IndirectParameterEnable
= true;
3714 prim
.VertexAccessType
= SEQUENTIAL
;
3715 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3718 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3719 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3723 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
3724 struct anv_address addr
,
3727 struct gen_mi_builder b
;
3728 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3730 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
),
3731 gen_mi_mem32(anv_address_add(addr
, 0)));
3733 struct gen_mi_value instance_count
= gen_mi_mem32(anv_address_add(addr
, 4));
3734 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3735 if (view_count
> 1) {
3736 #if GEN_IS_HASWELL || GEN_GEN >= 8
3737 instance_count
= gen_mi_imul_imm(&b
, instance_count
, view_count
);
3739 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3740 "MI_MATH is not supported on Ivy Bridge");
3743 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
), instance_count
);
3745 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3746 gen_mi_mem32(anv_address_add(addr
, 8)));
3749 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
),
3750 gen_mi_mem32(anv_address_add(addr
, 12)));
3751 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3752 gen_mi_mem32(anv_address_add(addr
, 16)));
3754 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3755 gen_mi_mem32(anv_address_add(addr
, 12)));
3756 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3760 void genX(CmdDrawIndirect
)(
3761 VkCommandBuffer commandBuffer
,
3763 VkDeviceSize offset
,
3767 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3768 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3769 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3770 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3772 if (anv_batch_has_error(&cmd_buffer
->batch
))
3775 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3777 if (cmd_buffer
->state
.conditional_render_enabled
)
3778 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3780 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3781 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3783 if (vs_prog_data
->uses_firstvertex
||
3784 vs_prog_data
->uses_baseinstance
)
3785 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3786 if (vs_prog_data
->uses_drawid
)
3787 emit_draw_index(cmd_buffer
, i
);
3789 /* Emitting draw index or vertex index BOs may result in needing
3790 * additional VF cache flushes.
3792 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3794 load_indirect_parameters(cmd_buffer
, draw
, false);
3796 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3797 prim
.IndirectParameterEnable
= true;
3798 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3799 prim
.VertexAccessType
= SEQUENTIAL
;
3800 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3803 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3809 void genX(CmdDrawIndexedIndirect
)(
3810 VkCommandBuffer commandBuffer
,
3812 VkDeviceSize offset
,
3816 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3817 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3818 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3819 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3821 if (anv_batch_has_error(&cmd_buffer
->batch
))
3824 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3826 if (cmd_buffer
->state
.conditional_render_enabled
)
3827 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3829 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3830 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3832 /* TODO: We need to stomp base vertex to 0 somehow */
3833 if (vs_prog_data
->uses_firstvertex
||
3834 vs_prog_data
->uses_baseinstance
)
3835 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3836 if (vs_prog_data
->uses_drawid
)
3837 emit_draw_index(cmd_buffer
, i
);
3839 /* Emitting draw index or vertex index BOs may result in needing
3840 * additional VF cache flushes.
3842 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3844 load_indirect_parameters(cmd_buffer
, draw
, true);
3846 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3847 prim
.IndirectParameterEnable
= true;
3848 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3849 prim
.VertexAccessType
= RANDOM
;
3850 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3853 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
3859 static struct gen_mi_value
3860 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3861 struct gen_mi_builder
*b
,
3862 struct anv_address count_address
,
3863 const bool conditional_render_enabled
)
3865 struct gen_mi_value ret
= gen_mi_imm(0);
3867 if (conditional_render_enabled
) {
3868 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3869 ret
= gen_mi_new_gpr(b
);
3870 gen_mi_store(b
, gen_mi_value_ref(b
, ret
), gen_mi_mem32(count_address
));
3873 /* Upload the current draw count from the draw parameters buffer to
3874 * MI_PREDICATE_SRC0.
3876 gen_mi_store(b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
3877 gen_mi_mem32(count_address
));
3879 gen_mi_store(b
, gen_mi_reg32(MI_PREDICATE_SRC1
+ 4), gen_mi_imm(0));
3886 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3887 struct gen_mi_builder
*b
,
3888 uint32_t draw_index
)
3890 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3891 gen_mi_store(b
, gen_mi_reg32(MI_PREDICATE_SRC1
), gen_mi_imm(draw_index
));
3893 if (draw_index
== 0) {
3894 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3895 mip
.LoadOperation
= LOAD_LOADINV
;
3896 mip
.CombineOperation
= COMBINE_SET
;
3897 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3900 /* While draw_index < draw_count the predicate's result will be
3901 * (draw_index == draw_count) ^ TRUE = TRUE
3902 * When draw_index == draw_count the result is
3903 * (TRUE) ^ TRUE = FALSE
3904 * After this all results will be:
3905 * (FALSE) ^ FALSE = FALSE
3907 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3908 mip
.LoadOperation
= LOAD_LOAD
;
3909 mip
.CombineOperation
= COMBINE_XOR
;
3910 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3915 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3917 emit_draw_count_predicate_with_conditional_render(
3918 struct anv_cmd_buffer
*cmd_buffer
,
3919 struct gen_mi_builder
*b
,
3920 uint32_t draw_index
,
3921 struct gen_mi_value max
)
3923 struct gen_mi_value pred
= gen_mi_ult(b
, gen_mi_imm(draw_index
), max
);
3924 pred
= gen_mi_iand(b
, pred
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
));
3927 gen_mi_store(b
, gen_mi_reg64(MI_PREDICATE_RESULT
), pred
);
3929 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3930 * so we emit MI_PREDICATE to set it.
3933 gen_mi_store(b
, gen_mi_reg64(MI_PREDICATE_SRC0
), pred
);
3934 gen_mi_store(b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3936 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3937 mip
.LoadOperation
= LOAD_LOADINV
;
3938 mip
.CombineOperation
= COMBINE_SET
;
3939 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3945 void genX(CmdDrawIndirectCount
)(
3946 VkCommandBuffer commandBuffer
,
3948 VkDeviceSize offset
,
3949 VkBuffer _countBuffer
,
3950 VkDeviceSize countBufferOffset
,
3951 uint32_t maxDrawCount
,
3954 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3955 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3956 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3957 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3958 struct anv_graphics_pipeline
*pipeline
= cmd_state
->gfx
.pipeline
;
3959 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3961 if (anv_batch_has_error(&cmd_buffer
->batch
))
3964 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3966 struct gen_mi_builder b
;
3967 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3968 struct anv_address count_address
=
3969 anv_address_add(count_buffer
->address
, countBufferOffset
);
3970 struct gen_mi_value max
=
3971 prepare_for_draw_count_predicate(cmd_buffer
, &b
, count_address
,
3972 cmd_state
->conditional_render_enabled
);
3974 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3975 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3977 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3978 if (cmd_state
->conditional_render_enabled
) {
3979 emit_draw_count_predicate_with_conditional_render(
3980 cmd_buffer
, &b
, i
, gen_mi_value_ref(&b
, max
));
3982 emit_draw_count_predicate(cmd_buffer
, &b
, i
);
3985 emit_draw_count_predicate(cmd_buffer
, &b
, i
);
3988 if (vs_prog_data
->uses_firstvertex
||
3989 vs_prog_data
->uses_baseinstance
)
3990 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3991 if (vs_prog_data
->uses_drawid
)
3992 emit_draw_index(cmd_buffer
, i
);
3994 /* Emitting draw index or vertex index BOs may result in needing
3995 * additional VF cache flushes.
3997 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3999 load_indirect_parameters(cmd_buffer
, draw
, false);
4001 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
4002 prim
.IndirectParameterEnable
= true;
4003 prim
.PredicateEnable
= true;
4004 prim
.VertexAccessType
= SEQUENTIAL
;
4005 prim
.PrimitiveTopologyType
= pipeline
->topology
;
4008 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
4013 gen_mi_value_unref(&b
, max
);
4016 void genX(CmdDrawIndexedIndirectCount
)(
4017 VkCommandBuffer commandBuffer
,
4019 VkDeviceSize offset
,
4020 VkBuffer _countBuffer
,
4021 VkDeviceSize countBufferOffset
,
4022 uint32_t maxDrawCount
,
4025 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4026 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
4027 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
4028 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4029 struct anv_graphics_pipeline
*pipeline
= cmd_state
->gfx
.pipeline
;
4030 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
4032 if (anv_batch_has_error(&cmd_buffer
->batch
))
4035 genX(cmd_buffer_flush_state
)(cmd_buffer
);
4037 struct gen_mi_builder b
;
4038 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4039 struct anv_address count_address
=
4040 anv_address_add(count_buffer
->address
, countBufferOffset
);
4041 struct gen_mi_value max
=
4042 prepare_for_draw_count_predicate(cmd_buffer
, &b
, count_address
,
4043 cmd_state
->conditional_render_enabled
);
4045 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
4046 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
4048 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4049 if (cmd_state
->conditional_render_enabled
) {
4050 emit_draw_count_predicate_with_conditional_render(
4051 cmd_buffer
, &b
, i
, gen_mi_value_ref(&b
, max
));
4053 emit_draw_count_predicate(cmd_buffer
, &b
, i
);
4056 emit_draw_count_predicate(cmd_buffer
, &b
, i
);
4059 /* TODO: We need to stomp base vertex to 0 somehow */
4060 if (vs_prog_data
->uses_firstvertex
||
4061 vs_prog_data
->uses_baseinstance
)
4062 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
4063 if (vs_prog_data
->uses_drawid
)
4064 emit_draw_index(cmd_buffer
, i
);
4066 /* Emitting draw index or vertex index BOs may result in needing
4067 * additional VF cache flushes.
4069 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4071 load_indirect_parameters(cmd_buffer
, draw
, true);
4073 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
4074 prim
.IndirectParameterEnable
= true;
4075 prim
.PredicateEnable
= true;
4076 prim
.VertexAccessType
= RANDOM
;
4077 prim
.PrimitiveTopologyType
= pipeline
->topology
;
4080 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
4085 gen_mi_value_unref(&b
, max
);
4088 void genX(CmdBeginTransformFeedbackEXT
)(
4089 VkCommandBuffer commandBuffer
,
4090 uint32_t firstCounterBuffer
,
4091 uint32_t counterBufferCount
,
4092 const VkBuffer
* pCounterBuffers
,
4093 const VkDeviceSize
* pCounterBufferOffsets
)
4095 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4097 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
4098 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
4099 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
4101 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
4103 * "Ssoftware must ensure that no HW stream output operations can be in
4104 * process or otherwise pending at the point that the MI_LOAD/STORE
4105 * commands are processed. This will likely require a pipeline flush."
4107 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4108 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4110 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
4111 /* If we have a counter buffer, this is a resume so we need to load the
4112 * value into the streamout offset register. Otherwise, this is a begin
4113 * and we need to reset it to zero.
4115 if (pCounterBuffers
&&
4116 idx
>= firstCounterBuffer
&&
4117 idx
- firstCounterBuffer
< counterBufferCount
&&
4118 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
4119 uint32_t cb_idx
= idx
- firstCounterBuffer
;
4120 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
4121 uint64_t offset
= pCounterBufferOffsets
?
4122 pCounterBufferOffsets
[cb_idx
] : 0;
4124 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4125 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
4126 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
4130 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
4131 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
4137 cmd_buffer
->state
.xfb_enabled
= true;
4138 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
4141 void genX(CmdEndTransformFeedbackEXT
)(
4142 VkCommandBuffer commandBuffer
,
4143 uint32_t firstCounterBuffer
,
4144 uint32_t counterBufferCount
,
4145 const VkBuffer
* pCounterBuffers
,
4146 const VkDeviceSize
* pCounterBufferOffsets
)
4148 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4150 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
4151 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
4152 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
4154 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
4156 * "Ssoftware must ensure that no HW stream output operations can be in
4157 * process or otherwise pending at the point that the MI_LOAD/STORE
4158 * commands are processed. This will likely require a pipeline flush."
4160 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4161 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4163 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
4164 unsigned idx
= firstCounterBuffer
+ cb_idx
;
4166 /* If we have a counter buffer, this is a resume so we need to load the
4167 * value into the streamout offset register. Otherwise, this is a begin
4168 * and we need to reset it to zero.
4170 if (pCounterBuffers
&&
4171 cb_idx
< counterBufferCount
&&
4172 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
4173 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
4174 uint64_t offset
= pCounterBufferOffsets
?
4175 pCounterBufferOffsets
[cb_idx
] : 0;
4177 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
4178 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
4180 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
4185 cmd_buffer
->state
.xfb_enabled
= false;
4186 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
4190 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
4192 struct anv_compute_pipeline
*pipeline
= cmd_buffer
->state
.compute
.pipeline
;
4194 assert(pipeline
->cs
);
4196 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->base
.l3_config
);
4198 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
4200 /* Apply any pending pipeline flushes we may have. We want to apply them
4201 * now because, if any of those flushes are for things like push constants,
4202 * the GPU will read the state at weird times.
4204 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4206 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
4207 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
4209 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4210 * the only bits that are changed are scoreboard related: Scoreboard
4211 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
4212 * these scoreboard related states, a MEDIA_STATE_FLUSH is
4215 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4216 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4218 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->base
.batch
);
4220 /* The workgroup size of the pipeline affects our push constant layout
4221 * so flag push constants as dirty if we change the pipeline.
4223 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4226 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
4227 cmd_buffer
->state
.compute
.pipeline_dirty
) {
4228 flush_descriptor_sets(cmd_buffer
,
4229 &cmd_buffer
->state
.compute
.base
,
4232 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
4233 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
4234 .BindingTablePointer
=
4235 cmd_buffer
->state
.binding_tables
[MESA_SHADER_COMPUTE
].offset
,
4236 .SamplerStatePointer
=
4237 cmd_buffer
->state
.samplers
[MESA_SHADER_COMPUTE
].offset
,
4239 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
4241 struct anv_state state
=
4242 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
4243 pipeline
->interface_descriptor_data
,
4244 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
4247 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4248 anv_batch_emit(&cmd_buffer
->batch
,
4249 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
4250 mid
.InterfaceDescriptorTotalLength
= size
;
4251 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
4255 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
4256 struct anv_state push_state
=
4257 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
4259 if (push_state
.alloc_size
) {
4260 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4261 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
4262 curbe
.CURBEDataStartAddress
= push_state
.offset
;
4266 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
4269 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
4271 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4277 verify_cmd_parser(const struct anv_device
*device
,
4278 int required_version
,
4279 const char *function
)
4281 if (device
->physical
->cmd_parser_version
< required_version
) {
4282 return vk_errorf(device
, device
->physical
,
4283 VK_ERROR_FEATURE_NOT_PRESENT
,
4284 "cmd parser version %d is required for %s",
4285 required_version
, function
);
4294 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
4295 uint32_t baseGroupX
,
4296 uint32_t baseGroupY
,
4297 uint32_t baseGroupZ
)
4299 if (anv_batch_has_error(&cmd_buffer
->batch
))
4302 struct anv_push_constants
*push
=
4303 &cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
4304 if (push
->cs
.base_work_group_id
[0] != baseGroupX
||
4305 push
->cs
.base_work_group_id
[1] != baseGroupY
||
4306 push
->cs
.base_work_group_id
[2] != baseGroupZ
) {
4307 push
->cs
.base_work_group_id
[0] = baseGroupX
;
4308 push
->cs
.base_work_group_id
[1] = baseGroupY
;
4309 push
->cs
.base_work_group_id
[2] = baseGroupZ
;
4311 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4315 void genX(CmdDispatch
)(
4316 VkCommandBuffer commandBuffer
,
4321 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
4325 emit_gpgpu_walker(struct anv_cmd_buffer
*cmd_buffer
,
4326 const struct anv_compute_pipeline
*pipeline
, bool indirect
,
4327 const struct brw_cs_prog_data
*prog_data
,
4328 uint32_t groupCountX
, uint32_t groupCountY
,
4329 uint32_t groupCountZ
)
4331 bool predicate
= (GEN_GEN
<= 7 && indirect
) ||
4332 cmd_buffer
->state
.conditional_render_enabled
;
4333 const struct anv_cs_parameters cs_params
= anv_cs_parameters(pipeline
);
4335 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
4336 ggw
.IndirectParameterEnable
= indirect
;
4337 ggw
.PredicateEnable
= predicate
;
4338 ggw
.SIMDSize
= cs_params
.simd_size
/ 16;
4339 ggw
.ThreadDepthCounterMaximum
= 0;
4340 ggw
.ThreadHeightCounterMaximum
= 0;
4341 ggw
.ThreadWidthCounterMaximum
= cs_params
.threads
- 1;
4342 ggw
.ThreadGroupIDXDimension
= groupCountX
;
4343 ggw
.ThreadGroupIDYDimension
= groupCountY
;
4344 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
4345 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
4346 ggw
.BottomExecutionMask
= 0xffffffff;
4349 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
4352 void genX(CmdDispatchBase
)(
4353 VkCommandBuffer commandBuffer
,
4354 uint32_t baseGroupX
,
4355 uint32_t baseGroupY
,
4356 uint32_t baseGroupZ
,
4357 uint32_t groupCountX
,
4358 uint32_t groupCountY
,
4359 uint32_t groupCountZ
)
4361 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4362 struct anv_compute_pipeline
*pipeline
= cmd_buffer
->state
.compute
.pipeline
;
4363 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
4365 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
4366 baseGroupY
, baseGroupZ
);
4368 if (anv_batch_has_error(&cmd_buffer
->batch
))
4371 if (prog_data
->uses_num_work_groups
) {
4372 struct anv_state state
=
4373 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
4374 uint32_t *sizes
= state
.map
;
4375 sizes
[0] = groupCountX
;
4376 sizes
[1] = groupCountY
;
4377 sizes
[2] = groupCountZ
;
4378 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
4379 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4380 .offset
= state
.offset
,
4383 /* The num_workgroups buffer goes in the binding table */
4384 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4387 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
4389 if (cmd_buffer
->state
.conditional_render_enabled
)
4390 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
4392 emit_gpgpu_walker(cmd_buffer
, pipeline
, false, prog_data
, groupCountX
,
4393 groupCountY
, groupCountZ
);
4396 #define GPGPU_DISPATCHDIMX 0x2500
4397 #define GPGPU_DISPATCHDIMY 0x2504
4398 #define GPGPU_DISPATCHDIMZ 0x2508
4400 void genX(CmdDispatchIndirect
)(
4401 VkCommandBuffer commandBuffer
,
4403 VkDeviceSize offset
)
4405 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4406 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
4407 struct anv_compute_pipeline
*pipeline
= cmd_buffer
->state
.compute
.pipeline
;
4408 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
4409 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
4410 UNUSED
struct anv_batch
*batch
= &cmd_buffer
->batch
;
4412 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
4415 /* Linux 4.4 added command parser version 5 which allows the GPGPU
4416 * indirect dispatch registers to be written.
4418 if (verify_cmd_parser(cmd_buffer
->device
, 5,
4419 "vkCmdDispatchIndirect") != VK_SUCCESS
)
4423 if (prog_data
->uses_num_work_groups
) {
4424 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
4426 /* The num_workgroups buffer goes in the binding table */
4427 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4430 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
4432 struct gen_mi_builder b
;
4433 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4435 struct gen_mi_value size_x
= gen_mi_mem32(anv_address_add(addr
, 0));
4436 struct gen_mi_value size_y
= gen_mi_mem32(anv_address_add(addr
, 4));
4437 struct gen_mi_value size_z
= gen_mi_mem32(anv_address_add(addr
, 8));
4439 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMX
), size_x
);
4440 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMY
), size_y
);
4441 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMZ
), size_z
);
4444 /* predicate = (compute_dispatch_indirect_x_size == 0); */
4445 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), size_x
);
4446 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
4447 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4448 mip
.LoadOperation
= LOAD_LOAD
;
4449 mip
.CombineOperation
= COMBINE_SET
;
4450 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4453 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
4454 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_y
);
4455 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4456 mip
.LoadOperation
= LOAD_LOAD
;
4457 mip
.CombineOperation
= COMBINE_OR
;
4458 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4461 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
4462 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_z
);
4463 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4464 mip
.LoadOperation
= LOAD_LOAD
;
4465 mip
.CombineOperation
= COMBINE_OR
;
4466 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4469 /* predicate = !predicate; */
4470 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4471 mip
.LoadOperation
= LOAD_LOADINV
;
4472 mip
.CombineOperation
= COMBINE_OR
;
4473 mip
.CompareOperation
= COMPARE_FALSE
;
4477 if (cmd_buffer
->state
.conditional_render_enabled
) {
4478 /* predicate &= !(conditional_rendering_predicate == 0); */
4479 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
),
4480 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
4481 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4482 mip
.LoadOperation
= LOAD_LOADINV
;
4483 mip
.CombineOperation
= COMBINE_AND
;
4484 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4489 #else /* GEN_GEN > 7 */
4490 if (cmd_buffer
->state
.conditional_render_enabled
)
4491 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
4494 emit_gpgpu_walker(cmd_buffer
, pipeline
, true, prog_data
, 0, 0, 0);
4498 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
4501 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4503 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
4506 #if GEN_GEN >= 8 && GEN_GEN < 10
4507 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
4509 * Software must clear the COLOR_CALC_STATE Valid field in
4510 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
4511 * with Pipeline Select set to GPGPU.
4513 * The internal hardware docs recommend the same workaround for Gen9
4516 if (pipeline
== GPGPU
)
4517 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
4521 if (pipeline
== _3D
) {
4522 /* There is a mid-object preemption workaround which requires you to
4523 * re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D. However,
4524 * even without preemption, we have issues with geometry flickering when
4525 * GPGPU and 3D are back-to-back and this seems to fix it. We don't
4528 const uint32_t subslices
=
4529 MAX2(cmd_buffer
->device
->physical
->subslice_total
, 1);
4530 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
4531 vfe
.MaximumNumberofThreads
=
4532 devinfo
->max_cs_threads
* subslices
- 1;
4533 vfe
.NumberofURBEntries
= 2;
4534 vfe
.URBEntryAllocationSize
= 2;
4537 /* We just emitted a dummy MEDIA_VFE_STATE so now that packet is
4538 * invalid. Set the compute pipeline to dirty to force a re-emit of the
4539 * pipeline in case we get back-to-back dispatch calls with the same
4540 * pipeline and a PIPELINE_SELECT in between.
4542 cmd_buffer
->state
.compute
.pipeline_dirty
= true;
4546 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
4547 * PIPELINE_SELECT [DevBWR+]":
4551 * Software must ensure all the write caches are flushed through a
4552 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
4553 * command to invalidate read only caches prior to programming
4554 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
4556 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4557 pc
.RenderTargetCacheFlushEnable
= true;
4558 pc
.DepthCacheFlushEnable
= true;
4559 pc
.DCFlushEnable
= true;
4560 pc
.PostSyncOperation
= NoWrite
;
4561 pc
.CommandStreamerStallEnable
= true;
4563 pc
.TileCacheFlushEnable
= true;
4565 /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must be
4566 * set with any PIPE_CONTROL with Depth Flush Enable bit set.
4568 pc
.DepthStallEnable
= true;
4572 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4573 pc
.TextureCacheInvalidationEnable
= true;
4574 pc
.ConstantCacheInvalidationEnable
= true;
4575 pc
.StateCacheInvalidationEnable
= true;
4576 pc
.InstructionCacheInvalidateEnable
= true;
4577 pc
.PostSyncOperation
= NoWrite
;
4579 pc
.TileCacheFlushEnable
= true;
4583 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
4587 ps
.PipelineSelection
= pipeline
;
4591 if (devinfo
->is_geminilake
) {
4594 * "This chicken bit works around a hardware issue with barrier logic
4595 * encountered when switching between GPGPU and 3D pipelines. To
4596 * workaround the issue, this mode bit should be set after a pipeline
4600 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
4602 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
4603 : GLK_BARRIER_MODE_3D_HULL
,
4604 .GLKBarrierModeMask
= 1);
4605 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
4609 cmd_buffer
->state
.current_pipeline
= pipeline
;
4613 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
4615 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
4619 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
4621 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
4625 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
4630 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
4632 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
4633 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
4634 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
4635 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
4636 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
4637 * Depth Flush Bit set, followed by another pipelined depth stall
4638 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
4639 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
4640 * via a preceding MI_FLUSH)."
4642 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4643 pipe
.DepthStallEnable
= true;
4645 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4646 pipe
.DepthCacheFlushEnable
= true;
4648 pipe
.TileCacheFlushEnable
= true;
4651 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4652 pipe
.DepthStallEnable
= true;
4656 /* From the Skylake PRM, 3DSTATE_VERTEX_BUFFERS:
4658 * "The VF cache needs to be invalidated before binding and then using
4659 * Vertex Buffers that overlap with any previously bound Vertex Buffer
4660 * (at a 64B granularity) since the last invalidation. A VF cache
4661 * invalidate is performed by setting the "VF Cache Invalidation Enable"
4662 * bit in PIPE_CONTROL."
4664 * This is implemented by carefully tracking all vertex and index buffer
4665 * bindings and flushing if the cache ever ends up with a range in the cache
4666 * that would exceed 4 GiB. This is implemented in three parts:
4668 * 1. genX(cmd_buffer_set_binding_for_gen8_vb_flush)() which must be called
4669 * every time a 3DSTATE_VERTEX_BUFFER packet is emitted and informs the
4670 * tracking code of the new binding. If this new binding would cause
4671 * the cache to have a too-large range on the next draw call, a pipeline
4672 * stall and VF cache invalidate are added to pending_pipeline_bits.
4674 * 2. genX(cmd_buffer_apply_pipe_flushes)() resets the cache tracking to
4675 * empty whenever we emit a VF invalidate.
4677 * 3. genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush)() must be called
4678 * after every 3DPRIMITIVE and copies the bound range into the dirty
4679 * range for each used buffer. This has to be a separate step because
4680 * we don't always re-bind all buffers and so 1. can't know which
4681 * buffers are actually bound.
4684 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(struct anv_cmd_buffer
*cmd_buffer
,
4686 struct anv_address vb_address
,
4689 if (GEN_GEN
< 8 || GEN_GEN
> 9 ||
4690 !cmd_buffer
->device
->physical
->use_softpin
)
4693 struct anv_vb_cache_range
*bound
, *dirty
;
4694 if (vb_index
== -1) {
4695 bound
= &cmd_buffer
->state
.gfx
.ib_bound_range
;
4696 dirty
= &cmd_buffer
->state
.gfx
.ib_dirty_range
;
4698 assert(vb_index
>= 0);
4699 assert(vb_index
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_bound_ranges
));
4700 assert(vb_index
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
4701 bound
= &cmd_buffer
->state
.gfx
.vb_bound_ranges
[vb_index
];
4702 dirty
= &cmd_buffer
->state
.gfx
.vb_dirty_ranges
[vb_index
];
4711 assert(vb_address
.bo
&& (vb_address
.bo
->flags
& EXEC_OBJECT_PINNED
));
4712 bound
->start
= gen_48b_address(anv_address_physical(vb_address
));
4713 bound
->end
= bound
->start
+ vb_size
;
4714 assert(bound
->end
> bound
->start
); /* No overflow */
4716 /* Align everything to a cache line */
4717 bound
->start
&= ~(64ull - 1ull);
4718 bound
->end
= align_u64(bound
->end
, 64);
4720 /* Compute the dirty range */
4721 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4722 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4724 /* If our range is larger than 32 bits, we have to flush */
4725 assert(bound
->end
- bound
->start
<= (1ull << 32));
4726 if (dirty
->end
- dirty
->start
> (1ull << 32)) {
4727 cmd_buffer
->state
.pending_pipe_bits
|=
4728 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
4733 genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush
)(struct anv_cmd_buffer
*cmd_buffer
,
4734 uint32_t access_type
,
4737 if (GEN_GEN
< 8 || GEN_GEN
> 9 ||
4738 !cmd_buffer
->device
->physical
->use_softpin
)
4741 if (access_type
== RANDOM
) {
4742 /* We have an index buffer */
4743 struct anv_vb_cache_range
*bound
= &cmd_buffer
->state
.gfx
.ib_bound_range
;
4744 struct anv_vb_cache_range
*dirty
= &cmd_buffer
->state
.gfx
.ib_dirty_range
;
4746 if (bound
->end
> bound
->start
) {
4747 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4748 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4752 uint64_t mask
= vb_used
;
4754 int i
= u_bit_scan64(&mask
);
4756 assert(i
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_bound_ranges
));
4757 assert(i
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
4759 struct anv_vb_cache_range
*bound
, *dirty
;
4760 bound
= &cmd_buffer
->state
.gfx
.vb_bound_ranges
[i
];
4761 dirty
= &cmd_buffer
->state
.gfx
.vb_dirty_ranges
[i
];
4763 if (bound
->end
> bound
->start
) {
4764 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4765 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4771 * Update the pixel hashing modes that determine the balancing of PS threads
4772 * across subslices and slices.
4774 * \param width Width bound of the rendering area (already scaled down if \p
4775 * scale is greater than 1).
4776 * \param height Height bound of the rendering area (already scaled down if \p
4777 * scale is greater than 1).
4778 * \param scale The number of framebuffer samples that could potentially be
4779 * affected by an individual channel of the PS thread. This is
4780 * typically one for single-sampled rendering, but for operations
4781 * like CCS resolves and fast clears a single PS invocation may
4782 * update a huge number of pixels, in which case a finer
4783 * balancing is desirable in order to maximally utilize the
4784 * bandwidth available. UINT_MAX can be used as shorthand for
4785 * "finest hashing mode available".
4788 genX(cmd_buffer_emit_hashing_mode
)(struct anv_cmd_buffer
*cmd_buffer
,
4789 unsigned width
, unsigned height
,
4793 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4794 const unsigned slice_hashing
[] = {
4795 /* Because all Gen9 platforms with more than one slice require
4796 * three-way subslice hashing, a single "normal" 16x16 slice hashing
4797 * block is guaranteed to suffer from substantial imbalance, with one
4798 * subslice receiving twice as much work as the other two in the
4801 * The performance impact of that would be particularly severe when
4802 * three-way hashing is also in use for slice balancing (which is the
4803 * case for all Gen9 GT4 platforms), because one of the slices
4804 * receives one every three 16x16 blocks in either direction, which
4805 * is roughly the periodicity of the underlying subslice imbalance
4806 * pattern ("roughly" because in reality the hardware's
4807 * implementation of three-way hashing doesn't do exact modulo 3
4808 * arithmetic, which somewhat decreases the magnitude of this effect
4809 * in practice). This leads to a systematic subslice imbalance
4810 * within that slice regardless of the size of the primitive. The
4811 * 32x32 hashing mode guarantees that the subslice imbalance within a
4812 * single slice hashing block is minimal, largely eliminating this
4816 /* Finest slice hashing mode available. */
4819 const unsigned subslice_hashing
[] = {
4820 /* 16x16 would provide a slight cache locality benefit especially
4821 * visible in the sampler L1 cache efficiency of low-bandwidth
4822 * non-LLC platforms, but it comes at the cost of greater subslice
4823 * imbalance for primitives of dimensions approximately intermediate
4824 * between 16x4 and 16x16.
4827 /* Finest subslice hashing mode available. */
4830 /* Dimensions of the smallest hashing block of a given hashing mode. If
4831 * the rendering area is smaller than this there can't possibly be any
4832 * benefit from switching to this mode, so we optimize out the
4835 const unsigned min_size
[][2] = {
4839 const unsigned idx
= scale
> 1;
4841 if (cmd_buffer
->state
.current_hash_scale
!= scale
&&
4842 (width
> min_size
[idx
][0] || height
> min_size
[idx
][1])) {
4845 anv_pack_struct(>_mode
, GENX(GT_MODE
),
4846 .SliceHashing
= (devinfo
->num_slices
> 1 ? slice_hashing
[idx
] : 0),
4847 .SliceHashingMask
= (devinfo
->num_slices
> 1 ? -1 : 0),
4848 .SubsliceHashing
= subslice_hashing
[idx
],
4849 .SubsliceHashingMask
= -1);
4851 cmd_buffer
->state
.pending_pipe_bits
|=
4852 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
4853 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4855 emit_lri(&cmd_buffer
->batch
, GENX(GT_MODE_num
), gt_mode
);
4857 cmd_buffer
->state
.current_hash_scale
= scale
;
4863 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
4865 struct anv_device
*device
= cmd_buffer
->device
;
4866 const struct anv_image_view
*iview
=
4867 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
4868 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
4870 /* FIXME: Width and Height are wrong */
4872 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
4874 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
4875 device
->isl_dev
.ds
.size
/ 4);
4879 struct isl_depth_stencil_hiz_emit_info info
= { };
4882 info
.view
= &iview
->planes
[0].isl
;
4884 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
4885 uint32_t depth_plane
=
4886 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
4887 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
4889 info
.depth_surf
= &surface
->isl
;
4891 info
.depth_address
=
4892 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4893 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
4894 image
->planes
[depth_plane
].address
.bo
,
4895 image
->planes
[depth_plane
].address
.offset
+
4898 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
4901 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
4902 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
4903 if (info
.hiz_usage
!= ISL_AUX_USAGE_NONE
) {
4904 assert(isl_aux_usage_has_hiz(info
.hiz_usage
));
4905 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
4908 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4909 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
4910 image
->planes
[depth_plane
].address
.bo
,
4911 image
->planes
[depth_plane
].address
.offset
+
4912 image
->planes
[depth_plane
].aux_surface
.offset
);
4914 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
4918 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4919 uint32_t stencil_plane
=
4920 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
4921 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
4923 info
.stencil_surf
= &surface
->isl
;
4925 info
.stencil_address
=
4926 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4927 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
4928 image
->planes
[stencil_plane
].address
.bo
,
4929 image
->planes
[stencil_plane
].address
.offset
+
4932 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
4935 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
4937 if (GEN_GEN
>= 12) {
4938 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
4939 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4941 /* GEN:BUG:1408224581
4943 * Workaround: Gen12LP Astep only An additional pipe control with
4944 * post-sync = store dword operation would be required.( w/a is to
4945 * have an additional pipe control after the stencil state whenever
4946 * the surface state bits of this state is changing).
4948 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4949 pc
.PostSyncOperation
= WriteImmediateData
;
4950 pc
.Address
= cmd_buffer
->device
->workaround_address
;
4953 cmd_buffer
->state
.hiz_enabled
= isl_aux_usage_has_hiz(info
.hiz_usage
);
4957 * This ANDs the view mask of the current subpass with the pending clear
4958 * views in the attachment to get the mask of views active in the subpass
4959 * that still need to be cleared.
4961 static inline uint32_t
4962 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
4963 const struct anv_attachment_state
*att_state
)
4965 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
4969 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
4970 const struct anv_attachment_state
*att_state
)
4972 if (!cmd_state
->subpass
->view_mask
)
4975 uint32_t pending_clear_mask
=
4976 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4978 return pending_clear_mask
& 1;
4982 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
4985 const uint32_t last_subpass_idx
=
4986 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
4987 const struct anv_subpass
*last_subpass
=
4988 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
4989 return last_subpass
== cmd_state
->subpass
;
4993 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
4994 uint32_t subpass_id
)
4996 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4997 struct anv_render_pass
*pass
= cmd_state
->pass
;
4998 struct anv_subpass
*subpass
= &pass
->subpasses
[subpass_id
];
4999 cmd_state
->subpass
= subpass
;
5001 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
5003 /* Our implementation of VK_KHR_multiview uses instancing to draw the
5004 * different views. If the client asks for instancing, we need to use the
5005 * Instance Data Step Rate to ensure that we repeat the client's
5006 * per-instance data once for each view. Since this bit is in
5007 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
5011 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
5013 /* It is possible to start a render pass with an old pipeline. Because the
5014 * render pass and subpass index are both baked into the pipeline, this is
5015 * highly unlikely. In order to do so, it requires that you have a render
5016 * pass with a single subpass and that you use that render pass twice
5017 * back-to-back and use the same pipeline at the start of the second render
5018 * pass as at the end of the first. In order to avoid unpredictable issues
5019 * with this edge case, we just dirty the pipeline at the start of every
5022 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
5024 /* Accumulate any subpass flushes that need to happen before the subpass */
5025 cmd_buffer
->state
.pending_pipe_bits
|=
5026 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
5028 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
5029 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
5031 bool is_multiview
= subpass
->view_mask
!= 0;
5033 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5034 const uint32_t a
= subpass
->attachments
[i
].attachment
;
5035 if (a
== VK_ATTACHMENT_UNUSED
)
5038 assert(a
< cmd_state
->pass
->attachment_count
);
5039 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5041 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
5042 const struct anv_image
*image
= iview
->image
;
5044 VkImageLayout target_layout
= subpass
->attachments
[i
].layout
;
5045 VkImageLayout target_stencil_layout
=
5046 subpass
->attachments
[i
].stencil_layout
;
5048 uint32_t base_layer
, layer_count
;
5049 if (image
->type
== VK_IMAGE_TYPE_3D
) {
5051 layer_count
= anv_minify(iview
->image
->extent
.depth
,
5052 iview
->planes
[0].isl
.base_level
);
5054 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
5055 layer_count
= fb
->layers
;
5058 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
5059 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5060 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5061 iview
->planes
[0].isl
.base_level
, 1,
5062 base_layer
, layer_count
,
5063 att_state
->current_layout
, target_layout
);
5064 att_state
->aux_usage
=
5065 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
5066 VK_IMAGE_ASPECT_COLOR_BIT
,
5067 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
,
5071 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5072 transition_depth_buffer(cmd_buffer
, image
,
5073 base_layer
, layer_count
,
5074 att_state
->current_layout
, target_layout
);
5075 att_state
->aux_usage
=
5076 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
5077 VK_IMAGE_ASPECT_DEPTH_BIT
,
5078 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
5082 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5083 transition_stencil_buffer(cmd_buffer
, image
,
5084 iview
->planes
[0].isl
.base_level
, 1,
5085 base_layer
, layer_count
,
5086 att_state
->current_stencil_layout
,
5087 target_stencil_layout
);
5089 att_state
->current_layout
= target_layout
;
5090 att_state
->current_stencil_layout
= target_stencil_layout
;
5092 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
5093 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5095 /* Multi-planar images are not supported as attachments */
5096 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5097 assert(image
->n_planes
== 1);
5099 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
5100 uint32_t clear_layer_count
= fb
->layers
;
5102 if (att_state
->fast_clear
&&
5103 do_first_layer_clear(cmd_state
, att_state
)) {
5104 /* We only support fast-clears on the first layer */
5105 assert(iview
->planes
[0].isl
.base_level
== 0);
5106 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
5108 union isl_color_value clear_color
= {};
5109 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
5110 if (iview
->image
->samples
== 1) {
5111 anv_image_ccs_op(cmd_buffer
, image
,
5112 iview
->planes
[0].isl
.format
,
5113 iview
->planes
[0].isl
.swizzle
,
5114 VK_IMAGE_ASPECT_COLOR_BIT
,
5115 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
5119 anv_image_mcs_op(cmd_buffer
, image
,
5120 iview
->planes
[0].isl
.format
,
5121 iview
->planes
[0].isl
.swizzle
,
5122 VK_IMAGE_ASPECT_COLOR_BIT
,
5123 0, 1, ISL_AUX_OP_FAST_CLEAR
,
5128 clear_layer_count
--;
5130 att_state
->pending_clear_views
&= ~1;
5132 if (isl_color_value_is_zero(clear_color
,
5133 iview
->planes
[0].isl
.format
)) {
5134 /* This image has the auxiliary buffer enabled. We can mark the
5135 * subresource as not needing a resolve because the clear color
5136 * will match what's in every RENDER_SURFACE_STATE object when
5137 * it's being used for sampling.
5139 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
5140 VK_IMAGE_ASPECT_COLOR_BIT
,
5141 ANV_FAST_CLEAR_DEFAULT_VALUE
);
5143 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
5144 VK_IMAGE_ASPECT_COLOR_BIT
,
5145 ANV_FAST_CLEAR_ANY
);
5149 /* From the VkFramebufferCreateInfo spec:
5151 * "If the render pass uses multiview, then layers must be one and each
5152 * attachment requires a number of layers that is greater than the
5153 * maximum bit index set in the view mask in the subpasses in which it
5156 * So if multiview is active we ignore the number of layers in the
5157 * framebuffer and instead we honor the view mask from the subpass.
5160 assert(image
->n_planes
== 1);
5161 uint32_t pending_clear_mask
=
5162 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
5165 for_each_bit(layer_idx
, pending_clear_mask
) {
5167 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
5169 anv_image_clear_color(cmd_buffer
, image
,
5170 VK_IMAGE_ASPECT_COLOR_BIT
,
5171 att_state
->aux_usage
,
5172 iview
->planes
[0].isl
.format
,
5173 iview
->planes
[0].isl
.swizzle
,
5174 iview
->planes
[0].isl
.base_level
,
5177 vk_to_isl_color(att_state
->clear_value
.color
));
5180 att_state
->pending_clear_views
&= ~pending_clear_mask
;
5181 } else if (clear_layer_count
> 0) {
5182 assert(image
->n_planes
== 1);
5183 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5184 att_state
->aux_usage
,
5185 iview
->planes
[0].isl
.format
,
5186 iview
->planes
[0].isl
.swizzle
,
5187 iview
->planes
[0].isl
.base_level
,
5188 base_clear_layer
, clear_layer_count
,
5190 vk_to_isl_color(att_state
->clear_value
.color
));
5192 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
5193 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
5194 if (att_state
->fast_clear
&& !is_multiview
) {
5195 /* We currently only support HiZ for single-LOD images */
5196 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5197 assert(isl_aux_usage_has_hiz(iview
->image
->planes
[0].aux_usage
));
5198 assert(iview
->planes
[0].isl
.base_level
== 0);
5201 anv_image_hiz_clear(cmd_buffer
, image
,
5202 att_state
->pending_clear_aspects
,
5203 iview
->planes
[0].isl
.base_level
,
5204 iview
->planes
[0].isl
.base_array_layer
,
5205 fb
->layers
, render_area
,
5206 att_state
->clear_value
.depthStencil
.stencil
);
5207 } else if (is_multiview
) {
5208 uint32_t pending_clear_mask
=
5209 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
5212 for_each_bit(layer_idx
, pending_clear_mask
) {
5214 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
5216 anv_image_clear_depth_stencil(cmd_buffer
, image
,
5217 att_state
->pending_clear_aspects
,
5218 att_state
->aux_usage
,
5219 iview
->planes
[0].isl
.base_level
,
5222 att_state
->clear_value
.depthStencil
.depth
,
5223 att_state
->clear_value
.depthStencil
.stencil
);
5226 att_state
->pending_clear_views
&= ~pending_clear_mask
;
5228 anv_image_clear_depth_stencil(cmd_buffer
, image
,
5229 att_state
->pending_clear_aspects
,
5230 att_state
->aux_usage
,
5231 iview
->planes
[0].isl
.base_level
,
5232 iview
->planes
[0].isl
.base_array_layer
,
5233 fb
->layers
, render_area
,
5234 att_state
->clear_value
.depthStencil
.depth
,
5235 att_state
->clear_value
.depthStencil
.stencil
);
5238 assert(att_state
->pending_clear_aspects
== 0);
5241 /* If multiview is enabled, then we are only done clearing when we no
5242 * longer have pending layers to clear, or when we have processed the
5243 * last subpass that uses this attachment.
5245 if (!is_multiview
||
5246 att_state
->pending_clear_views
== 0 ||
5247 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
5248 att_state
->pending_clear_aspects
= 0;
5251 att_state
->pending_load_aspects
= 0;
5254 /* We've transitioned all our images possibly fast clearing them. Now we
5255 * can fill out the surface states that we will use as render targets
5256 * during actual subpass rendering.
5258 VkResult result
= genX(cmd_buffer_alloc_att_surf_states
)(cmd_buffer
,
5260 if (result
!= VK_SUCCESS
)
5263 isl_null_fill_state(&cmd_buffer
->device
->isl_dev
,
5264 cmd_state
->null_surface_state
.map
,
5265 isl_extent3d(fb
->width
, fb
->height
, fb
->layers
));
5267 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5268 const uint32_t att
= subpass
->attachments
[i
].attachment
;
5269 if (att
== VK_ATTACHMENT_UNUSED
)
5272 assert(att
< cmd_state
->pass
->attachment_count
);
5273 struct anv_render_pass_attachment
*pass_att
= &pass
->attachments
[att
];
5274 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
5275 struct anv_image_view
*iview
= att_state
->image_view
;
5277 if (!vk_format_is_color(pass_att
->format
))
5280 const VkImageUsageFlagBits att_usage
= subpass
->attachments
[i
].usage
;
5281 assert(util_bitcount(att_usage
) == 1);
5283 struct anv_surface_state
*surface_state
;
5284 isl_surf_usage_flags_t isl_surf_usage
;
5285 enum isl_aux_usage isl_aux_usage
;
5286 if (att_usage
== VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
5287 surface_state
= &att_state
->color
;
5288 isl_surf_usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
5289 isl_aux_usage
= att_state
->aux_usage
;
5290 } else if (att_usage
== VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
) {
5291 surface_state
= &att_state
->input
;
5292 isl_surf_usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
5294 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
5295 VK_IMAGE_ASPECT_COLOR_BIT
,
5296 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
,
5297 att_state
->current_layout
);
5302 /* We had better have a surface state when we get here */
5303 assert(surface_state
->state
.map
);
5305 union isl_color_value clear_color
= { .u32
= { 0, } };
5306 if (pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
&&
5307 att_state
->fast_clear
)
5308 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
5310 anv_image_fill_surface_state(cmd_buffer
->device
,
5312 VK_IMAGE_ASPECT_COLOR_BIT
,
5313 &iview
->planes
[0].isl
,
5321 add_surface_state_relocs(cmd_buffer
, *surface_state
);
5324 pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
&&
5325 iview
->image
->planes
[0].aux_usage
!= ISL_AUX_USAGE_NONE
&&
5326 iview
->planes
[0].isl
.base_level
== 0 &&
5327 iview
->planes
[0].isl
.base_array_layer
== 0) {
5328 genX(copy_fast_clear_dwords
)(cmd_buffer
, surface_state
->state
,
5330 VK_IMAGE_ASPECT_COLOR_BIT
,
5331 false /* copy to ss */);
5336 /* The PIPE_CONTROL command description says:
5338 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
5339 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
5340 * Target Cache Flush by enabling this bit. When render target flush
5341 * is set due to new association of BTI, PS Scoreboard Stall bit must
5342 * be set in this packet."
5344 cmd_buffer
->state
.pending_pipe_bits
|=
5345 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
|
5346 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
5350 /* GEN:BUG:14010455700
5352 * ISL will change some CHICKEN registers depending on the depth surface
5353 * format, along with emitting the depth and stencil packets. In that case,
5354 * we want to do a depth flush and stall, so the pipeline is not using these
5355 * settings while we change the registers.
5357 cmd_buffer
->state
.pending_pipe_bits
|=
5358 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
|
5359 ANV_PIPE_DEPTH_STALL_BIT
|
5360 ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
5361 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5364 cmd_buffer_emit_depth_stencil(cmd_buffer
);
5367 static enum blorp_filter
5368 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
5371 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
5372 return BLORP_FILTER_SAMPLE_0
;
5373 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
5374 return BLORP_FILTER_AVERAGE
;
5375 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
5376 return BLORP_FILTER_MIN_SAMPLE
;
5377 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
5378 return BLORP_FILTER_MAX_SAMPLE
;
5380 return BLORP_FILTER_NONE
;
5385 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
5387 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5388 struct anv_subpass
*subpass
= cmd_state
->subpass
;
5389 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
5390 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
5392 /* We are done with the previous subpass and all rendering directly to that
5393 * subpass is now complete. Zero out all the surface states so we don't
5394 * accidentally use them between now and the next subpass.
5396 for (uint32_t i
= 0; i
< cmd_state
->pass
->attachment_count
; ++i
) {
5397 memset(&cmd_state
->attachments
[i
].color
, 0,
5398 sizeof(cmd_state
->attachments
[i
].color
));
5399 memset(&cmd_state
->attachments
[i
].input
, 0,
5400 sizeof(cmd_state
->attachments
[i
].input
));
5402 cmd_state
->null_surface_state
= ANV_STATE_NULL
;
5403 cmd_state
->attachment_states
= ANV_STATE_NULL
;
5405 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5406 const uint32_t a
= subpass
->attachments
[i
].attachment
;
5407 if (a
== VK_ATTACHMENT_UNUSED
)
5410 assert(a
< cmd_state
->pass
->attachment_count
);
5411 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5412 struct anv_image_view
*iview
= att_state
->image_view
;
5414 assert(util_bitcount(subpass
->attachments
[i
].usage
) == 1);
5415 if (subpass
->attachments
[i
].usage
==
5416 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
5417 /* We assume that if we're ending a subpass, we did do some rendering
5418 * so we may end up with compressed data.
5420 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
5421 VK_IMAGE_ASPECT_COLOR_BIT
,
5422 att_state
->aux_usage
,
5423 iview
->planes
[0].isl
.base_level
,
5424 iview
->planes
[0].isl
.base_array_layer
,
5426 } else if (subpass
->attachments
[i
].usage
==
5427 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
5428 /* We may be writing depth or stencil so we need to mark the surface.
5429 * Unfortunately, there's no way to know at this point whether the
5430 * depth or stencil tests used will actually write to the surface.
5432 * Even though stencil may be plane 1, it always shares a base_level
5435 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
5436 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5437 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
5438 VK_IMAGE_ASPECT_DEPTH_BIT
,
5439 att_state
->aux_usage
,
5440 ds_view
->base_level
,
5441 ds_view
->base_array_layer
,
5444 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5445 /* Even though stencil may be plane 1, it always shares a
5446 * base_level with depth.
5448 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
5449 VK_IMAGE_ASPECT_STENCIL_BIT
,
5451 ds_view
->base_level
,
5452 ds_view
->base_array_layer
,
5458 if (subpass
->has_color_resolve
) {
5459 /* We are about to do some MSAA resolves. We need to flush so that the
5460 * result of writes to the MSAA color attachments show up in the sampler
5461 * when we blit to the single-sampled resolve target.
5463 cmd_buffer
->state
.pending_pipe_bits
|=
5464 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
5465 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
5467 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
5468 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
5469 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
5471 if (dst_att
== VK_ATTACHMENT_UNUSED
)
5474 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
5475 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
5477 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
5478 /* From the Vulkan 1.0 spec:
5480 * If the first use of an attachment in a render pass is as a
5481 * resolve attachment, then the loadOp is effectively ignored
5482 * as the resolve is guaranteed to overwrite all pixels in the
5485 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
5488 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
5489 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
5491 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
5493 enum isl_aux_usage src_aux_usage
=
5494 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
5495 enum isl_aux_usage dst_aux_usage
=
5496 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
5498 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
5499 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
5501 anv_image_msaa_resolve(cmd_buffer
,
5502 src_iview
->image
, src_aux_usage
,
5503 src_iview
->planes
[0].isl
.base_level
,
5504 src_iview
->planes
[0].isl
.base_array_layer
,
5505 dst_iview
->image
, dst_aux_usage
,
5506 dst_iview
->planes
[0].isl
.base_level
,
5507 dst_iview
->planes
[0].isl
.base_array_layer
,
5508 VK_IMAGE_ASPECT_COLOR_BIT
,
5509 render_area
.offset
.x
, render_area
.offset
.y
,
5510 render_area
.offset
.x
, render_area
.offset
.y
,
5511 render_area
.extent
.width
,
5512 render_area
.extent
.height
,
5513 fb
->layers
, BLORP_FILTER_NONE
);
5517 if (subpass
->ds_resolve_attachment
) {
5518 /* We are about to do some MSAA resolves. We need to flush so that the
5519 * result of writes to the MSAA depth attachments show up in the sampler
5520 * when we blit to the single-sampled resolve target.
5522 cmd_buffer
->state
.pending_pipe_bits
|=
5523 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
5524 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
5526 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
5527 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
5529 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
5530 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
5532 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
5533 /* From the Vulkan 1.0 spec:
5535 * If the first use of an attachment in a render pass is as a
5536 * resolve attachment, then the loadOp is effectively ignored
5537 * as the resolve is guaranteed to overwrite all pixels in the
5540 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
5543 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
5544 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
5546 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
5548 struct anv_attachment_state
*src_state
=
5549 &cmd_state
->attachments
[src_att
];
5550 struct anv_attachment_state
*dst_state
=
5551 &cmd_state
->attachments
[dst_att
];
5553 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
5554 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
5556 /* MSAA resolves sample from the source attachment. Transition the
5557 * depth attachment first to get rid of any HiZ that we may not be
5560 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
5561 src_iview
->planes
[0].isl
.base_array_layer
,
5563 src_state
->current_layout
,
5564 VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
);
5565 src_state
->aux_usage
=
5566 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
5567 VK_IMAGE_ASPECT_DEPTH_BIT
,
5568 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
,
5569 VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
);
5570 src_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
;
5572 /* MSAA resolves write to the resolve attachment as if it were any
5573 * other transfer op. Transition the resolve attachment accordingly.
5575 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
5577 /* If our render area is the entire size of the image, we're going to
5578 * blow it all away so we can claim the initial layout is UNDEFINED
5579 * and we'll get a HiZ ambiguate instead of a resolve.
5581 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
5582 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
5583 render_area
.extent
.width
== dst_iview
->extent
.width
&&
5584 render_area
.extent
.height
== dst_iview
->extent
.height
)
5585 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
5587 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
5588 dst_iview
->planes
[0].isl
.base_array_layer
,
5591 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
5592 dst_state
->aux_usage
=
5593 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
5594 VK_IMAGE_ASPECT_DEPTH_BIT
,
5595 VK_IMAGE_USAGE_TRANSFER_DST_BIT
,
5596 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
5597 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
5599 enum blorp_filter filter
=
5600 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
5602 anv_image_msaa_resolve(cmd_buffer
,
5603 src_iview
->image
, src_state
->aux_usage
,
5604 src_iview
->planes
[0].isl
.base_level
,
5605 src_iview
->planes
[0].isl
.base_array_layer
,
5606 dst_iview
->image
, dst_state
->aux_usage
,
5607 dst_iview
->planes
[0].isl
.base_level
,
5608 dst_iview
->planes
[0].isl
.base_array_layer
,
5609 VK_IMAGE_ASPECT_DEPTH_BIT
,
5610 render_area
.offset
.x
, render_area
.offset
.y
,
5611 render_area
.offset
.x
, render_area
.offset
.y
,
5612 render_area
.extent
.width
,
5613 render_area
.extent
.height
,
5614 fb
->layers
, filter
);
5617 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
5618 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
5620 src_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
;
5621 dst_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
5623 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
5624 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
5626 enum blorp_filter filter
=
5627 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
5629 anv_image_msaa_resolve(cmd_buffer
,
5630 src_iview
->image
, src_aux_usage
,
5631 src_iview
->planes
[0].isl
.base_level
,
5632 src_iview
->planes
[0].isl
.base_array_layer
,
5633 dst_iview
->image
, dst_aux_usage
,
5634 dst_iview
->planes
[0].isl
.base_level
,
5635 dst_iview
->planes
[0].isl
.base_array_layer
,
5636 VK_IMAGE_ASPECT_STENCIL_BIT
,
5637 render_area
.offset
.x
, render_area
.offset
.y
,
5638 render_area
.offset
.x
, render_area
.offset
.y
,
5639 render_area
.extent
.width
,
5640 render_area
.extent
.height
,
5641 fb
->layers
, filter
);
5646 /* On gen7, we have to store a texturable version of the stencil buffer in
5647 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
5648 * forth at strategic points. Stencil writes are only allowed in following
5651 * - VK_IMAGE_LAYOUT_GENERAL
5652 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
5653 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
5654 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
5655 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
5657 * For general, we have no nice opportunity to transition so we do the copy
5658 * to the shadow unconditionally at the end of the subpass. For transfer
5659 * destinations, we can update it as part of the transfer op. For the other
5660 * layouts, we delay the copy until a transition into some other layout.
5662 if (subpass
->depth_stencil_attachment
) {
5663 uint32_t a
= subpass
->depth_stencil_attachment
->attachment
;
5664 assert(a
!= VK_ATTACHMENT_UNUSED
);
5666 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5667 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;;
5668 const struct anv_image
*image
= iview
->image
;
5670 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5671 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
5672 VK_IMAGE_ASPECT_STENCIL_BIT
);
5674 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
5675 att_state
->current_stencil_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
5676 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
5677 anv_image_copy_to_shadow(cmd_buffer
, image
,
5678 VK_IMAGE_ASPECT_STENCIL_BIT
,
5679 iview
->planes
[plane
].isl
.base_level
, 1,
5680 iview
->planes
[plane
].isl
.base_array_layer
,
5685 #endif /* GEN_GEN == 7 */
5687 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5688 const uint32_t a
= subpass
->attachments
[i
].attachment
;
5689 if (a
== VK_ATTACHMENT_UNUSED
)
5692 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
5695 assert(a
< cmd_state
->pass
->attachment_count
);
5696 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5697 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
5698 const struct anv_image
*image
= iview
->image
;
5700 /* Transition the image into the final layout for this render pass */
5701 VkImageLayout target_layout
=
5702 cmd_state
->pass
->attachments
[a
].final_layout
;
5703 VkImageLayout target_stencil_layout
=
5704 cmd_state
->pass
->attachments
[a
].stencil_final_layout
;
5706 uint32_t base_layer
, layer_count
;
5707 if (image
->type
== VK_IMAGE_TYPE_3D
) {
5709 layer_count
= anv_minify(iview
->image
->extent
.depth
,
5710 iview
->planes
[0].isl
.base_level
);
5712 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
5713 layer_count
= fb
->layers
;
5716 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
5717 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5718 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5719 iview
->planes
[0].isl
.base_level
, 1,
5720 base_layer
, layer_count
,
5721 att_state
->current_layout
, target_layout
);
5724 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5725 transition_depth_buffer(cmd_buffer
, image
,
5726 base_layer
, layer_count
,
5727 att_state
->current_layout
, target_layout
);
5730 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5731 transition_stencil_buffer(cmd_buffer
, image
,
5732 iview
->planes
[0].isl
.base_level
, 1,
5733 base_layer
, layer_count
,
5734 att_state
->current_stencil_layout
,
5735 target_stencil_layout
);
5739 /* Accumulate any subpass flushes that need to happen after the subpass.
5740 * Yes, they do get accumulated twice in the NextSubpass case but since
5741 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
5742 * ORing the bits in twice so it's harmless.
5744 cmd_buffer
->state
.pending_pipe_bits
|=
5745 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
5748 void genX(CmdBeginRenderPass
)(
5749 VkCommandBuffer commandBuffer
,
5750 const VkRenderPassBeginInfo
* pRenderPassBegin
,
5751 VkSubpassContents contents
)
5753 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5754 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
5755 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
5758 cmd_buffer
->state
.framebuffer
= framebuffer
;
5759 cmd_buffer
->state
.pass
= pass
;
5760 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
5762 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
,
5765 if (result
!= VK_SUCCESS
) {
5766 assert(anv_batch_has_error(&cmd_buffer
->batch
));
5770 genX(flush_pipeline_select_3d
)(cmd_buffer
);
5772 cmd_buffer_begin_subpass(cmd_buffer
, 0);
5775 void genX(CmdBeginRenderPass2
)(
5776 VkCommandBuffer commandBuffer
,
5777 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
5778 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
5780 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
5781 pSubpassBeginInfo
->contents
);
5784 void genX(CmdNextSubpass
)(
5785 VkCommandBuffer commandBuffer
,
5786 VkSubpassContents contents
)
5788 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5790 if (anv_batch_has_error(&cmd_buffer
->batch
))
5793 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
5795 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
5796 cmd_buffer_end_subpass(cmd_buffer
);
5797 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
5800 void genX(CmdNextSubpass2
)(
5801 VkCommandBuffer commandBuffer
,
5802 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
5803 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5805 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
5808 void genX(CmdEndRenderPass
)(
5809 VkCommandBuffer commandBuffer
)
5811 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5813 if (anv_batch_has_error(&cmd_buffer
->batch
))
5816 cmd_buffer_end_subpass(cmd_buffer
);
5818 cmd_buffer
->state
.hiz_enabled
= false;
5821 anv_dump_add_attachments(cmd_buffer
);
5824 /* Remove references to render pass specific state. This enables us to
5825 * detect whether or not we're in a renderpass.
5827 cmd_buffer
->state
.framebuffer
= NULL
;
5828 cmd_buffer
->state
.pass
= NULL
;
5829 cmd_buffer
->state
.subpass
= NULL
;
5832 void genX(CmdEndRenderPass2
)(
5833 VkCommandBuffer commandBuffer
,
5834 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5836 genX(CmdEndRenderPass
)(commandBuffer
);
5840 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
5842 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5843 struct gen_mi_builder b
;
5844 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5846 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
5847 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
5848 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
5850 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
5851 mip
.LoadOperation
= LOAD_LOADINV
;
5852 mip
.CombineOperation
= COMBINE_SET
;
5853 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
5858 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5859 void genX(CmdBeginConditionalRenderingEXT
)(
5860 VkCommandBuffer commandBuffer
,
5861 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5863 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5864 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5865 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5866 struct anv_address value_address
=
5867 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
5869 const bool isInverted
= pConditionalRenderingBegin
->flags
&
5870 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
5872 cmd_state
->conditional_render_enabled
= true;
5874 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5876 struct gen_mi_builder b
;
5877 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5879 /* Section 19.4 of the Vulkan 1.1.85 spec says:
5881 * If the value of the predicate in buffer memory changes
5882 * while conditional rendering is active, the rendering commands
5883 * may be discarded in an implementation-dependent way.
5884 * Some implementations may latch the value of the predicate
5885 * upon beginning conditional rendering while others
5886 * may read it before every rendering command.
5888 * So it's perfectly fine to read a value from the buffer once.
5890 struct gen_mi_value value
= gen_mi_mem32(value_address
);
5892 /* Precompute predicate result, it is necessary to support secondary
5893 * command buffers since it is unknown if conditional rendering is
5894 * inverted when populating them.
5896 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
5897 isInverted
? gen_mi_uge(&b
, gen_mi_imm(0), value
) :
5898 gen_mi_ult(&b
, gen_mi_imm(0), value
));
5901 void genX(CmdEndConditionalRenderingEXT
)(
5902 VkCommandBuffer commandBuffer
)
5904 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5905 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5907 cmd_state
->conditional_render_enabled
= false;
5911 /* Set of stage bits for which are pipelined, i.e. they get queued by the
5912 * command streamer for later execution.
5914 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
5915 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
5916 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
5917 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
5918 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
5919 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
5920 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
5921 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
5922 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
5923 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
5924 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
5925 VK_PIPELINE_STAGE_TRANSFER_BIT | \
5926 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
5927 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
5928 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
5930 void genX(CmdSetEvent
)(
5931 VkCommandBuffer commandBuffer
,
5933 VkPipelineStageFlags stageMask
)
5935 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5936 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5938 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
5939 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5941 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5942 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5943 pc
.StallAtPixelScoreboard
= true;
5944 pc
.CommandStreamerStallEnable
= true;
5947 pc
.DestinationAddressType
= DAT_PPGTT
,
5948 pc
.PostSyncOperation
= WriteImmediateData
,
5949 pc
.Address
= (struct anv_address
) {
5950 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5953 pc
.ImmediateData
= VK_EVENT_SET
;
5957 void genX(CmdResetEvent
)(
5958 VkCommandBuffer commandBuffer
,
5960 VkPipelineStageFlags stageMask
)
5962 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5963 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5965 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
5966 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5968 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5969 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5970 pc
.StallAtPixelScoreboard
= true;
5971 pc
.CommandStreamerStallEnable
= true;
5974 pc
.DestinationAddressType
= DAT_PPGTT
;
5975 pc
.PostSyncOperation
= WriteImmediateData
;
5976 pc
.Address
= (struct anv_address
) {
5977 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5980 pc
.ImmediateData
= VK_EVENT_RESET
;
5984 void genX(CmdWaitEvents
)(
5985 VkCommandBuffer commandBuffer
,
5986 uint32_t eventCount
,
5987 const VkEvent
* pEvents
,
5988 VkPipelineStageFlags srcStageMask
,
5989 VkPipelineStageFlags destStageMask
,
5990 uint32_t memoryBarrierCount
,
5991 const VkMemoryBarrier
* pMemoryBarriers
,
5992 uint32_t bufferMemoryBarrierCount
,
5993 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5994 uint32_t imageMemoryBarrierCount
,
5995 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5998 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6000 for (uint32_t i
= 0; i
< eventCount
; i
++) {
6001 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
6003 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
6004 sem
.WaitMode
= PollingMode
,
6005 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
6006 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
6007 sem
.SemaphoreAddress
= (struct anv_address
) {
6008 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
6014 anv_finishme("Implement events on gen7");
6017 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
6018 false, /* byRegion */
6019 memoryBarrierCount
, pMemoryBarriers
,
6020 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
6021 imageMemoryBarrierCount
, pImageMemoryBarriers
);
6024 VkResult
genX(CmdSetPerformanceOverrideINTEL
)(
6025 VkCommandBuffer commandBuffer
,
6026 const VkPerformanceOverrideInfoINTEL
* pOverrideInfo
)
6028 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6030 switch (pOverrideInfo
->type
) {
6031 case VK_PERFORMANCE_OVERRIDE_TYPE_NULL_HARDWARE_INTEL
: {
6035 anv_pack_struct(&dw
, GENX(CS_DEBUG_MODE2
),
6036 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
6037 .MediaInstructionDisable
= pOverrideInfo
->enable
,
6038 ._3DRenderingInstructionDisableMask
= true,
6039 .MediaInstructionDisableMask
= true);
6040 emit_lri(&cmd_buffer
->batch
, GENX(CS_DEBUG_MODE2_num
), dw
);
6042 anv_pack_struct(&dw
, GENX(INSTPM
),
6043 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
6044 .MediaInstructionDisable
= pOverrideInfo
->enable
,
6045 ._3DRenderingInstructionDisableMask
= true,
6046 .MediaInstructionDisableMask
= true);
6047 emit_lri(&cmd_buffer
->batch
, GENX(INSTPM_num
), dw
);
6052 case VK_PERFORMANCE_OVERRIDE_TYPE_FLUSH_GPU_CACHES_INTEL
:
6053 if (pOverrideInfo
->enable
) {
6054 /* FLUSH ALL THE THINGS! As requested by the MDAPI team. */
6055 cmd_buffer
->state
.pending_pipe_bits
|=
6056 ANV_PIPE_FLUSH_BITS
|
6057 ANV_PIPE_INVALIDATE_BITS
;
6058 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
6063 unreachable("Invalid override");
6069 VkResult
genX(CmdSetPerformanceStreamMarkerINTEL
)(
6070 VkCommandBuffer commandBuffer
,
6071 const VkPerformanceStreamMarkerInfoINTEL
* pMarkerInfo
)
6073 /* TODO: Waiting on the register to write, might depend on generation. */