2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
31 #include "common/gen_l3_config.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
36 emit_lrm(struct anv_batch
*batch
,
37 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
39 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
40 lrm
.RegisterAddress
= reg
;
41 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
46 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
48 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
49 lri
.RegisterOffset
= reg
;
54 #if GEN_IS_HASWELL || GEN_GEN >= 8
56 emit_lrr(struct anv_batch
*batch
, uint32_t dst
, uint32_t src
)
58 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
59 lrr
.SourceRegisterAddress
= src
;
60 lrr
.DestinationRegisterAddress
= dst
;
66 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
68 struct anv_device
*device
= cmd_buffer
->device
;
70 /* If we are emitting a new state base address we probably need to re-emit
73 cmd_buffer
->state
.descriptors_dirty
|= ~0;
75 /* Emit a render target cache flush.
77 * This isn't documented anywhere in the PRM. However, it seems to be
78 * necessary prior to changing the surface state base adress. Without
79 * this, we get GPU hangs when using multi-level command buffers which
80 * clear depth, reset state base address, and then go render stuff.
82 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
83 pc
.DCFlushEnable
= true;
84 pc
.RenderTargetCacheFlushEnable
= true;
85 pc
.CommandStreamerStallEnable
= true;
88 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
89 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
90 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
91 sba
.GeneralStateBaseAddressModifyEnable
= true;
93 sba
.SurfaceStateBaseAddress
=
94 anv_cmd_buffer_surface_base_address(cmd_buffer
);
95 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
96 sba
.SurfaceStateBaseAddressModifyEnable
= true;
98 sba
.DynamicStateBaseAddress
=
99 (struct anv_address
) { &device
->dynamic_state_pool
.block_pool
.bo
, 0 };
100 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
101 sba
.DynamicStateBaseAddressModifyEnable
= true;
103 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
104 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
105 sba
.IndirectObjectBaseAddressModifyEnable
= true;
107 sba
.InstructionBaseAddress
=
108 (struct anv_address
) { &device
->instruction_state_pool
.block_pool
.bo
, 0 };
109 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
110 sba
.InstructionBaseAddressModifyEnable
= true;
113 /* Broadwell requires that we specify a buffer size for a bunch of
114 * these fields. However, since we will be growing the BO's live, we
115 * just set them all to the maximum.
117 sba
.GeneralStateBufferSize
= 0xfffff;
118 sba
.GeneralStateBufferSizeModifyEnable
= true;
119 sba
.DynamicStateBufferSize
= 0xfffff;
120 sba
.DynamicStateBufferSizeModifyEnable
= true;
121 sba
.IndirectObjectBufferSize
= 0xfffff;
122 sba
.IndirectObjectBufferSizeModifyEnable
= true;
123 sba
.InstructionBufferSize
= 0xfffff;
124 sba
.InstructionBuffersizeModifyEnable
= true;
128 /* After re-setting the surface state base address, we have to do some
129 * cache flusing so that the sampler engine will pick up the new
130 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
131 * Shared Function > 3D Sampler > State > State Caching (page 96):
133 * Coherency with system memory in the state cache, like the texture
134 * cache is handled partially by software. It is expected that the
135 * command stream or shader will issue Cache Flush operation or
136 * Cache_Flush sampler message to ensure that the L1 cache remains
137 * coherent with system memory.
141 * Whenever the value of the Dynamic_State_Base_Addr,
142 * Surface_State_Base_Addr are altered, the L1 state cache must be
143 * invalidated to ensure the new surface or sampler state is fetched
144 * from system memory.
146 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
147 * which, according the PIPE_CONTROL instruction documentation in the
150 * Setting this bit is independent of any other bit in this packet.
151 * This bit controls the invalidation of the L1 and L2 state caches
152 * at the top of the pipe i.e. at the parsing time.
154 * Unfortunately, experimentation seems to indicate that state cache
155 * invalidation through a PIPE_CONTROL does nothing whatsoever in
156 * regards to surface state and binding tables. In stead, it seems that
157 * invalidating the texture cache is what is actually needed.
159 * XXX: As far as we have been able to determine through
160 * experimentation, shows that flush the texture cache appears to be
161 * sufficient. The theory here is that all of the sampling/rendering
162 * units cache the binding table in the texture cache. However, we have
163 * yet to be able to actually confirm this.
165 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
166 pc
.TextureCacheInvalidationEnable
= true;
167 pc
.ConstantCacheInvalidationEnable
= true;
168 pc
.StateCacheInvalidationEnable
= true;
173 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
174 struct anv_state state
, struct anv_address addr
)
176 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
179 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
180 state
.offset
+ isl_dev
->ss
.addr_offset
,
181 addr
.bo
, addr
.offset
);
182 if (result
!= VK_SUCCESS
)
183 anv_batch_set_error(&cmd_buffer
->batch
, result
);
187 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
188 struct anv_surface_state state
)
190 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
192 assert(!anv_address_is_null(state
.address
));
193 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
195 if (!anv_address_is_null(state
.aux_address
)) {
197 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
198 &cmd_buffer
->pool
->alloc
,
199 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
200 state
.aux_address
.bo
, state
.aux_address
.offset
);
201 if (result
!= VK_SUCCESS
)
202 anv_batch_set_error(&cmd_buffer
->batch
, result
);
205 if (!anv_address_is_null(state
.clear_address
)) {
207 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
208 &cmd_buffer
->pool
->alloc
,
210 isl_dev
->ss
.clear_color_state_offset
,
211 state
.clear_address
.bo
, state
.clear_address
.offset
);
212 if (result
!= VK_SUCCESS
)
213 anv_batch_set_error(&cmd_buffer
->batch
, result
);
218 color_attachment_compute_aux_usage(struct anv_device
* device
,
219 struct anv_cmd_state
* cmd_state
,
220 uint32_t att
, VkRect2D render_area
,
221 union isl_color_value
*fast_clear_color
)
223 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
224 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
226 assert(iview
->n_planes
== 1);
228 if (iview
->planes
[0].isl
.base_array_layer
>=
229 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
230 iview
->planes
[0].isl
.base_level
)) {
231 /* There is no aux buffer which corresponds to the level and layer(s)
234 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
235 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
236 att_state
->fast_clear
= false;
240 att_state
->aux_usage
=
241 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
242 VK_IMAGE_ASPECT_COLOR_BIT
,
243 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
245 /* If we don't have aux, then we should have returned early in the layer
246 * check above. If we got here, we must have something.
248 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
250 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
251 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
252 att_state
->input_aux_usage
= att_state
->aux_usage
;
254 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
256 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
257 * setting is only allowed if Surface Format supported for Fast
258 * Clear. In addition, if the surface is bound to the sampling
259 * engine, Surface Format must be supported for Render Target
260 * Compression for surfaces bound to the sampling engine."
262 * In other words, we can only sample from a fast-cleared image if it
263 * also supports color compression.
265 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
266 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
268 /* While fast-clear resolves and partial resolves are fairly cheap in the
269 * case where you render to most of the pixels, full resolves are not
270 * because they potentially involve reading and writing the entire
271 * framebuffer. If we can't texture with CCS_E, we should leave it off and
272 * limit ourselves to fast clears.
274 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
275 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
276 anv_perf_warn(device
->instance
, iview
->image
,
277 "Not temporarily enabling CCS_E.");
280 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
284 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
285 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
287 union isl_color_value clear_color
= {};
288 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
290 att_state
->clear_color_is_zero_one
=
291 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
292 att_state
->clear_color_is_zero
=
293 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
295 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
296 /* Start by getting the fast clear type. We use the first subpass
297 * layout here because we don't want to fast-clear if the first subpass
298 * to use the attachment can't handle fast-clears.
300 enum anv_fast_clear_type fast_clear_type
=
301 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
302 VK_IMAGE_ASPECT_COLOR_BIT
,
303 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
304 switch (fast_clear_type
) {
305 case ANV_FAST_CLEAR_NONE
:
306 att_state
->fast_clear
= false;
308 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
309 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
311 case ANV_FAST_CLEAR_ANY
:
312 att_state
->fast_clear
= true;
316 /* Potentially, we could do partial fast-clears but doing so has crazy
317 * alignment restrictions. It's easier to just restrict to full size
318 * fast clears for now.
320 if (render_area
.offset
.x
!= 0 ||
321 render_area
.offset
.y
!= 0 ||
322 render_area
.extent
.width
!= iview
->extent
.width
||
323 render_area
.extent
.height
!= iview
->extent
.height
)
324 att_state
->fast_clear
= false;
326 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
327 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
328 att_state
->fast_clear
= false;
330 /* We only allow fast clears to the first slice of an image (level 0,
331 * layer 0) and only for the entire slice. This guarantees us that, at
332 * any given time, there is only one clear color on any given image at
333 * any given time. At the time of our testing (Jan 17, 2018), there
334 * were no known applications which would benefit from fast-clearing
335 * more than just the first slice.
337 if (att_state
->fast_clear
&&
338 (iview
->planes
[0].isl
.base_level
> 0 ||
339 iview
->planes
[0].isl
.base_array_layer
> 0)) {
340 anv_perf_warn(device
->instance
, iview
->image
,
341 "Rendering with multi-lod or multi-layer framebuffer "
342 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
343 "baseArrayLayer > 0. Not fast clearing.");
344 att_state
->fast_clear
= false;
345 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
346 anv_perf_warn(device
->instance
, iview
->image
,
347 "Rendering to a multi-layer framebuffer with "
348 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
351 if (att_state
->fast_clear
)
352 *fast_clear_color
= clear_color
;
354 att_state
->fast_clear
= false;
359 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
360 struct anv_cmd_state
*cmd_state
,
361 uint32_t att
, VkRect2D render_area
)
363 struct anv_render_pass_attachment
*pass_att
=
364 &cmd_state
->pass
->attachments
[att
];
365 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
366 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
368 /* These will be initialized after the first subpass transition. */
369 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
370 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
373 /* We don't do any HiZ or depth fast-clears on gen7 yet */
374 att_state
->fast_clear
= false;
378 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
379 /* If we're just clearing stencil, we can always HiZ clear */
380 att_state
->fast_clear
= true;
384 /* Default to false for now */
385 att_state
->fast_clear
= false;
387 /* We must have depth in order to have HiZ */
388 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
391 const enum isl_aux_usage first_subpass_aux_usage
=
392 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
393 VK_IMAGE_ASPECT_DEPTH_BIT
,
394 pass_att
->first_subpass_layout
);
395 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
398 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
399 iview
->planes
[0].isl
.format
,
400 iview
->image
->samples
,
401 render_area
.offset
.x
,
402 render_area
.offset
.y
,
403 render_area
.offset
.x
+
404 render_area
.extent
.width
,
405 render_area
.offset
.y
+
406 render_area
.extent
.height
))
409 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
412 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
413 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
414 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
415 * only supports returning 0.0f. Gens prior to gen8 do not support this
421 /* If we got here, then we can fast clear */
422 att_state
->fast_clear
= true;
426 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
428 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
431 /* We only allocate input attachment states for color surfaces. Compression
432 * is not yet enabled for depth textures and stencil doesn't allow
433 * compression so we can just use the texture surface state from the view.
435 return vk_format_is_color(att
->format
);
438 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
439 * the initial layout is undefined, the HiZ buffer and depth buffer will
440 * represent the same data at the end of this operation.
443 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
444 const struct anv_image
*image
,
445 VkImageLayout initial_layout
,
446 VkImageLayout final_layout
)
448 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
449 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
450 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
451 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
452 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
453 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
455 enum isl_aux_op hiz_op
;
456 if (hiz_enabled
&& !enable_hiz
) {
457 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
458 } else if (!hiz_enabled
&& enable_hiz
) {
459 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
461 assert(hiz_enabled
== enable_hiz
);
462 /* If the same buffer will be used, no resolves are necessary. */
463 hiz_op
= ISL_AUX_OP_NONE
;
466 if (hiz_op
!= ISL_AUX_OP_NONE
)
467 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
471 #define MI_PREDICATE_SRC0 0x2400
472 #define MI_PREDICATE_SRC1 0x2408
475 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
476 const struct anv_image
*image
,
477 VkImageAspectFlagBits aspect
,
479 uint32_t base_layer
, uint32_t layer_count
,
482 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
484 /* We only have compression tracking for CCS_E */
485 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
488 for (uint32_t a
= 0; a
< layer_count
; a
++) {
489 uint32_t layer
= base_layer
+ a
;
490 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
491 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
494 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
500 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
501 const struct anv_image
*image
,
502 VkImageAspectFlagBits aspect
,
503 enum anv_fast_clear_type fast_clear
)
505 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
506 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
508 sdi
.ImmediateData
= fast_clear
;
511 /* Whenever we have fast-clear, we consider that slice to be compressed.
512 * This makes building predicates much easier.
514 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
515 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
518 #if GEN_IS_HASWELL || GEN_GEN >= 8
519 static inline uint32_t
520 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
522 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
524 .Operand1
= operand1
,
525 .Operand2
= operand2
,
529 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
535 #define CS_GPR(n) (0x2600 + (n) * 8)
537 /* This is only really practical on haswell and above because it requires
538 * MI math in order to get it correct.
540 #if GEN_GEN >= 8 || GEN_IS_HASWELL
542 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
543 const struct anv_image
*image
,
544 VkImageAspectFlagBits aspect
,
545 uint32_t level
, uint32_t array_layer
,
546 enum isl_aux_op resolve_op
,
547 enum anv_fast_clear_type fast_clear_supported
)
549 struct anv_address fast_clear_type_addr
=
550 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
552 /* Name some registers */
553 const int image_fc_reg
= MI_ALU_REG0
;
554 const int fc_imm_reg
= MI_ALU_REG1
;
555 const int pred_reg
= MI_ALU_REG2
;
559 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
560 /* In this case, we're doing a full resolve which means we want the
561 * resolve to happen if any compression (including fast-clears) is
564 * In order to simplify the logic a bit, we make the assumption that,
565 * if the first slice has been fast-cleared, it is also marked as
566 * compressed. See also set_image_fast_clear_state.
568 struct anv_address compression_state_addr
=
569 anv_image_get_compression_state_addr(cmd_buffer
->device
, image
,
570 aspect
, level
, array_layer
);
571 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
572 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
573 lrm
.MemoryAddress
= compression_state_addr
;
575 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
576 sdi
.Address
= compression_state_addr
;
577 sdi
.ImmediateData
= 0;
580 if (level
== 0 && array_layer
== 0) {
581 /* If the predicate is true, we want to write 0 to the fast clear type
582 * and, if it's false, leave it alone. We can do this by writing
584 * clear_type = clear_type & ~predicate;
586 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
587 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
588 lrm
.MemoryAddress
= fast_clear_type_addr
;
590 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
591 lrr
.DestinationRegisterAddress
= CS_GPR(pred_reg
);
592 lrr
.SourceRegisterAddress
= MI_PREDICATE_SRC0
;
595 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
596 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
597 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
598 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
599 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
601 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
602 srm
.MemoryAddress
= fast_clear_type_addr
;
603 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
606 } else if (level
== 0 && array_layer
== 0) {
607 /* In this case, we are doing a partial resolve to get rid of fast-clear
608 * colors. We don't care about the compression state but we do care
609 * about how much fast clear is allowed by the final layout.
611 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
612 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
614 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
615 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
616 lrm
.MemoryAddress
= fast_clear_type_addr
;
618 emit_lri(&cmd_buffer
->batch
, CS_GPR(image_fc_reg
) + 4, 0);
620 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
), fast_clear_supported
);
621 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
) + 4, 0);
623 /* We need to compute (fast_clear_supported < image->fast_clear).
624 * We do this by subtracting and storing the carry bit.
626 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
627 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, fc_imm_reg
);
628 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, image_fc_reg
);
629 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
630 dw
[4] = mi_alu(MI_ALU_STORE
, pred_reg
, MI_ALU_CF
);
632 /* Store the predicate */
633 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(pred_reg
));
635 /* If the predicate is true, we want to write 0 to the fast clear type
636 * and, if it's false, leave it alone. We can do this by writing
638 * clear_type = clear_type & ~predicate;
640 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
641 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
642 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
643 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
644 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
646 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
647 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
648 srm
.MemoryAddress
= fast_clear_type_addr
;
651 /* In this case, we're trying to do a partial resolve on a slice that
652 * doesn't have clear color. There's nothing to do.
654 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
658 /* We use the first half of src0 for the actual predicate. Set the second
659 * half of src0 and all of src1 to 0 as the predicate operation will be
660 * doing an implicit src0 != src1.
662 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
663 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
664 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
666 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
667 mip
.LoadOperation
= LOAD_LOADINV
;
668 mip
.CombineOperation
= COMBINE_SET
;
669 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
672 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
676 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
677 const struct anv_image
*image
,
678 VkImageAspectFlagBits aspect
,
679 uint32_t level
, uint32_t array_layer
,
680 enum isl_aux_op resolve_op
,
681 enum anv_fast_clear_type fast_clear_supported
)
683 struct anv_address fast_clear_type_addr
=
684 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
686 /* This only works for partial resolves and only when the clear color is
687 * all or nothing. On the upside, this emits less command streamer code
688 * and works on Ivybridge and Bay Trail.
690 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
691 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
693 /* We don't support fast clears on anything other than the first slice. */
694 if (level
> 0 || array_layer
> 0)
697 /* On gen8, we don't have a concept of default clear colors because we
698 * can't sample from CCS surfaces. It's enough to just load the fast clear
699 * state into the predicate register.
701 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
702 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
703 lrm
.MemoryAddress
= fast_clear_type_addr
;
705 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
706 sdi
.Address
= fast_clear_type_addr
;
707 sdi
.ImmediateData
= 0;
710 /* We use the first half of src0 for the actual predicate. Set the second
711 * half of src0 and all of src1 to 0 as the predicate operation will be
712 * doing an implicit src0 != src1.
714 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
715 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
716 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
718 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
719 mip
.LoadOperation
= LOAD_LOADINV
;
720 mip
.CombineOperation
= COMBINE_SET
;
721 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
724 #endif /* GEN_GEN <= 8 */
727 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
728 const struct anv_image
*image
,
729 VkImageAspectFlagBits aspect
,
730 uint32_t level
, uint32_t array_layer
,
731 enum isl_aux_op resolve_op
,
732 enum anv_fast_clear_type fast_clear_supported
)
734 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
737 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
738 aspect
, level
, array_layer
,
739 resolve_op
, fast_clear_supported
);
740 #else /* GEN_GEN <= 8 */
741 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
742 aspect
, level
, array_layer
,
743 resolve_op
, fast_clear_supported
);
746 /* CCS_D only supports full resolves and BLORP will assert on us if we try
747 * to do a partial resolve on a CCS_D surface.
749 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
750 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
751 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
753 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
754 array_layer
, 1, resolve_op
, NULL
, true);
758 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
759 const struct anv_image
*image
,
760 VkImageAspectFlagBits aspect
,
761 uint32_t array_layer
,
762 enum isl_aux_op resolve_op
,
763 enum anv_fast_clear_type fast_clear_supported
)
765 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
766 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
768 #if GEN_GEN >= 8 || GEN_IS_HASWELL
769 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
770 aspect
, 0, array_layer
,
771 resolve_op
, fast_clear_supported
);
773 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
774 array_layer
, 1, resolve_op
, NULL
, true);
776 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
781 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
782 const struct anv_image
*image
,
783 VkImageAspectFlagBits aspect
,
784 enum isl_aux_usage aux_usage
,
787 uint32_t layer_count
)
789 /* The aspect must be exactly one of the image aspects. */
790 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
792 /* The only compression types with more than just fast-clears are MCS,
793 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
794 * track the current fast-clear and compression state. This leaves us
795 * with just MCS and CCS_E.
797 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
798 aux_usage
!= ISL_AUX_USAGE_MCS
)
801 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
802 level
, base_layer
, layer_count
, true);
806 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
807 const struct anv_image
*image
,
808 VkImageAspectFlagBits aspect
)
810 assert(cmd_buffer
&& image
);
811 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
813 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
814 ANV_FAST_CLEAR_NONE
);
816 /* The fast clear value dword(s) will be copied into a surface state object.
817 * Ensure that the restrictions of the fields in the dword(s) are followed.
819 * CCS buffers on SKL+ can have any value set for the clear colors.
821 if (image
->samples
== 1 && GEN_GEN
>= 9)
824 /* Other combinations of auxiliary buffers and platforms require specific
825 * values in the clear value dword(s).
827 struct anv_address addr
=
828 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
831 for (unsigned i
= 0; i
< 4; i
++) {
832 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
834 sdi
.Address
.offset
+= i
* 4;
835 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
836 assert(image
->samples
> 1);
837 sdi
.ImmediateData
= 0;
841 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
843 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
844 /* Pre-SKL, the dword containing the clear values also contains
845 * other fields, so we need to initialize those fields to match the
846 * values that would be in a color attachment.
848 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
849 ISL_CHANNEL_SELECT_GREEN
<< 22 |
850 ISL_CHANNEL_SELECT_BLUE
<< 19 |
851 ISL_CHANNEL_SELECT_ALPHA
<< 16;
852 } else if (GEN_GEN
== 7) {
853 /* On IVB, the dword containing the clear values also contains
854 * other fields that must be zero or can be zero.
856 sdi
.ImmediateData
= 0;
862 /* Copy the fast-clear value dword(s) between a surface state object and an
863 * image's fast clear state buffer.
866 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
867 struct anv_state surface_state
,
868 const struct anv_image
*image
,
869 VkImageAspectFlagBits aspect
,
870 bool copy_from_surface_state
)
872 assert(cmd_buffer
&& image
);
873 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
875 struct anv_address ss_clear_addr
= {
876 .bo
= &cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
877 .offset
= surface_state
.offset
+
878 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
880 const struct anv_address entry_addr
=
881 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
882 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
884 if (copy_from_surface_state
) {
885 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, entry_addr
,
886 ss_clear_addr
, copy_size
);
888 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, ss_clear_addr
,
889 entry_addr
, copy_size
);
891 /* Updating a surface state object may require that the state cache be
892 * invalidated. From the SKL PRM, Shared Functions -> State -> State
895 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
896 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
897 * modified [...], the L1 state cache must be invalidated to ensure
898 * the new surface or sampler state is fetched from system memory.
900 * In testing, SKL doesn't actually seem to need this, but HSW does.
902 cmd_buffer
->state
.pending_pipe_bits
|=
903 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
908 * @brief Transitions a color buffer from one layout to another.
910 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
913 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
914 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
915 * this represents the maximum layers to transition at each
916 * specified miplevel.
919 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
920 const struct anv_image
*image
,
921 VkImageAspectFlagBits aspect
,
922 const uint32_t base_level
, uint32_t level_count
,
923 uint32_t base_layer
, uint32_t layer_count
,
924 VkImageLayout initial_layout
,
925 VkImageLayout final_layout
)
927 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
928 /* Validate the inputs. */
930 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
931 /* These values aren't supported for simplicity's sake. */
932 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
933 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
934 /* Ensure the subresource range is valid. */
935 uint64_t last_level_num
= base_level
+ level_count
;
936 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
937 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
938 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
939 assert(last_level_num
<= image
->levels
);
940 /* The spec disallows these final layouts. */
941 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
942 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
944 /* No work is necessary if the layout stays the same or if this subresource
945 * range lacks auxiliary data.
947 if (initial_layout
== final_layout
)
950 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
952 if (image
->planes
[plane
].shadow_surface
.isl
.size
> 0 &&
953 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
954 /* This surface is a linear compressed image with a tiled shadow surface
955 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
956 * we need to ensure the shadow copy is up-to-date.
958 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
959 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
960 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
961 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
963 anv_image_copy_to_shadow(cmd_buffer
, image
,
964 base_level
, level_count
,
965 base_layer
, layer_count
);
968 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
971 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
973 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
974 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
975 /* A subresource in the undefined layout may have been aliased and
976 * populated with any arrangement of bits. Therefore, we must initialize
977 * the related aux buffer and clear buffer entry with desirable values.
978 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
979 * images with VK_IMAGE_TILING_OPTIMAL.
981 * Initialize the relevant clear buffer entries.
983 if (base_level
== 0 && base_layer
== 0)
984 init_fast_clear_color(cmd_buffer
, image
, aspect
);
986 /* Initialize the aux buffers to enable correct rendering. In order to
987 * ensure that things such as storage images work correctly, aux buffers
988 * need to be initialized to valid data.
990 * Having an aux buffer with invalid data is a problem for two reasons:
992 * 1) Having an invalid value in the buffer can confuse the hardware.
993 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
994 * invalid and leads to the hardware doing strange things. It
995 * doesn't hang as far as we can tell but rendering corruption can
998 * 2) If this transition is into the GENERAL layout and we then use the
999 * image as a storage image, then we must have the aux buffer in the
1000 * pass-through state so that, if we then go to texture from the
1001 * image, we get the results of our storage image writes and not the
1002 * fast clear color or other random data.
1004 * For CCS both of the problems above are real demonstrable issues. In
1005 * that case, the only thing we can do is to perform an ambiguate to
1006 * transition the aux surface into the pass-through state.
1008 * For MCS, (2) is never an issue because we don't support multisampled
1009 * storage images. In theory, issue (1) is a problem with MCS but we've
1010 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1011 * theory, be interpreted as something but we don't know that all bit
1012 * patterns are actually valid. For 2x and 8x, you could easily end up
1013 * with the MCS referring to an invalid plane because not all bits of
1014 * the MCS value are actually used. Even though we've never seen issues
1015 * in the wild, it's best to play it safe and initialize the MCS. We
1016 * can use a fast-clear for MCS because we only ever touch from render
1017 * and texture (no image load store).
1019 if (image
->samples
== 1) {
1020 for (uint32_t l
= 0; l
< level_count
; l
++) {
1021 const uint32_t level
= base_level
+ l
;
1023 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1024 if (base_layer
>= aux_layers
)
1025 break; /* We will only get fewer layers as level increases */
1026 uint32_t level_layer_count
=
1027 MIN2(layer_count
, aux_layers
- base_layer
);
1029 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
1030 base_layer
, level_layer_count
,
1031 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1033 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1034 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1035 level
, base_layer
, level_layer_count
,
1040 if (image
->samples
== 4 || image
->samples
== 16) {
1041 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1042 "Doing a potentially unnecessary fast-clear to "
1043 "define an MCS buffer.");
1046 assert(base_level
== 0 && level_count
== 1);
1047 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
1048 base_layer
, layer_count
,
1049 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1054 const enum isl_aux_usage initial_aux_usage
=
1055 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1056 const enum isl_aux_usage final_aux_usage
=
1057 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1059 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1060 * We can handle transitions between CCS_D/E to and from NONE. What we
1061 * don't yet handle is switching between CCS_E and CCS_D within a given
1062 * image. Doing so in a performant way requires more detailed aux state
1063 * tracking such as what is done in i965. For now, just assume that we
1064 * only have one type of compression.
1066 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1067 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1068 initial_aux_usage
== final_aux_usage
);
1070 /* If initial aux usage is NONE, there is nothing to resolve */
1071 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1074 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1076 /* If the initial layout supports more fast clear than the final layout
1077 * then we need at least a partial resolve.
1079 const enum anv_fast_clear_type initial_fast_clear
=
1080 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1081 const enum anv_fast_clear_type final_fast_clear
=
1082 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1083 if (final_fast_clear
< initial_fast_clear
)
1084 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1086 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1087 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1088 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1090 if (resolve_op
== ISL_AUX_OP_NONE
)
1093 /* Perform a resolve to synchronize data between the main and aux buffer.
1094 * Before we begin, we must satisfy the cache flushing requirement specified
1095 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1097 * Any transition from any value in {Clear, Render, Resolve} to a
1098 * different value in {Clear, Render, Resolve} requires end of pipe
1101 * We perform a flush of the write cache before and after the clear and
1102 * resolve operations to meet this requirement.
1104 * Unlike other drawing, fast clear operations are not properly
1105 * synchronized. The first PIPE_CONTROL here likely ensures that the
1106 * contents of the previous render or clear hit the render target before we
1107 * resolve and the second likely ensures that the resolve is complete before
1108 * we do any more rendering or clearing.
1110 cmd_buffer
->state
.pending_pipe_bits
|=
1111 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1113 for (uint32_t l
= 0; l
< level_count
; l
++) {
1114 uint32_t level
= base_level
+ l
;
1116 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1117 if (base_layer
>= aux_layers
)
1118 break; /* We will only get fewer layers as level increases */
1119 uint32_t level_layer_count
=
1120 MIN2(layer_count
, aux_layers
- base_layer
);
1122 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1123 uint32_t array_layer
= base_layer
+ a
;
1124 if (image
->samples
== 1) {
1125 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
, aspect
,
1126 level
, array_layer
, resolve_op
,
1129 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
, aspect
,
1130 array_layer
, resolve_op
,
1136 cmd_buffer
->state
.pending_pipe_bits
|=
1137 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1141 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1144 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1145 struct anv_render_pass
*pass
,
1146 const VkRenderPassBeginInfo
*begin
)
1148 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1149 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1151 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1153 if (pass
->attachment_count
> 0) {
1154 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1155 pass
->attachment_count
*
1156 sizeof(state
->attachments
[0]),
1157 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1158 if (state
->attachments
== NULL
) {
1159 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1160 return anv_batch_set_error(&cmd_buffer
->batch
,
1161 VK_ERROR_OUT_OF_HOST_MEMORY
);
1164 state
->attachments
= NULL
;
1167 /* Reserve one for the NULL state. */
1168 unsigned num_states
= 1;
1169 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1170 if (vk_format_is_color(pass
->attachments
[i
].format
))
1173 if (need_input_attachment_state(&pass
->attachments
[i
]))
1177 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1178 state
->render_pass_states
=
1179 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1180 num_states
* ss_stride
, isl_dev
->ss
.align
);
1182 struct anv_state next_state
= state
->render_pass_states
;
1183 next_state
.alloc_size
= isl_dev
->ss
.size
;
1185 state
->null_surface_state
= next_state
;
1186 next_state
.offset
+= ss_stride
;
1187 next_state
.map
+= ss_stride
;
1189 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1190 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1191 state
->attachments
[i
].color
.state
= next_state
;
1192 next_state
.offset
+= ss_stride
;
1193 next_state
.map
+= ss_stride
;
1196 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1197 state
->attachments
[i
].input
.state
= next_state
;
1198 next_state
.offset
+= ss_stride
;
1199 next_state
.map
+= ss_stride
;
1202 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1203 state
->render_pass_states
.alloc_size
);
1206 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1207 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1209 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1210 isl_extent3d(framebuffer
->width
,
1211 framebuffer
->height
,
1212 framebuffer
->layers
));
1214 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1215 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1216 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1217 VkImageAspectFlags clear_aspects
= 0;
1218 VkImageAspectFlags load_aspects
= 0;
1220 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1221 /* color attachment */
1222 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1223 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1224 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1225 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1228 /* depthstencil attachment */
1229 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1230 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1231 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1232 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1233 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1236 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1237 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1238 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1239 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1240 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1245 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1246 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1247 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1249 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1251 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1252 anv_assert(iview
->vk_format
== att
->format
);
1254 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1255 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1257 union isl_color_value clear_color
= { .u32
= { 0, } };
1258 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1259 anv_assert(iview
->n_planes
== 1);
1260 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1261 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1262 state
, i
, begin
->renderArea
,
1265 anv_image_fill_surface_state(cmd_buffer
->device
,
1267 VK_IMAGE_ASPECT_COLOR_BIT
,
1268 &iview
->planes
[0].isl
,
1269 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1270 state
->attachments
[i
].aux_usage
,
1273 &state
->attachments
[i
].color
,
1276 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1278 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1283 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1284 anv_image_fill_surface_state(cmd_buffer
->device
,
1286 VK_IMAGE_ASPECT_COLOR_BIT
,
1287 &iview
->planes
[0].isl
,
1288 ISL_SURF_USAGE_TEXTURE_BIT
,
1289 state
->attachments
[i
].input_aux_usage
,
1292 &state
->attachments
[i
].input
,
1295 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1304 genX(BeginCommandBuffer
)(
1305 VkCommandBuffer commandBuffer
,
1306 const VkCommandBufferBeginInfo
* pBeginInfo
)
1308 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1310 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1311 * command buffer's state. Otherwise, we must *reset* its state. In both
1312 * cases we reset it.
1314 * From the Vulkan 1.0 spec:
1316 * If a command buffer is in the executable state and the command buffer
1317 * was allocated from a command pool with the
1318 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1319 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1320 * as if vkResetCommandBuffer had been called with
1321 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1322 * the command buffer in the recording state.
1324 anv_cmd_buffer_reset(cmd_buffer
);
1326 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1328 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1329 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1331 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1333 /* We sometimes store vertex data in the dynamic state buffer for blorp
1334 * operations and our dynamic state stream may re-use data from previous
1335 * command buffers. In order to prevent stale cache data, we flush the VF
1336 * cache. We could do this on every blorp call but that's not really
1337 * needed as all of the data will get written by the CPU prior to the GPU
1338 * executing anything. The chances are fairly high that they will use
1339 * blorp at least once per primary command buffer so it shouldn't be
1342 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1343 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1345 /* We send an "Indirect State Pointers Disable" packet at
1346 * EndCommandBuffer, so all push contant packets are ignored during a
1347 * context restore. Documentation says after that command, we need to
1348 * emit push constants again before any rendering operation. So we
1349 * flag them dirty here to make sure they get emitted.
1351 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1353 VkResult result
= VK_SUCCESS
;
1354 if (cmd_buffer
->usage_flags
&
1355 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1356 assert(pBeginInfo
->pInheritanceInfo
);
1357 cmd_buffer
->state
.pass
=
1358 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1359 cmd_buffer
->state
.subpass
=
1360 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1362 /* This is optional in the inheritance info. */
1363 cmd_buffer
->state
.framebuffer
=
1364 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1366 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1367 cmd_buffer
->state
.pass
, NULL
);
1369 /* Record that HiZ is enabled if we can. */
1370 if (cmd_buffer
->state
.framebuffer
) {
1371 const struct anv_image_view
* const iview
=
1372 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1375 VkImageLayout layout
=
1376 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1378 enum isl_aux_usage aux_usage
=
1379 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1380 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1382 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1386 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1392 /* From the PRM, Volume 2a:
1394 * "Indirect State Pointers Disable
1396 * At the completion of the post-sync operation associated with this pipe
1397 * control packet, the indirect state pointers in the hardware are
1398 * considered invalid; the indirect pointers are not saved in the context.
1399 * If any new indirect state commands are executed in the command stream
1400 * while the pipe control is pending, the new indirect state commands are
1403 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1404 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1405 * commands are only considered as Indirect State Pointers. Once ISP is
1406 * issued in a context, SW must initialize by programming push constant
1407 * commands for all the shaders (at least to zero length) before attempting
1408 * any rendering operation for the same context."
1410 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1411 * even though they point to a BO that has been already unreferenced at
1412 * the end of the previous batch buffer. This has been fine so far since
1413 * we are protected by these scratch page (every address not covered by
1414 * a BO should be pointing to the scratch page). But on CNL, it is
1415 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1418 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1419 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1420 * context restore, so the mentioned hang doesn't happen. However,
1421 * software must program push constant commands for all stages prior to
1422 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1424 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1425 * constants have been loaded into the EUs prior to disable the push constants
1426 * so that it doesn't hang a previous 3DPRIMITIVE.
1429 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1431 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1432 pc
.StallAtPixelScoreboard
= true;
1433 pc
.CommandStreamerStallEnable
= true;
1435 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1436 pc
.IndirectStatePointersDisable
= true;
1437 pc
.CommandStreamerStallEnable
= true;
1442 genX(EndCommandBuffer
)(
1443 VkCommandBuffer commandBuffer
)
1445 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1447 if (anv_batch_has_error(&cmd_buffer
->batch
))
1448 return cmd_buffer
->batch
.status
;
1450 /* We want every command buffer to start with the PMA fix in a known state,
1451 * so we disable it at the end of the command buffer.
1453 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1455 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1457 emit_isp_disable(cmd_buffer
);
1459 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1465 genX(CmdExecuteCommands
)(
1466 VkCommandBuffer commandBuffer
,
1467 uint32_t commandBufferCount
,
1468 const VkCommandBuffer
* pCmdBuffers
)
1470 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1472 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1474 if (anv_batch_has_error(&primary
->batch
))
1477 /* The secondary command buffers will assume that the PMA fix is disabled
1478 * when they begin executing. Make sure this is true.
1480 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1482 /* The secondary command buffer doesn't know which textures etc. have been
1483 * flushed prior to their execution. Apply those flushes now.
1485 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1487 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1488 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1490 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1491 assert(!anv_batch_has_error(&secondary
->batch
));
1493 if (secondary
->usage_flags
&
1494 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1495 /* If we're continuing a render pass from the primary, we need to
1496 * copy the surface states for the current subpass into the storage
1497 * we allocated for them in BeginCommandBuffer.
1499 struct anv_bo
*ss_bo
=
1500 &primary
->device
->surface_state_pool
.block_pool
.bo
;
1501 struct anv_state src_state
= primary
->state
.render_pass_states
;
1502 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1503 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1505 genX(cmd_buffer_so_memcpy
)(primary
,
1506 (struct anv_address
) {
1508 .offset
= dst_state
.offset
,
1510 (struct anv_address
) {
1512 .offset
= src_state
.offset
,
1514 src_state
.alloc_size
);
1517 anv_cmd_buffer_add_secondary(primary
, secondary
);
1520 /* The secondary may have selected a different pipeline (3D or compute) and
1521 * may have changed the current L3$ configuration. Reset our tracking
1522 * variables to invalid values to ensure that we re-emit these in the case
1523 * where we do any draws or compute dispatches from the primary after the
1524 * secondary has returned.
1526 primary
->state
.current_pipeline
= UINT32_MAX
;
1527 primary
->state
.current_l3_config
= NULL
;
1529 /* Each of the secondary command buffers will use its own state base
1530 * address. We need to re-emit state base address for the primary after
1531 * all of the secondaries are done.
1533 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1536 genX(cmd_buffer_emit_state_base_address
)(primary
);
1539 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1540 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1541 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1544 * Program the hardware to use the specified L3 configuration.
1547 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1548 const struct gen_l3_config
*cfg
)
1551 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1554 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1555 intel_logd("L3 config transition: ");
1556 gen_dump_l3_config(cfg
, stderr
);
1559 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1561 /* According to the hardware docs, the L3 partitioning can only be changed
1562 * while the pipeline is completely drained and the caches are flushed,
1563 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1565 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1566 pc
.DCFlushEnable
= true;
1567 pc
.PostSyncOperation
= NoWrite
;
1568 pc
.CommandStreamerStallEnable
= true;
1571 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1572 * invalidation of the relevant caches. Note that because RO invalidation
1573 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1574 * command is processed by the CS) we cannot combine it with the previous
1575 * stalling flush as the hardware documentation suggests, because that
1576 * would cause the CS to stall on previous rendering *after* RO
1577 * invalidation and wouldn't prevent the RO caches from being polluted by
1578 * concurrent rendering before the stall completes. This intentionally
1579 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1580 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1581 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1582 * already guarantee that there is no concurrent GPGPU kernel execution
1583 * (see SKL HSD 2132585).
1585 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1586 pc
.TextureCacheInvalidationEnable
= true;
1587 pc
.ConstantCacheInvalidationEnable
= true;
1588 pc
.InstructionCacheInvalidateEnable
= true;
1589 pc
.StateCacheInvalidationEnable
= true;
1590 pc
.PostSyncOperation
= NoWrite
;
1593 /* Now send a third stalling flush to make sure that invalidation is
1594 * complete when the L3 configuration registers are modified.
1596 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1597 pc
.DCFlushEnable
= true;
1598 pc
.PostSyncOperation
= NoWrite
;
1599 pc
.CommandStreamerStallEnable
= true;
1604 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1607 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1608 .SLMEnable
= has_slm
,
1609 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1610 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1611 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1612 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1614 /* Set up the L3 partitioning. */
1615 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1619 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1620 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1621 cfg
->n
[GEN_L3P_ALL
];
1622 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1623 cfg
->n
[GEN_L3P_ALL
];
1624 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1625 cfg
->n
[GEN_L3P_ALL
];
1627 assert(!cfg
->n
[GEN_L3P_ALL
]);
1629 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1630 * the matching space on the remaining banks has to be allocated to a
1631 * client (URB for all validated configurations) set to the
1632 * lower-bandwidth 2-bank address hashing mode.
1634 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1635 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1636 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1638 /* Minimum number of ways that can be allocated to the URB. */
1639 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1640 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1642 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1643 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1644 .ConvertDC_UC
= !has_dc
,
1645 .ConvertIS_UC
= !has_is
,
1646 .ConvertC_UC
= !has_c
,
1647 .ConvertT_UC
= !has_t
);
1649 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1650 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1651 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1653 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1654 .SLMEnable
= has_slm
,
1655 .URBLowBandwidth
= urb_low_bw
,
1656 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1658 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1660 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1661 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1663 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1664 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1665 .ISLowBandwidth
= 0,
1666 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1668 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1669 .TLowBandwidth
= 0);
1671 /* Set up the L3 partitioning. */
1672 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1673 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1674 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1677 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1678 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1679 * them disabled to avoid crashing the system hard.
1681 uint32_t scratch1
, chicken3
;
1682 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1683 .L3AtomicDisable
= !has_dc
);
1684 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1685 .L3AtomicDisableMask
= true,
1686 .L3AtomicDisable
= !has_dc
);
1687 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1688 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1694 cmd_buffer
->state
.current_l3_config
= cfg
;
1698 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1700 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1702 /* Flushes are pipelined while invalidations are handled immediately.
1703 * Therefore, if we're flushing anything then we need to schedule a stall
1704 * before any invalidations can happen.
1706 if (bits
& ANV_PIPE_FLUSH_BITS
)
1707 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1709 /* If we're going to do an invalidate and we have a pending CS stall that
1710 * has yet to be resolved, we do the CS stall now.
1712 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1713 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1714 bits
|= ANV_PIPE_CS_STALL_BIT
;
1715 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1718 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1719 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1720 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1721 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1722 pipe
.RenderTargetCacheFlushEnable
=
1723 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1725 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1726 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1727 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1730 * According to the Broadwell documentation, any PIPE_CONTROL with the
1731 * "Command Streamer Stall" bit set must also have another bit set,
1732 * with five different options:
1734 * - Render Target Cache Flush
1735 * - Depth Cache Flush
1736 * - Stall at Pixel Scoreboard
1737 * - Post-Sync Operation
1741 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1742 * mesa and it seems to work fine. The choice is fairly arbitrary.
1744 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1745 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1746 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1747 pipe
.StallAtPixelScoreboard
= true;
1750 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1753 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1754 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1756 * "If the VF Cache Invalidation Enable is set to a 1 in a
1757 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1758 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1759 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1762 * This appears to hang Broadwell, so we restrict it to just gen9.
1764 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1765 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1767 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1768 pipe
.StateCacheInvalidationEnable
=
1769 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1770 pipe
.ConstantCacheInvalidationEnable
=
1771 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1772 pipe
.VFCacheInvalidationEnable
=
1773 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1774 pipe
.TextureCacheInvalidationEnable
=
1775 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1776 pipe
.InstructionCacheInvalidateEnable
=
1777 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1779 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1781 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1782 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1783 * “Write Timestamp”.
1785 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1786 pipe
.PostSyncOperation
= WriteImmediateData
;
1788 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1792 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1795 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1798 void genX(CmdPipelineBarrier
)(
1799 VkCommandBuffer commandBuffer
,
1800 VkPipelineStageFlags srcStageMask
,
1801 VkPipelineStageFlags destStageMask
,
1803 uint32_t memoryBarrierCount
,
1804 const VkMemoryBarrier
* pMemoryBarriers
,
1805 uint32_t bufferMemoryBarrierCount
,
1806 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1807 uint32_t imageMemoryBarrierCount
,
1808 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1810 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1812 /* XXX: Right now, we're really dumb and just flush whatever categories
1813 * the app asks for. One of these days we may make this a bit better
1814 * but right now that's all the hardware allows for in most areas.
1816 VkAccessFlags src_flags
= 0;
1817 VkAccessFlags dst_flags
= 0;
1819 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1820 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1821 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1824 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1825 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1826 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1829 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1830 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1831 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1832 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1833 const VkImageSubresourceRange
*range
=
1834 &pImageMemoryBarriers
[i
].subresourceRange
;
1836 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1837 transition_depth_buffer(cmd_buffer
, image
,
1838 pImageMemoryBarriers
[i
].oldLayout
,
1839 pImageMemoryBarriers
[i
].newLayout
);
1840 } else if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1841 VkImageAspectFlags color_aspects
=
1842 anv_image_expand_aspects(image
, range
->aspectMask
);
1843 uint32_t aspect_bit
;
1845 uint32_t base_layer
, layer_count
;
1846 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1848 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1850 base_layer
= range
->baseArrayLayer
;
1851 layer_count
= anv_get_layerCount(image
, range
);
1854 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1855 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1856 range
->baseMipLevel
,
1857 anv_get_levelCount(image
, range
),
1858 base_layer
, layer_count
,
1859 pImageMemoryBarriers
[i
].oldLayout
,
1860 pImageMemoryBarriers
[i
].newLayout
);
1865 cmd_buffer
->state
.pending_pipe_bits
|=
1866 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1867 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1871 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1873 VkShaderStageFlags stages
=
1874 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1876 /* In order to avoid thrash, we assume that vertex and fragment stages
1877 * always exist. In the rare case where one is missing *and* the other
1878 * uses push concstants, this may be suboptimal. However, avoiding stalls
1879 * seems more important.
1881 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1883 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1887 const unsigned push_constant_kb
= 32;
1888 #elif GEN_IS_HASWELL
1889 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1891 const unsigned push_constant_kb
= 16;
1894 const unsigned num_stages
=
1895 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1896 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1898 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1899 * units of 2KB. Incidentally, these are the same platforms that have
1900 * 32KB worth of push constant space.
1902 if (push_constant_kb
== 32)
1903 size_per_stage
&= ~1u;
1905 uint32_t kb_used
= 0;
1906 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1907 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1908 anv_batch_emit(&cmd_buffer
->batch
,
1909 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1910 alloc
._3DCommandSubOpcode
= 18 + i
;
1911 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1912 alloc
.ConstantBufferSize
= push_size
;
1914 kb_used
+= push_size
;
1917 anv_batch_emit(&cmd_buffer
->batch
,
1918 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1919 alloc
.ConstantBufferOffset
= kb_used
;
1920 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1923 cmd_buffer
->state
.push_constant_stages
= stages
;
1925 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1927 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1928 * the next 3DPRIMITIVE command after programming the
1929 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1931 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1932 * pipeline setup, we need to dirty push constants.
1934 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1937 static const struct anv_descriptor
*
1938 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1939 const struct anv_pipeline_binding
*binding
)
1941 assert(binding
->set
< MAX_SETS
);
1942 const struct anv_descriptor_set
*set
=
1943 pipe_state
->descriptors
[binding
->set
];
1944 const uint32_t offset
=
1945 set
->layout
->binding
[binding
->binding
].descriptor_index
;
1946 return &set
->descriptors
[offset
+ binding
->index
];
1950 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1951 const struct anv_pipeline_binding
*binding
)
1953 assert(binding
->set
< MAX_SETS
);
1954 const struct anv_descriptor_set
*set
=
1955 pipe_state
->descriptors
[binding
->set
];
1957 uint32_t dynamic_offset_idx
=
1958 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
1959 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1962 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
1966 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1967 gl_shader_stage stage
,
1968 struct anv_state
*bt_state
)
1970 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1971 struct anv_cmd_pipeline_state
*pipe_state
;
1972 struct anv_pipeline
*pipeline
;
1973 uint32_t bias
, state_offset
;
1976 case MESA_SHADER_COMPUTE
:
1977 pipe_state
= &cmd_buffer
->state
.compute
.base
;
1981 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
1985 pipeline
= pipe_state
->pipeline
;
1987 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1988 *bt_state
= (struct anv_state
) { 0, };
1992 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1993 if (bias
+ map
->surface_count
== 0) {
1994 *bt_state
= (struct anv_state
) { 0, };
1998 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
1999 bias
+ map
->surface_count
,
2001 uint32_t *bt_map
= bt_state
->map
;
2003 if (bt_state
->map
== NULL
)
2004 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2006 if (stage
== MESA_SHADER_COMPUTE
&&
2007 get_cs_prog_data(pipeline
)->uses_num_work_groups
) {
2008 struct anv_state surface_state
;
2010 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2012 const enum isl_format format
=
2013 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2014 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2016 cmd_buffer
->state
.compute
.num_workgroups
,
2019 bt_map
[0] = surface_state
.offset
+ state_offset
;
2020 add_surface_reloc(cmd_buffer
, surface_state
,
2021 cmd_buffer
->state
.compute
.num_workgroups
);
2024 if (map
->surface_count
== 0)
2027 if (map
->image_count
> 0) {
2029 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
2030 if (result
!= VK_SUCCESS
)
2033 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
2037 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2038 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2040 struct anv_state surface_state
;
2042 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2043 /* Color attachment binding */
2044 assert(stage
== MESA_SHADER_FRAGMENT
);
2045 assert(binding
->binding
== 0);
2046 if (binding
->index
< subpass
->color_count
) {
2047 const unsigned att
=
2048 subpass
->color_attachments
[binding
->index
].attachment
;
2050 /* From the Vulkan 1.0.46 spec:
2052 * "If any color or depth/stencil attachments are
2053 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2056 if (att
== VK_ATTACHMENT_UNUSED
) {
2057 surface_state
= cmd_buffer
->state
.null_surface_state
;
2059 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2062 surface_state
= cmd_buffer
->state
.null_surface_state
;
2065 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2067 } else if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2068 struct anv_state surface_state
=
2069 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2071 struct anv_address constant_data
= {
2072 .bo
= &pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2073 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2075 unsigned constant_data_size
=
2076 pipeline
->shaders
[stage
]->constant_data_size
;
2078 const enum isl_format format
=
2079 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2080 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2081 surface_state
, format
,
2082 constant_data
, constant_data_size
, 1);
2084 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2085 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2089 const struct anv_descriptor
*desc
=
2090 anv_descriptor_for_binding(pipe_state
, binding
);
2092 switch (desc
->type
) {
2093 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2094 /* Nothing for us to do here */
2097 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2098 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2099 struct anv_surface_state sstate
=
2100 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2101 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2102 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2103 surface_state
= sstate
.state
;
2104 assert(surface_state
.alloc_size
);
2105 add_surface_state_relocs(cmd_buffer
, sstate
);
2108 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2109 assert(stage
== MESA_SHADER_FRAGMENT
);
2110 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2111 /* For depth and stencil input attachments, we treat it like any
2112 * old texture that a user may have bound.
2114 struct anv_surface_state sstate
=
2115 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2116 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2117 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2118 surface_state
= sstate
.state
;
2119 assert(surface_state
.alloc_size
);
2120 add_surface_state_relocs(cmd_buffer
, sstate
);
2122 /* For color input attachments, we create the surface state at
2123 * vkBeginRenderPass time so that we can include aux and clear
2124 * color information.
2126 assert(binding
->input_attachment_index
< subpass
->input_count
);
2127 const unsigned subpass_att
= binding
->input_attachment_index
;
2128 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2129 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2133 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2134 struct anv_surface_state sstate
= (binding
->write_only
)
2135 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2136 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2137 surface_state
= sstate
.state
;
2138 assert(surface_state
.alloc_size
);
2139 add_surface_state_relocs(cmd_buffer
, sstate
);
2141 struct brw_image_param
*image_param
=
2142 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2144 *image_param
= desc
->image_view
->planes
[binding
->plane
].storage_image_param
;
2148 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2149 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2150 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2151 surface_state
= desc
->buffer_view
->surface_state
;
2152 assert(surface_state
.alloc_size
);
2153 add_surface_reloc(cmd_buffer
, surface_state
,
2154 desc
->buffer_view
->address
);
2157 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2158 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2159 /* Compute the offset within the buffer */
2160 uint32_t dynamic_offset
=
2161 dynamic_offset_for_binding(pipe_state
, binding
);
2162 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2163 /* Clamp to the buffer size */
2164 offset
= MIN2(offset
, desc
->buffer
->size
);
2165 /* Clamp the range to the buffer size */
2166 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2168 struct anv_address address
=
2169 anv_address_add(desc
->buffer
->address
, offset
);
2172 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2173 enum isl_format format
=
2174 anv_isl_format_for_descriptor_type(desc
->type
);
2176 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2177 format
, address
, range
, 1);
2178 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2182 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2183 surface_state
= (binding
->write_only
)
2184 ? desc
->buffer_view
->writeonly_storage_surface_state
2185 : desc
->buffer_view
->storage_surface_state
;
2186 assert(surface_state
.alloc_size
);
2187 add_surface_reloc(cmd_buffer
, surface_state
,
2188 desc
->buffer_view
->address
);
2190 struct brw_image_param
*image_param
=
2191 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2193 *image_param
= desc
->buffer_view
->storage_image_param
;
2197 assert(!"Invalid descriptor type");
2201 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2203 assert(image
== map
->image_count
);
2206 anv_state_flush(cmd_buffer
->device
, *bt_state
);
2209 /* The PIPE_CONTROL command description says:
2211 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2212 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2213 * Target Cache Flush by enabling this bit. When render target flush
2214 * is set due to new association of BTI, PS Scoreboard Stall bit must
2215 * be set in this packet."
2217 * FINISHME: Currently we shuffle around the surface states in the binding
2218 * table based on if they are getting used or not. So, we've to do below
2219 * pipe control flush for every binding table upload. Make changes so
2220 * that we do it only when we modify render target surface states.
2222 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2223 pc
.RenderTargetCacheFlushEnable
= true;
2224 pc
.StallAtPixelScoreboard
= true;
2232 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2233 gl_shader_stage stage
,
2234 struct anv_state
*state
)
2236 struct anv_cmd_pipeline_state
*pipe_state
=
2237 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2238 &cmd_buffer
->state
.gfx
.base
;
2239 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2241 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2242 *state
= (struct anv_state
) { 0, };
2246 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2247 if (map
->sampler_count
== 0) {
2248 *state
= (struct anv_state
) { 0, };
2252 uint32_t size
= map
->sampler_count
* 16;
2253 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2255 if (state
->map
== NULL
)
2256 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2258 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2259 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2260 const struct anv_descriptor
*desc
=
2261 anv_descriptor_for_binding(pipe_state
, binding
);
2263 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2264 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2267 struct anv_sampler
*sampler
= desc
->sampler
;
2269 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2270 * happens to be zero.
2272 if (sampler
== NULL
)
2275 memcpy(state
->map
+ (s
* 16),
2276 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2279 anv_state_flush(cmd_buffer
->device
, *state
);
2285 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2287 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2289 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2290 pipeline
->active_stages
;
2292 VkResult result
= VK_SUCCESS
;
2293 anv_foreach_stage(s
, dirty
) {
2294 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2295 if (result
!= VK_SUCCESS
)
2297 result
= emit_binding_table(cmd_buffer
, s
,
2298 &cmd_buffer
->state
.binding_tables
[s
]);
2299 if (result
!= VK_SUCCESS
)
2303 if (result
!= VK_SUCCESS
) {
2304 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2306 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2307 if (result
!= VK_SUCCESS
)
2310 /* Re-emit state base addresses so we get the new surface state base
2311 * address before we start emitting binding tables etc.
2313 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2315 /* Re-emit all active binding tables */
2316 dirty
|= pipeline
->active_stages
;
2317 anv_foreach_stage(s
, dirty
) {
2318 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2319 if (result
!= VK_SUCCESS
) {
2320 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2323 result
= emit_binding_table(cmd_buffer
, s
,
2324 &cmd_buffer
->state
.binding_tables
[s
]);
2325 if (result
!= VK_SUCCESS
) {
2326 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2332 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2338 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2341 static const uint32_t sampler_state_opcodes
[] = {
2342 [MESA_SHADER_VERTEX
] = 43,
2343 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2344 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2345 [MESA_SHADER_GEOMETRY
] = 46,
2346 [MESA_SHADER_FRAGMENT
] = 47,
2347 [MESA_SHADER_COMPUTE
] = 0,
2350 static const uint32_t binding_table_opcodes
[] = {
2351 [MESA_SHADER_VERTEX
] = 38,
2352 [MESA_SHADER_TESS_CTRL
] = 39,
2353 [MESA_SHADER_TESS_EVAL
] = 40,
2354 [MESA_SHADER_GEOMETRY
] = 41,
2355 [MESA_SHADER_FRAGMENT
] = 42,
2356 [MESA_SHADER_COMPUTE
] = 0,
2359 anv_foreach_stage(s
, stages
) {
2360 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2361 assert(binding_table_opcodes
[s
] > 0);
2363 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2364 anv_batch_emit(&cmd_buffer
->batch
,
2365 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2366 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2367 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2371 /* Always emit binding table pointers if we're asked to, since on SKL
2372 * this is what flushes push constants. */
2373 anv_batch_emit(&cmd_buffer
->batch
,
2374 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2375 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2376 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2382 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2383 VkShaderStageFlags dirty_stages
)
2385 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2386 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2388 static const uint32_t push_constant_opcodes
[] = {
2389 [MESA_SHADER_VERTEX
] = 21,
2390 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2391 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2392 [MESA_SHADER_GEOMETRY
] = 22,
2393 [MESA_SHADER_FRAGMENT
] = 23,
2394 [MESA_SHADER_COMPUTE
] = 0,
2397 VkShaderStageFlags flushed
= 0;
2399 anv_foreach_stage(stage
, dirty_stages
) {
2400 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2401 assert(push_constant_opcodes
[stage
] > 0);
2403 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2404 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2406 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2407 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2408 const struct brw_stage_prog_data
*prog_data
=
2409 pipeline
->shaders
[stage
]->prog_data
;
2410 const struct anv_pipeline_bind_map
*bind_map
=
2411 &pipeline
->shaders
[stage
]->bind_map
;
2413 /* The Skylake PRM contains the following restriction:
2415 * "The driver must ensure The following case does not occur
2416 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2417 * buffer 3 read length equal to zero committed followed by a
2418 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2421 * To avoid this, we program the buffers in the highest slots.
2422 * This way, slot 0 is only used if slot 3 is also used.
2426 for (int i
= 3; i
>= 0; i
--) {
2427 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2428 if (range
->length
== 0)
2431 const unsigned surface
=
2432 prog_data
->binding_table
.ubo_start
+ range
->block
;
2434 assert(surface
<= bind_map
->surface_count
);
2435 const struct anv_pipeline_binding
*binding
=
2436 &bind_map
->surface_to_descriptor
[surface
];
2438 struct anv_address read_addr
;
2440 if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2441 struct anv_address constant_data
= {
2442 .bo
= &pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2443 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2445 unsigned constant_data_size
=
2446 pipeline
->shaders
[stage
]->constant_data_size
;
2448 read_len
= MIN2(range
->length
,
2449 DIV_ROUND_UP(constant_data_size
, 32) - range
->start
);
2450 read_addr
= anv_address_add(constant_data
,
2453 const struct anv_descriptor
*desc
=
2454 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2456 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2457 read_len
= MIN2(range
->length
,
2458 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2459 read_addr
= anv_address_add(desc
->buffer_view
->address
,
2462 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2464 uint32_t dynamic_offset
=
2465 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2466 uint32_t buf_offset
=
2467 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2468 uint32_t buf_range
=
2469 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2471 read_len
= MIN2(range
->length
,
2472 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2473 read_addr
= anv_address_add(desc
->buffer
->address
,
2474 buf_offset
+ range
->start
* 32);
2479 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2480 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2485 struct anv_state state
=
2486 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2488 if (state
.alloc_size
> 0) {
2489 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2490 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2491 .offset
= state
.offset
,
2493 c
.ConstantBody
.ReadLength
[n
] =
2494 DIV_ROUND_UP(state
.alloc_size
, 32);
2497 /* For Ivy Bridge, the push constants packets have a different
2498 * rule that would require us to iterate in the other direction
2499 * and possibly mess around with dynamic state base address.
2500 * Don't bother; just emit regular push constants at n = 0.
2502 struct anv_state state
=
2503 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2505 if (state
.alloc_size
> 0) {
2506 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2507 c
.ConstantBody
.ReadLength
[0] =
2508 DIV_ROUND_UP(state
.alloc_size
, 32);
2514 flushed
|= mesa_to_vk_shader_stage(stage
);
2517 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2521 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2523 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2526 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2527 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2528 vb_emit
|= pipeline
->vb_used
;
2530 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2532 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2534 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2537 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2538 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2540 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2541 GENX(3DSTATE_VERTEX_BUFFERS
));
2543 for_each_bit(vb
, vb_emit
) {
2544 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2545 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2547 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2548 .VertexBufferIndex
= vb
,
2551 .MemoryObjectControlState
= GENX(MOCS
),
2553 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2554 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2555 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2558 .AddressModifyEnable
= true,
2559 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2560 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2563 .BufferSize
= buffer
->size
- offset
2565 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2569 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2574 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2576 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2577 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2579 /* The exact descriptor layout is pulled from the pipeline, so we need
2580 * to re-emit binding tables on every pipeline change.
2582 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2584 /* If the pipeline changed, we may need to re-allocate push constant
2587 cmd_buffer_alloc_push_constants(cmd_buffer
);
2591 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2592 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2593 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2595 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2596 * stall needs to be sent just prior to any 3DSTATE_VS,
2597 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2598 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2599 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2600 * PIPE_CONTROL needs to be sent before any combination of VS
2601 * associated 3DSTATE."
2603 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2604 pc
.DepthStallEnable
= true;
2605 pc
.PostSyncOperation
= WriteImmediateData
;
2607 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2612 /* Render targets live in the same binding table as fragment descriptors */
2613 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2614 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2616 /* We emit the binding tables and sampler tables first, then emit push
2617 * constants and then finally emit binding table and sampler table
2618 * pointers. It has to happen in this order, since emitting the binding
2619 * tables may change the push constants (in case of storage images). After
2620 * emitting push constants, on SKL+ we have to emit the corresponding
2621 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2624 if (cmd_buffer
->state
.descriptors_dirty
)
2625 dirty
= flush_descriptor_sets(cmd_buffer
);
2627 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2628 /* Because we're pushing UBOs, we have to push whenever either
2629 * descriptors or push constants is dirty.
2631 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2632 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2633 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2637 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2639 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2640 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2642 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2643 ANV_CMD_DIRTY_PIPELINE
)) {
2644 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2645 pipeline
->depth_clamp_enable
);
2648 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2649 ANV_CMD_DIRTY_RENDER_TARGETS
))
2650 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2652 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2654 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2658 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2659 struct anv_address addr
,
2660 uint32_t size
, uint32_t index
)
2662 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2663 GENX(3DSTATE_VERTEX_BUFFERS
));
2665 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2666 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2667 .VertexBufferIndex
= index
,
2668 .AddressModifyEnable
= true,
2671 .MemoryObjectControlState
= GENX(MOCS
),
2672 .BufferStartingAddress
= addr
,
2675 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2676 .BufferStartingAddress
= addr
,
2677 .EndAddress
= anv_address_add(addr
, size
),
2683 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2684 struct anv_address addr
)
2686 emit_vertex_bo(cmd_buffer
, addr
, 8, ANV_SVGS_VB_INDEX
);
2690 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2691 uint32_t base_vertex
, uint32_t base_instance
)
2693 struct anv_state id_state
=
2694 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2696 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2697 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2699 anv_state_flush(cmd_buffer
->device
, id_state
);
2701 struct anv_address addr
= {
2702 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2703 .offset
= id_state
.offset
,
2706 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2710 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2712 struct anv_state state
=
2713 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2715 ((uint32_t *)state
.map
)[0] = draw_index
;
2717 anv_state_flush(cmd_buffer
->device
, state
);
2719 struct anv_address addr
= {
2720 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2721 .offset
= state
.offset
,
2724 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2728 VkCommandBuffer commandBuffer
,
2729 uint32_t vertexCount
,
2730 uint32_t instanceCount
,
2731 uint32_t firstVertex
,
2732 uint32_t firstInstance
)
2734 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2735 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2736 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2738 if (anv_batch_has_error(&cmd_buffer
->batch
))
2741 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2743 if (vs_prog_data
->uses_firstvertex
||
2744 vs_prog_data
->uses_baseinstance
)
2745 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2746 if (vs_prog_data
->uses_drawid
)
2747 emit_draw_index(cmd_buffer
, 0);
2749 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2750 * different views. We need to multiply instanceCount by the view count.
2752 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2754 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2755 prim
.VertexAccessType
= SEQUENTIAL
;
2756 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2757 prim
.VertexCountPerInstance
= vertexCount
;
2758 prim
.StartVertexLocation
= firstVertex
;
2759 prim
.InstanceCount
= instanceCount
;
2760 prim
.StartInstanceLocation
= firstInstance
;
2761 prim
.BaseVertexLocation
= 0;
2765 void genX(CmdDrawIndexed
)(
2766 VkCommandBuffer commandBuffer
,
2767 uint32_t indexCount
,
2768 uint32_t instanceCount
,
2769 uint32_t firstIndex
,
2770 int32_t vertexOffset
,
2771 uint32_t firstInstance
)
2773 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2774 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2775 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2777 if (anv_batch_has_error(&cmd_buffer
->batch
))
2780 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2782 if (vs_prog_data
->uses_firstvertex
||
2783 vs_prog_data
->uses_baseinstance
)
2784 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2785 if (vs_prog_data
->uses_drawid
)
2786 emit_draw_index(cmd_buffer
, 0);
2788 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2789 * different views. We need to multiply instanceCount by the view count.
2791 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2793 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2794 prim
.VertexAccessType
= RANDOM
;
2795 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2796 prim
.VertexCountPerInstance
= indexCount
;
2797 prim
.StartVertexLocation
= firstIndex
;
2798 prim
.InstanceCount
= instanceCount
;
2799 prim
.StartInstanceLocation
= firstInstance
;
2800 prim
.BaseVertexLocation
= vertexOffset
;
2804 /* Auto-Draw / Indirect Registers */
2805 #define GEN7_3DPRIM_END_OFFSET 0x2420
2806 #define GEN7_3DPRIM_START_VERTEX 0x2430
2807 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2808 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2809 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2810 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2812 /* MI_MATH only exists on Haswell+ */
2813 #if GEN_IS_HASWELL || GEN_GEN >= 8
2815 /* Emit dwords to multiply GPR0 by N */
2817 build_alu_multiply_gpr0(uint32_t *dw
, unsigned *dw_count
, uint32_t N
)
2819 VK_OUTARRAY_MAKE(out
, dw
, dw_count
);
2821 #define append_alu(opcode, operand1, operand2) \
2822 vk_outarray_append(&out, alu_dw) *alu_dw = mi_alu(opcode, operand1, operand2)
2825 unsigned top_bit
= 31 - __builtin_clz(N
);
2826 for (int i
= top_bit
- 1; i
>= 0; i
--) {
2827 /* We get our initial data in GPR0 and we write the final data out to
2828 * GPR0 but we use GPR1 as our scratch register.
2830 unsigned src_reg
= i
== top_bit
- 1 ? MI_ALU_REG0
: MI_ALU_REG1
;
2831 unsigned dst_reg
= i
== 0 ? MI_ALU_REG0
: MI_ALU_REG1
;
2833 /* Shift the current value left by 1 */
2834 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, src_reg
);
2835 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, src_reg
);
2836 append_alu(MI_ALU_ADD
, 0, 0);
2839 /* Store ACCU to R1 and add R0 to R1 */
2840 append_alu(MI_ALU_STORE
, MI_ALU_REG1
, MI_ALU_ACCU
);
2841 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
2842 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
2843 append_alu(MI_ALU_ADD
, 0, 0);
2846 append_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2853 emit_mul_gpr0(struct anv_batch
*batch
, uint32_t N
)
2855 uint32_t num_dwords
;
2856 build_alu_multiply_gpr0(NULL
, &num_dwords
, N
);
2858 uint32_t *dw
= anv_batch_emitn(batch
, 1 + num_dwords
, GENX(MI_MATH
));
2859 build_alu_multiply_gpr0(dw
+ 1, &num_dwords
, N
);
2862 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2865 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2866 struct anv_address addr
,
2869 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2871 emit_lrm(batch
, GEN7_3DPRIM_VERTEX_COUNT
, addr
.bo
, addr
.offset
);
2873 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2874 if (view_count
> 1) {
2875 #if GEN_IS_HASWELL || GEN_GEN >= 8
2876 emit_lrm(batch
, CS_GPR(0), addr
.bo
, addr
.offset
+ 4);
2877 emit_mul_gpr0(batch
, view_count
);
2878 emit_lrr(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, CS_GPR(0));
2880 anv_finishme("Multiview + indirect draw requires MI_MATH; "
2881 "MI_MATH is not supported on Ivy Bridge");
2882 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, addr
.bo
, addr
.offset
+ 4);
2885 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, addr
.bo
, addr
.offset
+ 4);
2888 emit_lrm(batch
, GEN7_3DPRIM_START_VERTEX
, addr
.bo
, addr
.offset
+ 8);
2891 emit_lrm(batch
, GEN7_3DPRIM_BASE_VERTEX
, addr
.bo
, addr
.offset
+ 12);
2892 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, addr
.bo
, addr
.offset
+ 16);
2894 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, addr
.bo
, addr
.offset
+ 12);
2895 emit_lri(batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
2899 void genX(CmdDrawIndirect
)(
2900 VkCommandBuffer commandBuffer
,
2902 VkDeviceSize offset
,
2906 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2907 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2908 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2909 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2911 if (anv_batch_has_error(&cmd_buffer
->batch
))
2914 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2916 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2917 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
2919 if (vs_prog_data
->uses_firstvertex
||
2920 vs_prog_data
->uses_baseinstance
)
2921 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
2922 if (vs_prog_data
->uses_drawid
)
2923 emit_draw_index(cmd_buffer
, i
);
2925 load_indirect_parameters(cmd_buffer
, draw
, false);
2927 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2928 prim
.IndirectParameterEnable
= true;
2929 prim
.VertexAccessType
= SEQUENTIAL
;
2930 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2937 void genX(CmdDrawIndexedIndirect
)(
2938 VkCommandBuffer commandBuffer
,
2940 VkDeviceSize offset
,
2944 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2945 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2946 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2947 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2949 if (anv_batch_has_error(&cmd_buffer
->batch
))
2952 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2954 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2955 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
2957 /* TODO: We need to stomp base vertex to 0 somehow */
2958 if (vs_prog_data
->uses_firstvertex
||
2959 vs_prog_data
->uses_baseinstance
)
2960 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
2961 if (vs_prog_data
->uses_drawid
)
2962 emit_draw_index(cmd_buffer
, i
);
2964 load_indirect_parameters(cmd_buffer
, draw
, true);
2966 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2967 prim
.IndirectParameterEnable
= true;
2968 prim
.VertexAccessType
= RANDOM
;
2969 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2977 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
2979 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2980 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
2983 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2984 if (result
!= VK_SUCCESS
) {
2985 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2987 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2988 if (result
!= VK_SUCCESS
)
2991 /* Re-emit state base addresses so we get the new surface state base
2992 * address before we start emitting binding tables etc.
2994 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2996 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2997 if (result
!= VK_SUCCESS
) {
2998 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3003 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3004 if (result
!= VK_SUCCESS
) {
3005 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3009 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3010 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3011 .BindingTablePointer
= surfaces
.offset
,
3012 .SamplerStatePointer
= samplers
.offset
,
3014 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3016 struct anv_state state
=
3017 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3018 pipeline
->interface_descriptor_data
,
3019 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3022 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3023 anv_batch_emit(&cmd_buffer
->batch
,
3024 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3025 mid
.InterfaceDescriptorTotalLength
= size
;
3026 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3033 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3035 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3036 MAYBE_UNUSED VkResult result
;
3038 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3040 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3042 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3044 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3045 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3047 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3048 * the only bits that are changed are scoreboard related: Scoreboard
3049 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3050 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3053 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3054 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3056 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3059 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3060 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3061 /* FIXME: figure out descriptors for gen7 */
3062 result
= flush_compute_descriptor_set(cmd_buffer
);
3063 if (result
!= VK_SUCCESS
)
3066 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3069 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3070 struct anv_state push_state
=
3071 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3073 if (push_state
.alloc_size
) {
3074 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3075 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3076 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3080 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3083 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3085 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3091 verify_cmd_parser(const struct anv_device
*device
,
3092 int required_version
,
3093 const char *function
)
3095 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3096 return vk_errorf(device
->instance
, device
->instance
,
3097 VK_ERROR_FEATURE_NOT_PRESENT
,
3098 "cmd parser version %d is required for %s",
3099 required_version
, function
);
3108 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3109 uint32_t baseGroupX
,
3110 uint32_t baseGroupY
,
3111 uint32_t baseGroupZ
)
3113 if (anv_batch_has_error(&cmd_buffer
->batch
))
3117 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, MESA_SHADER_COMPUTE
,
3118 base_work_group_id
);
3119 if (result
!= VK_SUCCESS
) {
3120 cmd_buffer
->batch
.status
= result
;
3124 struct anv_push_constants
*push
=
3125 cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3126 if (push
->base_work_group_id
[0] != baseGroupX
||
3127 push
->base_work_group_id
[1] != baseGroupY
||
3128 push
->base_work_group_id
[2] != baseGroupZ
) {
3129 push
->base_work_group_id
[0] = baseGroupX
;
3130 push
->base_work_group_id
[1] = baseGroupY
;
3131 push
->base_work_group_id
[2] = baseGroupZ
;
3133 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3137 void genX(CmdDispatch
)(
3138 VkCommandBuffer commandBuffer
,
3143 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3146 void genX(CmdDispatchBase
)(
3147 VkCommandBuffer commandBuffer
,
3148 uint32_t baseGroupX
,
3149 uint32_t baseGroupY
,
3150 uint32_t baseGroupZ
,
3151 uint32_t groupCountX
,
3152 uint32_t groupCountY
,
3153 uint32_t groupCountZ
)
3155 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3156 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3157 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3159 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3160 baseGroupY
, baseGroupZ
);
3162 if (anv_batch_has_error(&cmd_buffer
->batch
))
3165 if (prog_data
->uses_num_work_groups
) {
3166 struct anv_state state
=
3167 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3168 uint32_t *sizes
= state
.map
;
3169 sizes
[0] = groupCountX
;
3170 sizes
[1] = groupCountY
;
3171 sizes
[2] = groupCountZ
;
3172 anv_state_flush(cmd_buffer
->device
, state
);
3173 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3174 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3175 .offset
= state
.offset
,
3179 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3181 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3182 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3183 ggw
.ThreadDepthCounterMaximum
= 0;
3184 ggw
.ThreadHeightCounterMaximum
= 0;
3185 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3186 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3187 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3188 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3189 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3190 ggw
.BottomExecutionMask
= 0xffffffff;
3193 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3196 #define GPGPU_DISPATCHDIMX 0x2500
3197 #define GPGPU_DISPATCHDIMY 0x2504
3198 #define GPGPU_DISPATCHDIMZ 0x2508
3200 void genX(CmdDispatchIndirect
)(
3201 VkCommandBuffer commandBuffer
,
3203 VkDeviceSize offset
)
3205 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3206 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3207 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3208 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3209 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3210 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3212 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3215 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3216 * indirect dispatch registers to be written.
3218 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3219 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3223 if (prog_data
->uses_num_work_groups
)
3224 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3226 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3228 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, addr
.bo
, addr
.offset
);
3229 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, addr
.bo
, addr
.offset
+ 4);
3230 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, addr
.bo
, addr
.offset
+ 8);
3233 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
3234 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
3235 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
3236 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
3238 /* Load compute_dispatch_indirect_x_size into SRC0 */
3239 emit_lrm(batch
, MI_PREDICATE_SRC0
, addr
.bo
, addr
.offset
+ 0);
3241 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3242 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3243 mip
.LoadOperation
= LOAD_LOAD
;
3244 mip
.CombineOperation
= COMBINE_SET
;
3245 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3248 /* Load compute_dispatch_indirect_y_size into SRC0 */
3249 emit_lrm(batch
, MI_PREDICATE_SRC0
, addr
.bo
, addr
.offset
+ 4);
3251 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3252 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3253 mip
.LoadOperation
= LOAD_LOAD
;
3254 mip
.CombineOperation
= COMBINE_OR
;
3255 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3258 /* Load compute_dispatch_indirect_z_size into SRC0 */
3259 emit_lrm(batch
, MI_PREDICATE_SRC0
, addr
.bo
, addr
.offset
+ 8);
3261 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3262 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3263 mip
.LoadOperation
= LOAD_LOAD
;
3264 mip
.CombineOperation
= COMBINE_OR
;
3265 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3268 /* predicate = !predicate; */
3269 #define COMPARE_FALSE 1
3270 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3271 mip
.LoadOperation
= LOAD_LOADINV
;
3272 mip
.CombineOperation
= COMBINE_OR
;
3273 mip
.CompareOperation
= COMPARE_FALSE
;
3277 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3278 ggw
.IndirectParameterEnable
= true;
3279 ggw
.PredicateEnable
= GEN_GEN
<= 7;
3280 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3281 ggw
.ThreadDepthCounterMaximum
= 0;
3282 ggw
.ThreadHeightCounterMaximum
= 0;
3283 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3284 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3285 ggw
.BottomExecutionMask
= 0xffffffff;
3288 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3292 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3295 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3297 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3300 #if GEN_GEN >= 8 && GEN_GEN < 10
3301 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3303 * Software must clear the COLOR_CALC_STATE Valid field in
3304 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3305 * with Pipeline Select set to GPGPU.
3307 * The internal hardware docs recommend the same workaround for Gen9
3310 if (pipeline
== GPGPU
)
3311 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3314 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3315 * PIPELINE_SELECT [DevBWR+]":
3319 * Software must ensure all the write caches are flushed through a
3320 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3321 * command to invalidate read only caches prior to programming
3322 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3324 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3325 pc
.RenderTargetCacheFlushEnable
= true;
3326 pc
.DepthCacheFlushEnable
= true;
3327 pc
.DCFlushEnable
= true;
3328 pc
.PostSyncOperation
= NoWrite
;
3329 pc
.CommandStreamerStallEnable
= true;
3332 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3333 pc
.TextureCacheInvalidationEnable
= true;
3334 pc
.ConstantCacheInvalidationEnable
= true;
3335 pc
.StateCacheInvalidationEnable
= true;
3336 pc
.InstructionCacheInvalidateEnable
= true;
3337 pc
.PostSyncOperation
= NoWrite
;
3340 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3344 ps
.PipelineSelection
= pipeline
;
3348 if (devinfo
->is_geminilake
) {
3351 * "This chicken bit works around a hardware issue with barrier logic
3352 * encountered when switching between GPGPU and 3D pipelines. To
3353 * workaround the issue, this mode bit should be set after a pipeline
3357 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3359 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3360 : GLK_BARRIER_MODE_3D_HULL
,
3361 .GLKBarrierModeMask
= 1);
3362 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3366 cmd_buffer
->state
.current_pipeline
= pipeline
;
3370 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3372 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3376 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3378 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3382 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3387 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3389 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3390 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3391 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3392 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3393 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3394 * Depth Flush Bit set, followed by another pipelined depth stall
3395 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3396 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3397 * via a preceding MI_FLUSH)."
3399 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3400 pipe
.DepthStallEnable
= true;
3402 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3403 pipe
.DepthCacheFlushEnable
= true;
3405 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3406 pipe
.DepthStallEnable
= true;
3411 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3413 struct anv_device
*device
= cmd_buffer
->device
;
3414 const struct anv_image_view
*iview
=
3415 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3416 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3418 /* FIXME: Width and Height are wrong */
3420 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3422 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3423 device
->isl_dev
.ds
.size
/ 4);
3427 struct isl_depth_stencil_hiz_emit_info info
= {
3428 .mocs
= device
->default_mocs
,
3432 info
.view
= &iview
->planes
[0].isl
;
3434 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3435 uint32_t depth_plane
=
3436 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3437 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
3439 info
.depth_surf
= &surface
->isl
;
3441 info
.depth_address
=
3442 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3443 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
3444 image
->planes
[depth_plane
].address
.bo
,
3445 image
->planes
[depth_plane
].address
.offset
+
3449 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
3450 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
3451 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
3452 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
3455 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3456 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
3457 image
->planes
[depth_plane
].address
.bo
,
3458 image
->planes
[depth_plane
].address
.offset
+
3459 image
->planes
[depth_plane
].aux_surface
.offset
);
3461 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
3465 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3466 uint32_t stencil_plane
=
3467 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
3468 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
3470 info
.stencil_surf
= &surface
->isl
;
3472 info
.stencil_address
=
3473 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3474 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
3475 image
->planes
[stencil_plane
].address
.bo
,
3476 image
->planes
[stencil_plane
].address
.offset
+
3480 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
3482 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
3486 * This ANDs the view mask of the current subpass with the pending clear
3487 * views in the attachment to get the mask of views active in the subpass
3488 * that still need to be cleared.
3490 static inline uint32_t
3491 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
3492 const struct anv_attachment_state
*att_state
)
3494 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
3498 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
3499 const struct anv_attachment_state
*att_state
)
3501 if (!cmd_state
->subpass
->view_mask
)
3504 uint32_t pending_clear_mask
=
3505 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3507 return pending_clear_mask
& 1;
3511 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
3514 const uint32_t last_subpass_idx
=
3515 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
3516 const struct anv_subpass
*last_subpass
=
3517 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
3518 return last_subpass
== cmd_state
->subpass
;
3522 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
3523 uint32_t subpass_id
)
3525 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3526 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
3527 cmd_state
->subpass
= subpass
;
3529 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
3531 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3532 * different views. If the client asks for instancing, we need to use the
3533 * Instance Data Step Rate to ensure that we repeat the client's
3534 * per-instance data once for each view. Since this bit is in
3535 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
3539 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
3541 /* It is possible to start a render pass with an old pipeline. Because the
3542 * render pass and subpass index are both baked into the pipeline, this is
3543 * highly unlikely. In order to do so, it requires that you have a render
3544 * pass with a single subpass and that you use that render pass twice
3545 * back-to-back and use the same pipeline at the start of the second render
3546 * pass as at the end of the first. In order to avoid unpredictable issues
3547 * with this edge case, we just dirty the pipeline at the start of every
3550 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
3552 /* Accumulate any subpass flushes that need to happen before the subpass */
3553 cmd_buffer
->state
.pending_pipe_bits
|=
3554 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
3556 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
3557 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3559 bool is_multiview
= subpass
->view_mask
!= 0;
3561 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3562 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3563 if (a
== VK_ATTACHMENT_UNUSED
)
3566 assert(a
< cmd_state
->pass
->attachment_count
);
3567 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3569 struct anv_image_view
*iview
= fb
->attachments
[a
];
3570 const struct anv_image
*image
= iview
->image
;
3572 /* A resolve is necessary before use as an input attachment if the clear
3573 * color or auxiliary buffer usage isn't supported by the sampler.
3575 const bool input_needs_resolve
=
3576 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
3577 att_state
->input_aux_usage
!= att_state
->aux_usage
;
3579 VkImageLayout target_layout
;
3580 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
3581 !input_needs_resolve
) {
3582 /* Layout transitions before the final only help to enable sampling
3583 * as an input attachment. If the input attachment supports sampling
3584 * using the auxiliary surface, we can skip such transitions by
3585 * making the target layout one that is CCS-aware.
3587 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
3589 target_layout
= subpass
->attachments
[i
].layout
;
3592 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3593 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3595 uint32_t base_layer
, layer_count
;
3596 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3598 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3599 iview
->planes
[0].isl
.base_level
);
3601 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3602 layer_count
= fb
->layers
;
3605 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3606 iview
->planes
[0].isl
.base_level
, 1,
3607 base_layer
, layer_count
,
3608 att_state
->current_layout
, target_layout
);
3609 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3610 transition_depth_buffer(cmd_buffer
, image
,
3611 att_state
->current_layout
, target_layout
);
3612 att_state
->aux_usage
=
3613 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
3614 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
3616 att_state
->current_layout
= target_layout
;
3618 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
3619 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3621 /* Multi-planar images are not supported as attachments */
3622 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3623 assert(image
->n_planes
== 1);
3625 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
3626 uint32_t clear_layer_count
= fb
->layers
;
3628 if (att_state
->fast_clear
&&
3629 do_first_layer_clear(cmd_state
, att_state
)) {
3630 /* We only support fast-clears on the first layer */
3631 assert(iview
->planes
[0].isl
.base_level
== 0);
3632 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3634 union isl_color_value clear_color
= {};
3635 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
3636 if (iview
->image
->samples
== 1) {
3637 anv_image_ccs_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3638 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
3642 anv_image_mcs_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3643 0, 1, ISL_AUX_OP_FAST_CLEAR
,
3648 clear_layer_count
--;
3650 att_state
->pending_clear_views
&= ~1;
3652 if (att_state
->clear_color_is_zero
) {
3653 /* This image has the auxiliary buffer enabled. We can mark the
3654 * subresource as not needing a resolve because the clear color
3655 * will match what's in every RENDER_SURFACE_STATE object when
3656 * it's being used for sampling.
3658 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3659 VK_IMAGE_ASPECT_COLOR_BIT
,
3660 ANV_FAST_CLEAR_DEFAULT_VALUE
);
3662 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3663 VK_IMAGE_ASPECT_COLOR_BIT
,
3664 ANV_FAST_CLEAR_ANY
);
3668 /* From the VkFramebufferCreateInfo spec:
3670 * "If the render pass uses multiview, then layers must be one and each
3671 * attachment requires a number of layers that is greater than the
3672 * maximum bit index set in the view mask in the subpasses in which it
3675 * So if multiview is active we ignore the number of layers in the
3676 * framebuffer and instead we honor the view mask from the subpass.
3679 assert(image
->n_planes
== 1);
3680 uint32_t pending_clear_mask
=
3681 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3684 for_each_bit(layer_idx
, pending_clear_mask
) {
3686 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
3688 anv_image_clear_color(cmd_buffer
, image
,
3689 VK_IMAGE_ASPECT_COLOR_BIT
,
3690 att_state
->aux_usage
,
3691 iview
->planes
[0].isl
.format
,
3692 iview
->planes
[0].isl
.swizzle
,
3693 iview
->planes
[0].isl
.base_level
,
3696 vk_to_isl_color(att_state
->clear_value
.color
));
3699 att_state
->pending_clear_views
&= ~pending_clear_mask
;
3700 } else if (clear_layer_count
> 0) {
3701 assert(image
->n_planes
== 1);
3702 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3703 att_state
->aux_usage
,
3704 iview
->planes
[0].isl
.format
,
3705 iview
->planes
[0].isl
.swizzle
,
3706 iview
->planes
[0].isl
.base_level
,
3707 base_clear_layer
, clear_layer_count
,
3709 vk_to_isl_color(att_state
->clear_value
.color
));
3711 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
3712 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3713 if (att_state
->fast_clear
&& !is_multiview
) {
3714 /* We currently only support HiZ for single-layer images */
3715 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3716 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
3717 assert(iview
->planes
[0].isl
.base_level
== 0);
3718 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3719 assert(fb
->layers
== 1);
3722 anv_image_hiz_clear(cmd_buffer
, image
,
3723 att_state
->pending_clear_aspects
,
3724 iview
->planes
[0].isl
.base_level
,
3725 iview
->planes
[0].isl
.base_array_layer
,
3726 fb
->layers
, render_area
,
3727 att_state
->clear_value
.depthStencil
.stencil
);
3728 } else if (is_multiview
) {
3729 uint32_t pending_clear_mask
=
3730 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3733 for_each_bit(layer_idx
, pending_clear_mask
) {
3735 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
3737 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3738 att_state
->pending_clear_aspects
,
3739 att_state
->aux_usage
,
3740 iview
->planes
[0].isl
.base_level
,
3743 att_state
->clear_value
.depthStencil
.depth
,
3744 att_state
->clear_value
.depthStencil
.stencil
);
3747 att_state
->pending_clear_views
&= ~pending_clear_mask
;
3749 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3750 att_state
->pending_clear_aspects
,
3751 att_state
->aux_usage
,
3752 iview
->planes
[0].isl
.base_level
,
3753 iview
->planes
[0].isl
.base_array_layer
,
3754 fb
->layers
, render_area
,
3755 att_state
->clear_value
.depthStencil
.depth
,
3756 att_state
->clear_value
.depthStencil
.stencil
);
3759 assert(att_state
->pending_clear_aspects
== 0);
3763 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
3764 image
->planes
[0].aux_surface
.isl
.size
> 0 &&
3765 iview
->planes
[0].isl
.base_level
== 0 &&
3766 iview
->planes
[0].isl
.base_array_layer
== 0) {
3767 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
3768 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
3769 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3770 false /* copy to ss */);
3773 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
3774 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
3775 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
3776 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3777 false /* copy to ss */);
3781 if (subpass
->attachments
[i
].usage
==
3782 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
3783 /* We assume that if we're starting a subpass, we're going to do some
3784 * rendering so we may end up with compressed data.
3786 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
3787 VK_IMAGE_ASPECT_COLOR_BIT
,
3788 att_state
->aux_usage
,
3789 iview
->planes
[0].isl
.base_level
,
3790 iview
->planes
[0].isl
.base_array_layer
,
3792 } else if (subpass
->attachments
[i
].usage
==
3793 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
3794 /* We may be writing depth or stencil so we need to mark the surface.
3795 * Unfortunately, there's no way to know at this point whether the
3796 * depth or stencil tests used will actually write to the surface.
3798 * Even though stencil may be plane 1, it always shares a base_level
3801 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
3802 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3803 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3804 VK_IMAGE_ASPECT_DEPTH_BIT
,
3805 att_state
->aux_usage
,
3806 ds_view
->base_level
,
3807 ds_view
->base_array_layer
,
3810 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
3811 /* Even though stencil may be plane 1, it always shares a
3812 * base_level with depth.
3814 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3815 VK_IMAGE_ASPECT_STENCIL_BIT
,
3817 ds_view
->base_level
,
3818 ds_view
->base_array_layer
,
3823 /* If multiview is enabled, then we are only done clearing when we no
3824 * longer have pending layers to clear, or when we have processed the
3825 * last subpass that uses this attachment.
3827 if (!is_multiview
||
3828 att_state
->pending_clear_views
== 0 ||
3829 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
3830 att_state
->pending_clear_aspects
= 0;
3833 att_state
->pending_load_aspects
= 0;
3836 cmd_buffer_emit_depth_stencil(cmd_buffer
);
3840 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
3842 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3843 struct anv_subpass
*subpass
= cmd_state
->subpass
;
3844 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
3846 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
3848 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3849 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3850 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3851 if (a
== VK_ATTACHMENT_UNUSED
)
3854 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
3857 assert(a
< cmd_state
->pass
->attachment_count
);
3858 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3859 struct anv_image_view
*iview
= fb
->attachments
[a
];
3860 const struct anv_image
*image
= iview
->image
;
3862 /* Transition the image into the final layout for this render pass */
3863 VkImageLayout target_layout
=
3864 cmd_state
->pass
->attachments
[a
].final_layout
;
3866 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3867 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3869 uint32_t base_layer
, layer_count
;
3870 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3872 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3873 iview
->planes
[0].isl
.base_level
);
3875 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3876 layer_count
= fb
->layers
;
3879 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3880 iview
->planes
[0].isl
.base_level
, 1,
3881 base_layer
, layer_count
,
3882 att_state
->current_layout
, target_layout
);
3883 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3884 transition_depth_buffer(cmd_buffer
, image
,
3885 att_state
->current_layout
, target_layout
);
3889 /* Accumulate any subpass flushes that need to happen after the subpass.
3890 * Yes, they do get accumulated twice in the NextSubpass case but since
3891 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
3892 * ORing the bits in twice so it's harmless.
3894 cmd_buffer
->state
.pending_pipe_bits
|=
3895 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
3898 void genX(CmdBeginRenderPass
)(
3899 VkCommandBuffer commandBuffer
,
3900 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3901 VkSubpassContents contents
)
3903 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3904 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3905 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3907 cmd_buffer
->state
.framebuffer
= framebuffer
;
3908 cmd_buffer
->state
.pass
= pass
;
3909 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3911 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
3913 /* If we failed to setup the attachments we should not try to go further */
3914 if (result
!= VK_SUCCESS
) {
3915 assert(anv_batch_has_error(&cmd_buffer
->batch
));
3919 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3921 cmd_buffer_begin_subpass(cmd_buffer
, 0);
3924 void genX(CmdBeginRenderPass2KHR
)(
3925 VkCommandBuffer commandBuffer
,
3926 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
3927 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
3929 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
3930 pSubpassBeginInfo
->contents
);
3933 void genX(CmdNextSubpass
)(
3934 VkCommandBuffer commandBuffer
,
3935 VkSubpassContents contents
)
3937 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3939 if (anv_batch_has_error(&cmd_buffer
->batch
))
3942 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3944 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
3945 cmd_buffer_end_subpass(cmd_buffer
);
3946 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
3949 void genX(CmdNextSubpass2KHR
)(
3950 VkCommandBuffer commandBuffer
,
3951 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
3952 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
3954 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
3957 void genX(CmdEndRenderPass
)(
3958 VkCommandBuffer commandBuffer
)
3960 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3962 if (anv_batch_has_error(&cmd_buffer
->batch
))
3965 cmd_buffer_end_subpass(cmd_buffer
);
3967 cmd_buffer
->state
.hiz_enabled
= false;
3970 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
3973 /* Remove references to render pass specific state. This enables us to
3974 * detect whether or not we're in a renderpass.
3976 cmd_buffer
->state
.framebuffer
= NULL
;
3977 cmd_buffer
->state
.pass
= NULL
;
3978 cmd_buffer
->state
.subpass
= NULL
;
3981 void genX(CmdEndRenderPass2KHR
)(
3982 VkCommandBuffer commandBuffer
,
3983 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
3985 genX(CmdEndRenderPass
)(commandBuffer
);