2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
29 #include "common/gen_l3_config.h"
30 #include "genxml/gen_macros.h"
31 #include "genxml/genX_pack.h"
34 emit_lrm(struct anv_batch
*batch
,
35 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
37 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
38 lrm
.RegisterAddress
= reg
;
39 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
44 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
46 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
47 lri
.RegisterOffset
= reg
;
53 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
55 struct anv_device
*device
= cmd_buffer
->device
;
57 /* XXX: Do we need this on more than just BDW? */
59 /* Emit a render target cache flush.
61 * This isn't documented anywhere in the PRM. However, it seems to be
62 * necessary prior to changing the surface state base adress. Without
63 * this, we get GPU hangs when using multi-level command buffers which
64 * clear depth, reset state base address, and then go render stuff.
66 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
67 pc
.RenderTargetCacheFlushEnable
= true;
71 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
72 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
73 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
74 sba
.GeneralStateBaseAddressModifyEnable
= true;
76 sba
.SurfaceStateBaseAddress
=
77 anv_cmd_buffer_surface_base_address(cmd_buffer
);
78 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
79 sba
.SurfaceStateBaseAddressModifyEnable
= true;
81 sba
.DynamicStateBaseAddress
=
82 (struct anv_address
) { &device
->dynamic_state_block_pool
.bo
, 0 };
83 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
84 sba
.DynamicStateBaseAddressModifyEnable
= true;
86 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
87 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
88 sba
.IndirectObjectBaseAddressModifyEnable
= true;
90 sba
.InstructionBaseAddress
=
91 (struct anv_address
) { &device
->instruction_block_pool
.bo
, 0 };
92 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
93 sba
.InstructionBaseAddressModifyEnable
= true;
96 /* Broadwell requires that we specify a buffer size for a bunch of
97 * these fields. However, since we will be growing the BO's live, we
98 * just set them all to the maximum.
100 sba
.GeneralStateBufferSize
= 0xfffff;
101 sba
.GeneralStateBufferSizeModifyEnable
= true;
102 sba
.DynamicStateBufferSize
= 0xfffff;
103 sba
.DynamicStateBufferSizeModifyEnable
= true;
104 sba
.IndirectObjectBufferSize
= 0xfffff;
105 sba
.IndirectObjectBufferSizeModifyEnable
= true;
106 sba
.InstructionBufferSize
= 0xfffff;
107 sba
.InstructionBuffersizeModifyEnable
= true;
111 /* After re-setting the surface state base address, we have to do some
112 * cache flusing so that the sampler engine will pick up the new
113 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
114 * Shared Function > 3D Sampler > State > State Caching (page 96):
116 * Coherency with system memory in the state cache, like the texture
117 * cache is handled partially by software. It is expected that the
118 * command stream or shader will issue Cache Flush operation or
119 * Cache_Flush sampler message to ensure that the L1 cache remains
120 * coherent with system memory.
124 * Whenever the value of the Dynamic_State_Base_Addr,
125 * Surface_State_Base_Addr are altered, the L1 state cache must be
126 * invalidated to ensure the new surface or sampler state is fetched
127 * from system memory.
129 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
130 * which, according the PIPE_CONTROL instruction documentation in the
133 * Setting this bit is independent of any other bit in this packet.
134 * This bit controls the invalidation of the L1 and L2 state caches
135 * at the top of the pipe i.e. at the parsing time.
137 * Unfortunately, experimentation seems to indicate that state cache
138 * invalidation through a PIPE_CONTROL does nothing whatsoever in
139 * regards to surface state and binding tables. In stead, it seems that
140 * invalidating the texture cache is what is actually needed.
142 * XXX: As far as we have been able to determine through
143 * experimentation, shows that flush the texture cache appears to be
144 * sufficient. The theory here is that all of the sampling/rendering
145 * units cache the binding table in the texture cache. However, we have
146 * yet to be able to actually confirm this.
148 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
149 pc
.TextureCacheInvalidationEnable
= true;
154 genX(BeginCommandBuffer
)(
155 VkCommandBuffer commandBuffer
,
156 const VkCommandBufferBeginInfo
* pBeginInfo
)
158 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
160 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
161 * command buffer's state. Otherwise, we must *reset* its state. In both
164 * From the Vulkan 1.0 spec:
166 * If a command buffer is in the executable state and the command buffer
167 * was allocated from a command pool with the
168 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
169 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
170 * as if vkResetCommandBuffer had been called with
171 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
172 * the command buffer in the recording state.
174 anv_cmd_buffer_reset(cmd_buffer
);
176 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
178 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
179 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
181 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
183 if (cmd_buffer
->usage_flags
&
184 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
185 cmd_buffer
->state
.framebuffer
=
186 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
187 cmd_buffer
->state
.pass
=
188 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
189 cmd_buffer
->state
.subpass
=
190 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
192 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
199 genX(EndCommandBuffer
)(
200 VkCommandBuffer commandBuffer
)
202 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
204 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
210 genX(CmdExecuteCommands
)(
211 VkCommandBuffer commandBuffer
,
212 uint32_t commandBufferCount
,
213 const VkCommandBuffer
* pCmdBuffers
)
215 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
217 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
219 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
220 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
222 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
224 anv_cmd_buffer_add_secondary(primary
, secondary
);
227 /* Each of the secondary command buffers will use its own state base
228 * address. We need to re-emit state base address for the primary after
229 * all of the secondaries are done.
231 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
234 genX(cmd_buffer_emit_state_base_address
)(primary
);
237 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
238 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
239 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
242 * Program the hardware to use the specified L3 configuration.
245 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
246 const struct gen_l3_config
*cfg
)
249 if (cfg
== cmd_buffer
->state
.current_l3_config
)
252 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
253 fprintf(stderr
, "L3 config transition: ");
254 gen_dump_l3_config(cfg
, stderr
);
257 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
259 /* According to the hardware docs, the L3 partitioning can only be changed
260 * while the pipeline is completely drained and the caches are flushed,
261 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
263 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
264 pc
.DCFlushEnable
= true;
265 pc
.PostSyncOperation
= NoWrite
;
266 pc
.CommandStreamerStallEnable
= true;
269 /* ...followed by a second pipelined PIPE_CONTROL that initiates
270 * invalidation of the relevant caches. Note that because RO invalidation
271 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
272 * command is processed by the CS) we cannot combine it with the previous
273 * stalling flush as the hardware documentation suggests, because that
274 * would cause the CS to stall on previous rendering *after* RO
275 * invalidation and wouldn't prevent the RO caches from being polluted by
276 * concurrent rendering before the stall completes. This intentionally
277 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
278 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
279 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
280 * already guarantee that there is no concurrent GPGPU kernel execution
281 * (see SKL HSD 2132585).
283 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
284 pc
.TextureCacheInvalidationEnable
= true;
285 pc
.ConstantCacheInvalidationEnable
= true;
286 pc
.InstructionCacheInvalidateEnable
= true;
287 pc
.StateCacheInvalidationEnable
= true;
288 pc
.PostSyncOperation
= NoWrite
;
291 /* Now send a third stalling flush to make sure that invalidation is
292 * complete when the L3 configuration registers are modified.
294 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
295 pc
.DCFlushEnable
= true;
296 pc
.PostSyncOperation
= NoWrite
;
297 pc
.CommandStreamerStallEnable
= true;
302 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
305 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
306 .SLMEnable
= has_slm
,
307 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
308 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
309 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
310 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
312 /* Set up the L3 partitioning. */
313 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
317 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
318 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
320 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
322 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
325 assert(!cfg
->n
[GEN_L3P_ALL
]);
327 /* When enabled SLM only uses a portion of the L3 on half of the banks,
328 * the matching space on the remaining banks has to be allocated to a
329 * client (URB for all validated configurations) set to the
330 * lower-bandwidth 2-bank address hashing mode.
332 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
333 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
334 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
336 /* Minimum number of ways that can be allocated to the URB. */
337 const unsigned n0_urb
= (devinfo
->is_baytrail
? 32 : 0);
338 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
340 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
341 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
342 .ConvertDC_UC
= !has_dc
,
343 .ConvertIS_UC
= !has_is
,
344 .ConvertC_UC
= !has_c
,
345 .ConvertT_UC
= !has_t
);
347 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
348 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
349 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
351 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
352 .SLMEnable
= has_slm
,
353 .URBLowBandwidth
= urb_low_bw
,
354 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
356 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
358 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
359 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
361 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
362 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
364 .CAllocation
= cfg
->n
[GEN_L3P_C
],
366 .TAllocation
= cfg
->n
[GEN_L3P_T
],
369 /* Set up the L3 partitioning. */
370 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
371 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
372 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
375 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
376 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
377 * them disabled to avoid crashing the system hard.
379 uint32_t scratch1
, chicken3
;
380 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
381 .L3AtomicDisable
= !has_dc
);
382 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
383 .L3AtomicDisableMask
= true,
384 .L3AtomicDisable
= !has_dc
);
385 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
386 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
392 cmd_buffer
->state
.current_l3_config
= cfg
;
396 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
398 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
400 /* Flushes are pipelined while invalidations are handled immediately.
401 * Therefore, if we're flushing anything then we need to schedule a stall
402 * before any invalidations can happen.
404 if (bits
& ANV_PIPE_FLUSH_BITS
)
405 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
407 /* If we're going to do an invalidate and we have a pending CS stall that
408 * has yet to be resolved, we do the CS stall now.
410 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
411 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
412 bits
|= ANV_PIPE_CS_STALL_BIT
;
413 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
416 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
417 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
418 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
419 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
420 pipe
.RenderTargetCacheFlushEnable
=
421 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
423 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
424 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
425 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
428 * According to the Broadwell documentation, any PIPE_CONTROL with the
429 * "Command Streamer Stall" bit set must also have another bit set,
430 * with five different options:
432 * - Render Target Cache Flush
433 * - Depth Cache Flush
434 * - Stall at Pixel Scoreboard
435 * - Post-Sync Operation
439 * I chose "Stall at Pixel Scoreboard" since that's what we use in
440 * mesa and it seems to work fine. The choice is fairly arbitrary.
442 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
443 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
444 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
445 pipe
.StallAtPixelScoreboard
= true;
448 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
451 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
452 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
453 pipe
.StateCacheInvalidationEnable
=
454 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
455 pipe
.ConstantCacheInvalidationEnable
=
456 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
457 pipe
.VFCacheInvalidationEnable
=
458 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
459 pipe
.TextureCacheInvalidationEnable
=
460 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
461 pipe
.InstructionCacheInvalidateEnable
=
462 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
465 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
468 cmd_buffer
->state
.pending_pipe_bits
= bits
;
471 void genX(CmdPipelineBarrier
)(
472 VkCommandBuffer commandBuffer
,
473 VkPipelineStageFlags srcStageMask
,
474 VkPipelineStageFlags destStageMask
,
476 uint32_t memoryBarrierCount
,
477 const VkMemoryBarrier
* pMemoryBarriers
,
478 uint32_t bufferMemoryBarrierCount
,
479 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
480 uint32_t imageMemoryBarrierCount
,
481 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
483 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
486 /* XXX: Right now, we're really dumb and just flush whatever categories
487 * the app asks for. One of these days we may make this a bit better
488 * but right now that's all the hardware allows for in most areas.
490 VkAccessFlags src_flags
= 0;
491 VkAccessFlags dst_flags
= 0;
493 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
494 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
495 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
498 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
499 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
500 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
503 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
504 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
505 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
508 enum anv_pipe_bits pipe_bits
= 0;
510 for_each_bit(b
, src_flags
) {
511 switch ((VkAccessFlagBits
)(1 << b
)) {
512 case VK_ACCESS_SHADER_WRITE_BIT
:
513 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
515 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
516 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
518 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
519 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
521 case VK_ACCESS_TRANSFER_WRITE_BIT
:
522 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
523 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
526 break; /* Nothing to do */
530 for_each_bit(b
, dst_flags
) {
531 switch ((VkAccessFlagBits
)(1 << b
)) {
532 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
533 case VK_ACCESS_INDEX_READ_BIT
:
534 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
535 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
537 case VK_ACCESS_UNIFORM_READ_BIT
:
538 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
539 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
541 case VK_ACCESS_SHADER_READ_BIT
:
542 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
543 case VK_ACCESS_TRANSFER_READ_BIT
:
544 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
547 break; /* Nothing to do */
551 cmd_buffer
->state
.pending_pipe_bits
|= pipe_bits
;
555 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
557 VkShaderStageFlags stages
= cmd_buffer
->state
.pipeline
->active_stages
;
559 /* In order to avoid thrash, we assume that vertex and fragment stages
560 * always exist. In the rare case where one is missing *and* the other
561 * uses push concstants, this may be suboptimal. However, avoiding stalls
562 * seems more important.
564 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
566 if (stages
== cmd_buffer
->state
.push_constant_stages
)
570 const unsigned push_constant_kb
= 32;
572 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
574 const unsigned push_constant_kb
= 16;
577 const unsigned num_stages
=
578 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
579 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
581 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
582 * units of 2KB. Incidentally, these are the same platforms that have
583 * 32KB worth of push constant space.
585 if (push_constant_kb
== 32)
586 size_per_stage
&= ~1u;
588 uint32_t kb_used
= 0;
589 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
590 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
591 anv_batch_emit(&cmd_buffer
->batch
,
592 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
593 alloc
._3DCommandSubOpcode
= 18 + i
;
594 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
595 alloc
.ConstantBufferSize
= push_size
;
597 kb_used
+= push_size
;
600 anv_batch_emit(&cmd_buffer
->batch
,
601 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
602 alloc
.ConstantBufferOffset
= kb_used
;
603 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
606 cmd_buffer
->state
.push_constant_stages
= stages
;
608 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
610 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
611 * the next 3DPRIMITIVE command after programming the
612 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
614 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
615 * pipeline setup, we need to dirty push constants.
617 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
621 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
622 struct anv_state state
, struct anv_bo
*bo
,
625 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
627 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
628 state
.offset
+ isl_dev
->ss
.addr_offset
, bo
, offset
);
631 static struct anv_state
632 alloc_null_surface_state(struct anv_cmd_buffer
*cmd_buffer
,
633 struct anv_framebuffer
*fb
)
635 struct anv_state state
=
636 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
638 struct GENX(RENDER_SURFACE_STATE
) null_ss
= {
639 .SurfaceType
= SURFTYPE_NULL
,
640 .SurfaceArray
= fb
->layers
> 0,
641 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
645 .TiledSurface
= true,
647 .Width
= fb
->width
- 1,
648 .Height
= fb
->height
- 1,
649 .Depth
= fb
->layers
- 1,
650 .RenderTargetViewExtent
= fb
->layers
- 1,
653 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
.map
, &null_ss
);
655 if (!cmd_buffer
->device
->info
.has_llc
)
656 anv_state_clflush(state
);
663 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
664 gl_shader_stage stage
,
665 struct anv_state
*bt_state
)
667 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
668 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
669 struct anv_pipeline
*pipeline
;
670 uint32_t bias
, state_offset
;
673 case MESA_SHADER_COMPUTE
:
674 pipeline
= cmd_buffer
->state
.compute_pipeline
;
678 pipeline
= cmd_buffer
->state
.pipeline
;
683 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
684 *bt_state
= (struct anv_state
) { 0, };
688 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
689 if (bias
+ map
->surface_count
== 0) {
690 *bt_state
= (struct anv_state
) { 0, };
694 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
695 bias
+ map
->surface_count
,
697 uint32_t *bt_map
= bt_state
->map
;
699 if (bt_state
->map
== NULL
)
700 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
702 if (stage
== MESA_SHADER_COMPUTE
&&
703 get_cs_prog_data(cmd_buffer
->state
.compute_pipeline
)->uses_num_work_groups
) {
704 struct anv_bo
*bo
= cmd_buffer
->state
.num_workgroups_bo
;
705 uint32_t bo_offset
= cmd_buffer
->state
.num_workgroups_offset
;
707 struct anv_state surface_state
;
709 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
711 const enum isl_format format
=
712 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
713 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
714 format
, bo_offset
, 12, 1);
716 bt_map
[0] = surface_state
.offset
+ state_offset
;
717 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
720 if (map
->surface_count
== 0)
723 if (map
->image_count
> 0) {
725 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
726 if (result
!= VK_SUCCESS
)
729 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
733 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
734 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
736 struct anv_state surface_state
;
740 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
741 /* Color attachment binding */
742 assert(stage
== MESA_SHADER_FRAGMENT
);
743 assert(binding
->binding
== 0);
744 if (binding
->index
< subpass
->color_count
) {
745 const struct anv_image_view
*iview
=
746 fb
->attachments
[subpass
->color_attachments
[binding
->index
]];
748 assert(iview
->color_rt_surface_state
.alloc_size
);
749 surface_state
= iview
->color_rt_surface_state
;
750 add_surface_state_reloc(cmd_buffer
, iview
->color_rt_surface_state
,
751 iview
->bo
, iview
->offset
);
753 /* Null render target */
754 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
755 surface_state
= alloc_null_surface_state(cmd_buffer
, fb
);
758 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
762 struct anv_descriptor_set
*set
=
763 cmd_buffer
->state
.descriptors
[binding
->set
];
764 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
765 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
767 switch (desc
->type
) {
768 case VK_DESCRIPTOR_TYPE_SAMPLER
:
769 /* Nothing for us to do here */
772 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
773 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
774 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
775 surface_state
= desc
->image_view
->sampler_surface_state
;
776 assert(surface_state
.alloc_size
);
777 bo
= desc
->image_view
->bo
;
778 bo_offset
= desc
->image_view
->offset
;
781 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
782 surface_state
= desc
->image_view
->storage_surface_state
;
783 assert(surface_state
.alloc_size
);
784 bo
= desc
->image_view
->bo
;
785 bo_offset
= desc
->image_view
->offset
;
787 struct brw_image_param
*image_param
=
788 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
790 *image_param
= desc
->image_view
->storage_image_param
;
791 image_param
->surface_idx
= bias
+ s
;
795 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
796 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
797 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
798 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
799 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
800 surface_state
= desc
->buffer_view
->surface_state
;
801 assert(surface_state
.alloc_size
);
802 bo
= desc
->buffer_view
->bo
;
803 bo_offset
= desc
->buffer_view
->offset
;
806 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
807 surface_state
= desc
->buffer_view
->storage_surface_state
;
808 assert(surface_state
.alloc_size
);
809 bo
= desc
->buffer_view
->bo
;
810 bo_offset
= desc
->buffer_view
->offset
;
812 struct brw_image_param
*image_param
=
813 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
815 *image_param
= desc
->buffer_view
->storage_image_param
;
816 image_param
->surface_idx
= bias
+ s
;
820 assert(!"Invalid descriptor type");
824 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
825 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
827 assert(image
== map
->image_count
);
830 if (!cmd_buffer
->device
->info
.has_llc
)
831 anv_state_clflush(*bt_state
);
837 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
838 gl_shader_stage stage
,
839 struct anv_state
*state
)
841 struct anv_pipeline
*pipeline
;
843 if (stage
== MESA_SHADER_COMPUTE
)
844 pipeline
= cmd_buffer
->state
.compute_pipeline
;
846 pipeline
= cmd_buffer
->state
.pipeline
;
848 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
849 *state
= (struct anv_state
) { 0, };
853 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
854 if (map
->sampler_count
== 0) {
855 *state
= (struct anv_state
) { 0, };
859 uint32_t size
= map
->sampler_count
* 16;
860 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
862 if (state
->map
== NULL
)
863 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
865 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
866 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
867 struct anv_descriptor_set
*set
=
868 cmd_buffer
->state
.descriptors
[binding
->set
];
869 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
870 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
872 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
873 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
876 struct anv_sampler
*sampler
= desc
->sampler
;
878 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
879 * happens to be zero.
884 memcpy(state
->map
+ (s
* 16),
885 sampler
->state
, sizeof(sampler
->state
));
888 if (!cmd_buffer
->device
->info
.has_llc
)
889 anv_state_clflush(*state
);
895 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
897 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
898 cmd_buffer
->state
.pipeline
->active_stages
;
900 VkResult result
= VK_SUCCESS
;
901 anv_foreach_stage(s
, dirty
) {
902 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
903 if (result
!= VK_SUCCESS
)
905 result
= emit_binding_table(cmd_buffer
, s
,
906 &cmd_buffer
->state
.binding_tables
[s
]);
907 if (result
!= VK_SUCCESS
)
911 if (result
!= VK_SUCCESS
) {
912 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
914 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
915 assert(result
== VK_SUCCESS
);
917 /* Re-emit state base addresses so we get the new surface state base
918 * address before we start emitting binding tables etc.
920 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
922 /* Re-emit all active binding tables */
923 dirty
|= cmd_buffer
->state
.pipeline
->active_stages
;
924 anv_foreach_stage(s
, dirty
) {
925 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
926 if (result
!= VK_SUCCESS
)
928 result
= emit_binding_table(cmd_buffer
, s
,
929 &cmd_buffer
->state
.binding_tables
[s
]);
930 if (result
!= VK_SUCCESS
)
935 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
941 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
944 static const uint32_t sampler_state_opcodes
[] = {
945 [MESA_SHADER_VERTEX
] = 43,
946 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
947 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
948 [MESA_SHADER_GEOMETRY
] = 46,
949 [MESA_SHADER_FRAGMENT
] = 47,
950 [MESA_SHADER_COMPUTE
] = 0,
953 static const uint32_t binding_table_opcodes
[] = {
954 [MESA_SHADER_VERTEX
] = 38,
955 [MESA_SHADER_TESS_CTRL
] = 39,
956 [MESA_SHADER_TESS_EVAL
] = 40,
957 [MESA_SHADER_GEOMETRY
] = 41,
958 [MESA_SHADER_FRAGMENT
] = 42,
959 [MESA_SHADER_COMPUTE
] = 0,
962 anv_foreach_stage(s
, stages
) {
963 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
964 anv_batch_emit(&cmd_buffer
->batch
,
965 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
966 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
967 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
971 /* Always emit binding table pointers if we're asked to, since on SKL
972 * this is what flushes push constants. */
973 anv_batch_emit(&cmd_buffer
->batch
,
974 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
975 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
976 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
982 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
984 static const uint32_t push_constant_opcodes
[] = {
985 [MESA_SHADER_VERTEX
] = 21,
986 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
987 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
988 [MESA_SHADER_GEOMETRY
] = 22,
989 [MESA_SHADER_FRAGMENT
] = 23,
990 [MESA_SHADER_COMPUTE
] = 0,
993 VkShaderStageFlags flushed
= 0;
995 anv_foreach_stage(stage
, cmd_buffer
->state
.push_constants_dirty
) {
996 if (stage
== MESA_SHADER_COMPUTE
)
999 struct anv_state state
= anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
1001 if (state
.offset
== 0) {
1002 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
)
1003 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
1005 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
1006 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
],
1007 c
.ConstantBody
= (struct GENX(3DSTATE_CONSTANT_BODY
)) {
1009 .PointerToConstantBuffer2
= { &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, state
.offset
},
1010 .ConstantBuffer2ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1012 .PointerToConstantBuffer0
= { .offset
= state
.offset
},
1013 .ConstantBuffer0ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1019 flushed
|= mesa_to_vk_shader_stage(stage
);
1022 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_ALL_GRAPHICS
;
1028 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1030 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1033 uint32_t vb_emit
= cmd_buffer
->state
.vb_dirty
& pipeline
->vb_used
;
1035 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
1037 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1039 genX(flush_pipeline_select_3d
)(cmd_buffer
);
1042 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
1043 const uint32_t num_dwords
= 1 + num_buffers
* 4;
1045 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
1046 GENX(3DSTATE_VERTEX_BUFFERS
));
1048 for_each_bit(vb
, vb_emit
) {
1049 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1050 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
1052 struct GENX(VERTEX_BUFFER_STATE
) state
= {
1053 .VertexBufferIndex
= vb
,
1056 .MemoryObjectControlState
= GENX(MOCS
),
1058 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
1059 .InstanceDataStepRate
= 1,
1060 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1063 .AddressModifyEnable
= true,
1064 .BufferPitch
= pipeline
->binding_stride
[vb
],
1065 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
1068 .BufferSize
= buffer
->size
- offset
1070 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
1074 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
1079 cmd_buffer
->state
.vb_dirty
&= ~vb_emit
;
1081 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1082 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1084 /* The exact descriptor layout is pulled from the pipeline, so we need
1085 * to re-emit binding tables on every pipeline change.
1087 cmd_buffer
->state
.descriptors_dirty
|=
1088 cmd_buffer
->state
.pipeline
->active_stages
;
1090 /* If the pipeline changed, we may need to re-allocate push constant
1093 cmd_buffer_alloc_push_constants(cmd_buffer
);
1097 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
1098 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
1099 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
1101 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
1102 * stall needs to be sent just prior to any 3DSTATE_VS,
1103 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
1104 * 3DSTATE_BINDING_TABLE_POINTER_VS,
1105 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
1106 * PIPE_CONTROL needs to be sent before any combination of VS
1107 * associated 3DSTATE."
1109 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1110 pc
.DepthStallEnable
= true;
1111 pc
.PostSyncOperation
= WriteImmediateData
;
1113 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1118 /* Render targets live in the same binding table as fragment descriptors */
1119 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
1120 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
1122 /* We emit the binding tables and sampler tables first, then emit push
1123 * constants and then finally emit binding table and sampler table
1124 * pointers. It has to happen in this order, since emitting the binding
1125 * tables may change the push constants (in case of storage images). After
1126 * emitting push constants, on SKL+ we have to emit the corresponding
1127 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
1130 if (cmd_buffer
->state
.descriptors_dirty
)
1131 dirty
= flush_descriptor_sets(cmd_buffer
);
1133 if (cmd_buffer
->state
.push_constants_dirty
) {
1135 /* On Sky Lake and later, the binding table pointers commands are
1136 * what actually flush the changes to push constant state so we need
1137 * to dirty them so they get re-emitted below.
1139 dirty
|= cmd_buffer_flush_push_constants(cmd_buffer
);
1141 cmd_buffer_flush_push_constants(cmd_buffer
);
1146 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
1148 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
1149 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
1151 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
1152 ANV_CMD_DIRTY_PIPELINE
)) {
1153 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
1154 pipeline
->depth_clamp_enable
);
1157 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
1158 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
1160 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
1162 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1166 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
1167 struct anv_bo
*bo
, uint32_t offset
)
1169 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
1170 GENX(3DSTATE_VERTEX_BUFFERS
));
1172 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
1173 &(struct GENX(VERTEX_BUFFER_STATE
)) {
1174 .VertexBufferIndex
= 32, /* Reserved for this */
1175 .AddressModifyEnable
= true,
1178 .MemoryObjectControlState
= GENX(MOCS
),
1179 .BufferStartingAddress
= { bo
, offset
},
1182 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1183 .BufferStartingAddress
= { bo
, offset
},
1184 .EndAddress
= { bo
, offset
+ 8 },
1190 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
1191 uint32_t base_vertex
, uint32_t base_instance
)
1193 struct anv_state id_state
=
1194 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
1196 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
1197 ((uint32_t *)id_state
.map
)[1] = base_instance
;
1199 if (!cmd_buffer
->device
->info
.has_llc
)
1200 anv_state_clflush(id_state
);
1202 emit_base_vertex_instance_bo(cmd_buffer
,
1203 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, id_state
.offset
);
1207 VkCommandBuffer commandBuffer
,
1208 uint32_t vertexCount
,
1209 uint32_t instanceCount
,
1210 uint32_t firstVertex
,
1211 uint32_t firstInstance
)
1213 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1214 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1215 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1217 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1219 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1220 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
1222 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1223 prim
.VertexAccessType
= SEQUENTIAL
;
1224 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1225 prim
.VertexCountPerInstance
= vertexCount
;
1226 prim
.StartVertexLocation
= firstVertex
;
1227 prim
.InstanceCount
= instanceCount
;
1228 prim
.StartInstanceLocation
= firstInstance
;
1229 prim
.BaseVertexLocation
= 0;
1233 void genX(CmdDrawIndexed
)(
1234 VkCommandBuffer commandBuffer
,
1235 uint32_t indexCount
,
1236 uint32_t instanceCount
,
1237 uint32_t firstIndex
,
1238 int32_t vertexOffset
,
1239 uint32_t firstInstance
)
1241 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1242 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1243 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1245 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1247 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1248 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
1250 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1251 prim
.VertexAccessType
= RANDOM
;
1252 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1253 prim
.VertexCountPerInstance
= indexCount
;
1254 prim
.StartVertexLocation
= firstIndex
;
1255 prim
.InstanceCount
= instanceCount
;
1256 prim
.StartInstanceLocation
= firstInstance
;
1257 prim
.BaseVertexLocation
= vertexOffset
;
1261 /* Auto-Draw / Indirect Registers */
1262 #define GEN7_3DPRIM_END_OFFSET 0x2420
1263 #define GEN7_3DPRIM_START_VERTEX 0x2430
1264 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
1265 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
1266 #define GEN7_3DPRIM_START_INSTANCE 0x243C
1267 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
1269 void genX(CmdDrawIndirect
)(
1270 VkCommandBuffer commandBuffer
,
1272 VkDeviceSize offset
,
1276 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1277 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1278 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1279 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1280 struct anv_bo
*bo
= buffer
->bo
;
1281 uint32_t bo_offset
= buffer
->offset
+ offset
;
1283 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1285 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1286 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
1288 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1289 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1290 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1291 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
1292 emit_lri(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
1294 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1295 prim
.IndirectParameterEnable
= true;
1296 prim
.VertexAccessType
= SEQUENTIAL
;
1297 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1301 void genX(CmdDrawIndexedIndirect
)(
1302 VkCommandBuffer commandBuffer
,
1304 VkDeviceSize offset
,
1308 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1309 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1310 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1311 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1312 struct anv_bo
*bo
= buffer
->bo
;
1313 uint32_t bo_offset
= buffer
->offset
+ offset
;
1315 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1317 /* TODO: We need to stomp base vertex to 0 somehow */
1318 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1319 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
1321 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1322 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1323 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1324 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
1325 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
1327 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1328 prim
.IndirectParameterEnable
= true;
1329 prim
.VertexAccessType
= RANDOM
;
1330 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1335 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
1337 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1338 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
1341 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
1342 if (result
!= VK_SUCCESS
)
1344 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1345 if (result
!= VK_SUCCESS
)
1348 struct anv_state push_state
= anv_cmd_buffer_cs_push_constants(cmd_buffer
);
1350 if (push_state
.alloc_size
) {
1351 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
1352 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
1353 curbe
.CURBEDataStartAddress
= push_state
.offset
;
1357 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
1358 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
1359 .BindingTablePointer
= surfaces
.offset
,
1360 .SamplerStatePointer
= samplers
.offset
,
1362 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
1364 struct anv_state state
=
1365 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
1366 pipeline
->interface_descriptor_data
,
1367 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
1370 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
1371 anv_batch_emit(&cmd_buffer
->batch
,
1372 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
1373 mid
.InterfaceDescriptorTotalLength
= size
;
1374 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
1381 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1383 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1384 MAYBE_UNUSED VkResult result
;
1386 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
1388 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1390 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
1392 if (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)
1393 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1395 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
1396 (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)) {
1397 /* FIXME: figure out descriptors for gen7 */
1398 result
= flush_compute_descriptor_set(cmd_buffer
);
1399 assert(result
== VK_SUCCESS
);
1400 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
1403 cmd_buffer
->state
.compute_dirty
= 0;
1405 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1411 verify_cmd_parser(const struct anv_device
*device
,
1412 int required_version
,
1413 const char *function
)
1415 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
1416 vk_errorf(VK_ERROR_FEATURE_NOT_PRESENT
,
1417 "cmd parser version %d is required for %s",
1418 required_version
, function
);
1427 void genX(CmdDispatch
)(
1428 VkCommandBuffer commandBuffer
,
1433 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1434 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1435 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1437 if (prog_data
->uses_num_work_groups
) {
1438 struct anv_state state
=
1439 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
1440 uint32_t *sizes
= state
.map
;
1444 if (!cmd_buffer
->device
->info
.has_llc
)
1445 anv_state_clflush(state
);
1446 cmd_buffer
->state
.num_workgroups_offset
= state
.offset
;
1447 cmd_buffer
->state
.num_workgroups_bo
=
1448 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
;
1451 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1453 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
1454 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
1455 ggw
.ThreadDepthCounterMaximum
= 0;
1456 ggw
.ThreadHeightCounterMaximum
= 0;
1457 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
1458 ggw
.ThreadGroupIDXDimension
= x
;
1459 ggw
.ThreadGroupIDYDimension
= y
;
1460 ggw
.ThreadGroupIDZDimension
= z
;
1461 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
1462 ggw
.BottomExecutionMask
= 0xffffffff;
1465 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
1468 #define GPGPU_DISPATCHDIMX 0x2500
1469 #define GPGPU_DISPATCHDIMY 0x2504
1470 #define GPGPU_DISPATCHDIMZ 0x2508
1472 #define MI_PREDICATE_SRC0 0x2400
1473 #define MI_PREDICATE_SRC1 0x2408
1475 void genX(CmdDispatchIndirect
)(
1476 VkCommandBuffer commandBuffer
,
1478 VkDeviceSize offset
)
1480 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1481 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1482 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1483 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1484 struct anv_bo
*bo
= buffer
->bo
;
1485 uint32_t bo_offset
= buffer
->offset
+ offset
;
1486 struct anv_batch
*batch
= &cmd_buffer
->batch
;
1489 /* Linux 4.4 added command parser version 5 which allows the GPGPU
1490 * indirect dispatch registers to be written.
1492 if (!verify_cmd_parser(cmd_buffer
->device
, 5, "vkCmdDispatchIndirect"))
1496 if (prog_data
->uses_num_work_groups
) {
1497 cmd_buffer
->state
.num_workgroups_offset
= bo_offset
;
1498 cmd_buffer
->state
.num_workgroups_bo
= bo
;
1501 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1503 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
1504 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
1505 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
1508 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
1509 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
1510 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
1511 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
1513 /* Load compute_dispatch_indirect_x_size into SRC0 */
1514 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
1516 /* predicate = (compute_dispatch_indirect_x_size == 0); */
1517 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1518 mip
.LoadOperation
= LOAD_LOAD
;
1519 mip
.CombineOperation
= COMBINE_SET
;
1520 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1523 /* Load compute_dispatch_indirect_y_size into SRC0 */
1524 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
1526 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
1527 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1528 mip
.LoadOperation
= LOAD_LOAD
;
1529 mip
.CombineOperation
= COMBINE_OR
;
1530 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1533 /* Load compute_dispatch_indirect_z_size into SRC0 */
1534 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
1536 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
1537 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1538 mip
.LoadOperation
= LOAD_LOAD
;
1539 mip
.CombineOperation
= COMBINE_OR
;
1540 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1543 /* predicate = !predicate; */
1544 #define COMPARE_FALSE 1
1545 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1546 mip
.LoadOperation
= LOAD_LOADINV
;
1547 mip
.CombineOperation
= COMBINE_OR
;
1548 mip
.CompareOperation
= COMPARE_FALSE
;
1552 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
1553 ggw
.IndirectParameterEnable
= true;
1554 ggw
.PredicateEnable
= GEN_GEN
<= 7;
1555 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
1556 ggw
.ThreadDepthCounterMaximum
= 0;
1557 ggw
.ThreadHeightCounterMaximum
= 0;
1558 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
1559 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
1560 ggw
.BottomExecutionMask
= 0xffffffff;
1563 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
1567 flush_pipeline_before_pipeline_select(struct anv_cmd_buffer
*cmd_buffer
,
1570 #if GEN_GEN >= 8 && GEN_GEN < 10
1571 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
1573 * Software must clear the COLOR_CALC_STATE Valid field in
1574 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
1575 * with Pipeline Select set to GPGPU.
1577 * The internal hardware docs recommend the same workaround for Gen9
1580 if (pipeline
== GPGPU
)
1581 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
1583 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
1584 * PIPELINE_SELECT [DevBWR+]":
1588 * Software must ensure all the write caches are flushed through a
1589 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
1590 * command to invalidate read only caches prior to programming
1591 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
1593 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1594 pc
.RenderTargetCacheFlushEnable
= true;
1595 pc
.DepthCacheFlushEnable
= true;
1596 pc
.DCFlushEnable
= true;
1597 pc
.PostSyncOperation
= NoWrite
;
1598 pc
.CommandStreamerStallEnable
= true;
1601 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1602 pc
.TextureCacheInvalidationEnable
= true;
1603 pc
.ConstantCacheInvalidationEnable
= true;
1604 pc
.StateCacheInvalidationEnable
= true;
1605 pc
.InstructionCacheInvalidateEnable
= true;
1606 pc
.PostSyncOperation
= NoWrite
;
1612 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
1614 if (cmd_buffer
->state
.current_pipeline
!= _3D
) {
1615 flush_pipeline_before_pipeline_select(cmd_buffer
, _3D
);
1617 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
1621 ps
.PipelineSelection
= _3D
;
1624 cmd_buffer
->state
.current_pipeline
= _3D
;
1629 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
1631 if (cmd_buffer
->state
.current_pipeline
!= GPGPU
) {
1632 flush_pipeline_before_pipeline_select(cmd_buffer
, GPGPU
);
1634 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
1638 ps
.PipelineSelection
= GPGPU
;
1641 cmd_buffer
->state
.current_pipeline
= GPGPU
;
1646 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
1648 struct anv_device
*device
= cmd_buffer
->device
;
1649 const struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1650 const struct anv_image_view
*iview
=
1651 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1652 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
1653 const bool has_depth
= image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
1654 const bool has_hiz
= image
!= NULL
&& anv_image_has_hiz(image
);
1655 const bool has_stencil
=
1656 image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
1658 /* FIXME: Implement the PMA stall W/A */
1659 /* FIXME: Width and Height are wrong */
1661 /* Emit 3DSTATE_DEPTH_BUFFER */
1663 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
1664 db
.SurfaceType
= SURFTYPE_2D
;
1665 db
.DepthWriteEnable
= true;
1666 db
.StencilWriteEnable
= has_stencil
;
1668 if (cmd_buffer
->state
.pass
->subpass_count
== 1) {
1669 db
.HierarchicalDepthBufferEnable
= has_hiz
;
1671 anv_finishme("Multiple-subpass HiZ not implemented");
1674 db
.SurfaceFormat
= isl_surf_get_depth_format(&device
->isl_dev
,
1675 &image
->depth_surface
.isl
);
1677 db
.SurfaceBaseAddress
= (struct anv_address
) {
1679 .offset
= image
->offset
+ image
->depth_surface
.offset
,
1681 db
.DepthBufferObjectControlState
= GENX(MOCS
);
1683 db
.SurfacePitch
= image
->depth_surface
.isl
.row_pitch
- 1;
1684 db
.Height
= image
->extent
.height
- 1;
1685 db
.Width
= image
->extent
.width
- 1;
1686 db
.LOD
= iview
->isl
.base_level
;
1687 db
.Depth
= image
->array_size
- 1; /* FIXME: 3-D */
1688 db
.MinimumArrayElement
= iview
->isl
.base_array_layer
;
1692 isl_surf_get_array_pitch_el_rows(&image
->depth_surface
.isl
) >> 2;
1694 db
.RenderTargetViewExtent
= 1 - 1;
1697 /* Even when no depth buffer is present, the hardware requires that
1698 * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
1700 * If a null depth buffer is bound, the driver must instead bind depth as:
1701 * 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
1702 * 3DSTATE_DEPTH.Width = 1
1703 * 3DSTATE_DEPTH.Height = 1
1704 * 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
1705 * 3DSTATE_DEPTH.SurfaceBaseAddress = 0
1706 * 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
1707 * 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
1708 * 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
1710 * The PRM is wrong, though. The width and height must be programmed to
1711 * actual framebuffer's width and height, even when neither depth buffer
1712 * nor stencil buffer is present. Also, D16_UNORM is not allowed to
1713 * be combined with a stencil buffer so we use D32_FLOAT instead.
1715 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
1716 db
.SurfaceType
= SURFTYPE_2D
;
1717 db
.SurfaceFormat
= D32_FLOAT
;
1718 db
.Width
= fb
->width
- 1;
1719 db
.Height
= fb
->height
- 1;
1720 db
.StencilWriteEnable
= has_stencil
;
1725 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
) {
1726 hdb
.HierarchicalDepthBufferObjectControlState
= GENX(MOCS
);
1727 hdb
.SurfacePitch
= image
->hiz_surface
.isl
.row_pitch
- 1;
1728 hdb
.SurfaceBaseAddress
= (struct anv_address
) {
1730 .offset
= image
->offset
+ image
->hiz_surface
.offset
,
1733 /* From the SKL PRM Vol2a:
1735 * The interpretation of this field is dependent on Surface Type
1737 * - SURFTYPE_1D: distance in pixels between array slices
1738 * - SURFTYPE_2D/CUBE: distance in rows between array slices
1739 * - SURFTYPE_3D: distance in rows between R - slices
1742 image
->hiz_surface
.isl
.dim
== ISL_SURF_DIM_1D
?
1743 isl_surf_get_array_pitch_el(&image
->hiz_surface
.isl
) >> 2 :
1744 isl_surf_get_array_pitch_el_rows(&image
->hiz_surface
.isl
) >> 2;
1748 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
);
1751 /* Emit 3DSTATE_STENCIL_BUFFER */
1753 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
) {
1754 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1755 sb
.StencilBufferEnable
= true;
1757 sb
.StencilBufferObjectControlState
= GENX(MOCS
);
1759 sb
.SurfacePitch
= image
->stencil_surface
.isl
.row_pitch
- 1;
1762 sb
.SurfaceQPitch
= isl_surf_get_array_pitch_el_rows(&image
->stencil_surface
.isl
) >> 2;
1764 sb
.SurfaceBaseAddress
= (struct anv_address
) {
1766 .offset
= image
->offset
+ image
->stencil_surface
.offset
,
1770 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
);
1773 /* From the IVB PRM Vol2P1, 11.5.5.4 3DSTATE_CLEAR_PARAMS:
1775 * 3DSTATE_CLEAR_PARAMS must always be programmed in the along with
1776 * the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER,
1777 * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER)
1779 * Testing also shows that some variant of this restriction may exist HSW+.
1780 * On BDW+, it is not possible to emit 2 of these packets consecutively when
1781 * both have DepthClearValueValid set. An analysis of such state programming
1782 * on SKL showed that the GPU doesn't register the latter packet's clear
1785 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CLEAR_PARAMS
), cp
) {
1787 cp
.DepthClearValueValid
= true;
1789 cmd_buffer
->state
.subpass
->depth_stencil_attachment
;
1790 cp
.DepthClearValue
=
1791 cmd_buffer
->state
.attachments
[ds
].clear_value
.depthStencil
.depth
;
1797 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
1798 struct anv_subpass
*subpass
)
1800 cmd_buffer
->state
.subpass
= subpass
;
1802 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1804 cmd_buffer_emit_depth_stencil(cmd_buffer
);
1805 genX(cmd_buffer_emit_hz_op
)(cmd_buffer
, BLORP_HIZ_OP_HIZ_RESOLVE
);
1806 genX(cmd_buffer_emit_hz_op
)(cmd_buffer
, BLORP_HIZ_OP_DEPTH_CLEAR
);
1808 anv_cmd_buffer_clear_subpass(cmd_buffer
);
1811 void genX(CmdBeginRenderPass
)(
1812 VkCommandBuffer commandBuffer
,
1813 const VkRenderPassBeginInfo
* pRenderPassBegin
,
1814 VkSubpassContents contents
)
1816 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1817 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
1818 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
1820 cmd_buffer
->state
.framebuffer
= framebuffer
;
1821 cmd_buffer
->state
.pass
= pass
;
1822 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
1823 anv_cmd_state_setup_attachments(cmd_buffer
, pRenderPassBegin
);
1825 genX(flush_pipeline_select_3d
)(cmd_buffer
);
1827 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
1830 void genX(CmdNextSubpass
)(
1831 VkCommandBuffer commandBuffer
,
1832 VkSubpassContents contents
)
1834 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1836 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1838 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
1839 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
1842 void genX(CmdEndRenderPass
)(
1843 VkCommandBuffer commandBuffer
)
1845 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1847 genX(cmd_buffer_emit_hz_op
)(cmd_buffer
, BLORP_HIZ_OP_DEPTH_RESOLVE
);
1848 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
1851 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
1856 emit_ps_depth_count(struct anv_cmd_buffer
*cmd_buffer
,
1857 struct anv_bo
*bo
, uint32_t offset
)
1859 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1860 pc
.DestinationAddressType
= DAT_PPGTT
;
1861 pc
.PostSyncOperation
= WritePSDepthCount
;
1862 pc
.DepthStallEnable
= true;
1863 pc
.Address
= (struct anv_address
) { bo
, offset
};
1865 if (GEN_GEN
== 9 && cmd_buffer
->device
->info
.gt
== 4)
1866 pc
.CommandStreamerStallEnable
= true;
1871 emit_query_availability(struct anv_cmd_buffer
*cmd_buffer
,
1872 struct anv_bo
*bo
, uint32_t offset
)
1874 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1875 pc
.DestinationAddressType
= DAT_PPGTT
;
1876 pc
.PostSyncOperation
= WriteImmediateData
;
1877 pc
.Address
= (struct anv_address
) { bo
, offset
};
1878 pc
.ImmediateData
= 1;
1882 void genX(CmdBeginQuery
)(
1883 VkCommandBuffer commandBuffer
,
1884 VkQueryPool queryPool
,
1886 VkQueryControlFlags flags
)
1888 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1889 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
1891 /* Workaround: When meta uses the pipeline with the VS disabled, it seems
1892 * that the pipelining of the depth write breaks. What we see is that
1893 * samples from the render pass clear leaks into the first query
1894 * immediately after the clear. Doing a pipecontrol with a post-sync
1895 * operation and DepthStallEnable seems to work around the issue.
1897 if (cmd_buffer
->state
.need_query_wa
) {
1898 cmd_buffer
->state
.need_query_wa
= false;
1899 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1900 pc
.DepthCacheFlushEnable
= true;
1901 pc
.DepthStallEnable
= true;
1905 switch (pool
->type
) {
1906 case VK_QUERY_TYPE_OCCLUSION
:
1907 emit_ps_depth_count(cmd_buffer
, &pool
->bo
,
1908 query
* sizeof(struct anv_query_pool_slot
));
1911 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
1917 void genX(CmdEndQuery
)(
1918 VkCommandBuffer commandBuffer
,
1919 VkQueryPool queryPool
,
1922 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1923 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
1925 switch (pool
->type
) {
1926 case VK_QUERY_TYPE_OCCLUSION
:
1927 emit_ps_depth_count(cmd_buffer
, &pool
->bo
,
1928 query
* sizeof(struct anv_query_pool_slot
) + 8);
1930 emit_query_availability(cmd_buffer
, &pool
->bo
,
1931 query
* sizeof(struct anv_query_pool_slot
) + 16);
1934 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
1940 #define TIMESTAMP 0x2358
1942 void genX(CmdWriteTimestamp
)(
1943 VkCommandBuffer commandBuffer
,
1944 VkPipelineStageFlagBits pipelineStage
,
1945 VkQueryPool queryPool
,
1948 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1949 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
1950 uint32_t offset
= query
* sizeof(struct anv_query_pool_slot
);
1952 assert(pool
->type
== VK_QUERY_TYPE_TIMESTAMP
);
1954 switch (pipelineStage
) {
1955 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
:
1956 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
1957 srm
.RegisterAddress
= TIMESTAMP
;
1958 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
};
1960 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
1961 srm
.RegisterAddress
= TIMESTAMP
+ 4;
1962 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
+ 4 };
1967 /* Everything else is bottom-of-pipe */
1968 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1969 pc
.DestinationAddressType
= DAT_PPGTT
;
1970 pc
.PostSyncOperation
= WriteTimestamp
;
1971 pc
.Address
= (struct anv_address
) { &pool
->bo
, offset
};
1973 if (GEN_GEN
== 9 && cmd_buffer
->device
->info
.gt
== 4)
1974 pc
.CommandStreamerStallEnable
= true;
1979 emit_query_availability(cmd_buffer
, &pool
->bo
, query
+ 16);
1982 #if GEN_GEN > 7 || GEN_IS_HASWELL
1984 #define alu_opcode(v) __gen_uint((v), 20, 31)
1985 #define alu_operand1(v) __gen_uint((v), 10, 19)
1986 #define alu_operand2(v) __gen_uint((v), 0, 9)
1987 #define alu(opcode, operand1, operand2) \
1988 alu_opcode(opcode) | alu_operand1(operand1) | alu_operand2(operand2)
1990 #define OPCODE_NOOP 0x000
1991 #define OPCODE_LOAD 0x080
1992 #define OPCODE_LOADINV 0x480
1993 #define OPCODE_LOAD0 0x081
1994 #define OPCODE_LOAD1 0x481
1995 #define OPCODE_ADD 0x100
1996 #define OPCODE_SUB 0x101
1997 #define OPCODE_AND 0x102
1998 #define OPCODE_OR 0x103
1999 #define OPCODE_XOR 0x104
2000 #define OPCODE_STORE 0x180
2001 #define OPCODE_STOREINV 0x580
2003 #define OPERAND_R0 0x00
2004 #define OPERAND_R1 0x01
2005 #define OPERAND_R2 0x02
2006 #define OPERAND_R3 0x03
2007 #define OPERAND_R4 0x04
2008 #define OPERAND_SRCA 0x20
2009 #define OPERAND_SRCB 0x21
2010 #define OPERAND_ACCU 0x31
2011 #define OPERAND_ZF 0x32
2012 #define OPERAND_CF 0x33
2014 #define CS_GPR(n) (0x2600 + (n) * 8)
2017 emit_load_alu_reg_u64(struct anv_batch
*batch
, uint32_t reg
,
2018 struct anv_bo
*bo
, uint32_t offset
)
2020 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2021 lrm
.RegisterAddress
= reg
,
2022 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
2024 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2025 lrm
.RegisterAddress
= reg
+ 4;
2026 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
2031 store_query_result(struct anv_batch
*batch
, uint32_t reg
,
2032 struct anv_bo
*bo
, uint32_t offset
, VkQueryResultFlags flags
)
2034 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2035 srm
.RegisterAddress
= reg
;
2036 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
2039 if (flags
& VK_QUERY_RESULT_64_BIT
) {
2040 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2041 srm
.RegisterAddress
= reg
+ 4;
2042 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
2047 void genX(CmdCopyQueryPoolResults
)(
2048 VkCommandBuffer commandBuffer
,
2049 VkQueryPool queryPool
,
2050 uint32_t firstQuery
,
2051 uint32_t queryCount
,
2052 VkBuffer destBuffer
,
2053 VkDeviceSize destOffset
,
2054 VkDeviceSize destStride
,
2055 VkQueryResultFlags flags
)
2057 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2058 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2059 ANV_FROM_HANDLE(anv_buffer
, buffer
, destBuffer
);
2060 uint32_t slot_offset
, dst_offset
;
2062 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
2063 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2064 pc
.CommandStreamerStallEnable
= true;
2065 pc
.StallAtPixelScoreboard
= true;
2069 dst_offset
= buffer
->offset
+ destOffset
;
2070 for (uint32_t i
= 0; i
< queryCount
; i
++) {
2072 slot_offset
= (firstQuery
+ i
) * sizeof(struct anv_query_pool_slot
);
2073 switch (pool
->type
) {
2074 case VK_QUERY_TYPE_OCCLUSION
:
2075 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2076 CS_GPR(0), &pool
->bo
, slot_offset
);
2077 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2078 CS_GPR(1), &pool
->bo
, slot_offset
+ 8);
2080 /* FIXME: We need to clamp the result for 32 bit. */
2082 uint32_t *dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
2083 dw
[1] = alu(OPCODE_LOAD
, OPERAND_SRCA
, OPERAND_R1
);
2084 dw
[2] = alu(OPCODE_LOAD
, OPERAND_SRCB
, OPERAND_R0
);
2085 dw
[3] = alu(OPCODE_SUB
, 0, 0);
2086 dw
[4] = alu(OPCODE_STORE
, OPERAND_R2
, OPERAND_ACCU
);
2089 case VK_QUERY_TYPE_TIMESTAMP
:
2090 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2091 CS_GPR(2), &pool
->bo
, slot_offset
);
2095 unreachable("unhandled query type");
2098 store_query_result(&cmd_buffer
->batch
,
2099 CS_GPR(2), buffer
->bo
, dst_offset
, flags
);
2101 if (flags
& VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
) {
2102 emit_load_alu_reg_u64(&cmd_buffer
->batch
, CS_GPR(0),
2103 &pool
->bo
, slot_offset
+ 16);
2104 if (flags
& VK_QUERY_RESULT_64_BIT
)
2105 store_query_result(&cmd_buffer
->batch
,
2106 CS_GPR(0), buffer
->bo
, dst_offset
+ 8, flags
);
2108 store_query_result(&cmd_buffer
->batch
,
2109 CS_GPR(0), buffer
->bo
, dst_offset
+ 4, flags
);
2112 dst_offset
+= destStride
;
2117 void genX(CmdCopyQueryPoolResults
)(
2118 VkCommandBuffer commandBuffer
,
2119 VkQueryPool queryPool
,
2120 uint32_t firstQuery
,
2121 uint32_t queryCount
,
2122 VkBuffer destBuffer
,
2123 VkDeviceSize destOffset
,
2124 VkDeviceSize destStride
,
2125 VkQueryResultFlags flags
)
2127 anv_finishme("Queries not yet supported on Ivy Bridge");