2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "common/gen_l3_config.h"
31 #include "genxml/gen_macros.h"
32 #include "genxml/genX_pack.h"
35 emit_lrm(struct anv_batch
*batch
,
36 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
38 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
39 lrm
.RegisterAddress
= reg
;
40 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
45 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
47 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
48 lri
.RegisterOffset
= reg
;
54 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
56 struct anv_device
*device
= cmd_buffer
->device
;
58 /* XXX: Do we need this on more than just BDW? */
60 /* Emit a render target cache flush.
62 * This isn't documented anywhere in the PRM. However, it seems to be
63 * necessary prior to changing the surface state base adress. Without
64 * this, we get GPU hangs when using multi-level command buffers which
65 * clear depth, reset state base address, and then go render stuff.
67 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
68 pc
.RenderTargetCacheFlushEnable
= true;
72 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
73 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
74 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
75 sba
.GeneralStateBaseAddressModifyEnable
= true;
77 sba
.SurfaceStateBaseAddress
=
78 anv_cmd_buffer_surface_base_address(cmd_buffer
);
79 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
80 sba
.SurfaceStateBaseAddressModifyEnable
= true;
82 sba
.DynamicStateBaseAddress
=
83 (struct anv_address
) { &device
->dynamic_state_block_pool
.bo
, 0 };
84 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
85 sba
.DynamicStateBaseAddressModifyEnable
= true;
87 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
88 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
89 sba
.IndirectObjectBaseAddressModifyEnable
= true;
91 sba
.InstructionBaseAddress
=
92 (struct anv_address
) { &device
->instruction_block_pool
.bo
, 0 };
93 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
94 sba
.InstructionBaseAddressModifyEnable
= true;
97 /* Broadwell requires that we specify a buffer size for a bunch of
98 * these fields. However, since we will be growing the BO's live, we
99 * just set them all to the maximum.
101 sba
.GeneralStateBufferSize
= 0xfffff;
102 sba
.GeneralStateBufferSizeModifyEnable
= true;
103 sba
.DynamicStateBufferSize
= 0xfffff;
104 sba
.DynamicStateBufferSizeModifyEnable
= true;
105 sba
.IndirectObjectBufferSize
= 0xfffff;
106 sba
.IndirectObjectBufferSizeModifyEnable
= true;
107 sba
.InstructionBufferSize
= 0xfffff;
108 sba
.InstructionBuffersizeModifyEnable
= true;
112 /* After re-setting the surface state base address, we have to do some
113 * cache flusing so that the sampler engine will pick up the new
114 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
115 * Shared Function > 3D Sampler > State > State Caching (page 96):
117 * Coherency with system memory in the state cache, like the texture
118 * cache is handled partially by software. It is expected that the
119 * command stream or shader will issue Cache Flush operation or
120 * Cache_Flush sampler message to ensure that the L1 cache remains
121 * coherent with system memory.
125 * Whenever the value of the Dynamic_State_Base_Addr,
126 * Surface_State_Base_Addr are altered, the L1 state cache must be
127 * invalidated to ensure the new surface or sampler state is fetched
128 * from system memory.
130 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
131 * which, according the PIPE_CONTROL instruction documentation in the
134 * Setting this bit is independent of any other bit in this packet.
135 * This bit controls the invalidation of the L1 and L2 state caches
136 * at the top of the pipe i.e. at the parsing time.
138 * Unfortunately, experimentation seems to indicate that state cache
139 * invalidation through a PIPE_CONTROL does nothing whatsoever in
140 * regards to surface state and binding tables. In stead, it seems that
141 * invalidating the texture cache is what is actually needed.
143 * XXX: As far as we have been able to determine through
144 * experimentation, shows that flush the texture cache appears to be
145 * sufficient. The theory here is that all of the sampling/rendering
146 * units cache the binding table in the texture cache. However, we have
147 * yet to be able to actually confirm this.
149 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
150 pc
.TextureCacheInvalidationEnable
= true;
155 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
156 struct anv_state state
,
157 struct anv_bo
*bo
, uint32_t offset
)
159 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
161 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
162 state
.offset
+ isl_dev
->ss
.addr_offset
, bo
, offset
);
166 add_image_view_relocs(struct anv_cmd_buffer
*cmd_buffer
,
167 const struct anv_image_view
*iview
,
168 enum isl_aux_usage aux_usage
,
169 struct anv_state state
)
171 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
173 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
174 state
.offset
+ isl_dev
->ss
.addr_offset
,
175 iview
->bo
, iview
->offset
);
177 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
178 uint32_t aux_offset
= iview
->offset
+ iview
->image
->aux_surface
.offset
;
180 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
181 * used to store other information. This should be ok, however, because
182 * surface buffer addresses are always 4K page alinged.
184 assert((aux_offset
& 0xfff) == 0);
185 uint32_t *aux_addr_dw
= state
.map
+ isl_dev
->ss
.aux_addr_offset
;
186 aux_offset
+= *aux_addr_dw
& 0xfff;
188 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
189 state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
190 iview
->bo
, aux_offset
);
195 color_is_zero_one(VkClearColorValue value
, enum isl_format format
)
197 if (isl_format_has_int_channel(format
)) {
198 for (unsigned i
= 0; i
< 4; i
++) {
199 if (value
.int32
[i
] != 0 && value
.int32
[i
] != 1)
203 for (unsigned i
= 0; i
< 4; i
++) {
204 if (value
.float32
[i
] != 0.0f
&& value
.float32
[i
] != 1.0f
)
213 color_attachment_compute_aux_usage(struct anv_device
*device
,
214 struct anv_attachment_state
*att_state
,
215 struct anv_image_view
*iview
,
216 VkRect2D render_area
,
217 union isl_color_value
*fast_clear_color
)
219 if (iview
->image
->aux_surface
.isl
.size
== 0) {
220 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
221 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
222 att_state
->fast_clear
= false;
226 assert(iview
->image
->aux_surface
.isl
.usage
& ISL_SURF_USAGE_CCS_BIT
);
228 att_state
->clear_color_is_zero_one
=
229 color_is_zero_one(att_state
->clear_value
.color
, iview
->isl
.format
);
231 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
232 /* Start off assuming fast clears are possible */
233 att_state
->fast_clear
= true;
235 /* Potentially, we could do partial fast-clears but doing so has crazy
236 * alignment restrictions. It's easier to just restrict to full size
237 * fast clears for now.
239 if (render_area
.offset
.x
!= 0 ||
240 render_area
.offset
.y
!= 0 ||
241 render_area
.extent
.width
!= iview
->extent
.width
||
242 render_area
.extent
.height
!= iview
->extent
.height
)
243 att_state
->fast_clear
= false;
246 /* On gen7, we can't do multi-LOD or multi-layer fast-clears. We
247 * technically can, but it comes with crazy restrictions that we
248 * don't want to deal with now.
250 if (iview
->isl
.base_level
> 0 ||
251 iview
->isl
.base_array_layer
> 0 ||
252 iview
->isl
.array_len
> 1)
253 att_state
->fast_clear
= false;
256 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
257 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
258 att_state
->fast_clear
= false;
260 if (att_state
->fast_clear
) {
261 memcpy(fast_clear_color
->u32
, att_state
->clear_value
.color
.uint32
,
262 sizeof(fast_clear_color
->u32
));
265 att_state
->fast_clear
= false;
268 if (isl_format_supports_lossless_compression(&device
->info
,
269 iview
->isl
.format
)) {
270 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
271 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_E
;
272 } else if (att_state
->fast_clear
) {
273 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
275 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
277 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
278 * setting is only allowed if Surface Format supported for Fast
279 * Clear. In addition, if the surface is bound to the sampling
280 * engine, Surface Format must be supported for Render Target
281 * Compression for surfaces bound to the sampling engine."
283 * In other words, we can't sample from a fast-cleared image if it
284 * doesn't also support color compression.
286 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
287 } else if (GEN_GEN
== 8) {
288 /* Broadwell can sample from fast-cleared images */
289 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
291 /* Ivy Bridge and Haswell cannot */
292 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
295 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
296 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
301 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
303 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
306 /* We only allocate input attachment states for color and depth surfaces.
307 * Stencil doesn't allow compression so we can just use the texture surface
308 * state from the view
310 return vk_format_is_color(att
->format
) || vk_format_has_depth(att
->format
);
314 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
317 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
318 struct anv_render_pass
*pass
,
319 const VkRenderPassBeginInfo
*begin
)
321 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
322 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
324 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
326 if (pass
->attachment_count
== 0) {
327 state
->attachments
= NULL
;
331 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
332 pass
->attachment_count
*
333 sizeof(state
->attachments
[0]),
334 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
335 if (state
->attachments
== NULL
) {
336 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
340 bool need_null_state
= false;
341 unsigned num_states
= 0;
342 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
343 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
346 /* We need a null state for any depth-stencil-only subpasses.
347 * Importantly, this includes depth/stencil clears so we create one
348 * whenever we have depth or stencil
350 need_null_state
= true;
353 if (need_input_attachment_state(&pass
->attachments
[i
]))
356 num_states
+= need_null_state
;
358 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
359 state
->render_pass_states
=
360 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
361 num_states
* ss_stride
, isl_dev
->ss
.align
);
363 struct anv_state next_state
= state
->render_pass_states
;
364 next_state
.alloc_size
= isl_dev
->ss
.size
;
366 if (need_null_state
) {
367 state
->null_surface_state
= next_state
;
368 next_state
.offset
+= ss_stride
;
369 next_state
.map
+= ss_stride
;
372 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
373 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
374 state
->attachments
[i
].color_rt_state
= next_state
;
375 next_state
.offset
+= ss_stride
;
376 next_state
.map
+= ss_stride
;
379 if (need_input_attachment_state(&pass
->attachments
[i
])) {
380 state
->attachments
[i
].input_att_state
= next_state
;
381 next_state
.offset
+= ss_stride
;
382 next_state
.map
+= ss_stride
;
385 assert(next_state
.offset
== state
->render_pass_states
.offset
+
386 state
->render_pass_states
.alloc_size
);
389 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
390 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
392 if (need_null_state
) {
393 struct GENX(RENDER_SURFACE_STATE
) null_ss
= {
394 .SurfaceType
= SURFTYPE_NULL
,
395 .SurfaceArray
= framebuffer
->layers
> 0,
396 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
400 .TiledSurface
= true,
402 .Width
= framebuffer
->width
- 1,
403 .Height
= framebuffer
->height
- 1,
404 .Depth
= framebuffer
->layers
- 1,
405 .RenderTargetViewExtent
= framebuffer
->layers
- 1,
407 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
->null_surface_state
.map
,
411 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
412 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
413 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
414 VkImageAspectFlags clear_aspects
= 0;
416 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
417 /* color attachment */
418 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
419 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
422 /* depthstencil attachment */
423 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
424 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
425 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
427 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
428 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
429 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
433 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
435 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
437 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
438 assert(iview
->vk_format
== att
->format
);
440 union isl_color_value clear_color
= { .u32
= { 0, } };
441 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
442 color_attachment_compute_aux_usage(cmd_buffer
->device
,
443 &state
->attachments
[i
],
444 iview
, begin
->renderArea
,
447 struct isl_view view
= iview
->isl
;
448 view
.usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
449 isl_surf_fill_state(isl_dev
,
450 state
->attachments
[i
].color_rt_state
.map
,
451 .surf
= &iview
->image
->color_surface
.isl
,
453 .aux_surf
= &iview
->image
->aux_surface
.isl
,
454 .aux_usage
= state
->attachments
[i
].aux_usage
,
455 .clear_color
= clear_color
,
456 .mocs
= cmd_buffer
->device
->default_mocs
);
458 add_image_view_relocs(cmd_buffer
, iview
,
459 state
->attachments
[i
].aux_usage
,
460 state
->attachments
[i
].color_rt_state
);
462 state
->attachments
[i
].aux_usage
= ISL_AUX_USAGE_NONE
;
463 state
->attachments
[i
].input_aux_usage
= ISL_AUX_USAGE_NONE
;
466 if (need_input_attachment_state(&pass
->attachments
[i
])) {
467 const struct isl_surf
*surf
;
468 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
469 surf
= &iview
->image
->color_surface
.isl
;
471 surf
= &iview
->image
->depth_surface
.isl
;
474 struct isl_view view
= iview
->isl
;
475 view
.usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
476 isl_surf_fill_state(isl_dev
,
477 state
->attachments
[i
].input_att_state
.map
,
480 .aux_surf
= &iview
->image
->aux_surface
.isl
,
481 .aux_usage
= state
->attachments
[i
].input_aux_usage
,
482 .clear_color
= clear_color
,
483 .mocs
= cmd_buffer
->device
->default_mocs
);
485 add_image_view_relocs(cmd_buffer
, iview
,
486 state
->attachments
[i
].input_aux_usage
,
487 state
->attachments
[i
].input_att_state
);
491 if (!cmd_buffer
->device
->info
.has_llc
)
492 anv_state_clflush(state
->render_pass_states
);
497 genX(BeginCommandBuffer
)(
498 VkCommandBuffer commandBuffer
,
499 const VkCommandBufferBeginInfo
* pBeginInfo
)
501 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
503 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
504 * command buffer's state. Otherwise, we must *reset* its state. In both
507 * From the Vulkan 1.0 spec:
509 * If a command buffer is in the executable state and the command buffer
510 * was allocated from a command pool with the
511 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
512 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
513 * as if vkResetCommandBuffer had been called with
514 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
515 * the command buffer in the recording state.
517 anv_cmd_buffer_reset(cmd_buffer
);
519 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
521 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
522 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
524 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
526 if (cmd_buffer
->usage_flags
&
527 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
528 cmd_buffer
->state
.pass
=
529 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
530 cmd_buffer
->state
.subpass
=
531 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
532 cmd_buffer
->state
.framebuffer
= NULL
;
534 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, cmd_buffer
->state
.pass
,
537 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
544 genX(EndCommandBuffer
)(
545 VkCommandBuffer commandBuffer
)
547 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
549 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
551 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
557 genX(CmdExecuteCommands
)(
558 VkCommandBuffer commandBuffer
,
559 uint32_t commandBufferCount
,
560 const VkCommandBuffer
* pCmdBuffers
)
562 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
564 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
566 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
567 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
569 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
571 if (secondary
->usage_flags
&
572 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
573 /* If we're continuing a render pass from the primary, we need to
574 * copy the surface states for the current subpass into the storage
575 * we allocated for them in BeginCommandBuffer.
577 struct anv_bo
*ss_bo
= &primary
->device
->surface_state_block_pool
.bo
;
578 struct anv_state src_state
= primary
->state
.render_pass_states
;
579 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
580 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
582 genX(cmd_buffer_gpu_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
583 ss_bo
, src_state
.offset
,
584 src_state
.alloc_size
);
587 anv_cmd_buffer_add_secondary(primary
, secondary
);
590 /* Each of the secondary command buffers will use its own state base
591 * address. We need to re-emit state base address for the primary after
592 * all of the secondaries are done.
594 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
597 genX(cmd_buffer_emit_state_base_address
)(primary
);
600 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
601 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
602 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
605 * Program the hardware to use the specified L3 configuration.
608 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
609 const struct gen_l3_config
*cfg
)
612 if (cfg
== cmd_buffer
->state
.current_l3_config
)
615 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
616 fprintf(stderr
, "L3 config transition: ");
617 gen_dump_l3_config(cfg
, stderr
);
620 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
622 /* According to the hardware docs, the L3 partitioning can only be changed
623 * while the pipeline is completely drained and the caches are flushed,
624 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
626 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
627 pc
.DCFlushEnable
= true;
628 pc
.PostSyncOperation
= NoWrite
;
629 pc
.CommandStreamerStallEnable
= true;
632 /* ...followed by a second pipelined PIPE_CONTROL that initiates
633 * invalidation of the relevant caches. Note that because RO invalidation
634 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
635 * command is processed by the CS) we cannot combine it with the previous
636 * stalling flush as the hardware documentation suggests, because that
637 * would cause the CS to stall on previous rendering *after* RO
638 * invalidation and wouldn't prevent the RO caches from being polluted by
639 * concurrent rendering before the stall completes. This intentionally
640 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
641 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
642 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
643 * already guarantee that there is no concurrent GPGPU kernel execution
644 * (see SKL HSD 2132585).
646 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
647 pc
.TextureCacheInvalidationEnable
= true;
648 pc
.ConstantCacheInvalidationEnable
= true;
649 pc
.InstructionCacheInvalidateEnable
= true;
650 pc
.StateCacheInvalidationEnable
= true;
651 pc
.PostSyncOperation
= NoWrite
;
654 /* Now send a third stalling flush to make sure that invalidation is
655 * complete when the L3 configuration registers are modified.
657 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
658 pc
.DCFlushEnable
= true;
659 pc
.PostSyncOperation
= NoWrite
;
660 pc
.CommandStreamerStallEnable
= true;
665 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
668 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
669 .SLMEnable
= has_slm
,
670 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
671 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
672 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
673 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
675 /* Set up the L3 partitioning. */
676 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
680 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
681 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
683 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
685 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
688 assert(!cfg
->n
[GEN_L3P_ALL
]);
690 /* When enabled SLM only uses a portion of the L3 on half of the banks,
691 * the matching space on the remaining banks has to be allocated to a
692 * client (URB for all validated configurations) set to the
693 * lower-bandwidth 2-bank address hashing mode.
695 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
696 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
697 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
699 /* Minimum number of ways that can be allocated to the URB. */
700 const unsigned n0_urb
= (devinfo
->is_baytrail
? 32 : 0);
701 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
703 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
704 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
705 .ConvertDC_UC
= !has_dc
,
706 .ConvertIS_UC
= !has_is
,
707 .ConvertC_UC
= !has_c
,
708 .ConvertT_UC
= !has_t
);
710 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
711 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
712 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
714 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
715 .SLMEnable
= has_slm
,
716 .URBLowBandwidth
= urb_low_bw
,
717 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
719 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
721 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
722 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
724 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
725 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
727 .CAllocation
= cfg
->n
[GEN_L3P_C
],
729 .TAllocation
= cfg
->n
[GEN_L3P_T
],
732 /* Set up the L3 partitioning. */
733 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
734 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
735 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
738 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
739 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
740 * them disabled to avoid crashing the system hard.
742 uint32_t scratch1
, chicken3
;
743 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
744 .L3AtomicDisable
= !has_dc
);
745 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
746 .L3AtomicDisableMask
= true,
747 .L3AtomicDisable
= !has_dc
);
748 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
749 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
755 cmd_buffer
->state
.current_l3_config
= cfg
;
759 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
761 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
763 /* Flushes are pipelined while invalidations are handled immediately.
764 * Therefore, if we're flushing anything then we need to schedule a stall
765 * before any invalidations can happen.
767 if (bits
& ANV_PIPE_FLUSH_BITS
)
768 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
770 /* If we're going to do an invalidate and we have a pending CS stall that
771 * has yet to be resolved, we do the CS stall now.
773 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
774 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
775 bits
|= ANV_PIPE_CS_STALL_BIT
;
776 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
779 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
780 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
781 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
782 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
783 pipe
.RenderTargetCacheFlushEnable
=
784 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
786 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
787 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
788 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
791 * According to the Broadwell documentation, any PIPE_CONTROL with the
792 * "Command Streamer Stall" bit set must also have another bit set,
793 * with five different options:
795 * - Render Target Cache Flush
796 * - Depth Cache Flush
797 * - Stall at Pixel Scoreboard
798 * - Post-Sync Operation
802 * I chose "Stall at Pixel Scoreboard" since that's what we use in
803 * mesa and it seems to work fine. The choice is fairly arbitrary.
805 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
806 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
807 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
808 pipe
.StallAtPixelScoreboard
= true;
811 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
814 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
815 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
816 pipe
.StateCacheInvalidationEnable
=
817 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
818 pipe
.ConstantCacheInvalidationEnable
=
819 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
820 pipe
.VFCacheInvalidationEnable
=
821 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
822 pipe
.TextureCacheInvalidationEnable
=
823 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
824 pipe
.InstructionCacheInvalidateEnable
=
825 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
828 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
831 cmd_buffer
->state
.pending_pipe_bits
= bits
;
834 void genX(CmdPipelineBarrier
)(
835 VkCommandBuffer commandBuffer
,
836 VkPipelineStageFlags srcStageMask
,
837 VkPipelineStageFlags destStageMask
,
839 uint32_t memoryBarrierCount
,
840 const VkMemoryBarrier
* pMemoryBarriers
,
841 uint32_t bufferMemoryBarrierCount
,
842 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
843 uint32_t imageMemoryBarrierCount
,
844 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
846 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
849 /* XXX: Right now, we're really dumb and just flush whatever categories
850 * the app asks for. One of these days we may make this a bit better
851 * but right now that's all the hardware allows for in most areas.
853 VkAccessFlags src_flags
= 0;
854 VkAccessFlags dst_flags
= 0;
856 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
857 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
858 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
861 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
862 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
863 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
866 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
867 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
868 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
871 enum anv_pipe_bits pipe_bits
= 0;
873 for_each_bit(b
, src_flags
) {
874 switch ((VkAccessFlagBits
)(1 << b
)) {
875 case VK_ACCESS_SHADER_WRITE_BIT
:
876 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
878 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
879 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
881 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
882 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
884 case VK_ACCESS_TRANSFER_WRITE_BIT
:
885 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
886 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
889 break; /* Nothing to do */
893 for_each_bit(b
, dst_flags
) {
894 switch ((VkAccessFlagBits
)(1 << b
)) {
895 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
896 case VK_ACCESS_INDEX_READ_BIT
:
897 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
898 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
900 case VK_ACCESS_UNIFORM_READ_BIT
:
901 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
902 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
904 case VK_ACCESS_SHADER_READ_BIT
:
905 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
906 case VK_ACCESS_TRANSFER_READ_BIT
:
907 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
910 break; /* Nothing to do */
914 cmd_buffer
->state
.pending_pipe_bits
|= pipe_bits
;
918 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
920 VkShaderStageFlags stages
= cmd_buffer
->state
.pipeline
->active_stages
;
922 /* In order to avoid thrash, we assume that vertex and fragment stages
923 * always exist. In the rare case where one is missing *and* the other
924 * uses push concstants, this may be suboptimal. However, avoiding stalls
925 * seems more important.
927 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
929 if (stages
== cmd_buffer
->state
.push_constant_stages
)
933 const unsigned push_constant_kb
= 32;
935 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
937 const unsigned push_constant_kb
= 16;
940 const unsigned num_stages
=
941 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
942 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
944 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
945 * units of 2KB. Incidentally, these are the same platforms that have
946 * 32KB worth of push constant space.
948 if (push_constant_kb
== 32)
949 size_per_stage
&= ~1u;
951 uint32_t kb_used
= 0;
952 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
953 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
954 anv_batch_emit(&cmd_buffer
->batch
,
955 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
956 alloc
._3DCommandSubOpcode
= 18 + i
;
957 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
958 alloc
.ConstantBufferSize
= push_size
;
960 kb_used
+= push_size
;
963 anv_batch_emit(&cmd_buffer
->batch
,
964 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
965 alloc
.ConstantBufferOffset
= kb_used
;
966 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
969 cmd_buffer
->state
.push_constant_stages
= stages
;
971 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
973 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
974 * the next 3DPRIMITIVE command after programming the
975 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
977 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
978 * pipeline setup, we need to dirty push constants.
980 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
984 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
985 gl_shader_stage stage
,
986 struct anv_state
*bt_state
)
988 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
989 struct anv_pipeline
*pipeline
;
990 uint32_t bias
, state_offset
;
993 case MESA_SHADER_COMPUTE
:
994 pipeline
= cmd_buffer
->state
.compute_pipeline
;
998 pipeline
= cmd_buffer
->state
.pipeline
;
1003 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1004 *bt_state
= (struct anv_state
) { 0, };
1008 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1009 if (bias
+ map
->surface_count
== 0) {
1010 *bt_state
= (struct anv_state
) { 0, };
1014 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
1015 bias
+ map
->surface_count
,
1017 uint32_t *bt_map
= bt_state
->map
;
1019 if (bt_state
->map
== NULL
)
1020 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1022 if (stage
== MESA_SHADER_COMPUTE
&&
1023 get_cs_prog_data(cmd_buffer
->state
.compute_pipeline
)->uses_num_work_groups
) {
1024 struct anv_bo
*bo
= cmd_buffer
->state
.num_workgroups_bo
;
1025 uint32_t bo_offset
= cmd_buffer
->state
.num_workgroups_offset
;
1027 struct anv_state surface_state
;
1029 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
1031 const enum isl_format format
=
1032 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
1033 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1034 format
, bo_offset
, 12, 1);
1036 bt_map
[0] = surface_state
.offset
+ state_offset
;
1037 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
1040 if (map
->surface_count
== 0)
1043 if (map
->image_count
> 0) {
1045 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
1046 if (result
!= VK_SUCCESS
)
1049 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
1053 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
1054 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
1056 struct anv_state surface_state
;
1058 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
1059 /* Color attachment binding */
1060 assert(stage
== MESA_SHADER_FRAGMENT
);
1061 assert(binding
->binding
== 0);
1062 if (binding
->index
< subpass
->color_count
) {
1063 const unsigned att
= subpass
->color_attachments
[binding
->index
];
1064 surface_state
= cmd_buffer
->state
.attachments
[att
].color_rt_state
;
1066 surface_state
= cmd_buffer
->state
.null_surface_state
;
1069 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1073 struct anv_descriptor_set
*set
=
1074 cmd_buffer
->state
.descriptors
[binding
->set
];
1075 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1076 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1078 switch (desc
->type
) {
1079 case VK_DESCRIPTOR_TYPE_SAMPLER
:
1080 /* Nothing for us to do here */
1083 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
1084 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
1085 surface_state
= desc
->image_view
->sampler_surface_state
;
1086 assert(surface_state
.alloc_size
);
1087 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1088 desc
->image_view
->image
->aux_usage
,
1092 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
1093 assert(stage
== MESA_SHADER_FRAGMENT
);
1094 if (desc
->image_view
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
1095 /* For stencil input attachments, we treat it like any old texture
1096 * that a user may have bound.
1098 surface_state
= desc
->image_view
->sampler_surface_state
;
1099 assert(surface_state
.alloc_size
);
1100 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1101 desc
->image_view
->image
->aux_usage
,
1104 /* For depth and color input attachments, we create the surface
1105 * state at vkBeginRenderPass time so that we can include aux
1106 * and clear color information.
1108 assert(binding
->input_attachment_index
< subpass
->input_count
);
1109 const unsigned subpass_att
= binding
->input_attachment_index
;
1110 const unsigned att
= subpass
->input_attachments
[subpass_att
];
1111 surface_state
= cmd_buffer
->state
.attachments
[att
].input_att_state
;
1115 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
1116 surface_state
= desc
->image_view
->storage_surface_state
;
1117 assert(surface_state
.alloc_size
);
1118 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1119 desc
->image_view
->image
->aux_usage
,
1122 struct brw_image_param
*image_param
=
1123 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1125 *image_param
= desc
->image_view
->storage_image_param
;
1126 image_param
->surface_idx
= bias
+ s
;
1130 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
1131 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
1132 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
1133 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
1134 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
1135 surface_state
= desc
->buffer_view
->surface_state
;
1136 assert(surface_state
.alloc_size
);
1137 add_surface_state_reloc(cmd_buffer
, surface_state
,
1138 desc
->buffer_view
->bo
,
1139 desc
->buffer_view
->offset
);
1142 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
1143 surface_state
= desc
->buffer_view
->storage_surface_state
;
1144 assert(surface_state
.alloc_size
);
1145 add_surface_state_reloc(cmd_buffer
, surface_state
,
1146 desc
->buffer_view
->bo
,
1147 desc
->buffer_view
->offset
);
1149 struct brw_image_param
*image_param
=
1150 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1152 *image_param
= desc
->buffer_view
->storage_image_param
;
1153 image_param
->surface_idx
= bias
+ s
;
1157 assert(!"Invalid descriptor type");
1161 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1163 assert(image
== map
->image_count
);
1166 if (!cmd_buffer
->device
->info
.has_llc
)
1167 anv_state_clflush(*bt_state
);
1173 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
1174 gl_shader_stage stage
,
1175 struct anv_state
*state
)
1177 struct anv_pipeline
*pipeline
;
1179 if (stage
== MESA_SHADER_COMPUTE
)
1180 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1182 pipeline
= cmd_buffer
->state
.pipeline
;
1184 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1185 *state
= (struct anv_state
) { 0, };
1189 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1190 if (map
->sampler_count
== 0) {
1191 *state
= (struct anv_state
) { 0, };
1195 uint32_t size
= map
->sampler_count
* 16;
1196 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
1198 if (state
->map
== NULL
)
1199 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1201 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
1202 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
1203 struct anv_descriptor_set
*set
=
1204 cmd_buffer
->state
.descriptors
[binding
->set
];
1205 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1206 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1208 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
1209 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
1212 struct anv_sampler
*sampler
= desc
->sampler
;
1214 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
1215 * happens to be zero.
1217 if (sampler
== NULL
)
1220 memcpy(state
->map
+ (s
* 16),
1221 sampler
->state
, sizeof(sampler
->state
));
1224 if (!cmd_buffer
->device
->info
.has_llc
)
1225 anv_state_clflush(*state
);
1231 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
1233 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
1234 cmd_buffer
->state
.pipeline
->active_stages
;
1236 VkResult result
= VK_SUCCESS
;
1237 anv_foreach_stage(s
, dirty
) {
1238 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1239 if (result
!= VK_SUCCESS
)
1241 result
= emit_binding_table(cmd_buffer
, s
,
1242 &cmd_buffer
->state
.binding_tables
[s
]);
1243 if (result
!= VK_SUCCESS
)
1247 if (result
!= VK_SUCCESS
) {
1248 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1250 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1251 assert(result
== VK_SUCCESS
);
1253 /* Re-emit state base addresses so we get the new surface state base
1254 * address before we start emitting binding tables etc.
1256 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1258 /* Re-emit all active binding tables */
1259 dirty
|= cmd_buffer
->state
.pipeline
->active_stages
;
1260 anv_foreach_stage(s
, dirty
) {
1261 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1262 if (result
!= VK_SUCCESS
)
1264 result
= emit_binding_table(cmd_buffer
, s
,
1265 &cmd_buffer
->state
.binding_tables
[s
]);
1266 if (result
!= VK_SUCCESS
)
1271 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
1277 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
1280 static const uint32_t sampler_state_opcodes
[] = {
1281 [MESA_SHADER_VERTEX
] = 43,
1282 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
1283 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
1284 [MESA_SHADER_GEOMETRY
] = 46,
1285 [MESA_SHADER_FRAGMENT
] = 47,
1286 [MESA_SHADER_COMPUTE
] = 0,
1289 static const uint32_t binding_table_opcodes
[] = {
1290 [MESA_SHADER_VERTEX
] = 38,
1291 [MESA_SHADER_TESS_CTRL
] = 39,
1292 [MESA_SHADER_TESS_EVAL
] = 40,
1293 [MESA_SHADER_GEOMETRY
] = 41,
1294 [MESA_SHADER_FRAGMENT
] = 42,
1295 [MESA_SHADER_COMPUTE
] = 0,
1298 anv_foreach_stage(s
, stages
) {
1299 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
1300 anv_batch_emit(&cmd_buffer
->batch
,
1301 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
1302 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
1303 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
1307 /* Always emit binding table pointers if we're asked to, since on SKL
1308 * this is what flushes push constants. */
1309 anv_batch_emit(&cmd_buffer
->batch
,
1310 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
1311 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
1312 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
1318 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1320 static const uint32_t push_constant_opcodes
[] = {
1321 [MESA_SHADER_VERTEX
] = 21,
1322 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
1323 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
1324 [MESA_SHADER_GEOMETRY
] = 22,
1325 [MESA_SHADER_FRAGMENT
] = 23,
1326 [MESA_SHADER_COMPUTE
] = 0,
1329 VkShaderStageFlags flushed
= 0;
1331 anv_foreach_stage(stage
, cmd_buffer
->state
.push_constants_dirty
) {
1332 if (stage
== MESA_SHADER_COMPUTE
)
1335 struct anv_state state
= anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
1337 if (state
.offset
== 0) {
1338 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
)
1339 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
1341 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
1342 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
],
1343 c
.ConstantBody
= (struct GENX(3DSTATE_CONSTANT_BODY
)) {
1345 .PointerToConstantBuffer2
= { &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, state
.offset
},
1346 .ConstantBuffer2ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1348 .PointerToConstantBuffer0
= { .offset
= state
.offset
},
1349 .ConstantBuffer0ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1355 flushed
|= mesa_to_vk_shader_stage(stage
);
1358 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_ALL_GRAPHICS
;
1364 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1366 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1369 uint32_t vb_emit
= cmd_buffer
->state
.vb_dirty
& pipeline
->vb_used
;
1371 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
1373 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1375 genX(flush_pipeline_select_3d
)(cmd_buffer
);
1378 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
1379 const uint32_t num_dwords
= 1 + num_buffers
* 4;
1381 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
1382 GENX(3DSTATE_VERTEX_BUFFERS
));
1384 for_each_bit(vb
, vb_emit
) {
1385 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1386 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
1388 struct GENX(VERTEX_BUFFER_STATE
) state
= {
1389 .VertexBufferIndex
= vb
,
1392 .MemoryObjectControlState
= GENX(MOCS
),
1394 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
1395 .InstanceDataStepRate
= 1,
1396 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1399 .AddressModifyEnable
= true,
1400 .BufferPitch
= pipeline
->binding_stride
[vb
],
1401 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
1404 .BufferSize
= buffer
->size
- offset
1406 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
1410 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
1415 cmd_buffer
->state
.vb_dirty
&= ~vb_emit
;
1417 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1418 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1420 /* The exact descriptor layout is pulled from the pipeline, so we need
1421 * to re-emit binding tables on every pipeline change.
1423 cmd_buffer
->state
.descriptors_dirty
|=
1424 cmd_buffer
->state
.pipeline
->active_stages
;
1426 /* If the pipeline changed, we may need to re-allocate push constant
1429 cmd_buffer_alloc_push_constants(cmd_buffer
);
1433 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
1434 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
1435 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
1437 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
1438 * stall needs to be sent just prior to any 3DSTATE_VS,
1439 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
1440 * 3DSTATE_BINDING_TABLE_POINTER_VS,
1441 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
1442 * PIPE_CONTROL needs to be sent before any combination of VS
1443 * associated 3DSTATE."
1445 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1446 pc
.DepthStallEnable
= true;
1447 pc
.PostSyncOperation
= WriteImmediateData
;
1449 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1454 /* Render targets live in the same binding table as fragment descriptors */
1455 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
1456 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
1458 /* We emit the binding tables and sampler tables first, then emit push
1459 * constants and then finally emit binding table and sampler table
1460 * pointers. It has to happen in this order, since emitting the binding
1461 * tables may change the push constants (in case of storage images). After
1462 * emitting push constants, on SKL+ we have to emit the corresponding
1463 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
1466 if (cmd_buffer
->state
.descriptors_dirty
)
1467 dirty
= flush_descriptor_sets(cmd_buffer
);
1469 if (cmd_buffer
->state
.push_constants_dirty
) {
1471 /* On Sky Lake and later, the binding table pointers commands are
1472 * what actually flush the changes to push constant state so we need
1473 * to dirty them so they get re-emitted below.
1475 dirty
|= cmd_buffer_flush_push_constants(cmd_buffer
);
1477 cmd_buffer_flush_push_constants(cmd_buffer
);
1482 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
1484 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
1485 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
1487 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
1488 ANV_CMD_DIRTY_PIPELINE
)) {
1489 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
1490 pipeline
->depth_clamp_enable
);
1493 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
1494 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
1496 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
1498 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1502 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
1503 struct anv_bo
*bo
, uint32_t offset
)
1505 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
1506 GENX(3DSTATE_VERTEX_BUFFERS
));
1508 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
1509 &(struct GENX(VERTEX_BUFFER_STATE
)) {
1510 .VertexBufferIndex
= 32, /* Reserved for this */
1511 .AddressModifyEnable
= true,
1514 .MemoryObjectControlState
= GENX(MOCS
),
1515 .BufferStartingAddress
= { bo
, offset
},
1518 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1519 .BufferStartingAddress
= { bo
, offset
},
1520 .EndAddress
= { bo
, offset
+ 8 },
1526 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
1527 uint32_t base_vertex
, uint32_t base_instance
)
1529 struct anv_state id_state
=
1530 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
1532 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
1533 ((uint32_t *)id_state
.map
)[1] = base_instance
;
1535 if (!cmd_buffer
->device
->info
.has_llc
)
1536 anv_state_clflush(id_state
);
1538 emit_base_vertex_instance_bo(cmd_buffer
,
1539 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, id_state
.offset
);
1543 VkCommandBuffer commandBuffer
,
1544 uint32_t vertexCount
,
1545 uint32_t instanceCount
,
1546 uint32_t firstVertex
,
1547 uint32_t firstInstance
)
1549 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1550 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1551 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1553 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1555 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1556 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
1558 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1559 prim
.VertexAccessType
= SEQUENTIAL
;
1560 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1561 prim
.VertexCountPerInstance
= vertexCount
;
1562 prim
.StartVertexLocation
= firstVertex
;
1563 prim
.InstanceCount
= instanceCount
;
1564 prim
.StartInstanceLocation
= firstInstance
;
1565 prim
.BaseVertexLocation
= 0;
1569 void genX(CmdDrawIndexed
)(
1570 VkCommandBuffer commandBuffer
,
1571 uint32_t indexCount
,
1572 uint32_t instanceCount
,
1573 uint32_t firstIndex
,
1574 int32_t vertexOffset
,
1575 uint32_t firstInstance
)
1577 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1578 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1579 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1581 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1583 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1584 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
1586 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1587 prim
.VertexAccessType
= RANDOM
;
1588 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1589 prim
.VertexCountPerInstance
= indexCount
;
1590 prim
.StartVertexLocation
= firstIndex
;
1591 prim
.InstanceCount
= instanceCount
;
1592 prim
.StartInstanceLocation
= firstInstance
;
1593 prim
.BaseVertexLocation
= vertexOffset
;
1597 /* Auto-Draw / Indirect Registers */
1598 #define GEN7_3DPRIM_END_OFFSET 0x2420
1599 #define GEN7_3DPRIM_START_VERTEX 0x2430
1600 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
1601 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
1602 #define GEN7_3DPRIM_START_INSTANCE 0x243C
1603 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
1605 void genX(CmdDrawIndirect
)(
1606 VkCommandBuffer commandBuffer
,
1608 VkDeviceSize offset
,
1612 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1613 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1614 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1615 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1616 struct anv_bo
*bo
= buffer
->bo
;
1617 uint32_t bo_offset
= buffer
->offset
+ offset
;
1619 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1621 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1622 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
1624 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1625 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1626 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1627 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
1628 emit_lri(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
1630 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1631 prim
.IndirectParameterEnable
= true;
1632 prim
.VertexAccessType
= SEQUENTIAL
;
1633 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1637 void genX(CmdDrawIndexedIndirect
)(
1638 VkCommandBuffer commandBuffer
,
1640 VkDeviceSize offset
,
1644 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1645 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1646 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1647 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1648 struct anv_bo
*bo
= buffer
->bo
;
1649 uint32_t bo_offset
= buffer
->offset
+ offset
;
1651 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1653 /* TODO: We need to stomp base vertex to 0 somehow */
1654 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1655 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
1657 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1658 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1659 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1660 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
1661 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
1663 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1664 prim
.IndirectParameterEnable
= true;
1665 prim
.VertexAccessType
= RANDOM
;
1666 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1671 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
1673 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1674 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
1677 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1678 if (result
!= VK_SUCCESS
) {
1679 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1680 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1681 assert(result
== VK_SUCCESS
);
1683 /* Re-emit state base addresses so we get the new surface state base
1684 * address before we start emitting binding tables etc.
1686 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1688 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1689 assert(result
== VK_SUCCESS
);
1692 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
1693 assert(result
== VK_SUCCESS
);
1695 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
1696 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
1697 .BindingTablePointer
= surfaces
.offset
,
1698 .SamplerStatePointer
= samplers
.offset
,
1700 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
1702 struct anv_state state
=
1703 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
1704 pipeline
->interface_descriptor_data
,
1705 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
1708 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
1709 anv_batch_emit(&cmd_buffer
->batch
,
1710 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
1711 mid
.InterfaceDescriptorTotalLength
= size
;
1712 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
1719 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1721 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1722 MAYBE_UNUSED VkResult result
;
1724 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
1726 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1728 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
1730 if (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1731 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
1733 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
1734 * the only bits that are changed are scoreboard related: Scoreboard
1735 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
1736 * these scoreboard related states, a MEDIA_STATE_FLUSH is
1739 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
1740 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1742 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1745 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
1746 (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)) {
1747 /* FIXME: figure out descriptors for gen7 */
1748 result
= flush_compute_descriptor_set(cmd_buffer
);
1749 assert(result
== VK_SUCCESS
);
1750 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
1753 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
1754 struct anv_state push_state
=
1755 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
1757 if (push_state
.alloc_size
) {
1758 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
1759 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
1760 curbe
.CURBEDataStartAddress
= push_state
.offset
;
1765 cmd_buffer
->state
.compute_dirty
= 0;
1767 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1773 verify_cmd_parser(const struct anv_device
*device
,
1774 int required_version
,
1775 const char *function
)
1777 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
1778 vk_errorf(VK_ERROR_FEATURE_NOT_PRESENT
,
1779 "cmd parser version %d is required for %s",
1780 required_version
, function
);
1789 void genX(CmdDispatch
)(
1790 VkCommandBuffer commandBuffer
,
1795 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1796 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1797 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1799 if (prog_data
->uses_num_work_groups
) {
1800 struct anv_state state
=
1801 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
1802 uint32_t *sizes
= state
.map
;
1806 if (!cmd_buffer
->device
->info
.has_llc
)
1807 anv_state_clflush(state
);
1808 cmd_buffer
->state
.num_workgroups_offset
= state
.offset
;
1809 cmd_buffer
->state
.num_workgroups_bo
=
1810 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
;
1813 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1815 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
1816 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
1817 ggw
.ThreadDepthCounterMaximum
= 0;
1818 ggw
.ThreadHeightCounterMaximum
= 0;
1819 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
1820 ggw
.ThreadGroupIDXDimension
= x
;
1821 ggw
.ThreadGroupIDYDimension
= y
;
1822 ggw
.ThreadGroupIDZDimension
= z
;
1823 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
1824 ggw
.BottomExecutionMask
= 0xffffffff;
1827 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
1830 #define GPGPU_DISPATCHDIMX 0x2500
1831 #define GPGPU_DISPATCHDIMY 0x2504
1832 #define GPGPU_DISPATCHDIMZ 0x2508
1834 #define MI_PREDICATE_SRC0 0x2400
1835 #define MI_PREDICATE_SRC1 0x2408
1837 void genX(CmdDispatchIndirect
)(
1838 VkCommandBuffer commandBuffer
,
1840 VkDeviceSize offset
)
1842 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1843 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1844 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1845 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1846 struct anv_bo
*bo
= buffer
->bo
;
1847 uint32_t bo_offset
= buffer
->offset
+ offset
;
1848 struct anv_batch
*batch
= &cmd_buffer
->batch
;
1851 /* Linux 4.4 added command parser version 5 which allows the GPGPU
1852 * indirect dispatch registers to be written.
1854 if (!verify_cmd_parser(cmd_buffer
->device
, 5, "vkCmdDispatchIndirect"))
1858 if (prog_data
->uses_num_work_groups
) {
1859 cmd_buffer
->state
.num_workgroups_offset
= bo_offset
;
1860 cmd_buffer
->state
.num_workgroups_bo
= bo
;
1863 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1865 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
1866 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
1867 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
1870 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
1871 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
1872 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
1873 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
1875 /* Load compute_dispatch_indirect_x_size into SRC0 */
1876 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
1878 /* predicate = (compute_dispatch_indirect_x_size == 0); */
1879 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1880 mip
.LoadOperation
= LOAD_LOAD
;
1881 mip
.CombineOperation
= COMBINE_SET
;
1882 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1885 /* Load compute_dispatch_indirect_y_size into SRC0 */
1886 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
1888 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
1889 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1890 mip
.LoadOperation
= LOAD_LOAD
;
1891 mip
.CombineOperation
= COMBINE_OR
;
1892 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1895 /* Load compute_dispatch_indirect_z_size into SRC0 */
1896 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
1898 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
1899 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1900 mip
.LoadOperation
= LOAD_LOAD
;
1901 mip
.CombineOperation
= COMBINE_OR
;
1902 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1905 /* predicate = !predicate; */
1906 #define COMPARE_FALSE 1
1907 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1908 mip
.LoadOperation
= LOAD_LOADINV
;
1909 mip
.CombineOperation
= COMBINE_OR
;
1910 mip
.CompareOperation
= COMPARE_FALSE
;
1914 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
1915 ggw
.IndirectParameterEnable
= true;
1916 ggw
.PredicateEnable
= GEN_GEN
<= 7;
1917 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
1918 ggw
.ThreadDepthCounterMaximum
= 0;
1919 ggw
.ThreadHeightCounterMaximum
= 0;
1920 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
1921 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
1922 ggw
.BottomExecutionMask
= 0xffffffff;
1925 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
1929 flush_pipeline_before_pipeline_select(struct anv_cmd_buffer
*cmd_buffer
,
1932 #if GEN_GEN >= 8 && GEN_GEN < 10
1933 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
1935 * Software must clear the COLOR_CALC_STATE Valid field in
1936 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
1937 * with Pipeline Select set to GPGPU.
1939 * The internal hardware docs recommend the same workaround for Gen9
1942 if (pipeline
== GPGPU
)
1943 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
1945 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
1946 * PIPELINE_SELECT [DevBWR+]":
1950 * Software must ensure all the write caches are flushed through a
1951 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
1952 * command to invalidate read only caches prior to programming
1953 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
1955 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1956 pc
.RenderTargetCacheFlushEnable
= true;
1957 pc
.DepthCacheFlushEnable
= true;
1958 pc
.DCFlushEnable
= true;
1959 pc
.PostSyncOperation
= NoWrite
;
1960 pc
.CommandStreamerStallEnable
= true;
1963 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1964 pc
.TextureCacheInvalidationEnable
= true;
1965 pc
.ConstantCacheInvalidationEnable
= true;
1966 pc
.StateCacheInvalidationEnable
= true;
1967 pc
.InstructionCacheInvalidateEnable
= true;
1968 pc
.PostSyncOperation
= NoWrite
;
1974 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
1976 if (cmd_buffer
->state
.current_pipeline
!= _3D
) {
1977 flush_pipeline_before_pipeline_select(cmd_buffer
, _3D
);
1979 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
1983 ps
.PipelineSelection
= _3D
;
1986 cmd_buffer
->state
.current_pipeline
= _3D
;
1991 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
1993 if (cmd_buffer
->state
.current_pipeline
!= GPGPU
) {
1994 flush_pipeline_before_pipeline_select(cmd_buffer
, GPGPU
);
1996 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
2000 ps
.PipelineSelection
= GPGPU
;
2003 cmd_buffer
->state
.current_pipeline
= GPGPU
;
2008 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
2013 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
2015 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
2016 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
2017 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
2018 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
2019 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
2020 * Depth Flush Bit set, followed by another pipelined depth stall
2021 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
2022 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
2023 * via a preceding MI_FLUSH)."
2025 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2026 pipe
.DepthStallEnable
= true;
2028 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2029 pipe
.DepthCacheFlushEnable
= true;
2031 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2032 pipe
.DepthStallEnable
= true;
2037 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
2039 struct anv_device
*device
= cmd_buffer
->device
;
2040 const struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
2041 const struct anv_image_view
*iview
=
2042 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2043 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
2044 const bool has_depth
= image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
2045 const bool has_hiz
= image
!= NULL
&& anv_image_has_hiz(image
);
2046 const bool has_stencil
=
2047 image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
2049 /* FIXME: Implement the PMA stall W/A */
2050 /* FIXME: Width and Height are wrong */
2052 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
2054 /* Emit 3DSTATE_DEPTH_BUFFER */
2056 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
2057 db
.SurfaceType
= SURFTYPE_2D
;
2058 db
.DepthWriteEnable
= true;
2059 db
.StencilWriteEnable
= has_stencil
;
2061 if (cmd_buffer
->state
.pass
->subpass_count
== 1) {
2062 db
.HierarchicalDepthBufferEnable
= has_hiz
;
2064 anv_finishme("Multiple-subpass HiZ not implemented");
2067 db
.SurfaceFormat
= isl_surf_get_depth_format(&device
->isl_dev
,
2068 &image
->depth_surface
.isl
);
2070 db
.SurfaceBaseAddress
= (struct anv_address
) {
2072 .offset
= image
->offset
+ image
->depth_surface
.offset
,
2074 db
.DepthBufferObjectControlState
= GENX(MOCS
);
2076 db
.SurfacePitch
= image
->depth_surface
.isl
.row_pitch
- 1;
2077 db
.Height
= image
->extent
.height
- 1;
2078 db
.Width
= image
->extent
.width
- 1;
2079 db
.LOD
= iview
->isl
.base_level
;
2080 db
.Depth
= image
->array_size
- 1; /* FIXME: 3-D */
2081 db
.MinimumArrayElement
= iview
->isl
.base_array_layer
;
2085 isl_surf_get_array_pitch_el_rows(&image
->depth_surface
.isl
) >> 2;
2087 db
.RenderTargetViewExtent
= 1 - 1;
2090 /* Even when no depth buffer is present, the hardware requires that
2091 * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
2093 * If a null depth buffer is bound, the driver must instead bind depth as:
2094 * 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
2095 * 3DSTATE_DEPTH.Width = 1
2096 * 3DSTATE_DEPTH.Height = 1
2097 * 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
2098 * 3DSTATE_DEPTH.SurfaceBaseAddress = 0
2099 * 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
2100 * 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
2101 * 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
2103 * The PRM is wrong, though. The width and height must be programmed to
2104 * actual framebuffer's width and height, even when neither depth buffer
2105 * nor stencil buffer is present. Also, D16_UNORM is not allowed to
2106 * be combined with a stencil buffer so we use D32_FLOAT instead.
2108 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
2109 db
.SurfaceType
= SURFTYPE_2D
;
2110 db
.SurfaceFormat
= D32_FLOAT
;
2111 db
.Width
= fb
->width
- 1;
2112 db
.Height
= fb
->height
- 1;
2113 db
.StencilWriteEnable
= has_stencil
;
2118 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
) {
2119 hdb
.HierarchicalDepthBufferObjectControlState
= GENX(MOCS
);
2120 hdb
.SurfacePitch
= image
->aux_surface
.isl
.row_pitch
- 1;
2121 hdb
.SurfaceBaseAddress
= (struct anv_address
) {
2123 .offset
= image
->offset
+ image
->aux_surface
.offset
,
2126 /* From the SKL PRM Vol2a:
2128 * The interpretation of this field is dependent on Surface Type
2130 * - SURFTYPE_1D: distance in pixels between array slices
2131 * - SURFTYPE_2D/CUBE: distance in rows between array slices
2132 * - SURFTYPE_3D: distance in rows between R - slices
2135 image
->aux_surface
.isl
.dim
== ISL_SURF_DIM_1D
?
2136 isl_surf_get_array_pitch_el(&image
->aux_surface
.isl
) >> 2 :
2137 isl_surf_get_array_pitch_el_rows(&image
->aux_surface
.isl
) >> 2;
2141 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
);
2144 /* Emit 3DSTATE_STENCIL_BUFFER */
2146 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
) {
2147 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2148 sb
.StencilBufferEnable
= true;
2150 sb
.StencilBufferObjectControlState
= GENX(MOCS
);
2152 sb
.SurfacePitch
= image
->stencil_surface
.isl
.row_pitch
- 1;
2155 sb
.SurfaceQPitch
= isl_surf_get_array_pitch_el_rows(&image
->stencil_surface
.isl
) >> 2;
2157 sb
.SurfaceBaseAddress
= (struct anv_address
) {
2159 .offset
= image
->offset
+ image
->stencil_surface
.offset
,
2163 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
);
2166 /* From the IVB PRM Vol2P1, 11.5.5.4 3DSTATE_CLEAR_PARAMS:
2168 * 3DSTATE_CLEAR_PARAMS must always be programmed in the along with
2169 * the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER,
2170 * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER)
2172 * Testing also shows that some variant of this restriction may exist HSW+.
2173 * On BDW+, it is not possible to emit 2 of these packets consecutively when
2174 * both have DepthClearValueValid set. An analysis of such state programming
2175 * on SKL showed that the GPU doesn't register the latter packet's clear
2178 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CLEAR_PARAMS
), cp
) {
2180 cp
.DepthClearValueValid
= true;
2182 cmd_buffer
->state
.subpass
->depth_stencil_attachment
;
2183 cp
.DepthClearValue
=
2184 cmd_buffer
->state
.attachments
[ds
].clear_value
.depthStencil
.depth
;
2190 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
2191 struct anv_subpass
*subpass
)
2193 cmd_buffer
->state
.subpass
= subpass
;
2195 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
2197 cmd_buffer_emit_depth_stencil(cmd_buffer
);
2198 genX(cmd_buffer_emit_hz_op
)(cmd_buffer
, BLORP_HIZ_OP_HIZ_RESOLVE
);
2199 genX(cmd_buffer_emit_hz_op
)(cmd_buffer
, BLORP_HIZ_OP_DEPTH_CLEAR
);
2201 anv_cmd_buffer_clear_subpass(cmd_buffer
);
2204 void genX(CmdBeginRenderPass
)(
2205 VkCommandBuffer commandBuffer
,
2206 const VkRenderPassBeginInfo
* pRenderPassBegin
,
2207 VkSubpassContents contents
)
2209 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2210 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2211 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
2213 cmd_buffer
->state
.framebuffer
= framebuffer
;
2214 cmd_buffer
->state
.pass
= pass
;
2215 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
2216 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
2218 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2220 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
2223 void genX(CmdNextSubpass
)(
2224 VkCommandBuffer commandBuffer
,
2225 VkSubpassContents contents
)
2227 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2229 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
2231 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2232 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
2235 void genX(CmdEndRenderPass
)(
2236 VkCommandBuffer commandBuffer
)
2238 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2240 genX(cmd_buffer_emit_hz_op
)(cmd_buffer
, BLORP_HIZ_OP_DEPTH_RESOLVE
);
2241 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2244 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
2249 emit_ps_depth_count(struct anv_cmd_buffer
*cmd_buffer
,
2250 struct anv_bo
*bo
, uint32_t offset
)
2252 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2253 pc
.DestinationAddressType
= DAT_PPGTT
;
2254 pc
.PostSyncOperation
= WritePSDepthCount
;
2255 pc
.DepthStallEnable
= true;
2256 pc
.Address
= (struct anv_address
) { bo
, offset
};
2258 if (GEN_GEN
== 9 && cmd_buffer
->device
->info
.gt
== 4)
2259 pc
.CommandStreamerStallEnable
= true;
2264 emit_query_availability(struct anv_cmd_buffer
*cmd_buffer
,
2265 struct anv_bo
*bo
, uint32_t offset
)
2267 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2268 pc
.DestinationAddressType
= DAT_PPGTT
;
2269 pc
.PostSyncOperation
= WriteImmediateData
;
2270 pc
.Address
= (struct anv_address
) { bo
, offset
};
2271 pc
.ImmediateData
= 1;
2275 void genX(CmdBeginQuery
)(
2276 VkCommandBuffer commandBuffer
,
2277 VkQueryPool queryPool
,
2279 VkQueryControlFlags flags
)
2281 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2282 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2284 /* Workaround: When meta uses the pipeline with the VS disabled, it seems
2285 * that the pipelining of the depth write breaks. What we see is that
2286 * samples from the render pass clear leaks into the first query
2287 * immediately after the clear. Doing a pipecontrol with a post-sync
2288 * operation and DepthStallEnable seems to work around the issue.
2290 if (cmd_buffer
->state
.need_query_wa
) {
2291 cmd_buffer
->state
.need_query_wa
= false;
2292 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2293 pc
.DepthCacheFlushEnable
= true;
2294 pc
.DepthStallEnable
= true;
2298 switch (pool
->type
) {
2299 case VK_QUERY_TYPE_OCCLUSION
:
2300 emit_ps_depth_count(cmd_buffer
, &pool
->bo
,
2301 query
* sizeof(struct anv_query_pool_slot
));
2304 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
2310 void genX(CmdEndQuery
)(
2311 VkCommandBuffer commandBuffer
,
2312 VkQueryPool queryPool
,
2315 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2316 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2318 switch (pool
->type
) {
2319 case VK_QUERY_TYPE_OCCLUSION
:
2320 emit_ps_depth_count(cmd_buffer
, &pool
->bo
,
2321 query
* sizeof(struct anv_query_pool_slot
) + 8);
2323 emit_query_availability(cmd_buffer
, &pool
->bo
,
2324 query
* sizeof(struct anv_query_pool_slot
) + 16);
2327 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
2333 #define TIMESTAMP 0x2358
2335 void genX(CmdWriteTimestamp
)(
2336 VkCommandBuffer commandBuffer
,
2337 VkPipelineStageFlagBits pipelineStage
,
2338 VkQueryPool queryPool
,
2341 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2342 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2343 uint32_t offset
= query
* sizeof(struct anv_query_pool_slot
);
2345 assert(pool
->type
== VK_QUERY_TYPE_TIMESTAMP
);
2347 switch (pipelineStage
) {
2348 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
:
2349 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2350 srm
.RegisterAddress
= TIMESTAMP
;
2351 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
};
2353 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2354 srm
.RegisterAddress
= TIMESTAMP
+ 4;
2355 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
+ 4 };
2360 /* Everything else is bottom-of-pipe */
2361 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2362 pc
.DestinationAddressType
= DAT_PPGTT
;
2363 pc
.PostSyncOperation
= WriteTimestamp
;
2364 pc
.Address
= (struct anv_address
) { &pool
->bo
, offset
};
2366 if (GEN_GEN
== 9 && cmd_buffer
->device
->info
.gt
== 4)
2367 pc
.CommandStreamerStallEnable
= true;
2372 emit_query_availability(cmd_buffer
, &pool
->bo
, query
+ 16);
2375 #if GEN_GEN > 7 || GEN_IS_HASWELL
2377 #define alu_opcode(v) __gen_uint((v), 20, 31)
2378 #define alu_operand1(v) __gen_uint((v), 10, 19)
2379 #define alu_operand2(v) __gen_uint((v), 0, 9)
2380 #define alu(opcode, operand1, operand2) \
2381 alu_opcode(opcode) | alu_operand1(operand1) | alu_operand2(operand2)
2383 #define OPCODE_NOOP 0x000
2384 #define OPCODE_LOAD 0x080
2385 #define OPCODE_LOADINV 0x480
2386 #define OPCODE_LOAD0 0x081
2387 #define OPCODE_LOAD1 0x481
2388 #define OPCODE_ADD 0x100
2389 #define OPCODE_SUB 0x101
2390 #define OPCODE_AND 0x102
2391 #define OPCODE_OR 0x103
2392 #define OPCODE_XOR 0x104
2393 #define OPCODE_STORE 0x180
2394 #define OPCODE_STOREINV 0x580
2396 #define OPERAND_R0 0x00
2397 #define OPERAND_R1 0x01
2398 #define OPERAND_R2 0x02
2399 #define OPERAND_R3 0x03
2400 #define OPERAND_R4 0x04
2401 #define OPERAND_SRCA 0x20
2402 #define OPERAND_SRCB 0x21
2403 #define OPERAND_ACCU 0x31
2404 #define OPERAND_ZF 0x32
2405 #define OPERAND_CF 0x33
2407 #define CS_GPR(n) (0x2600 + (n) * 8)
2410 emit_load_alu_reg_u64(struct anv_batch
*batch
, uint32_t reg
,
2411 struct anv_bo
*bo
, uint32_t offset
)
2413 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2414 lrm
.RegisterAddress
= reg
,
2415 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
2417 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2418 lrm
.RegisterAddress
= reg
+ 4;
2419 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
2424 store_query_result(struct anv_batch
*batch
, uint32_t reg
,
2425 struct anv_bo
*bo
, uint32_t offset
, VkQueryResultFlags flags
)
2427 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2428 srm
.RegisterAddress
= reg
;
2429 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
2432 if (flags
& VK_QUERY_RESULT_64_BIT
) {
2433 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2434 srm
.RegisterAddress
= reg
+ 4;
2435 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
2440 void genX(CmdCopyQueryPoolResults
)(
2441 VkCommandBuffer commandBuffer
,
2442 VkQueryPool queryPool
,
2443 uint32_t firstQuery
,
2444 uint32_t queryCount
,
2445 VkBuffer destBuffer
,
2446 VkDeviceSize destOffset
,
2447 VkDeviceSize destStride
,
2448 VkQueryResultFlags flags
)
2450 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2451 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2452 ANV_FROM_HANDLE(anv_buffer
, buffer
, destBuffer
);
2453 uint32_t slot_offset
, dst_offset
;
2455 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
2456 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2457 pc
.CommandStreamerStallEnable
= true;
2458 pc
.StallAtPixelScoreboard
= true;
2462 dst_offset
= buffer
->offset
+ destOffset
;
2463 for (uint32_t i
= 0; i
< queryCount
; i
++) {
2465 slot_offset
= (firstQuery
+ i
) * sizeof(struct anv_query_pool_slot
);
2466 switch (pool
->type
) {
2467 case VK_QUERY_TYPE_OCCLUSION
:
2468 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2469 CS_GPR(0), &pool
->bo
, slot_offset
);
2470 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2471 CS_GPR(1), &pool
->bo
, slot_offset
+ 8);
2473 /* FIXME: We need to clamp the result for 32 bit. */
2475 uint32_t *dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
2476 dw
[1] = alu(OPCODE_LOAD
, OPERAND_SRCA
, OPERAND_R1
);
2477 dw
[2] = alu(OPCODE_LOAD
, OPERAND_SRCB
, OPERAND_R0
);
2478 dw
[3] = alu(OPCODE_SUB
, 0, 0);
2479 dw
[4] = alu(OPCODE_STORE
, OPERAND_R2
, OPERAND_ACCU
);
2482 case VK_QUERY_TYPE_TIMESTAMP
:
2483 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2484 CS_GPR(2), &pool
->bo
, slot_offset
);
2488 unreachable("unhandled query type");
2491 store_query_result(&cmd_buffer
->batch
,
2492 CS_GPR(2), buffer
->bo
, dst_offset
, flags
);
2494 if (flags
& VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
) {
2495 emit_load_alu_reg_u64(&cmd_buffer
->batch
, CS_GPR(0),
2496 &pool
->bo
, slot_offset
+ 16);
2497 if (flags
& VK_QUERY_RESULT_64_BIT
)
2498 store_query_result(&cmd_buffer
->batch
,
2499 CS_GPR(0), buffer
->bo
, dst_offset
+ 8, flags
);
2501 store_query_result(&cmd_buffer
->batch
,
2502 CS_GPR(0), buffer
->bo
, dst_offset
+ 4, flags
);
2505 dst_offset
+= destStride
;
2510 void genX(CmdCopyQueryPoolResults
)(
2511 VkCommandBuffer commandBuffer
,
2512 VkQueryPool queryPool
,
2513 uint32_t firstQuery
,
2514 uint32_t queryCount
,
2515 VkBuffer destBuffer
,
2516 VkDeviceSize destOffset
,
2517 VkDeviceSize destStride
,
2518 VkQueryResultFlags flags
)
2520 anv_finishme("Queries not yet supported on Ivy Bridge");