2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
31 #include "common/gen_l3_config.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
36 emit_lrm(struct anv_batch
*batch
,
37 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
39 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
40 lrm
.RegisterAddress
= reg
;
41 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
46 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
48 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
49 lri
.RegisterOffset
= reg
;
54 #if GEN_IS_HASWELL || GEN_GEN >= 8
56 emit_lrr(struct anv_batch
*batch
, uint32_t dst
, uint32_t src
)
58 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
59 lrr
.SourceRegisterAddress
= src
;
60 lrr
.DestinationRegisterAddress
= dst
;
66 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
68 struct anv_device
*device
= cmd_buffer
->device
;
70 /* Emit a render target cache flush.
72 * This isn't documented anywhere in the PRM. However, it seems to be
73 * necessary prior to changing the surface state base adress. Without
74 * this, we get GPU hangs when using multi-level command buffers which
75 * clear depth, reset state base address, and then go render stuff.
77 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
78 pc
.DCFlushEnable
= true;
79 pc
.RenderTargetCacheFlushEnable
= true;
80 pc
.CommandStreamerStallEnable
= true;
83 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
84 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
85 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
86 sba
.GeneralStateBaseAddressModifyEnable
= true;
88 sba
.SurfaceStateBaseAddress
=
89 anv_cmd_buffer_surface_base_address(cmd_buffer
);
90 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
91 sba
.SurfaceStateBaseAddressModifyEnable
= true;
93 sba
.DynamicStateBaseAddress
=
94 (struct anv_address
) { &device
->dynamic_state_pool
.block_pool
.bo
, 0 };
95 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
96 sba
.DynamicStateBaseAddressModifyEnable
= true;
98 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
99 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
100 sba
.IndirectObjectBaseAddressModifyEnable
= true;
102 sba
.InstructionBaseAddress
=
103 (struct anv_address
) { &device
->instruction_state_pool
.block_pool
.bo
, 0 };
104 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
105 sba
.InstructionBaseAddressModifyEnable
= true;
108 /* Broadwell requires that we specify a buffer size for a bunch of
109 * these fields. However, since we will be growing the BO's live, we
110 * just set them all to the maximum.
112 sba
.GeneralStateBufferSize
= 0xfffff;
113 sba
.GeneralStateBufferSizeModifyEnable
= true;
114 sba
.DynamicStateBufferSize
= 0xfffff;
115 sba
.DynamicStateBufferSizeModifyEnable
= true;
116 sba
.IndirectObjectBufferSize
= 0xfffff;
117 sba
.IndirectObjectBufferSizeModifyEnable
= true;
118 sba
.InstructionBufferSize
= 0xfffff;
119 sba
.InstructionBuffersizeModifyEnable
= true;
123 /* After re-setting the surface state base address, we have to do some
124 * cache flusing so that the sampler engine will pick up the new
125 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
126 * Shared Function > 3D Sampler > State > State Caching (page 96):
128 * Coherency with system memory in the state cache, like the texture
129 * cache is handled partially by software. It is expected that the
130 * command stream or shader will issue Cache Flush operation or
131 * Cache_Flush sampler message to ensure that the L1 cache remains
132 * coherent with system memory.
136 * Whenever the value of the Dynamic_State_Base_Addr,
137 * Surface_State_Base_Addr are altered, the L1 state cache must be
138 * invalidated to ensure the new surface or sampler state is fetched
139 * from system memory.
141 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
142 * which, according the PIPE_CONTROL instruction documentation in the
145 * Setting this bit is independent of any other bit in this packet.
146 * This bit controls the invalidation of the L1 and L2 state caches
147 * at the top of the pipe i.e. at the parsing time.
149 * Unfortunately, experimentation seems to indicate that state cache
150 * invalidation through a PIPE_CONTROL does nothing whatsoever in
151 * regards to surface state and binding tables. In stead, it seems that
152 * invalidating the texture cache is what is actually needed.
154 * XXX: As far as we have been able to determine through
155 * experimentation, shows that flush the texture cache appears to be
156 * sufficient. The theory here is that all of the sampling/rendering
157 * units cache the binding table in the texture cache. However, we have
158 * yet to be able to actually confirm this.
160 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
161 pc
.TextureCacheInvalidationEnable
= true;
162 pc
.ConstantCacheInvalidationEnable
= true;
163 pc
.StateCacheInvalidationEnable
= true;
168 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
169 struct anv_state state
,
170 struct anv_bo
*bo
, uint32_t offset
)
172 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
175 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
176 state
.offset
+ isl_dev
->ss
.addr_offset
, bo
, offset
);
177 if (result
!= VK_SUCCESS
)
178 anv_batch_set_error(&cmd_buffer
->batch
, result
);
182 add_image_relocs(struct anv_cmd_buffer
* const cmd_buffer
,
183 const struct anv_image
* const image
,
184 const VkImageAspectFlags aspect_mask
,
185 const enum isl_aux_usage aux_usage
,
186 const struct anv_state state
)
188 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
189 const uint32_t surf_offset
= image
->offset
+
190 anv_image_get_surface_for_aspect_mask(image
, aspect_mask
)->offset
;
192 add_surface_state_reloc(cmd_buffer
, state
, image
->bo
, surf_offset
);
194 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
195 uint32_t aux_offset
= image
->offset
+ image
->aux_surface
.offset
;
197 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
198 * used to store other information. This should be ok, however, because
199 * surface buffer addresses are always 4K page alinged.
201 assert((aux_offset
& 0xfff) == 0);
202 uint32_t *aux_addr_dw
= state
.map
+ isl_dev
->ss
.aux_addr_offset
;
203 aux_offset
+= *aux_addr_dw
& 0xfff;
206 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
207 &cmd_buffer
->pool
->alloc
,
208 state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
209 image
->bo
, aux_offset
);
210 if (result
!= VK_SUCCESS
)
211 anv_batch_set_error(&cmd_buffer
->batch
, result
);
216 color_is_zero_one(VkClearColorValue value
, enum isl_format format
)
218 if (isl_format_has_int_channel(format
)) {
219 for (unsigned i
= 0; i
< 4; i
++) {
220 if (value
.int32
[i
] != 0 && value
.int32
[i
] != 1)
224 for (unsigned i
= 0; i
< 4; i
++) {
225 if (value
.float32
[i
] != 0.0f
&& value
.float32
[i
] != 1.0f
)
234 color_attachment_compute_aux_usage(struct anv_device
* device
,
235 struct anv_cmd_state
* cmd_state
,
236 uint32_t att
, VkRect2D render_area
,
237 union isl_color_value
*fast_clear_color
)
239 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
240 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
242 if (iview
->isl
.base_array_layer
>=
243 anv_image_aux_layers(iview
->image
, iview
->isl
.base_level
)) {
244 /* There is no aux buffer which corresponds to the level and layer(s)
247 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
248 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
249 att_state
->fast_clear
= false;
251 } else if (iview
->image
->aux_usage
== ISL_AUX_USAGE_MCS
) {
252 att_state
->aux_usage
= ISL_AUX_USAGE_MCS
;
253 att_state
->input_aux_usage
= ISL_AUX_USAGE_MCS
;
254 att_state
->fast_clear
= false;
256 } else if (iview
->image
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
257 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
258 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_E
;
260 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
261 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
263 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
264 * setting is only allowed if Surface Format supported for Fast
265 * Clear. In addition, if the surface is bound to the sampling
266 * engine, Surface Format must be supported for Render Target
267 * Compression for surfaces bound to the sampling engine."
269 * In other words, we can only sample from a fast-cleared image if it
270 * also supports color compression.
272 if (isl_format_supports_ccs_e(&device
->info
, iview
->isl
.format
)) {
273 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
275 /* While fast-clear resolves and partial resolves are fairly cheap in the
276 * case where you render to most of the pixels, full resolves are not
277 * because they potentially involve reading and writing the entire
278 * framebuffer. If we can't texture with CCS_E, we should leave it off and
279 * limit ourselves to fast clears.
281 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
282 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
283 anv_perf_warn("Not temporarily enabling CCS_E.");
286 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
290 assert(iview
->image
->aux_surface
.isl
.usage
& ISL_SURF_USAGE_CCS_BIT
);
292 att_state
->clear_color_is_zero_one
=
293 color_is_zero_one(att_state
->clear_value
.color
, iview
->isl
.format
);
294 att_state
->clear_color_is_zero
=
295 att_state
->clear_value
.color
.uint32
[0] == 0 &&
296 att_state
->clear_value
.color
.uint32
[1] == 0 &&
297 att_state
->clear_value
.color
.uint32
[2] == 0 &&
298 att_state
->clear_value
.color
.uint32
[3] == 0;
300 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
301 /* Start off assuming fast clears are possible */
302 att_state
->fast_clear
= true;
304 /* Potentially, we could do partial fast-clears but doing so has crazy
305 * alignment restrictions. It's easier to just restrict to full size
306 * fast clears for now.
308 if (render_area
.offset
.x
!= 0 ||
309 render_area
.offset
.y
!= 0 ||
310 render_area
.extent
.width
!= iview
->extent
.width
||
311 render_area
.extent
.height
!= iview
->extent
.height
)
312 att_state
->fast_clear
= false;
314 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
315 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
316 att_state
->fast_clear
= false;
318 /* We allow fast clears when all aux layers of the miplevel are targeted.
319 * See add_fast_clear_state_buffer() for more information. Also, because
320 * we only either do a fast clear or a normal clear and not both, this
321 * complies with the gen7 restriction of not fast-clearing multiple
324 if (cmd_state
->framebuffer
->layers
!=
325 anv_image_aux_layers(iview
->image
, iview
->isl
.base_level
)) {
326 att_state
->fast_clear
= false;
328 anv_perf_warn("Not fast-clearing the first layer in "
329 "a multi-layer fast clear.");
333 /* We only allow fast clears in the GENERAL layout if the auxiliary
334 * buffer is always enabled and the fast-clear value is all 0's. See
335 * add_fast_clear_state_buffer() for more information.
337 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
338 VK_IMAGE_LAYOUT_GENERAL
&&
339 (!att_state
->clear_color_is_zero
||
340 iview
->image
->aux_usage
== ISL_AUX_USAGE_NONE
)) {
341 att_state
->fast_clear
= false;
344 if (att_state
->fast_clear
) {
345 memcpy(fast_clear_color
->u32
, att_state
->clear_value
.color
.uint32
,
346 sizeof(fast_clear_color
->u32
));
349 att_state
->fast_clear
= false;
354 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
356 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
359 /* We only allocate input attachment states for color surfaces. Compression
360 * is not yet enabled for depth textures and stencil doesn't allow
361 * compression so we can just use the texture surface state from the view.
363 return vk_format_is_color(att
->format
);
366 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
367 * the initial layout is undefined, the HiZ buffer and depth buffer will
368 * represent the same data at the end of this operation.
371 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
372 const struct anv_image
*image
,
373 VkImageLayout initial_layout
,
374 VkImageLayout final_layout
)
378 /* A transition is a no-op if HiZ is not enabled, or if the initial and
379 * final layouts are equal.
381 * The undefined layout indicates that the user doesn't care about the data
382 * that's currently in the buffer. Therefore, a data-preserving resolve
383 * operation is not needed.
385 if (image
->aux_usage
!= ISL_AUX_USAGE_HIZ
|| initial_layout
== final_layout
)
388 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
389 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
, image
->aspects
,
391 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
392 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
, image
->aspects
,
395 enum blorp_hiz_op hiz_op
;
396 if (hiz_enabled
&& !enable_hiz
) {
397 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
398 } else if (!hiz_enabled
&& enable_hiz
) {
399 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
401 assert(hiz_enabled
== enable_hiz
);
402 /* If the same buffer will be used, no resolves are necessary. */
403 hiz_op
= BLORP_HIZ_OP_NONE
;
406 if (hiz_op
!= BLORP_HIZ_OP_NONE
)
407 anv_gen8_hiz_op_resolve(cmd_buffer
, image
, hiz_op
);
410 enum fast_clear_state_field
{
411 FAST_CLEAR_STATE_FIELD_CLEAR_COLOR
,
412 FAST_CLEAR_STATE_FIELD_NEEDS_RESOLVE
,
415 static inline uint32_t
416 get_fast_clear_state_offset(const struct anv_device
*device
,
417 const struct anv_image
*image
,
418 unsigned level
, enum fast_clear_state_field field
)
420 assert(device
&& image
);
421 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
422 assert(level
< anv_image_aux_levels(image
));
423 uint32_t offset
= image
->offset
+ image
->aux_surface
.offset
+
424 image
->aux_surface
.isl
.size
+
425 anv_fast_clear_state_entry_size(device
) * level
;
428 case FAST_CLEAR_STATE_FIELD_NEEDS_RESOLVE
:
429 offset
+= device
->isl_dev
.ss
.clear_value_size
;
431 case FAST_CLEAR_STATE_FIELD_CLEAR_COLOR
:
435 assert(offset
< image
->offset
+ image
->size
);
439 #define MI_PREDICATE_SRC0 0x2400
440 #define MI_PREDICATE_SRC1 0x2408
442 /* Manages the state of an color image subresource to ensure resolves are
443 * performed properly.
446 genX(set_image_needs_resolve
)(struct anv_cmd_buffer
*cmd_buffer
,
447 const struct anv_image
*image
,
448 unsigned level
, bool needs_resolve
)
450 assert(cmd_buffer
&& image
);
451 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
452 assert(level
< anv_image_aux_levels(image
));
454 const uint32_t resolve_flag_offset
=
455 get_fast_clear_state_offset(cmd_buffer
->device
, image
, level
,
456 FAST_CLEAR_STATE_FIELD_NEEDS_RESOLVE
);
458 /* The HW docs say that there is no way to guarantee the completion of
459 * the following command. We use it nevertheless because it shows no
460 * issues in testing is currently being used in the GL driver.
462 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
463 sdi
.Address
= (struct anv_address
) { image
->bo
, resolve_flag_offset
};
464 sdi
.ImmediateData
= needs_resolve
;
469 genX(load_needs_resolve_predicate
)(struct anv_cmd_buffer
*cmd_buffer
,
470 const struct anv_image
*image
,
473 assert(cmd_buffer
&& image
);
474 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
475 assert(level
< anv_image_aux_levels(image
));
477 const uint32_t resolve_flag_offset
=
478 get_fast_clear_state_offset(cmd_buffer
->device
, image
, level
,
479 FAST_CLEAR_STATE_FIELD_NEEDS_RESOLVE
);
481 /* Make the pending predicated resolve a no-op if one is not needed.
482 * predicate = do_resolve = resolve_flag != 0;
484 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
485 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
486 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, 0);
487 emit_lrm(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4,
488 image
->bo
, resolve_flag_offset
);
489 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
490 mip
.LoadOperation
= LOAD_LOADINV
;
491 mip
.CombineOperation
= COMBINE_SET
;
492 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
497 init_fast_clear_state_entry(struct anv_cmd_buffer
*cmd_buffer
,
498 const struct anv_image
*image
,
501 assert(cmd_buffer
&& image
);
502 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
503 assert(level
< anv_image_aux_levels(image
));
505 /* The resolve flag should updated to signify that fast-clear/compression
506 * data needs to be removed when leaving the undefined layout. Such data
507 * may need to be removed if it would cause accesses to the color buffer
508 * to return incorrect data. The fast clear data in CCS_D buffers should
509 * be removed because CCS_D isn't enabled all the time.
511 genX(set_image_needs_resolve
)(cmd_buffer
, image
, level
,
512 image
->aux_usage
== ISL_AUX_USAGE_NONE
);
514 /* The fast clear value dword(s) will be copied into a surface state object.
515 * Ensure that the restrictions of the fields in the dword(s) are followed.
517 * CCS buffers on SKL+ can have any value set for the clear colors.
519 if (image
->samples
== 1 && GEN_GEN
>= 9)
522 /* Other combinations of auxiliary buffers and platforms require specific
523 * values in the clear value dword(s).
526 for (; i
< cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
; i
+= 4) {
527 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
528 const uint32_t entry_offset
=
529 get_fast_clear_state_offset(cmd_buffer
->device
, image
, level
,
530 FAST_CLEAR_STATE_FIELD_CLEAR_COLOR
);
531 sdi
.Address
= (struct anv_address
) { image
->bo
, entry_offset
+ i
};
534 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
535 assert(image
->aux_usage
== ISL_AUX_USAGE_MCS
);
536 sdi
.ImmediateData
= 0;
537 } else if (GEN_VERSIONx10
>= 75) {
538 /* Pre-SKL, the dword containing the clear values also contains
539 * other fields, so we need to initialize those fields to match the
540 * values that would be in a color attachment.
543 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
544 ISL_CHANNEL_SELECT_GREEN
<< 22 |
545 ISL_CHANNEL_SELECT_BLUE
<< 19 |
546 ISL_CHANNEL_SELECT_ALPHA
<< 16;
547 } else if (GEN_VERSIONx10
== 70) {
548 /* On IVB, the dword containing the clear values also contains
549 * other fields that must be zero or can be zero.
552 sdi
.ImmediateData
= 0;
558 /* Copy the fast-clear value dword(s) between a surface state object and an
559 * image's fast clear state buffer.
562 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
563 struct anv_state surface_state
,
564 const struct anv_image
*image
,
566 bool copy_from_surface_state
)
568 assert(cmd_buffer
&& image
);
569 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
570 assert(level
< anv_image_aux_levels(image
));
572 struct anv_bo
*ss_bo
=
573 &cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
;
574 uint32_t ss_clear_offset
= surface_state
.offset
+
575 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
;
576 uint32_t entry_offset
=
577 get_fast_clear_state_offset(cmd_buffer
->device
, image
, level
,
578 FAST_CLEAR_STATE_FIELD_CLEAR_COLOR
);
579 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
581 if (copy_from_surface_state
) {
582 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, image
->bo
, entry_offset
,
583 ss_bo
, ss_clear_offset
, copy_size
);
585 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, ss_bo
, ss_clear_offset
,
586 image
->bo
, entry_offset
, copy_size
);
588 /* Updating a surface state object may require that the state cache be
589 * invalidated. From the SKL PRM, Shared Functions -> State -> State
592 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
593 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
594 * modified [...], the L1 state cache must be invalidated to ensure
595 * the new surface or sampler state is fetched from system memory.
597 * In testing, SKL doesn't actually seem to need this, but HSW does.
599 cmd_buffer
->state
.pending_pipe_bits
|=
600 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
605 * @brief Transitions a color buffer from one layout to another.
607 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
610 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
611 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
612 * this represents the maximum layers to transition at each
613 * specified miplevel.
616 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
617 const struct anv_image
*image
,
618 const uint32_t base_level
, uint32_t level_count
,
619 uint32_t base_layer
, uint32_t layer_count
,
620 VkImageLayout initial_layout
,
621 VkImageLayout final_layout
)
623 /* Validate the inputs. */
625 assert(image
&& image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
626 /* These values aren't supported for simplicity's sake. */
627 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
628 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
629 /* Ensure the subresource range is valid. */
630 uint64_t last_level_num
= base_level
+ level_count
;
631 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
632 const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
633 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
634 assert(last_level_num
<= image
->levels
);
635 /* The spec disallows these final layouts. */
636 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
637 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
639 /* No work is necessary if the layout stays the same or if this subresource
640 * range lacks auxiliary data.
642 if (initial_layout
== final_layout
||
643 base_layer
>= anv_image_aux_layers(image
, base_level
))
646 /* A transition of a 3D subresource works on all slices at a time. */
647 if (image
->type
== VK_IMAGE_TYPE_3D
) {
649 layer_count
= anv_minify(image
->extent
.depth
, base_level
);
652 /* We're interested in the subresource range subset that has aux data. */
653 level_count
= MIN2(level_count
, anv_image_aux_levels(image
) - base_level
);
654 layer_count
= MIN2(layer_count
,
655 anv_image_aux_layers(image
, base_level
) - base_layer
);
656 last_level_num
= base_level
+ level_count
;
658 /* Record whether or not the layout is undefined. Pre-initialized images
659 * with auxiliary buffers have a non-linear layout and are thus undefined.
661 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
662 const bool undef_layout
= initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
663 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
;
665 /* Do preparatory work before the resolve operation or return early if no
666 * resolve is actually needed.
669 /* A subresource in the undefined layout may have been aliased and
670 * populated with any arrangement of bits. Therefore, we must initialize
671 * the related aux buffer and clear buffer entry with desirable values.
673 * Initialize the relevant clear buffer entries.
675 for (unsigned level
= base_level
; level
< last_level_num
; level
++)
676 init_fast_clear_state_entry(cmd_buffer
, image
, level
);
678 /* Initialize the aux buffers to enable correct rendering. This operation
679 * requires up to two steps: one to rid the aux buffer of data that may
680 * cause GPU hangs, and another to ensure that writes done without aux
681 * will be visible to reads done with aux.
683 * Having an aux buffer with invalid data is possible for CCS buffers
684 * SKL+ and for MCS buffers with certain sample counts (2x and 8x). One
685 * easy way to get to a valid state is to fast-clear the specified range.
687 * Even for MCS buffers that have sample counts that don't require
688 * certain bits to be reserved (4x and 8x), we're unsure if the hardware
689 * will be okay with the sample mappings given by the undefined buffer.
690 * We don't have any data to show that this is a problem, but we want to
691 * avoid causing difficult-to-debug problems.
693 if ((GEN_GEN
>= 9 && image
->samples
== 1) || image
->samples
> 1) {
694 if (image
->samples
== 4 || image
->samples
== 16) {
695 anv_perf_warn("Doing a potentially unnecessary fast-clear to "
696 "define an MCS buffer.");
699 anv_image_fast_clear(cmd_buffer
, image
, base_level
, level_count
,
700 base_layer
, layer_count
);
702 /* At this point, some elements of the CCS buffer may have the fast-clear
703 * bit-arrangement. As the user writes to a subresource, we need to have
704 * the associated CCS elements enter the ambiguated state. This enables
705 * reads (implicit or explicit) to reflect the user-written data instead
706 * of the clear color. The only time such elements will not change their
707 * state as described above, is in a final layout that doesn't have CCS
708 * enabled. In this case, we must force the associated CCS buffers of the
709 * specified range to enter the ambiguated state in advance.
711 if (image
->samples
== 1 && image
->aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
712 final_layout
!= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
713 /* The CCS_D buffer may not be enabled in the final layout. Continue
714 * executing this function to perform a resolve.
716 anv_perf_warn("Performing an additional resolve for CCS_D layout "
717 "transition. Consider always leaving it on or "
718 "performing an ambiguation pass.");
720 /* Writes in the final layout will be aware of the auxiliary buffer.
721 * In addition, the clear buffer entries and the auxiliary buffers
722 * have been populated with values that will result in correct
727 } else if (initial_layout
!= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
728 /* Resolves are only necessary if the subresource may contain blocks
729 * fast-cleared to values unsupported in other layouts. This only occurs
730 * if the initial layout is COLOR_ATTACHMENT_OPTIMAL.
733 } else if (image
->samples
> 1) {
734 /* MCS buffers don't need resolving. */
738 /* Perform a resolve to synchronize data between the main and aux buffer.
739 * Before we begin, we must satisfy the cache flushing requirement specified
740 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
742 * Any transition from any value in {Clear, Render, Resolve} to a
743 * different value in {Clear, Render, Resolve} requires end of pipe
746 * We perform a flush of the write cache before and after the clear and
747 * resolve operations to meet this requirement.
749 * Unlike other drawing, fast clear operations are not properly
750 * synchronized. The first PIPE_CONTROL here likely ensures that the
751 * contents of the previous render or clear hit the render target before we
752 * resolve and the second likely ensures that the resolve is complete before
753 * we do any more rendering or clearing.
755 cmd_buffer
->state
.pending_pipe_bits
|=
756 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
758 for (uint32_t level
= base_level
; level
< last_level_num
; level
++) {
760 /* The number of layers changes at each 3D miplevel. */
761 if (image
->type
== VK_IMAGE_TYPE_3D
) {
762 layer_count
= MIN2(layer_count
, anv_image_aux_layers(image
, level
));
765 genX(load_needs_resolve_predicate
)(cmd_buffer
, image
, level
);
767 /* Create a surface state with the right clear color and perform the
770 struct anv_state surface_state
=
771 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
772 isl_surf_fill_state(&cmd_buffer
->device
->isl_dev
, surface_state
.map
,
773 .surf
= &image
->color_surface
.isl
,
774 .view
= &(struct isl_view
) {
775 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
776 .format
= image
->color_surface
.isl
.format
,
777 .swizzle
= ISL_SWIZZLE_IDENTITY
,
780 .base_array_layer
= base_layer
,
781 .array_len
= layer_count
,
783 .aux_surf
= &image
->aux_surface
.isl
,
784 .aux_usage
= image
->aux_usage
== ISL_AUX_USAGE_NONE
?
785 ISL_AUX_USAGE_CCS_D
: image
->aux_usage
,
786 .mocs
= cmd_buffer
->device
->default_mocs
);
787 add_image_relocs(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
788 image
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
789 ISL_AUX_USAGE_CCS_E
: ISL_AUX_USAGE_CCS_D
,
791 anv_state_flush(cmd_buffer
->device
, surface_state
);
792 genX(copy_fast_clear_dwords
)(cmd_buffer
, surface_state
, image
, level
,
793 false /* copy to ss */);
794 anv_ccs_resolve(cmd_buffer
, surface_state
, image
, level
, layer_count
,
795 image
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
796 BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
797 BLORP_FAST_CLEAR_OP_RESOLVE_FULL
);
799 genX(set_image_needs_resolve
)(cmd_buffer
, image
, level
, false);
802 cmd_buffer
->state
.pending_pipe_bits
|=
803 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
807 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
810 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
811 struct anv_render_pass
*pass
,
812 const VkRenderPassBeginInfo
*begin
)
814 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
815 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
817 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
819 if (pass
->attachment_count
> 0) {
820 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
821 pass
->attachment_count
*
822 sizeof(state
->attachments
[0]),
823 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
824 if (state
->attachments
== NULL
) {
825 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
826 return anv_batch_set_error(&cmd_buffer
->batch
,
827 VK_ERROR_OUT_OF_HOST_MEMORY
);
830 state
->attachments
= NULL
;
833 /* Reserve one for the NULL state. */
834 unsigned num_states
= 1;
835 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
836 if (vk_format_is_color(pass
->attachments
[i
].format
))
839 if (need_input_attachment_state(&pass
->attachments
[i
]))
843 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
844 state
->render_pass_states
=
845 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
846 num_states
* ss_stride
, isl_dev
->ss
.align
);
848 struct anv_state next_state
= state
->render_pass_states
;
849 next_state
.alloc_size
= isl_dev
->ss
.size
;
851 state
->null_surface_state
= next_state
;
852 next_state
.offset
+= ss_stride
;
853 next_state
.map
+= ss_stride
;
855 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
856 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
857 state
->attachments
[i
].color_rt_state
= next_state
;
858 next_state
.offset
+= ss_stride
;
859 next_state
.map
+= ss_stride
;
862 if (need_input_attachment_state(&pass
->attachments
[i
])) {
863 state
->attachments
[i
].input_att_state
= next_state
;
864 next_state
.offset
+= ss_stride
;
865 next_state
.map
+= ss_stride
;
868 assert(next_state
.offset
== state
->render_pass_states
.offset
+
869 state
->render_pass_states
.alloc_size
);
872 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
873 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
875 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
876 isl_extent3d(framebuffer
->width
,
878 framebuffer
->layers
));
880 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
881 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
882 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
883 VkImageAspectFlags clear_aspects
= 0;
885 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
886 /* color attachment */
887 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
888 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
891 /* depthstencil attachment */
892 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
893 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
894 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
896 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
897 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
898 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
902 state
->attachments
[i
].current_layout
= att
->initial_layout
;
903 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
905 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
907 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
908 anv_assert(iview
->vk_format
== att
->format
);
910 union isl_color_value clear_color
= { .u32
= { 0, } };
911 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
912 color_attachment_compute_aux_usage(cmd_buffer
->device
,
913 state
, i
, begin
->renderArea
,
916 struct isl_view view
= iview
->isl
;
917 view
.usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
918 view
.swizzle
= anv_swizzle_for_render(view
.swizzle
);
919 isl_surf_fill_state(isl_dev
,
920 state
->attachments
[i
].color_rt_state
.map
,
921 .surf
= &iview
->image
->color_surface
.isl
,
923 .aux_surf
= &iview
->image
->aux_surface
.isl
,
924 .aux_usage
= state
->attachments
[i
].aux_usage
,
925 .clear_color
= clear_color
,
926 .mocs
= cmd_buffer
->device
->default_mocs
);
928 add_image_relocs(cmd_buffer
, iview
->image
, iview
->aspect_mask
,
929 state
->attachments
[i
].aux_usage
,
930 state
->attachments
[i
].color_rt_state
);
932 /* This field will be initialized after the first subpass
935 state
->attachments
[i
].aux_usage
= ISL_AUX_USAGE_NONE
;
937 state
->attachments
[i
].input_aux_usage
= ISL_AUX_USAGE_NONE
;
940 if (need_input_attachment_state(&pass
->attachments
[i
])) {
941 struct isl_view view
= iview
->isl
;
942 view
.usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
943 isl_surf_fill_state(isl_dev
,
944 state
->attachments
[i
].input_att_state
.map
,
945 .surf
= &iview
->image
->color_surface
.isl
,
947 .aux_surf
= &iview
->image
->aux_surface
.isl
,
948 .aux_usage
= state
->attachments
[i
].input_aux_usage
,
949 .clear_color
= clear_color
,
950 .mocs
= cmd_buffer
->device
->default_mocs
);
952 add_image_relocs(cmd_buffer
, iview
->image
, iview
->aspect_mask
,
953 state
->attachments
[i
].input_aux_usage
,
954 state
->attachments
[i
].input_att_state
);
958 anv_state_flush(cmd_buffer
->device
, state
->render_pass_states
);
965 genX(BeginCommandBuffer
)(
966 VkCommandBuffer commandBuffer
,
967 const VkCommandBufferBeginInfo
* pBeginInfo
)
969 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
971 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
972 * command buffer's state. Otherwise, we must *reset* its state. In both
975 * From the Vulkan 1.0 spec:
977 * If a command buffer is in the executable state and the command buffer
978 * was allocated from a command pool with the
979 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
980 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
981 * as if vkResetCommandBuffer had been called with
982 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
983 * the command buffer in the recording state.
985 anv_cmd_buffer_reset(cmd_buffer
);
987 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
989 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
990 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
992 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
994 /* We sometimes store vertex data in the dynamic state buffer for blorp
995 * operations and our dynamic state stream may re-use data from previous
996 * command buffers. In order to prevent stale cache data, we flush the VF
997 * cache. We could do this on every blorp call but that's not really
998 * needed as all of the data will get written by the CPU prior to the GPU
999 * executing anything. The chances are fairly high that they will use
1000 * blorp at least once per primary command buffer so it shouldn't be
1003 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1004 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1006 VkResult result
= VK_SUCCESS
;
1007 if (cmd_buffer
->usage_flags
&
1008 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1009 cmd_buffer
->state
.pass
=
1010 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1011 cmd_buffer
->state
.subpass
=
1012 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1013 cmd_buffer
->state
.framebuffer
= NULL
;
1015 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1016 cmd_buffer
->state
.pass
, NULL
);
1018 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1025 genX(EndCommandBuffer
)(
1026 VkCommandBuffer commandBuffer
)
1028 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1030 if (anv_batch_has_error(&cmd_buffer
->batch
))
1031 return cmd_buffer
->batch
.status
;
1033 /* We want every command buffer to start with the PMA fix in a known state,
1034 * so we disable it at the end of the command buffer.
1036 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1038 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1040 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1046 genX(CmdExecuteCommands
)(
1047 VkCommandBuffer commandBuffer
,
1048 uint32_t commandBufferCount
,
1049 const VkCommandBuffer
* pCmdBuffers
)
1051 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1053 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1055 if (anv_batch_has_error(&primary
->batch
))
1058 /* The secondary command buffers will assume that the PMA fix is disabled
1059 * when they begin executing. Make sure this is true.
1061 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1063 /* The secondary command buffer doesn't know which textures etc. have been
1064 * flushed prior to their execution. Apply those flushes now.
1066 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1068 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1069 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1071 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1072 assert(!anv_batch_has_error(&secondary
->batch
));
1074 if (secondary
->usage_flags
&
1075 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1076 /* If we're continuing a render pass from the primary, we need to
1077 * copy the surface states for the current subpass into the storage
1078 * we allocated for them in BeginCommandBuffer.
1080 struct anv_bo
*ss_bo
=
1081 &primary
->device
->surface_state_pool
.block_pool
.bo
;
1082 struct anv_state src_state
= primary
->state
.render_pass_states
;
1083 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1084 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1086 genX(cmd_buffer_so_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
1087 ss_bo
, src_state
.offset
,
1088 src_state
.alloc_size
);
1091 anv_cmd_buffer_add_secondary(primary
, secondary
);
1094 /* Each of the secondary command buffers will use its own state base
1095 * address. We need to re-emit state base address for the primary after
1096 * all of the secondaries are done.
1098 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1101 genX(cmd_buffer_emit_state_base_address
)(primary
);
1104 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1105 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1106 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1109 * Program the hardware to use the specified L3 configuration.
1112 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1113 const struct gen_l3_config
*cfg
)
1116 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1119 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1120 fprintf(stderr
, "L3 config transition: ");
1121 gen_dump_l3_config(cfg
, stderr
);
1124 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1126 /* According to the hardware docs, the L3 partitioning can only be changed
1127 * while the pipeline is completely drained and the caches are flushed,
1128 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1130 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1131 pc
.DCFlushEnable
= true;
1132 pc
.PostSyncOperation
= NoWrite
;
1133 pc
.CommandStreamerStallEnable
= true;
1136 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1137 * invalidation of the relevant caches. Note that because RO invalidation
1138 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1139 * command is processed by the CS) we cannot combine it with the previous
1140 * stalling flush as the hardware documentation suggests, because that
1141 * would cause the CS to stall on previous rendering *after* RO
1142 * invalidation and wouldn't prevent the RO caches from being polluted by
1143 * concurrent rendering before the stall completes. This intentionally
1144 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1145 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1146 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1147 * already guarantee that there is no concurrent GPGPU kernel execution
1148 * (see SKL HSD 2132585).
1150 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1151 pc
.TextureCacheInvalidationEnable
= true;
1152 pc
.ConstantCacheInvalidationEnable
= true;
1153 pc
.InstructionCacheInvalidateEnable
= true;
1154 pc
.StateCacheInvalidationEnable
= true;
1155 pc
.PostSyncOperation
= NoWrite
;
1158 /* Now send a third stalling flush to make sure that invalidation is
1159 * complete when the L3 configuration registers are modified.
1161 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1162 pc
.DCFlushEnable
= true;
1163 pc
.PostSyncOperation
= NoWrite
;
1164 pc
.CommandStreamerStallEnable
= true;
1169 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1172 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1173 .SLMEnable
= has_slm
,
1174 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1175 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1176 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1177 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1179 /* Set up the L3 partitioning. */
1180 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1184 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1185 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1186 cfg
->n
[GEN_L3P_ALL
];
1187 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1188 cfg
->n
[GEN_L3P_ALL
];
1189 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1190 cfg
->n
[GEN_L3P_ALL
];
1192 assert(!cfg
->n
[GEN_L3P_ALL
]);
1194 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1195 * the matching space on the remaining banks has to be allocated to a
1196 * client (URB for all validated configurations) set to the
1197 * lower-bandwidth 2-bank address hashing mode.
1199 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1200 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1201 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1203 /* Minimum number of ways that can be allocated to the URB. */
1204 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1205 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1207 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1208 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1209 .ConvertDC_UC
= !has_dc
,
1210 .ConvertIS_UC
= !has_is
,
1211 .ConvertC_UC
= !has_c
,
1212 .ConvertT_UC
= !has_t
);
1214 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1215 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1216 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1218 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1219 .SLMEnable
= has_slm
,
1220 .URBLowBandwidth
= urb_low_bw
,
1221 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1223 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1225 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1226 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1228 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1229 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1230 .ISLowBandwidth
= 0,
1231 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1233 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1234 .TLowBandwidth
= 0);
1236 /* Set up the L3 partitioning. */
1237 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1238 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1239 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1242 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1243 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1244 * them disabled to avoid crashing the system hard.
1246 uint32_t scratch1
, chicken3
;
1247 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1248 .L3AtomicDisable
= !has_dc
);
1249 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1250 .L3AtomicDisableMask
= true,
1251 .L3AtomicDisable
= !has_dc
);
1252 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1253 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1259 cmd_buffer
->state
.current_l3_config
= cfg
;
1263 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1265 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1267 /* Flushes are pipelined while invalidations are handled immediately.
1268 * Therefore, if we're flushing anything then we need to schedule a stall
1269 * before any invalidations can happen.
1271 if (bits
& ANV_PIPE_FLUSH_BITS
)
1272 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1274 /* If we're going to do an invalidate and we have a pending CS stall that
1275 * has yet to be resolved, we do the CS stall now.
1277 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1278 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1279 bits
|= ANV_PIPE_CS_STALL_BIT
;
1280 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1283 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1284 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1285 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1286 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1287 pipe
.RenderTargetCacheFlushEnable
=
1288 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1290 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1291 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1292 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1295 * According to the Broadwell documentation, any PIPE_CONTROL with the
1296 * "Command Streamer Stall" bit set must also have another bit set,
1297 * with five different options:
1299 * - Render Target Cache Flush
1300 * - Depth Cache Flush
1301 * - Stall at Pixel Scoreboard
1302 * - Post-Sync Operation
1306 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1307 * mesa and it seems to work fine. The choice is fairly arbitrary.
1309 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1310 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1311 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1312 pipe
.StallAtPixelScoreboard
= true;
1315 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1318 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1319 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1320 pipe
.StateCacheInvalidationEnable
=
1321 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1322 pipe
.ConstantCacheInvalidationEnable
=
1323 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1324 pipe
.VFCacheInvalidationEnable
=
1325 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1326 pipe
.TextureCacheInvalidationEnable
=
1327 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1328 pipe
.InstructionCacheInvalidateEnable
=
1329 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1332 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1335 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1338 void genX(CmdPipelineBarrier
)(
1339 VkCommandBuffer commandBuffer
,
1340 VkPipelineStageFlags srcStageMask
,
1341 VkPipelineStageFlags destStageMask
,
1343 uint32_t memoryBarrierCount
,
1344 const VkMemoryBarrier
* pMemoryBarriers
,
1345 uint32_t bufferMemoryBarrierCount
,
1346 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1347 uint32_t imageMemoryBarrierCount
,
1348 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1350 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1352 /* XXX: Right now, we're really dumb and just flush whatever categories
1353 * the app asks for. One of these days we may make this a bit better
1354 * but right now that's all the hardware allows for in most areas.
1356 VkAccessFlags src_flags
= 0;
1357 VkAccessFlags dst_flags
= 0;
1359 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1360 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1361 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1364 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1365 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1366 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1369 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1370 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1371 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1372 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1373 const VkImageSubresourceRange
*range
=
1374 &pImageMemoryBarriers
[i
].subresourceRange
;
1376 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1377 transition_depth_buffer(cmd_buffer
, image
,
1378 pImageMemoryBarriers
[i
].oldLayout
,
1379 pImageMemoryBarriers
[i
].newLayout
);
1380 } else if (range
->aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
) {
1381 transition_color_buffer(cmd_buffer
, image
,
1382 range
->baseMipLevel
,
1383 anv_get_levelCount(image
, range
),
1384 range
->baseArrayLayer
,
1385 anv_get_layerCount(image
, range
),
1386 pImageMemoryBarriers
[i
].oldLayout
,
1387 pImageMemoryBarriers
[i
].newLayout
);
1391 cmd_buffer
->state
.pending_pipe_bits
|=
1392 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1393 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1397 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1399 VkShaderStageFlags stages
= cmd_buffer
->state
.pipeline
->active_stages
;
1401 /* In order to avoid thrash, we assume that vertex and fragment stages
1402 * always exist. In the rare case where one is missing *and* the other
1403 * uses push concstants, this may be suboptimal. However, avoiding stalls
1404 * seems more important.
1406 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1408 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1412 const unsigned push_constant_kb
= 32;
1413 #elif GEN_IS_HASWELL
1414 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1416 const unsigned push_constant_kb
= 16;
1419 const unsigned num_stages
=
1420 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1421 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1423 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1424 * units of 2KB. Incidentally, these are the same platforms that have
1425 * 32KB worth of push constant space.
1427 if (push_constant_kb
== 32)
1428 size_per_stage
&= ~1u;
1430 uint32_t kb_used
= 0;
1431 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1432 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1433 anv_batch_emit(&cmd_buffer
->batch
,
1434 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1435 alloc
._3DCommandSubOpcode
= 18 + i
;
1436 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1437 alloc
.ConstantBufferSize
= push_size
;
1439 kb_used
+= push_size
;
1442 anv_batch_emit(&cmd_buffer
->batch
,
1443 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1444 alloc
.ConstantBufferOffset
= kb_used
;
1445 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1448 cmd_buffer
->state
.push_constant_stages
= stages
;
1450 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1452 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1453 * the next 3DPRIMITIVE command after programming the
1454 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1456 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1457 * pipeline setup, we need to dirty push constants.
1459 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1463 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1464 gl_shader_stage stage
,
1465 struct anv_state
*bt_state
)
1467 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1468 struct anv_pipeline
*pipeline
;
1469 uint32_t bias
, state_offset
;
1472 case MESA_SHADER_COMPUTE
:
1473 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1477 pipeline
= cmd_buffer
->state
.pipeline
;
1482 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1483 *bt_state
= (struct anv_state
) { 0, };
1487 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1488 if (bias
+ map
->surface_count
== 0) {
1489 *bt_state
= (struct anv_state
) { 0, };
1493 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
1494 bias
+ map
->surface_count
,
1496 uint32_t *bt_map
= bt_state
->map
;
1498 if (bt_state
->map
== NULL
)
1499 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1501 if (stage
== MESA_SHADER_COMPUTE
&&
1502 get_cs_prog_data(cmd_buffer
->state
.compute_pipeline
)->uses_num_work_groups
) {
1503 struct anv_bo
*bo
= cmd_buffer
->state
.num_workgroups_bo
;
1504 uint32_t bo_offset
= cmd_buffer
->state
.num_workgroups_offset
;
1506 struct anv_state surface_state
;
1508 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
1510 const enum isl_format format
=
1511 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
1512 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1513 format
, bo_offset
, 12, 1);
1515 bt_map
[0] = surface_state
.offset
+ state_offset
;
1516 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
1519 if (map
->surface_count
== 0)
1522 if (map
->image_count
> 0) {
1524 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
1525 if (result
!= VK_SUCCESS
)
1528 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
1532 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
1533 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
1535 struct anv_state surface_state
;
1537 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
1538 /* Color attachment binding */
1539 assert(stage
== MESA_SHADER_FRAGMENT
);
1540 assert(binding
->binding
== 0);
1541 if (binding
->index
< subpass
->color_count
) {
1542 const unsigned att
=
1543 subpass
->color_attachments
[binding
->index
].attachment
;
1545 /* From the Vulkan 1.0.46 spec:
1547 * "If any color or depth/stencil attachments are
1548 * VK_ATTACHMENT_UNUSED, then no writes occur for those
1551 if (att
== VK_ATTACHMENT_UNUSED
) {
1552 surface_state
= cmd_buffer
->state
.null_surface_state
;
1554 surface_state
= cmd_buffer
->state
.attachments
[att
].color_rt_state
;
1557 surface_state
= cmd_buffer
->state
.null_surface_state
;
1560 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1564 struct anv_descriptor_set
*set
=
1565 cmd_buffer
->state
.descriptors
[binding
->set
];
1566 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1567 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1569 switch (desc
->type
) {
1570 case VK_DESCRIPTOR_TYPE_SAMPLER
:
1571 /* Nothing for us to do here */
1574 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
1575 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
1576 enum isl_aux_usage aux_usage
;
1577 if (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) {
1578 surface_state
= desc
->image_view
->general_sampler_surface_state
;
1579 aux_usage
= desc
->image_view
->general_sampler_aux_usage
;
1581 surface_state
= desc
->image_view
->optimal_sampler_surface_state
;
1582 aux_usage
= desc
->image_view
->optimal_sampler_aux_usage
;
1584 assert(surface_state
.alloc_size
);
1585 add_image_relocs(cmd_buffer
, desc
->image_view
->image
,
1586 desc
->image_view
->aspect_mask
,
1587 aux_usage
, surface_state
);
1590 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
1591 assert(stage
== MESA_SHADER_FRAGMENT
);
1592 if (desc
->image_view
->aspect_mask
!= VK_IMAGE_ASPECT_COLOR_BIT
) {
1593 /* For depth and stencil input attachments, we treat it like any
1594 * old texture that a user may have bound.
1596 enum isl_aux_usage aux_usage
;
1597 if (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) {
1598 surface_state
= desc
->image_view
->general_sampler_surface_state
;
1599 aux_usage
= desc
->image_view
->general_sampler_aux_usage
;
1601 surface_state
= desc
->image_view
->optimal_sampler_surface_state
;
1602 aux_usage
= desc
->image_view
->optimal_sampler_aux_usage
;
1604 assert(surface_state
.alloc_size
);
1605 add_image_relocs(cmd_buffer
, desc
->image_view
->image
,
1606 desc
->image_view
->aspect_mask
,
1607 aux_usage
, surface_state
);
1609 /* For color input attachments, we create the surface state at
1610 * vkBeginRenderPass time so that we can include aux and clear
1611 * color information.
1613 assert(binding
->input_attachment_index
< subpass
->input_count
);
1614 const unsigned subpass_att
= binding
->input_attachment_index
;
1615 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
1616 surface_state
= cmd_buffer
->state
.attachments
[att
].input_att_state
;
1620 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
1621 surface_state
= (binding
->write_only
)
1622 ? desc
->image_view
->writeonly_storage_surface_state
1623 : desc
->image_view
->storage_surface_state
;
1624 assert(surface_state
.alloc_size
);
1625 add_image_relocs(cmd_buffer
, desc
->image_view
->image
,
1626 desc
->image_view
->aspect_mask
,
1627 desc
->image_view
->image
->aux_usage
, surface_state
);
1629 struct brw_image_param
*image_param
=
1630 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1632 *image_param
= desc
->image_view
->storage_image_param
;
1633 image_param
->surface_idx
= bias
+ s
;
1637 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
1638 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
1639 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
1640 surface_state
= desc
->buffer_view
->surface_state
;
1641 assert(surface_state
.alloc_size
);
1642 add_surface_state_reloc(cmd_buffer
, surface_state
,
1643 desc
->buffer_view
->bo
,
1644 desc
->buffer_view
->offset
);
1647 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
1648 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
1649 uint32_t dynamic_offset_idx
=
1650 pipeline
->layout
->set
[binding
->set
].dynamic_offset_start
+
1651 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1654 /* Compute the offset within the buffer */
1655 uint64_t offset
= desc
->offset
+
1656 cmd_buffer
->state
.dynamic_offsets
[dynamic_offset_idx
];
1657 /* Clamp to the buffer size */
1658 offset
= MIN2(offset
, desc
->buffer
->size
);
1659 /* Clamp the range to the buffer size */
1660 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
1663 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
1664 enum isl_format format
=
1665 anv_isl_format_for_descriptor_type(desc
->type
);
1667 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1668 format
, offset
, range
, 1);
1669 add_surface_state_reloc(cmd_buffer
, surface_state
,
1671 desc
->buffer
->offset
+ offset
);
1675 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
1676 surface_state
= (binding
->write_only
)
1677 ? desc
->buffer_view
->writeonly_storage_surface_state
1678 : desc
->buffer_view
->storage_surface_state
;
1679 assert(surface_state
.alloc_size
);
1680 add_surface_state_reloc(cmd_buffer
, surface_state
,
1681 desc
->buffer_view
->bo
,
1682 desc
->buffer_view
->offset
);
1684 struct brw_image_param
*image_param
=
1685 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1687 *image_param
= desc
->buffer_view
->storage_image_param
;
1688 image_param
->surface_idx
= bias
+ s
;
1692 assert(!"Invalid descriptor type");
1696 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1698 assert(image
== map
->image_count
);
1701 anv_state_flush(cmd_buffer
->device
, *bt_state
);
1707 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
1708 gl_shader_stage stage
,
1709 struct anv_state
*state
)
1711 struct anv_pipeline
*pipeline
;
1713 if (stage
== MESA_SHADER_COMPUTE
)
1714 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1716 pipeline
= cmd_buffer
->state
.pipeline
;
1718 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1719 *state
= (struct anv_state
) { 0, };
1723 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1724 if (map
->sampler_count
== 0) {
1725 *state
= (struct anv_state
) { 0, };
1729 uint32_t size
= map
->sampler_count
* 16;
1730 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
1732 if (state
->map
== NULL
)
1733 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1735 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
1736 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
1737 struct anv_descriptor_set
*set
=
1738 cmd_buffer
->state
.descriptors
[binding
->set
];
1739 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1740 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1742 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
1743 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
1746 struct anv_sampler
*sampler
= desc
->sampler
;
1748 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
1749 * happens to be zero.
1751 if (sampler
== NULL
)
1754 memcpy(state
->map
+ (s
* 16),
1755 sampler
->state
, sizeof(sampler
->state
));
1758 anv_state_flush(cmd_buffer
->device
, *state
);
1764 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
1766 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
1767 cmd_buffer
->state
.pipeline
->active_stages
;
1769 VkResult result
= VK_SUCCESS
;
1770 anv_foreach_stage(s
, dirty
) {
1771 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1772 if (result
!= VK_SUCCESS
)
1774 result
= emit_binding_table(cmd_buffer
, s
,
1775 &cmd_buffer
->state
.binding_tables
[s
]);
1776 if (result
!= VK_SUCCESS
)
1780 if (result
!= VK_SUCCESS
) {
1781 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1783 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1784 if (result
!= VK_SUCCESS
)
1787 /* Re-emit state base addresses so we get the new surface state base
1788 * address before we start emitting binding tables etc.
1790 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1792 /* Re-emit all active binding tables */
1793 dirty
|= cmd_buffer
->state
.pipeline
->active_stages
;
1794 anv_foreach_stage(s
, dirty
) {
1795 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1796 if (result
!= VK_SUCCESS
) {
1797 anv_batch_set_error(&cmd_buffer
->batch
, result
);
1800 result
= emit_binding_table(cmd_buffer
, s
,
1801 &cmd_buffer
->state
.binding_tables
[s
]);
1802 if (result
!= VK_SUCCESS
) {
1803 anv_batch_set_error(&cmd_buffer
->batch
, result
);
1809 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
1815 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
1818 static const uint32_t sampler_state_opcodes
[] = {
1819 [MESA_SHADER_VERTEX
] = 43,
1820 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
1821 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
1822 [MESA_SHADER_GEOMETRY
] = 46,
1823 [MESA_SHADER_FRAGMENT
] = 47,
1824 [MESA_SHADER_COMPUTE
] = 0,
1827 static const uint32_t binding_table_opcodes
[] = {
1828 [MESA_SHADER_VERTEX
] = 38,
1829 [MESA_SHADER_TESS_CTRL
] = 39,
1830 [MESA_SHADER_TESS_EVAL
] = 40,
1831 [MESA_SHADER_GEOMETRY
] = 41,
1832 [MESA_SHADER_FRAGMENT
] = 42,
1833 [MESA_SHADER_COMPUTE
] = 0,
1836 anv_foreach_stage(s
, stages
) {
1837 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
1838 anv_batch_emit(&cmd_buffer
->batch
,
1839 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
1840 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
1841 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
1845 /* Always emit binding table pointers if we're asked to, since on SKL
1846 * this is what flushes push constants. */
1847 anv_batch_emit(&cmd_buffer
->batch
,
1848 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
1849 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
1850 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
1856 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1858 static const uint32_t push_constant_opcodes
[] = {
1859 [MESA_SHADER_VERTEX
] = 21,
1860 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
1861 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
1862 [MESA_SHADER_GEOMETRY
] = 22,
1863 [MESA_SHADER_FRAGMENT
] = 23,
1864 [MESA_SHADER_COMPUTE
] = 0,
1867 VkShaderStageFlags flushed
= 0;
1869 anv_foreach_stage(stage
, cmd_buffer
->state
.push_constants_dirty
) {
1870 if (stage
== MESA_SHADER_COMPUTE
)
1873 struct anv_state state
= anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
1875 if (state
.offset
== 0) {
1876 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
)
1877 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
1879 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
1880 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
],
1881 c
.ConstantBody
= (struct GENX(3DSTATE_CONSTANT_BODY
)) {
1883 .Buffer
[2] = { &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
, state
.offset
},
1884 .ReadLength
[2] = DIV_ROUND_UP(state
.alloc_size
, 32),
1886 .Buffer
[0] = { .offset
= state
.offset
},
1887 .ReadLength
[0] = DIV_ROUND_UP(state
.alloc_size
, 32),
1893 flushed
|= mesa_to_vk_shader_stage(stage
);
1896 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_ALL_GRAPHICS
;
1902 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1904 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1907 uint32_t vb_emit
= cmd_buffer
->state
.vb_dirty
& pipeline
->vb_used
;
1909 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
1911 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1913 genX(flush_pipeline_select_3d
)(cmd_buffer
);
1916 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
1917 const uint32_t num_dwords
= 1 + num_buffers
* 4;
1919 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
1920 GENX(3DSTATE_VERTEX_BUFFERS
));
1922 for_each_bit(vb
, vb_emit
) {
1923 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1924 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
1926 struct GENX(VERTEX_BUFFER_STATE
) state
= {
1927 .VertexBufferIndex
= vb
,
1930 .MemoryObjectControlState
= GENX(MOCS
),
1932 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
1933 /* Our implementation of VK_KHR_multiview uses instancing to draw
1934 * the different views. If the client asks for instancing, we
1935 * need to use the Instance Data Step Rate to ensure that we
1936 * repeat the client's per-instance data once for each view.
1938 .InstanceDataStepRate
= anv_subpass_view_count(pipeline
->subpass
),
1939 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1942 .AddressModifyEnable
= true,
1943 .BufferPitch
= pipeline
->binding_stride
[vb
],
1944 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
1947 .BufferSize
= buffer
->size
- offset
1949 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
1953 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
1958 cmd_buffer
->state
.vb_dirty
&= ~vb_emit
;
1960 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1961 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1963 /* The exact descriptor layout is pulled from the pipeline, so we need
1964 * to re-emit binding tables on every pipeline change.
1966 cmd_buffer
->state
.descriptors_dirty
|=
1967 cmd_buffer
->state
.pipeline
->active_stages
;
1969 /* If the pipeline changed, we may need to re-allocate push constant
1972 cmd_buffer_alloc_push_constants(cmd_buffer
);
1976 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
1977 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
1978 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
1980 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
1981 * stall needs to be sent just prior to any 3DSTATE_VS,
1982 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
1983 * 3DSTATE_BINDING_TABLE_POINTER_VS,
1984 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
1985 * PIPE_CONTROL needs to be sent before any combination of VS
1986 * associated 3DSTATE."
1988 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1989 pc
.DepthStallEnable
= true;
1990 pc
.PostSyncOperation
= WriteImmediateData
;
1992 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1997 /* Render targets live in the same binding table as fragment descriptors */
1998 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
1999 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2001 /* We emit the binding tables and sampler tables first, then emit push
2002 * constants and then finally emit binding table and sampler table
2003 * pointers. It has to happen in this order, since emitting the binding
2004 * tables may change the push constants (in case of storage images). After
2005 * emitting push constants, on SKL+ we have to emit the corresponding
2006 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2009 if (cmd_buffer
->state
.descriptors_dirty
)
2010 dirty
= flush_descriptor_sets(cmd_buffer
);
2012 if (cmd_buffer
->state
.push_constants_dirty
) {
2014 /* On Sky Lake and later, the binding table pointers commands are
2015 * what actually flush the changes to push constant state so we need
2016 * to dirty them so they get re-emitted below.
2018 dirty
|= cmd_buffer_flush_push_constants(cmd_buffer
);
2020 cmd_buffer_flush_push_constants(cmd_buffer
);
2025 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2027 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2028 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2030 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2031 ANV_CMD_DIRTY_PIPELINE
)) {
2032 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2033 pipeline
->depth_clamp_enable
);
2036 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
2037 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2039 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2041 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2045 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2046 struct anv_bo
*bo
, uint32_t offset
,
2047 uint32_t size
, uint32_t index
)
2049 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2050 GENX(3DSTATE_VERTEX_BUFFERS
));
2052 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2053 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2054 .VertexBufferIndex
= index
,
2055 .AddressModifyEnable
= true,
2058 .MemoryObjectControlState
= GENX(MOCS
),
2059 .BufferStartingAddress
= { bo
, offset
},
2062 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2063 .BufferStartingAddress
= { bo
, offset
},
2064 .EndAddress
= { bo
, offset
+ size
},
2070 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2071 struct anv_bo
*bo
, uint32_t offset
)
2073 emit_vertex_bo(cmd_buffer
, bo
, offset
, 8, ANV_SVGS_VB_INDEX
);
2077 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2078 uint32_t base_vertex
, uint32_t base_instance
)
2080 struct anv_state id_state
=
2081 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2083 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2084 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2086 anv_state_flush(cmd_buffer
->device
, id_state
);
2088 emit_base_vertex_instance_bo(cmd_buffer
,
2089 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
, id_state
.offset
);
2093 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2095 struct anv_state state
=
2096 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2098 ((uint32_t *)state
.map
)[0] = draw_index
;
2100 anv_state_flush(cmd_buffer
->device
, state
);
2102 emit_vertex_bo(cmd_buffer
,
2103 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2104 state
.offset
, 4, ANV_DRAWID_VB_INDEX
);
2108 VkCommandBuffer commandBuffer
,
2109 uint32_t vertexCount
,
2110 uint32_t instanceCount
,
2111 uint32_t firstVertex
,
2112 uint32_t firstInstance
)
2114 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2115 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2116 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2118 if (anv_batch_has_error(&cmd_buffer
->batch
))
2121 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2123 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2124 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2125 if (vs_prog_data
->uses_drawid
)
2126 emit_draw_index(cmd_buffer
, 0);
2128 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2129 * different views. We need to multiply instanceCount by the view count.
2131 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2133 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2134 prim
.VertexAccessType
= SEQUENTIAL
;
2135 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2136 prim
.VertexCountPerInstance
= vertexCount
;
2137 prim
.StartVertexLocation
= firstVertex
;
2138 prim
.InstanceCount
= instanceCount
;
2139 prim
.StartInstanceLocation
= firstInstance
;
2140 prim
.BaseVertexLocation
= 0;
2144 void genX(CmdDrawIndexed
)(
2145 VkCommandBuffer commandBuffer
,
2146 uint32_t indexCount
,
2147 uint32_t instanceCount
,
2148 uint32_t firstIndex
,
2149 int32_t vertexOffset
,
2150 uint32_t firstInstance
)
2152 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2153 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2154 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2156 if (anv_batch_has_error(&cmd_buffer
->batch
))
2159 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2161 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2162 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2163 if (vs_prog_data
->uses_drawid
)
2164 emit_draw_index(cmd_buffer
, 0);
2166 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2167 * different views. We need to multiply instanceCount by the view count.
2169 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2171 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2172 prim
.VertexAccessType
= RANDOM
;
2173 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2174 prim
.VertexCountPerInstance
= indexCount
;
2175 prim
.StartVertexLocation
= firstIndex
;
2176 prim
.InstanceCount
= instanceCount
;
2177 prim
.StartInstanceLocation
= firstInstance
;
2178 prim
.BaseVertexLocation
= vertexOffset
;
2182 /* Auto-Draw / Indirect Registers */
2183 #define GEN7_3DPRIM_END_OFFSET 0x2420
2184 #define GEN7_3DPRIM_START_VERTEX 0x2430
2185 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2186 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2187 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2188 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2190 /* MI_MATH only exists on Haswell+ */
2191 #if GEN_IS_HASWELL || GEN_GEN >= 8
2194 mi_alu(uint32_t opcode
, uint32_t op1
, uint32_t op2
)
2196 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
2197 .ALUOpcode
= opcode
,
2203 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
2208 #define CS_GPR(n) (0x2600 + (n) * 8)
2210 /* Emit dwords to multiply GPR0 by N */
2212 build_alu_multiply_gpr0(uint32_t *dw
, unsigned *dw_count
, uint32_t N
)
2214 VK_OUTARRAY_MAKE(out
, dw
, dw_count
);
2216 #define append_alu(opcode, operand1, operand2) \
2217 vk_outarray_append(&out, alu_dw) *alu_dw = mi_alu(opcode, operand1, operand2)
2220 unsigned top_bit
= 31 - __builtin_clz(N
);
2221 for (int i
= top_bit
- 1; i
>= 0; i
--) {
2222 /* We get our initial data in GPR0 and we write the final data out to
2223 * GPR0 but we use GPR1 as our scratch register.
2225 unsigned src_reg
= i
== top_bit
- 1 ? MI_ALU_REG0
: MI_ALU_REG1
;
2226 unsigned dst_reg
= i
== 0 ? MI_ALU_REG0
: MI_ALU_REG1
;
2228 /* Shift the current value left by 1 */
2229 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, src_reg
);
2230 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, src_reg
);
2231 append_alu(MI_ALU_ADD
, 0, 0);
2234 /* Store ACCU to R1 and add R0 to R1 */
2235 append_alu(MI_ALU_STORE
, MI_ALU_REG1
, MI_ALU_ACCU
);
2236 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
2237 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
2238 append_alu(MI_ALU_ADD
, 0, 0);
2241 append_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2248 emit_mul_gpr0(struct anv_batch
*batch
, uint32_t N
)
2250 uint32_t num_dwords
;
2251 build_alu_multiply_gpr0(NULL
, &num_dwords
, N
);
2253 uint32_t *dw
= anv_batch_emitn(batch
, 1 + num_dwords
, GENX(MI_MATH
));
2254 build_alu_multiply_gpr0(dw
+ 1, &num_dwords
, N
);
2257 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2260 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2261 struct anv_buffer
*buffer
, uint64_t offset
,
2264 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2265 struct anv_bo
*bo
= buffer
->bo
;
2266 uint32_t bo_offset
= buffer
->offset
+ offset
;
2268 emit_lrm(batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
2270 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2271 if (view_count
> 1) {
2272 #if GEN_IS_HASWELL || GEN_GEN >= 8
2273 emit_lrm(batch
, CS_GPR(0), bo
, bo_offset
+ 4);
2274 emit_mul_gpr0(batch
, view_count
);
2275 emit_lrr(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, CS_GPR(0));
2277 anv_finishme("Multiview + indirect draw requires MI_MATH\n"
2278 "MI_MATH is not supported on Ivy Bridge");
2279 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
2282 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
2285 emit_lrm(batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
2288 emit_lrm(batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
2289 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
2291 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
2292 emit_lri(batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
2296 void genX(CmdDrawIndirect
)(
2297 VkCommandBuffer commandBuffer
,
2299 VkDeviceSize offset
,
2303 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2304 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2305 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2306 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2308 if (anv_batch_has_error(&cmd_buffer
->batch
))
2311 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2313 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2314 struct anv_bo
*bo
= buffer
->bo
;
2315 uint32_t bo_offset
= buffer
->offset
+ offset
;
2317 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2318 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
2319 if (vs_prog_data
->uses_drawid
)
2320 emit_draw_index(cmd_buffer
, i
);
2322 load_indirect_parameters(cmd_buffer
, buffer
, offset
, false);
2324 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2325 prim
.IndirectParameterEnable
= true;
2326 prim
.VertexAccessType
= SEQUENTIAL
;
2327 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2334 void genX(CmdDrawIndexedIndirect
)(
2335 VkCommandBuffer commandBuffer
,
2337 VkDeviceSize offset
,
2341 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2342 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2343 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2344 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2346 if (anv_batch_has_error(&cmd_buffer
->batch
))
2349 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2351 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2352 struct anv_bo
*bo
= buffer
->bo
;
2353 uint32_t bo_offset
= buffer
->offset
+ offset
;
2355 /* TODO: We need to stomp base vertex to 0 somehow */
2356 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2357 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
2358 if (vs_prog_data
->uses_drawid
)
2359 emit_draw_index(cmd_buffer
, i
);
2361 load_indirect_parameters(cmd_buffer
, buffer
, offset
, true);
2363 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2364 prim
.IndirectParameterEnable
= true;
2365 prim
.VertexAccessType
= RANDOM
;
2366 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2374 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
2376 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2377 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
2380 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2381 if (result
!= VK_SUCCESS
) {
2382 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2384 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2385 if (result
!= VK_SUCCESS
)
2388 /* Re-emit state base addresses so we get the new surface state base
2389 * address before we start emitting binding tables etc.
2391 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2393 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2394 if (result
!= VK_SUCCESS
) {
2395 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2400 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
2401 if (result
!= VK_SUCCESS
) {
2402 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2406 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
2407 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
2408 .BindingTablePointer
= surfaces
.offset
,
2409 .SamplerStatePointer
= samplers
.offset
,
2411 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
2413 struct anv_state state
=
2414 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
2415 pipeline
->interface_descriptor_data
,
2416 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
2419 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
2420 anv_batch_emit(&cmd_buffer
->batch
,
2421 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
2422 mid
.InterfaceDescriptorTotalLength
= size
;
2423 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
2430 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2432 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2433 MAYBE_UNUSED VkResult result
;
2435 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
2437 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2439 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
2441 if (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2442 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
2444 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
2445 * the only bits that are changed are scoreboard related: Scoreboard
2446 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
2447 * these scoreboard related states, a MEDIA_STATE_FLUSH is
2450 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2451 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2453 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2456 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
2457 (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)) {
2458 /* FIXME: figure out descriptors for gen7 */
2459 result
= flush_compute_descriptor_set(cmd_buffer
);
2460 if (result
!= VK_SUCCESS
)
2463 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
2466 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
2467 struct anv_state push_state
=
2468 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
2470 if (push_state
.alloc_size
) {
2471 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
2472 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
2473 curbe
.CURBEDataStartAddress
= push_state
.offset
;
2478 cmd_buffer
->state
.compute_dirty
= 0;
2480 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2486 verify_cmd_parser(const struct anv_device
*device
,
2487 int required_version
,
2488 const char *function
)
2490 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
2491 return vk_errorf(VK_ERROR_FEATURE_NOT_PRESENT
,
2492 "cmd parser version %d is required for %s",
2493 required_version
, function
);
2501 void genX(CmdDispatch
)(
2502 VkCommandBuffer commandBuffer
,
2507 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2508 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2509 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
2511 if (anv_batch_has_error(&cmd_buffer
->batch
))
2514 if (prog_data
->uses_num_work_groups
) {
2515 struct anv_state state
=
2516 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
2517 uint32_t *sizes
= state
.map
;
2521 anv_state_flush(cmd_buffer
->device
, state
);
2522 cmd_buffer
->state
.num_workgroups_offset
= state
.offset
;
2523 cmd_buffer
->state
.num_workgroups_bo
=
2524 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
;
2527 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
2529 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
2530 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
2531 ggw
.ThreadDepthCounterMaximum
= 0;
2532 ggw
.ThreadHeightCounterMaximum
= 0;
2533 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
2534 ggw
.ThreadGroupIDXDimension
= x
;
2535 ggw
.ThreadGroupIDYDimension
= y
;
2536 ggw
.ThreadGroupIDZDimension
= z
;
2537 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
2538 ggw
.BottomExecutionMask
= 0xffffffff;
2541 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
2544 #define GPGPU_DISPATCHDIMX 0x2500
2545 #define GPGPU_DISPATCHDIMY 0x2504
2546 #define GPGPU_DISPATCHDIMZ 0x2508
2548 void genX(CmdDispatchIndirect
)(
2549 VkCommandBuffer commandBuffer
,
2551 VkDeviceSize offset
)
2553 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2554 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2555 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2556 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
2557 struct anv_bo
*bo
= buffer
->bo
;
2558 uint32_t bo_offset
= buffer
->offset
+ offset
;
2559 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2562 /* Linux 4.4 added command parser version 5 which allows the GPGPU
2563 * indirect dispatch registers to be written.
2565 if (verify_cmd_parser(cmd_buffer
->device
, 5,
2566 "vkCmdDispatchIndirect") != VK_SUCCESS
)
2570 if (prog_data
->uses_num_work_groups
) {
2571 cmd_buffer
->state
.num_workgroups_offset
= bo_offset
;
2572 cmd_buffer
->state
.num_workgroups_bo
= bo
;
2575 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
2577 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
2578 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
2579 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
2582 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
2583 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
2584 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
2585 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
2587 /* Load compute_dispatch_indirect_x_size into SRC0 */
2588 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
2590 /* predicate = (compute_dispatch_indirect_x_size == 0); */
2591 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2592 mip
.LoadOperation
= LOAD_LOAD
;
2593 mip
.CombineOperation
= COMBINE_SET
;
2594 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2597 /* Load compute_dispatch_indirect_y_size into SRC0 */
2598 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
2600 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
2601 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2602 mip
.LoadOperation
= LOAD_LOAD
;
2603 mip
.CombineOperation
= COMBINE_OR
;
2604 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2607 /* Load compute_dispatch_indirect_z_size into SRC0 */
2608 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
2610 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
2611 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2612 mip
.LoadOperation
= LOAD_LOAD
;
2613 mip
.CombineOperation
= COMBINE_OR
;
2614 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2617 /* predicate = !predicate; */
2618 #define COMPARE_FALSE 1
2619 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2620 mip
.LoadOperation
= LOAD_LOADINV
;
2621 mip
.CombineOperation
= COMBINE_OR
;
2622 mip
.CompareOperation
= COMPARE_FALSE
;
2626 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
2627 ggw
.IndirectParameterEnable
= true;
2628 ggw
.PredicateEnable
= GEN_GEN
<= 7;
2629 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
2630 ggw
.ThreadDepthCounterMaximum
= 0;
2631 ggw
.ThreadHeightCounterMaximum
= 0;
2632 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
2633 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
2634 ggw
.BottomExecutionMask
= 0xffffffff;
2637 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
2641 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
2644 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
2647 #if GEN_GEN >= 8 && GEN_GEN < 10
2648 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
2650 * Software must clear the COLOR_CALC_STATE Valid field in
2651 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
2652 * with Pipeline Select set to GPGPU.
2654 * The internal hardware docs recommend the same workaround for Gen9
2657 if (pipeline
== GPGPU
)
2658 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
2661 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
2662 * PIPELINE_SELECT [DevBWR+]":
2666 * Software must ensure all the write caches are flushed through a
2667 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
2668 * command to invalidate read only caches prior to programming
2669 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
2671 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2672 pc
.RenderTargetCacheFlushEnable
= true;
2673 pc
.DepthCacheFlushEnable
= true;
2674 pc
.DCFlushEnable
= true;
2675 pc
.PostSyncOperation
= NoWrite
;
2676 pc
.CommandStreamerStallEnable
= true;
2679 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2680 pc
.TextureCacheInvalidationEnable
= true;
2681 pc
.ConstantCacheInvalidationEnable
= true;
2682 pc
.StateCacheInvalidationEnable
= true;
2683 pc
.InstructionCacheInvalidateEnable
= true;
2684 pc
.PostSyncOperation
= NoWrite
;
2687 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
2691 ps
.PipelineSelection
= pipeline
;
2694 cmd_buffer
->state
.current_pipeline
= pipeline
;
2698 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
2700 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
2704 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
2706 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
2710 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
2715 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
2717 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
2718 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
2719 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
2720 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
2721 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
2722 * Depth Flush Bit set, followed by another pipelined depth stall
2723 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
2724 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
2725 * via a preceding MI_FLUSH)."
2727 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2728 pipe
.DepthStallEnable
= true;
2730 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2731 pipe
.DepthCacheFlushEnable
= true;
2733 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2734 pipe
.DepthStallEnable
= true;
2739 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
2741 struct anv_device
*device
= cmd_buffer
->device
;
2742 const struct anv_image_view
*iview
=
2743 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2744 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
2746 /* FIXME: Width and Height are wrong */
2748 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
2750 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
2751 device
->isl_dev
.ds
.size
/ 4);
2755 struct isl_depth_stencil_hiz_emit_info info
= {
2756 .mocs
= device
->default_mocs
,
2760 info
.view
= &iview
->isl
;
2762 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
2763 info
.depth_surf
= &image
->depth_surface
.isl
;
2765 info
.depth_address
=
2766 anv_batch_emit_reloc(&cmd_buffer
->batch
,
2767 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
2769 image
->offset
+ image
->depth_surface
.offset
);
2772 cmd_buffer
->state
.subpass
->depth_stencil_attachment
.attachment
;
2773 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
2774 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
2775 info
.hiz_surf
= &image
->aux_surface
.isl
;
2778 anv_batch_emit_reloc(&cmd_buffer
->batch
,
2779 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
2781 image
->offset
+ image
->aux_surface
.offset
);
2783 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
2787 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
2788 info
.stencil_surf
= &image
->stencil_surface
.isl
;
2790 info
.stencil_address
=
2791 anv_batch_emit_reloc(&cmd_buffer
->batch
,
2792 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
2794 image
->offset
+ image
->stencil_surface
.offset
);
2797 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
2799 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
2804 * @brief Perform any layout transitions required at the beginning and/or end
2805 * of the current subpass for depth buffers.
2807 * TODO: Consider preprocessing the attachment reference array at render pass
2808 * create time to determine if no layout transition is needed at the
2809 * beginning and/or end of each subpass.
2811 * @param cmd_buffer The command buffer the transition is happening within.
2812 * @param subpass_end If true, marks that the transition is happening at the
2813 * end of the subpass.
2816 cmd_buffer_subpass_transition_layouts(struct anv_cmd_buffer
* const cmd_buffer
,
2817 const bool subpass_end
)
2819 /* We need a non-NULL command buffer. */
2822 const struct anv_cmd_state
* const cmd_state
= &cmd_buffer
->state
;
2823 const struct anv_subpass
* const subpass
= cmd_state
->subpass
;
2825 /* This function must be called within a subpass. */
2828 /* If there are attachment references, the array shouldn't be NULL.
2830 if (subpass
->attachment_count
> 0)
2831 assert(subpass
->attachments
);
2833 /* Iterate over the array of attachment references. */
2834 for (const VkAttachmentReference
*att_ref
= subpass
->attachments
;
2835 att_ref
< subpass
->attachments
+ subpass
->attachment_count
; att_ref
++) {
2837 /* If the attachment is unused, we can't perform a layout transition. */
2838 if (att_ref
->attachment
== VK_ATTACHMENT_UNUSED
)
2841 /* This attachment index shouldn't go out of bounds. */
2842 assert(att_ref
->attachment
< cmd_state
->pass
->attachment_count
);
2844 const struct anv_render_pass_attachment
* const att_desc
=
2845 &cmd_state
->pass
->attachments
[att_ref
->attachment
];
2846 struct anv_attachment_state
* const att_state
=
2847 &cmd_buffer
->state
.attachments
[att_ref
->attachment
];
2849 /* The attachment should not be used in a subpass after its last. */
2850 assert(att_desc
->last_subpass_idx
>= anv_get_subpass_id(cmd_state
));
2852 if (subpass_end
&& anv_get_subpass_id(cmd_state
) <
2853 att_desc
->last_subpass_idx
) {
2854 /* We're calling this function on a buffer twice in one subpass and
2855 * this is not the last use of the buffer. The layout should not have
2856 * changed from the first call and no transition is necessary.
2858 assert(att_state
->current_layout
== att_ref
->layout
||
2859 att_state
->current_layout
==
2860 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
2864 /* The attachment index must be less than the number of attachments
2865 * within the framebuffer.
2867 assert(att_ref
->attachment
< cmd_state
->framebuffer
->attachment_count
);
2869 const struct anv_image_view
* const iview
=
2870 cmd_state
->framebuffer
->attachments
[att_ref
->attachment
];
2871 const struct anv_image
* const image
= iview
->image
;
2873 /* Get the appropriate target layout for this attachment. */
2874 VkImageLayout target_layout
;
2876 /* A resolve is necessary before use as an input attachment if the clear
2877 * color or auxiliary buffer usage isn't supported by the sampler.
2879 const bool input_needs_resolve
=
2880 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
2881 att_state
->input_aux_usage
!= att_state
->aux_usage
;
2883 target_layout
= att_desc
->final_layout
;
2884 } else if (iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
2885 !input_needs_resolve
) {
2886 /* Layout transitions before the final only help to enable sampling as
2887 * an input attachment. If the input attachment supports sampling
2888 * using the auxiliary surface, we can skip such transitions by making
2889 * the target layout one that is CCS-aware.
2891 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
2893 target_layout
= att_ref
->layout
;
2896 /* Perform the layout transition. */
2897 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
2898 transition_depth_buffer(cmd_buffer
, image
,
2899 att_state
->current_layout
, target_layout
);
2900 att_state
->aux_usage
=
2901 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
2902 image
->aspects
, target_layout
);
2903 } else if (image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
2904 transition_color_buffer(cmd_buffer
, image
,
2905 iview
->isl
.base_level
, 1,
2906 iview
->isl
.base_array_layer
,
2907 iview
->isl
.array_len
,
2908 att_state
->current_layout
, target_layout
);
2911 att_state
->current_layout
= target_layout
;
2915 /* Update the clear value dword(s) in surface state objects or the fast clear
2916 * state buffer entry for the color attachments used in this subpass.
2919 cmd_buffer_subpass_sync_fast_clear_values(struct anv_cmd_buffer
*cmd_buffer
)
2921 assert(cmd_buffer
&& cmd_buffer
->state
.subpass
);
2923 const struct anv_cmd_state
*state
= &cmd_buffer
->state
;
2925 /* Iterate through every color attachment used in this subpass. */
2926 for (uint32_t i
= 0; i
< state
->subpass
->color_count
; ++i
) {
2928 /* The attachment should be one of the attachments described in the
2929 * render pass and used in the subpass.
2931 const uint32_t a
= state
->subpass
->color_attachments
[i
].attachment
;
2932 assert(a
< state
->pass
->attachment_count
);
2933 if (a
== VK_ATTACHMENT_UNUSED
)
2936 /* Store some information regarding this attachment. */
2937 const struct anv_attachment_state
*att_state
= &state
->attachments
[a
];
2938 const struct anv_image_view
*iview
= state
->framebuffer
->attachments
[a
];
2939 const struct anv_render_pass_attachment
*rp_att
=
2940 &state
->pass
->attachments
[a
];
2942 if (att_state
->aux_usage
== ISL_AUX_USAGE_NONE
)
2945 /* The fast clear state entry must be updated if a fast clear is going to
2946 * happen. The surface state must be updated if the clear value from a
2947 * prior fast clear may be needed.
2949 if (att_state
->pending_clear_aspects
&& att_state
->fast_clear
) {
2950 /* Update the fast clear state entry. */
2951 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color_rt_state
,
2952 iview
->image
, iview
->isl
.base_level
,
2953 true /* copy from ss */);
2955 /* Fast-clears impact whether or not a resolve will be necessary. */
2956 if (iview
->image
->aux_usage
== ISL_AUX_USAGE_CCS_E
&&
2957 att_state
->clear_color_is_zero
) {
2958 /* This image always has the auxiliary buffer enabled. We can mark
2959 * the subresource as not needing a resolve because the clear color
2960 * will match what's in every RENDER_SURFACE_STATE object when it's
2961 * being used for sampling.
2963 genX(set_image_needs_resolve
)(cmd_buffer
, iview
->image
,
2964 iview
->isl
.base_level
, false);
2966 genX(set_image_needs_resolve
)(cmd_buffer
, iview
->image
,
2967 iview
->isl
.base_level
, true);
2969 } else if (rp_att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
2970 /* The attachment may have been fast-cleared in a previous render
2971 * pass and the value is needed now. Update the surface state(s).
2973 * TODO: Do this only once per render pass instead of every subpass.
2975 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color_rt_state
,
2976 iview
->image
, iview
->isl
.base_level
,
2977 false /* copy to ss */);
2979 if (need_input_attachment_state(rp_att
) &&
2980 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
2981 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input_att_state
,
2982 iview
->image
, iview
->isl
.base_level
,
2983 false /* copy to ss */);
2991 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
2992 struct anv_subpass
*subpass
)
2994 cmd_buffer
->state
.subpass
= subpass
;
2996 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
2998 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2999 * different views. If the client asks for instancing, we need to use the
3000 * Instance Data Step Rate to ensure that we repeat the client's
3001 * per-instance data once for each view. Since this bit is in
3002 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
3006 cmd_buffer
->state
.vb_dirty
|= ~0;
3008 /* Perform transitions to the subpass layout before any writes have
3011 cmd_buffer_subpass_transition_layouts(cmd_buffer
, false);
3013 /* Update clear values *after* performing automatic layout transitions.
3014 * This ensures that transitions from the UNDEFINED layout have had a chance
3015 * to populate the clear value buffer with the correct values for the
3016 * LOAD_OP_LOAD loadOp and that the fast-clears will update the buffer
3017 * without the aforementioned layout transition overwriting the fast-clear
3020 cmd_buffer_subpass_sync_fast_clear_values(cmd_buffer
);
3022 cmd_buffer_emit_depth_stencil(cmd_buffer
);
3024 anv_cmd_buffer_clear_subpass(cmd_buffer
);
3027 void genX(CmdBeginRenderPass
)(
3028 VkCommandBuffer commandBuffer
,
3029 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3030 VkSubpassContents contents
)
3032 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3033 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3034 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3036 cmd_buffer
->state
.framebuffer
= framebuffer
;
3037 cmd_buffer
->state
.pass
= pass
;
3038 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3040 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
3042 /* If we failed to setup the attachments we should not try to go further */
3043 if (result
!= VK_SUCCESS
) {
3044 assert(anv_batch_has_error(&cmd_buffer
->batch
));
3048 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3050 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
3052 cmd_buffer
->state
.pending_pipe_bits
|=
3053 cmd_buffer
->state
.pass
->subpass_flushes
[0];
3056 void genX(CmdNextSubpass
)(
3057 VkCommandBuffer commandBuffer
,
3058 VkSubpassContents contents
)
3060 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3062 if (anv_batch_has_error(&cmd_buffer
->batch
))
3065 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3067 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
3069 /* Perform transitions to the final layout after all writes have occurred.
3071 cmd_buffer_subpass_transition_layouts(cmd_buffer
, true);
3073 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
3075 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
3076 cmd_buffer
->state
.pending_pipe_bits
|=
3077 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
3080 void genX(CmdEndRenderPass
)(
3081 VkCommandBuffer commandBuffer
)
3083 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3085 if (anv_batch_has_error(&cmd_buffer
->batch
))
3088 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
3090 /* Perform transitions to the final layout after all writes have occurred.
3092 cmd_buffer_subpass_transition_layouts(cmd_buffer
, true);
3094 cmd_buffer
->state
.pending_pipe_bits
|=
3095 cmd_buffer
->state
.pass
->subpass_flushes
[cmd_buffer
->state
.pass
->subpass_count
];
3097 cmd_buffer
->state
.hiz_enabled
= false;
3100 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
3103 /* Remove references to render pass specific state. This enables us to
3104 * detect whether or not we're in a renderpass.
3106 cmd_buffer
->state
.framebuffer
= NULL
;
3107 cmd_buffer
->state
.pass
= NULL
;
3108 cmd_buffer
->state
.subpass
= NULL
;