2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
29 #include "genxml/gen_macros.h"
30 #include "genxml/genX_pack.h"
33 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
35 struct anv_device
*device
= cmd_buffer
->device
;
36 struct anv_bo
*scratch_bo
= NULL
;
38 cmd_buffer
->state
.scratch_size
=
39 anv_block_pool_size(&device
->scratch_block_pool
);
40 if (cmd_buffer
->state
.scratch_size
> 0)
41 scratch_bo
= &device
->scratch_block_pool
.bo
;
43 /* XXX: Do we need this on more than just BDW? */
45 /* Emit a render target cache flush.
47 * This isn't documented anywhere in the PRM. However, it seems to be
48 * necessary prior to changing the surface state base adress. Without
49 * this, we get GPU hangs when using multi-level command buffers which
50 * clear depth, reset state base address, and then go render stuff.
52 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
53 pc
.RenderTargetCacheFlushEnable
= true;
57 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
58 sba
.GeneralStateBaseAddress
= (struct anv_address
) { scratch_bo
, 0 };
59 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
60 sba
.GeneralStateBaseAddressModifyEnable
= true;
62 sba
.SurfaceStateBaseAddress
=
63 anv_cmd_buffer_surface_base_address(cmd_buffer
);
64 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
65 sba
.SurfaceStateBaseAddressModifyEnable
= true;
67 sba
.DynamicStateBaseAddress
=
68 (struct anv_address
) { &device
->dynamic_state_block_pool
.bo
, 0 };
69 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
),
70 sba
.DynamicStateBaseAddressModifyEnable
= true,
72 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
73 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
74 sba
.IndirectObjectBaseAddressModifyEnable
= true;
76 sba
.InstructionBaseAddress
=
77 (struct anv_address
) { &device
->instruction_block_pool
.bo
, 0 };
78 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
79 sba
.InstructionBaseAddressModifyEnable
= true;
82 /* Broadwell requires that we specify a buffer size for a bunch of
83 * these fields. However, since we will be growing the BO's live, we
84 * just set them all to the maximum.
86 sba
.GeneralStateBufferSize
= 0xfffff;
87 sba
.GeneralStateBufferSizeModifyEnable
= true;
88 sba
.DynamicStateBufferSize
= 0xfffff;
89 sba
.DynamicStateBufferSizeModifyEnable
= true;
90 sba
.IndirectObjectBufferSize
= 0xfffff;
91 sba
.IndirectObjectBufferSizeModifyEnable
= true;
92 sba
.InstructionBufferSize
= 0xfffff;
93 sba
.InstructionBuffersizeModifyEnable
= true;
97 /* After re-setting the surface state base address, we have to do some
98 * cache flusing so that the sampler engine will pick up the new
99 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
100 * Shared Function > 3D Sampler > State > State Caching (page 96):
102 * Coherency with system memory in the state cache, like the texture
103 * cache is handled partially by software. It is expected that the
104 * command stream or shader will issue Cache Flush operation or
105 * Cache_Flush sampler message to ensure that the L1 cache remains
106 * coherent with system memory.
110 * Whenever the value of the Dynamic_State_Base_Addr,
111 * Surface_State_Base_Addr are altered, the L1 state cache must be
112 * invalidated to ensure the new surface or sampler state is fetched
113 * from system memory.
115 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
116 * which, according the PIPE_CONTROL instruction documentation in the
119 * Setting this bit is independent of any other bit in this packet.
120 * This bit controls the invalidation of the L1 and L2 state caches
121 * at the top of the pipe i.e. at the parsing time.
123 * Unfortunately, experimentation seems to indicate that state cache
124 * invalidation through a PIPE_CONTROL does nothing whatsoever in
125 * regards to surface state and binding tables. In stead, it seems that
126 * invalidating the texture cache is what is actually needed.
128 * XXX: As far as we have been able to determine through
129 * experimentation, shows that flush the texture cache appears to be
130 * sufficient. The theory here is that all of the sampling/rendering
131 * units cache the binding table in the texture cache. However, we have
132 * yet to be able to actually confirm this.
134 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
135 pc
.TextureCacheInvalidationEnable
= true;
139 void genX(CmdPipelineBarrier
)(
140 VkCommandBuffer commandBuffer
,
141 VkPipelineStageFlags srcStageMask
,
142 VkPipelineStageFlags destStageMask
,
144 uint32_t memoryBarrierCount
,
145 const VkMemoryBarrier
* pMemoryBarriers
,
146 uint32_t bufferMemoryBarrierCount
,
147 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
148 uint32_t imageMemoryBarrierCount
,
149 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
151 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
154 /* XXX: Right now, we're really dumb and just flush whatever categories
155 * the app asks for. One of these days we may make this a bit better
156 * but right now that's all the hardware allows for in most areas.
158 VkAccessFlags src_flags
= 0;
159 VkAccessFlags dst_flags
= 0;
161 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
162 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
163 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
166 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
167 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
168 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
171 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
172 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
173 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
176 /* Mask out the Source access flags we care about */
177 const uint32_t src_mask
=
178 VK_ACCESS_SHADER_WRITE_BIT
|
179 VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
|
180 VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
|
181 VK_ACCESS_TRANSFER_WRITE_BIT
;
183 src_flags
= src_flags
& src_mask
;
185 /* Mask out the destination access flags we care about */
186 const uint32_t dst_mask
=
187 VK_ACCESS_INDIRECT_COMMAND_READ_BIT
|
188 VK_ACCESS_INDEX_READ_BIT
|
189 VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
|
190 VK_ACCESS_UNIFORM_READ_BIT
|
191 VK_ACCESS_SHADER_READ_BIT
|
192 VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
|
193 VK_ACCESS_TRANSFER_READ_BIT
;
195 dst_flags
= dst_flags
& dst_mask
;
197 /* The src flags represent how things were used previously. This is
198 * what we use for doing flushes.
200 struct GENX(PIPE_CONTROL
) flush_cmd
= {
201 GENX(PIPE_CONTROL_header
),
202 .PostSyncOperation
= NoWrite
,
205 for_each_bit(b
, src_flags
) {
206 switch ((VkAccessFlagBits
)(1 << b
)) {
207 case VK_ACCESS_SHADER_WRITE_BIT
:
208 flush_cmd
.DCFlushEnable
= true;
210 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
211 flush_cmd
.RenderTargetCacheFlushEnable
= true;
213 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
214 flush_cmd
.DepthCacheFlushEnable
= true;
216 case VK_ACCESS_TRANSFER_WRITE_BIT
:
217 flush_cmd
.RenderTargetCacheFlushEnable
= true;
218 flush_cmd
.DepthCacheFlushEnable
= true;
221 unreachable("should've masked this out by now");
225 /* If we end up doing two PIPE_CONTROLs, the first, flusing one also has to
226 * stall and wait for the flushing to finish, so we don't re-dirty the
227 * caches with in-flight rendering after the second PIPE_CONTROL
232 flush_cmd
.CommandStreamerStallEnable
= true;
234 if (src_flags
&& dst_flags
) {
235 dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
, GENX(PIPE_CONTROL_length
));
236 GENX(PIPE_CONTROL_pack
)(&cmd_buffer
->batch
, dw
, &flush_cmd
);
239 /* The dst flags represent how things will be used in the future. This
240 * is what we use for doing cache invalidations.
242 struct GENX(PIPE_CONTROL
) invalidate_cmd
= {
243 GENX(PIPE_CONTROL_header
),
244 .PostSyncOperation
= NoWrite
,
247 for_each_bit(b
, dst_flags
) {
248 switch ((VkAccessFlagBits
)(1 << b
)) {
249 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
250 case VK_ACCESS_INDEX_READ_BIT
:
251 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
252 invalidate_cmd
.VFCacheInvalidationEnable
= true;
254 case VK_ACCESS_UNIFORM_READ_BIT
:
255 invalidate_cmd
.ConstantCacheInvalidationEnable
= true;
257 case VK_ACCESS_SHADER_READ_BIT
:
258 invalidate_cmd
.TextureCacheInvalidationEnable
= true;
260 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
261 invalidate_cmd
.TextureCacheInvalidationEnable
= true;
263 case VK_ACCESS_TRANSFER_READ_BIT
:
264 invalidate_cmd
.TextureCacheInvalidationEnable
= true;
267 unreachable("should've masked this out by now");
272 dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
, GENX(PIPE_CONTROL_length
));
273 GENX(PIPE_CONTROL_pack
)(&cmd_buffer
->batch
, dw
, &invalidate_cmd
);
278 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
280 VkShaderStageFlags stages
= cmd_buffer
->state
.pipeline
->active_stages
;
282 /* In order to avoid thrash, we assume that vertex and fragment stages
283 * always exist. In the rare case where one is missing *and* the other
284 * uses push concstants, this may be suboptimal. However, avoiding stalls
285 * seems more important.
287 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
289 if (stages
== cmd_buffer
->state
.push_constant_stages
)
293 const unsigned push_constant_kb
= 32;
295 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
297 const unsigned push_constant_kb
= 16;
300 const unsigned num_stages
=
301 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
302 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
304 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
305 * units of 2KB. Incidentally, these are the same platforms that have
306 * 32KB worth of push constant space.
308 if (push_constant_kb
== 32)
309 size_per_stage
&= ~1u;
311 uint32_t kb_used
= 0;
312 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
313 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
314 anv_batch_emit(&cmd_buffer
->batch
,
315 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
316 alloc
._3DCommandSubOpcode
= 18 + i
;
317 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
318 alloc
.ConstantBufferSize
= push_size
;
320 kb_used
+= push_size
;
323 anv_batch_emit(&cmd_buffer
->batch
,
324 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
325 alloc
.ConstantBufferOffset
= kb_used
;
326 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
329 cmd_buffer
->state
.push_constant_stages
= stages
;
331 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
333 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
334 * the next 3DPRIMITIVE command after programming the
335 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
337 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
338 * pipeline setup, we need to dirty push constants.
340 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
344 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
346 static const uint32_t push_constant_opcodes
[] = {
347 [MESA_SHADER_VERTEX
] = 21,
348 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
349 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
350 [MESA_SHADER_GEOMETRY
] = 22,
351 [MESA_SHADER_FRAGMENT
] = 23,
352 [MESA_SHADER_COMPUTE
] = 0,
355 VkShaderStageFlags flushed
= 0;
357 anv_foreach_stage(stage
, cmd_buffer
->state
.push_constants_dirty
) {
358 if (stage
== MESA_SHADER_COMPUTE
)
361 struct anv_state state
= anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
363 if (state
.offset
== 0) {
364 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
)
365 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
367 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
368 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
],
369 c
.ConstantBody
= (struct GENX(3DSTATE_CONSTANT_BODY
)) {
371 .PointerToConstantBuffer2
= { &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, state
.offset
},
372 .ConstantBuffer2ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
374 .PointerToConstantBuffer0
= { .offset
= state
.offset
},
375 .ConstantBuffer0ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
381 flushed
|= mesa_to_vk_shader_stage(stage
);
384 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_ALL_GRAPHICS
;
390 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
392 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
395 uint32_t vb_emit
= cmd_buffer
->state
.vb_dirty
& pipeline
->vb_used
;
397 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
399 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
);
401 genX(flush_pipeline_select_3d
)(cmd_buffer
);
404 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
405 const uint32_t num_dwords
= 1 + num_buffers
* 4;
407 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
408 GENX(3DSTATE_VERTEX_BUFFERS
));
410 for_each_bit(vb
, vb_emit
) {
411 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
412 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
414 struct GENX(VERTEX_BUFFER_STATE
) state
= {
415 .VertexBufferIndex
= vb
,
418 .MemoryObjectControlState
= GENX(MOCS
),
420 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
421 .InstanceDataStepRate
= 1,
422 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
425 .AddressModifyEnable
= true,
426 .BufferPitch
= pipeline
->binding_stride
[vb
],
427 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
430 .BufferSize
= buffer
->size
- offset
432 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
436 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
441 cmd_buffer
->state
.vb_dirty
&= ~vb_emit
;
443 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
444 /* If somebody compiled a pipeline after starting a command buffer the
445 * scratch bo may have grown since we started this cmd buffer (and
446 * emitted STATE_BASE_ADDRESS). If we're binding that pipeline now,
447 * reemit STATE_BASE_ADDRESS so that we use the bigger scratch bo. */
448 if (cmd_buffer
->state
.scratch_size
< pipeline
->total_scratch
)
449 anv_cmd_buffer_emit_state_base_address(cmd_buffer
);
451 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
453 /* If the pipeline changed, we may need to re-allocate push constant
456 cmd_buffer_alloc_push_constants(cmd_buffer
);
460 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
461 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
462 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
464 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
465 * stall needs to be sent just prior to any 3DSTATE_VS,
466 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
467 * 3DSTATE_BINDING_TABLE_POINTER_VS,
468 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
469 * PIPE_CONTROL needs to be sent before any combination of VS
470 * associated 3DSTATE."
472 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
473 pc
.DepthStallEnable
= true;
474 pc
.PostSyncOperation
= WriteImmediateData
;
476 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
481 /* We emit the binding tables and sampler tables first, then emit push
482 * constants and then finally emit binding table and sampler table
483 * pointers. It has to happen in this order, since emitting the binding
484 * tables may change the push constants (in case of storage images). After
485 * emitting push constants, on SKL+ we have to emit the corresponding
486 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
489 if (cmd_buffer
->state
.descriptors_dirty
)
490 dirty
= gen7_cmd_buffer_flush_descriptor_sets(cmd_buffer
);
492 if (cmd_buffer
->state
.push_constants_dirty
) {
494 /* On Sky Lake and later, the binding table pointers commands are
495 * what actually flush the changes to push constant state so we need
496 * to dirty them so they get re-emitted below.
498 dirty
|= cmd_buffer_flush_push_constants(cmd_buffer
);
500 cmd_buffer_flush_push_constants(cmd_buffer
);
505 gen7_cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
507 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
508 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
510 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
511 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
513 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
517 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
518 struct anv_bo
*bo
, uint32_t offset
)
520 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
521 GENX(3DSTATE_VERTEX_BUFFERS
));
523 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
524 &(struct GENX(VERTEX_BUFFER_STATE
)) {
525 .VertexBufferIndex
= 32, /* Reserved for this */
526 .AddressModifyEnable
= true,
529 .MemoryObjectControlState
= GENX(MOCS
),
530 .BufferStartingAddress
= { bo
, offset
},
533 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
534 .BufferStartingAddress
= { bo
, offset
},
535 .EndAddress
= { bo
, offset
+ 8 },
541 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
542 uint32_t base_vertex
, uint32_t base_instance
)
544 struct anv_state id_state
=
545 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
547 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
548 ((uint32_t *)id_state
.map
)[1] = base_instance
;
550 if (!cmd_buffer
->device
->info
.has_llc
)
551 anv_state_clflush(id_state
);
553 emit_base_vertex_instance_bo(cmd_buffer
,
554 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, id_state
.offset
);
558 VkCommandBuffer commandBuffer
,
559 uint32_t vertexCount
,
560 uint32_t instanceCount
,
561 uint32_t firstVertex
,
562 uint32_t firstInstance
)
564 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
565 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
566 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
568 genX(cmd_buffer_flush_state
)(cmd_buffer
);
570 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
571 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
573 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
574 prim
.VertexAccessType
= SEQUENTIAL
;
575 prim
.PrimitiveTopologyType
= pipeline
->topology
;
576 prim
.VertexCountPerInstance
= vertexCount
;
577 prim
.StartVertexLocation
= firstVertex
;
578 prim
.InstanceCount
= instanceCount
;
579 prim
.StartInstanceLocation
= firstInstance
;
580 prim
.BaseVertexLocation
= 0;
584 void genX(CmdDrawIndexed
)(
585 VkCommandBuffer commandBuffer
,
587 uint32_t instanceCount
,
589 int32_t vertexOffset
,
590 uint32_t firstInstance
)
592 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
593 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
594 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
596 genX(cmd_buffer_flush_state
)(cmd_buffer
);
598 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
599 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
601 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
602 prim
.VertexAccessType
= RANDOM
;
603 prim
.PrimitiveTopologyType
= pipeline
->topology
;
604 prim
.VertexCountPerInstance
= indexCount
;
605 prim
.StartVertexLocation
= firstIndex
;
606 prim
.InstanceCount
= instanceCount
;
607 prim
.StartInstanceLocation
= firstInstance
;
608 prim
.BaseVertexLocation
= vertexOffset
;
612 /* Auto-Draw / Indirect Registers */
613 #define GEN7_3DPRIM_END_OFFSET 0x2420
614 #define GEN7_3DPRIM_START_VERTEX 0x2430
615 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
616 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
617 #define GEN7_3DPRIM_START_INSTANCE 0x243C
618 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
621 emit_lrm(struct anv_batch
*batch
,
622 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
624 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
625 lrm
.RegisterAddress
= reg
;
626 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
631 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
633 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
634 lri
.RegisterOffset
= reg
;
639 void genX(CmdDrawIndirect
)(
640 VkCommandBuffer commandBuffer
,
646 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
647 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
648 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
649 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
650 struct anv_bo
*bo
= buffer
->bo
;
651 uint32_t bo_offset
= buffer
->offset
+ offset
;
653 genX(cmd_buffer_flush_state
)(cmd_buffer
);
655 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
656 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
658 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
659 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
660 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
661 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
662 emit_lri(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
664 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
665 prim
.IndirectParameterEnable
= true;
666 prim
.VertexAccessType
= SEQUENTIAL
;
667 prim
.PrimitiveTopologyType
= pipeline
->topology
;
671 void genX(CmdDrawIndexedIndirect
)(
672 VkCommandBuffer commandBuffer
,
678 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
679 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
680 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
681 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
682 struct anv_bo
*bo
= buffer
->bo
;
683 uint32_t bo_offset
= buffer
->offset
+ offset
;
685 genX(cmd_buffer_flush_state
)(cmd_buffer
);
687 /* TODO: We need to stomp base vertex to 0 somehow */
688 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
689 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
691 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
692 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
693 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
694 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
695 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
697 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
698 prim
.IndirectParameterEnable
= true;
699 prim
.VertexAccessType
= RANDOM
;
700 prim
.PrimitiveTopologyType
= pipeline
->topology
;
707 verify_cmd_parser(const struct anv_device
*device
,
708 int required_version
,
709 const char *function
)
711 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
712 vk_errorf(VK_ERROR_FEATURE_NOT_PRESENT
,
713 "cmd parser version %d is required for %s",
714 required_version
, function
);
723 void genX(CmdDispatch
)(
724 VkCommandBuffer commandBuffer
,
729 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
730 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
731 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
733 if (prog_data
->uses_num_work_groups
) {
734 struct anv_state state
=
735 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
736 uint32_t *sizes
= state
.map
;
740 if (!cmd_buffer
->device
->info
.has_llc
)
741 anv_state_clflush(state
);
742 cmd_buffer
->state
.num_workgroups_offset
= state
.offset
;
743 cmd_buffer
->state
.num_workgroups_bo
=
744 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
;
747 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
749 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
750 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
751 ggw
.ThreadDepthCounterMaximum
= 0;
752 ggw
.ThreadHeightCounterMaximum
= 0;
753 ggw
.ThreadWidthCounterMaximum
= pipeline
->cs_thread_width_max
- 1;
754 ggw
.ThreadGroupIDXDimension
= x
;
755 ggw
.ThreadGroupIDYDimension
= y
;
756 ggw
.ThreadGroupIDZDimension
= z
;
757 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
758 ggw
.BottomExecutionMask
= 0xffffffff;
761 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
764 #define GPGPU_DISPATCHDIMX 0x2500
765 #define GPGPU_DISPATCHDIMY 0x2504
766 #define GPGPU_DISPATCHDIMZ 0x2508
768 #define MI_PREDICATE_SRC0 0x2400
769 #define MI_PREDICATE_SRC1 0x2408
771 void genX(CmdDispatchIndirect
)(
772 VkCommandBuffer commandBuffer
,
776 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
777 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
778 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
779 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
780 struct anv_bo
*bo
= buffer
->bo
;
781 uint32_t bo_offset
= buffer
->offset
+ offset
;
782 struct anv_batch
*batch
= &cmd_buffer
->batch
;
785 /* Linux 4.4 added command parser version 5 which allows the GPGPU
786 * indirect dispatch registers to be written.
788 if (!verify_cmd_parser(cmd_buffer
->device
, 5, "vkCmdDispatchIndirect"))
792 if (prog_data
->uses_num_work_groups
) {
793 cmd_buffer
->state
.num_workgroups_offset
= bo_offset
;
794 cmd_buffer
->state
.num_workgroups_bo
= bo
;
797 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
799 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
800 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
801 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
804 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
805 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
806 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
807 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
809 /* Load compute_dispatch_indirect_x_size into SRC0 */
810 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
812 /* predicate = (compute_dispatch_indirect_x_size == 0); */
813 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
814 mip
.LoadOperation
= LOAD_LOAD
;
815 mip
.CombineOperation
= COMBINE_SET
;
816 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
819 /* Load compute_dispatch_indirect_y_size into SRC0 */
820 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
822 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
823 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
824 mip
.LoadOperation
= LOAD_LOAD
;
825 mip
.CombineOperation
= COMBINE_OR
;
826 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
829 /* Load compute_dispatch_indirect_z_size into SRC0 */
830 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
832 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
833 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
834 mip
.LoadOperation
= LOAD_LOAD
;
835 mip
.CombineOperation
= COMBINE_OR
;
836 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
839 /* predicate = !predicate; */
840 #define COMPARE_FALSE 1
841 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
842 mip
.LoadOperation
= LOAD_LOADINV
;
843 mip
.CombineOperation
= COMBINE_OR
;
844 mip
.CompareOperation
= COMPARE_FALSE
;
848 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
849 ggw
.IndirectParameterEnable
= true;
850 ggw
.PredicateEnable
= GEN_GEN
<= 7;
851 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
852 ggw
.ThreadDepthCounterMaximum
= 0;
853 ggw
.ThreadHeightCounterMaximum
= 0;
854 ggw
.ThreadWidthCounterMaximum
= pipeline
->cs_thread_width_max
- 1;
855 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
856 ggw
.BottomExecutionMask
= 0xffffffff;
859 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
863 flush_pipeline_before_pipeline_select(struct anv_cmd_buffer
*cmd_buffer
,
866 #if GEN_GEN >= 8 && GEN_GEN < 10
867 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
869 * Software must clear the COLOR_CALC_STATE Valid field in
870 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
871 * with Pipeline Select set to GPGPU.
873 * The internal hardware docs recommend the same workaround for Gen9
876 if (pipeline
== GPGPU
)
877 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
879 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
880 * PIPELINE_SELECT [DevBWR+]":
884 * Software must ensure all the write caches are flushed through a
885 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
886 * command to invalidate read only caches prior to programming
887 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
889 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
890 pc
.RenderTargetCacheFlushEnable
= true;
891 pc
.DepthCacheFlushEnable
= true;
892 pc
.DCFlushEnable
= true;
893 pc
.PostSyncOperation
= NoWrite
;
894 pc
.CommandStreamerStallEnable
= true;
897 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
898 pc
.TextureCacheInvalidationEnable
= true;
899 pc
.ConstantCacheInvalidationEnable
= true;
900 pc
.StateCacheInvalidationEnable
= true;
901 pc
.InstructionCacheInvalidateEnable
= true;
902 pc
.PostSyncOperation
= NoWrite
;
908 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
910 if (cmd_buffer
->state
.current_pipeline
!= _3D
) {
911 flush_pipeline_before_pipeline_select(cmd_buffer
, _3D
);
913 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
917 ps
.PipelineSelection
= _3D
;
920 cmd_buffer
->state
.current_pipeline
= _3D
;
925 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
927 if (cmd_buffer
->state
.current_pipeline
!= GPGPU
) {
928 flush_pipeline_before_pipeline_select(cmd_buffer
, GPGPU
);
930 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
934 ps
.PipelineSelection
= GPGPU
;
937 cmd_buffer
->state
.current_pipeline
= GPGPU
;
942 genX(cmd_buffer_alloc_null_surface_state
)(struct anv_cmd_buffer
*cmd_buffer
,
943 struct anv_framebuffer
*fb
)
945 struct anv_state state
=
946 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
948 struct GENX(RENDER_SURFACE_STATE
) null_ss
= {
949 .SurfaceType
= SURFTYPE_NULL
,
950 .SurfaceArray
= fb
->layers
> 0,
951 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
955 .TiledSurface
= true,
957 .Width
= fb
->width
- 1,
958 .Height
= fb
->height
- 1,
959 .Depth
= fb
->layers
- 1,
960 .RenderTargetViewExtent
= fb
->layers
- 1,
963 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
.map
, &null_ss
);
965 if (!cmd_buffer
->device
->info
.has_llc
)
966 anv_state_clflush(state
);
972 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
974 struct anv_device
*device
= cmd_buffer
->device
;
975 const struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
976 const struct anv_image_view
*iview
=
977 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
978 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
979 const bool has_depth
= image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
980 const bool has_stencil
=
981 image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
983 /* FIXME: Implement the PMA stall W/A */
984 /* FIXME: Width and Height are wrong */
986 /* Emit 3DSTATE_DEPTH_BUFFER */
988 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
989 db
.SurfaceType
= SURFTYPE_2D
;
990 db
.DepthWriteEnable
= true;
991 db
.StencilWriteEnable
= has_stencil
;
992 db
.HierarchicalDepthBufferEnable
= false;
994 db
.SurfaceFormat
= isl_surf_get_depth_format(&device
->isl_dev
,
995 &image
->depth_surface
.isl
);
997 db
.SurfaceBaseAddress
= (struct anv_address
) {
999 .offset
= image
->offset
+ image
->depth_surface
.offset
,
1001 db
.DepthBufferObjectControlState
= GENX(MOCS
),
1003 db
.SurfacePitch
= image
->depth_surface
.isl
.row_pitch
- 1;
1004 db
.Height
= fb
->height
- 1;
1005 db
.Width
= fb
->width
- 1;
1008 db
.MinimumArrayElement
= 0;
1012 isl_surf_get_array_pitch_el_rows(&image
->depth_surface
.isl
) >> 2,
1014 db
.RenderTargetViewExtent
= 1 - 1;
1017 /* Even when no depth buffer is present, the hardware requires that
1018 * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
1020 * If a null depth buffer is bound, the driver must instead bind depth as:
1021 * 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
1022 * 3DSTATE_DEPTH.Width = 1
1023 * 3DSTATE_DEPTH.Height = 1
1024 * 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
1025 * 3DSTATE_DEPTH.SurfaceBaseAddress = 0
1026 * 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
1027 * 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
1028 * 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
1030 * The PRM is wrong, though. The width and height must be programmed to
1031 * actual framebuffer's width and height, even when neither depth buffer
1032 * nor stencil buffer is present. Also, D16_UNORM is not allowed to
1033 * be combined with a stencil buffer so we use D32_FLOAT instead.
1035 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
1036 db
.SurfaceType
= SURFTYPE_2D
;
1037 db
.SurfaceFormat
= D32_FLOAT
;
1038 db
.Width
= fb
->width
- 1;
1039 db
.Height
= fb
->height
- 1;
1040 db
.StencilWriteEnable
= has_stencil
;
1044 /* Emit 3DSTATE_STENCIL_BUFFER */
1046 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
) {
1047 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1048 sb
.StencilBufferEnable
= true,
1050 sb
.StencilBufferObjectControlState
= GENX(MOCS
),
1052 /* Stencil buffers have strange pitch. The PRM says:
1054 * The pitch must be set to 2x the value computed based on width,
1055 * as the stencil buffer is stored with two rows interleaved.
1057 sb
.SurfacePitch
= 2 * image
->stencil_surface
.isl
.row_pitch
- 1,
1060 sb
.SurfaceQPitch
= isl_surf_get_array_pitch_el_rows(&image
->stencil_surface
.isl
) >> 2,
1062 sb
.SurfaceBaseAddress
= (struct anv_address
) {
1064 .offset
= image
->offset
+ image
->stencil_surface
.offset
,
1068 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
);
1071 /* Disable hierarchial depth buffers. */
1072 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hz
);
1074 /* Clear the clear params. */
1075 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CLEAR_PARAMS
), cp
);
1079 * @see anv_cmd_buffer_set_subpass()
1082 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
1083 struct anv_subpass
*subpass
)
1085 cmd_buffer
->state
.subpass
= subpass
;
1087 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
1089 cmd_buffer_emit_depth_stencil(cmd_buffer
);
1092 void genX(CmdBeginRenderPass
)(
1093 VkCommandBuffer commandBuffer
,
1094 const VkRenderPassBeginInfo
* pRenderPassBegin
,
1095 VkSubpassContents contents
)
1097 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1098 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
1099 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
1101 cmd_buffer
->state
.framebuffer
= framebuffer
;
1102 cmd_buffer
->state
.pass
= pass
;
1103 anv_cmd_state_setup_attachments(cmd_buffer
, pRenderPassBegin
);
1105 genX(flush_pipeline_select_3d
)(cmd_buffer
);
1107 const VkRect2D
*render_area
= &pRenderPassBegin
->renderArea
;
1109 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), r
) {
1110 r
.ClippedDrawingRectangleYMin
= MAX2(render_area
->offset
.y
, 0);
1111 r
.ClippedDrawingRectangleXMin
= MAX2(render_area
->offset
.x
, 0);
1112 r
.ClippedDrawingRectangleYMax
=
1113 render_area
->offset
.y
+ render_area
->extent
.height
- 1;
1114 r
.ClippedDrawingRectangleXMax
=
1115 render_area
->offset
.x
+ render_area
->extent
.width
- 1;
1116 r
.DrawingRectangleOriginY
= 0;
1117 r
.DrawingRectangleOriginX
= 0;
1120 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
1121 anv_cmd_buffer_clear_subpass(cmd_buffer
);
1124 void genX(CmdNextSubpass
)(
1125 VkCommandBuffer commandBuffer
,
1126 VkSubpassContents contents
)
1128 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1130 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1132 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
1133 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
1134 anv_cmd_buffer_clear_subpass(cmd_buffer
);
1137 void genX(CmdEndRenderPass
)(
1138 VkCommandBuffer commandBuffer
)
1140 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1142 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
1146 emit_ps_depth_count(struct anv_batch
*batch
,
1147 struct anv_bo
*bo
, uint32_t offset
)
1149 anv_batch_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1150 pc
.DestinationAddressType
= DAT_PPGTT
;
1151 pc
.PostSyncOperation
= WritePSDepthCount
;
1152 pc
.DepthStallEnable
= true;
1153 pc
.Address
= (struct anv_address
) { bo
, offset
};
1158 emit_query_availability(struct anv_batch
*batch
,
1159 struct anv_bo
*bo
, uint32_t offset
)
1161 anv_batch_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1162 pc
.DestinationAddressType
= DAT_PPGTT
;
1163 pc
.PostSyncOperation
= WriteImmediateData
;
1164 pc
.Address
= (struct anv_address
) { bo
, offset
};
1165 pc
.ImmediateData
= 1;
1169 void genX(CmdBeginQuery
)(
1170 VkCommandBuffer commandBuffer
,
1171 VkQueryPool queryPool
,
1173 VkQueryControlFlags flags
)
1175 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1176 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
1178 /* Workaround: When meta uses the pipeline with the VS disabled, it seems
1179 * that the pipelining of the depth write breaks. What we see is that
1180 * samples from the render pass clear leaks into the first query
1181 * immediately after the clear. Doing a pipecontrol with a post-sync
1182 * operation and DepthStallEnable seems to work around the issue.
1184 if (cmd_buffer
->state
.need_query_wa
) {
1185 cmd_buffer
->state
.need_query_wa
= false;
1186 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1187 pc
.DepthCacheFlushEnable
= true;
1188 pc
.DepthStallEnable
= true;
1192 switch (pool
->type
) {
1193 case VK_QUERY_TYPE_OCCLUSION
:
1194 emit_ps_depth_count(&cmd_buffer
->batch
, &pool
->bo
,
1195 query
* sizeof(struct anv_query_pool_slot
));
1198 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
1204 void genX(CmdEndQuery
)(
1205 VkCommandBuffer commandBuffer
,
1206 VkQueryPool queryPool
,
1209 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1210 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
1212 switch (pool
->type
) {
1213 case VK_QUERY_TYPE_OCCLUSION
:
1214 emit_ps_depth_count(&cmd_buffer
->batch
, &pool
->bo
,
1215 query
* sizeof(struct anv_query_pool_slot
) + 8);
1217 emit_query_availability(&cmd_buffer
->batch
, &pool
->bo
,
1218 query
* sizeof(struct anv_query_pool_slot
) + 16);
1221 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
1227 #define TIMESTAMP 0x2358
1229 void genX(CmdWriteTimestamp
)(
1230 VkCommandBuffer commandBuffer
,
1231 VkPipelineStageFlagBits pipelineStage
,
1232 VkQueryPool queryPool
,
1235 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1236 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
1237 uint32_t offset
= query
* sizeof(struct anv_query_pool_slot
);
1239 assert(pool
->type
== VK_QUERY_TYPE_TIMESTAMP
);
1241 switch (pipelineStage
) {
1242 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
:
1243 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
1244 srm
.RegisterAddress
= TIMESTAMP
;
1245 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
};
1247 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
1248 srm
.RegisterAddress
= TIMESTAMP
+ 4;
1249 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
+ 4 };
1254 /* Everything else is bottom-of-pipe */
1255 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1256 pc
.DestinationAddressType
= DAT_PPGTT
,
1257 pc
.PostSyncOperation
= WriteTimestamp
,
1258 pc
.Address
= (struct anv_address
) { &pool
->bo
, offset
};
1263 emit_query_availability(&cmd_buffer
->batch
, &pool
->bo
, query
+ 16);
1266 #if GEN_GEN > 7 || GEN_IS_HASWELL
1268 #define alu_opcode(v) __gen_uint((v), 20, 31)
1269 #define alu_operand1(v) __gen_uint((v), 10, 19)
1270 #define alu_operand2(v) __gen_uint((v), 0, 9)
1271 #define alu(opcode, operand1, operand2) \
1272 alu_opcode(opcode) | alu_operand1(operand1) | alu_operand2(operand2)
1274 #define OPCODE_NOOP 0x000
1275 #define OPCODE_LOAD 0x080
1276 #define OPCODE_LOADINV 0x480
1277 #define OPCODE_LOAD0 0x081
1278 #define OPCODE_LOAD1 0x481
1279 #define OPCODE_ADD 0x100
1280 #define OPCODE_SUB 0x101
1281 #define OPCODE_AND 0x102
1282 #define OPCODE_OR 0x103
1283 #define OPCODE_XOR 0x104
1284 #define OPCODE_STORE 0x180
1285 #define OPCODE_STOREINV 0x580
1287 #define OPERAND_R0 0x00
1288 #define OPERAND_R1 0x01
1289 #define OPERAND_R2 0x02
1290 #define OPERAND_R3 0x03
1291 #define OPERAND_R4 0x04
1292 #define OPERAND_SRCA 0x20
1293 #define OPERAND_SRCB 0x21
1294 #define OPERAND_ACCU 0x31
1295 #define OPERAND_ZF 0x32
1296 #define OPERAND_CF 0x33
1298 #define CS_GPR(n) (0x2600 + (n) * 8)
1301 emit_load_alu_reg_u64(struct anv_batch
*batch
, uint32_t reg
,
1302 struct anv_bo
*bo
, uint32_t offset
)
1304 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
1305 lrm
.RegisterAddress
= reg
,
1306 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
1308 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
1309 lrm
.RegisterAddress
= reg
+ 4;
1310 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
1315 store_query_result(struct anv_batch
*batch
, uint32_t reg
,
1316 struct anv_bo
*bo
, uint32_t offset
, VkQueryResultFlags flags
)
1318 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
1319 srm
.RegisterAddress
= reg
;
1320 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
1323 if (flags
& VK_QUERY_RESULT_64_BIT
) {
1324 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
1325 srm
.RegisterAddress
= reg
+ 4;
1326 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
1331 void genX(CmdCopyQueryPoolResults
)(
1332 VkCommandBuffer commandBuffer
,
1333 VkQueryPool queryPool
,
1334 uint32_t firstQuery
,
1335 uint32_t queryCount
,
1336 VkBuffer destBuffer
,
1337 VkDeviceSize destOffset
,
1338 VkDeviceSize destStride
,
1339 VkQueryResultFlags flags
)
1341 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1342 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
1343 ANV_FROM_HANDLE(anv_buffer
, buffer
, destBuffer
);
1344 uint32_t slot_offset
, dst_offset
;
1346 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
1347 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1348 pc
.CommandStreamerStallEnable
= true;
1349 pc
.StallAtPixelScoreboard
= true;
1353 dst_offset
= buffer
->offset
+ destOffset
;
1354 for (uint32_t i
= 0; i
< queryCount
; i
++) {
1356 slot_offset
= (firstQuery
+ i
) * sizeof(struct anv_query_pool_slot
);
1357 switch (pool
->type
) {
1358 case VK_QUERY_TYPE_OCCLUSION
:
1359 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
1360 CS_GPR(0), &pool
->bo
, slot_offset
);
1361 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
1362 CS_GPR(1), &pool
->bo
, slot_offset
+ 8);
1364 /* FIXME: We need to clamp the result for 32 bit. */
1366 uint32_t *dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
1367 dw
[1] = alu(OPCODE_LOAD
, OPERAND_SRCA
, OPERAND_R1
);
1368 dw
[2] = alu(OPCODE_LOAD
, OPERAND_SRCB
, OPERAND_R0
);
1369 dw
[3] = alu(OPCODE_SUB
, 0, 0);
1370 dw
[4] = alu(OPCODE_STORE
, OPERAND_R2
, OPERAND_ACCU
);
1373 case VK_QUERY_TYPE_TIMESTAMP
:
1374 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
1375 CS_GPR(2), &pool
->bo
, slot_offset
);
1379 unreachable("unhandled query type");
1382 store_query_result(&cmd_buffer
->batch
,
1383 CS_GPR(2), buffer
->bo
, dst_offset
, flags
);
1385 if (flags
& VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
) {
1386 emit_load_alu_reg_u64(&cmd_buffer
->batch
, CS_GPR(0),
1387 &pool
->bo
, slot_offset
+ 16);
1388 if (flags
& VK_QUERY_RESULT_64_BIT
)
1389 store_query_result(&cmd_buffer
->batch
,
1390 CS_GPR(0), buffer
->bo
, dst_offset
+ 8, flags
);
1392 store_query_result(&cmd_buffer
->batch
,
1393 CS_GPR(0), buffer
->bo
, dst_offset
+ 4, flags
);
1396 dst_offset
+= destStride
;