2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_l3_config.h"
33 #include "genxml/gen_macros.h"
34 #include "genxml/genX_pack.h"
36 /* We reserve GPR 14 and 15 for conditional rendering */
37 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
38 #define __gen_get_batch_dwords anv_batch_emit_dwords
39 #define __gen_address_offset anv_address_add
40 #include "common/gen_mi_builder.h"
43 emit_lrm(struct anv_batch
*batch
, uint32_t reg
, struct anv_address addr
)
45 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
46 lrm
.RegisterAddress
= reg
;
47 lrm
.MemoryAddress
= addr
;
52 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
54 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
55 lri
.RegisterOffset
= reg
;
60 #if GEN_IS_HASWELL || GEN_GEN >= 8
62 emit_lrr(struct anv_batch
*batch
, uint32_t dst
, uint32_t src
)
64 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
65 lrr
.SourceRegisterAddress
= src
;
66 lrr
.DestinationRegisterAddress
= dst
;
72 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
74 struct anv_device
*device
= cmd_buffer
->device
;
76 /* If we are emitting a new state base address we probably need to re-emit
79 cmd_buffer
->state
.descriptors_dirty
|= ~0;
81 /* Emit a render target cache flush.
83 * This isn't documented anywhere in the PRM. However, it seems to be
84 * necessary prior to changing the surface state base adress. Without
85 * this, we get GPU hangs when using multi-level command buffers which
86 * clear depth, reset state base address, and then go render stuff.
88 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
89 pc
.DCFlushEnable
= true;
90 pc
.RenderTargetCacheFlushEnable
= true;
91 pc
.CommandStreamerStallEnable
= true;
94 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
95 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
96 sba
.GeneralStateMOCS
= GENX(MOCS
);
97 sba
.GeneralStateBaseAddressModifyEnable
= true;
99 sba
.SurfaceStateBaseAddress
=
100 anv_cmd_buffer_surface_base_address(cmd_buffer
);
101 sba
.SurfaceStateMOCS
= GENX(MOCS
);
102 sba
.SurfaceStateBaseAddressModifyEnable
= true;
104 sba
.DynamicStateBaseAddress
=
105 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
106 sba
.DynamicStateMOCS
= GENX(MOCS
);
107 sba
.DynamicStateBaseAddressModifyEnable
= true;
109 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
110 sba
.IndirectObjectMOCS
= GENX(MOCS
);
111 sba
.IndirectObjectBaseAddressModifyEnable
= true;
113 sba
.InstructionBaseAddress
=
114 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
115 sba
.InstructionMOCS
= GENX(MOCS
);
116 sba
.InstructionBaseAddressModifyEnable
= true;
119 /* Broadwell requires that we specify a buffer size for a bunch of
120 * these fields. However, since we will be growing the BO's live, we
121 * just set them all to the maximum.
123 sba
.GeneralStateBufferSize
= 0xfffff;
124 sba
.GeneralStateBufferSizeModifyEnable
= true;
125 sba
.DynamicStateBufferSize
= 0xfffff;
126 sba
.DynamicStateBufferSizeModifyEnable
= true;
127 sba
.IndirectObjectBufferSize
= 0xfffff;
128 sba
.IndirectObjectBufferSizeModifyEnable
= true;
129 sba
.InstructionBufferSize
= 0xfffff;
130 sba
.InstructionBuffersizeModifyEnable
= true;
133 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
134 sba
.BindlessSurfaceStateMOCS
= GENX(MOCS
);
135 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
136 sba
.BindlessSurfaceStateSize
= 0;
139 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
140 sba
.BindlessSamplerStateMOCS
= GENX(MOCS
);
141 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
142 sba
.BindlessSamplerStateBufferSize
= 0;
146 /* After re-setting the surface state base address, we have to do some
147 * cache flusing so that the sampler engine will pick up the new
148 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
149 * Shared Function > 3D Sampler > State > State Caching (page 96):
151 * Coherency with system memory in the state cache, like the texture
152 * cache is handled partially by software. It is expected that the
153 * command stream or shader will issue Cache Flush operation or
154 * Cache_Flush sampler message to ensure that the L1 cache remains
155 * coherent with system memory.
159 * Whenever the value of the Dynamic_State_Base_Addr,
160 * Surface_State_Base_Addr are altered, the L1 state cache must be
161 * invalidated to ensure the new surface or sampler state is fetched
162 * from system memory.
164 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
165 * which, according the PIPE_CONTROL instruction documentation in the
168 * Setting this bit is independent of any other bit in this packet.
169 * This bit controls the invalidation of the L1 and L2 state caches
170 * at the top of the pipe i.e. at the parsing time.
172 * Unfortunately, experimentation seems to indicate that state cache
173 * invalidation through a PIPE_CONTROL does nothing whatsoever in
174 * regards to surface state and binding tables. In stead, it seems that
175 * invalidating the texture cache is what is actually needed.
177 * XXX: As far as we have been able to determine through
178 * experimentation, shows that flush the texture cache appears to be
179 * sufficient. The theory here is that all of the sampling/rendering
180 * units cache the binding table in the texture cache. However, we have
181 * yet to be able to actually confirm this.
183 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
184 pc
.TextureCacheInvalidationEnable
= true;
185 pc
.ConstantCacheInvalidationEnable
= true;
186 pc
.StateCacheInvalidationEnable
= true;
191 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
192 struct anv_state state
, struct anv_address addr
)
194 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
197 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
198 state
.offset
+ isl_dev
->ss
.addr_offset
,
199 addr
.bo
, addr
.offset
);
200 if (result
!= VK_SUCCESS
)
201 anv_batch_set_error(&cmd_buffer
->batch
, result
);
205 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
206 struct anv_surface_state state
)
208 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
210 assert(!anv_address_is_null(state
.address
));
211 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
213 if (!anv_address_is_null(state
.aux_address
)) {
215 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
216 &cmd_buffer
->pool
->alloc
,
217 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
218 state
.aux_address
.bo
, state
.aux_address
.offset
);
219 if (result
!= VK_SUCCESS
)
220 anv_batch_set_error(&cmd_buffer
->batch
, result
);
223 if (!anv_address_is_null(state
.clear_address
)) {
225 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
226 &cmd_buffer
->pool
->alloc
,
228 isl_dev
->ss
.clear_color_state_offset
,
229 state
.clear_address
.bo
, state
.clear_address
.offset
);
230 if (result
!= VK_SUCCESS
)
231 anv_batch_set_error(&cmd_buffer
->batch
, result
);
236 color_attachment_compute_aux_usage(struct anv_device
* device
,
237 struct anv_cmd_state
* cmd_state
,
238 uint32_t att
, VkRect2D render_area
,
239 union isl_color_value
*fast_clear_color
)
241 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
242 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
244 assert(iview
->n_planes
== 1);
246 if (iview
->planes
[0].isl
.base_array_layer
>=
247 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
248 iview
->planes
[0].isl
.base_level
)) {
249 /* There is no aux buffer which corresponds to the level and layer(s)
252 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
253 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
254 att_state
->fast_clear
= false;
258 att_state
->aux_usage
=
259 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
260 VK_IMAGE_ASPECT_COLOR_BIT
,
261 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
263 /* If we don't have aux, then we should have returned early in the layer
264 * check above. If we got here, we must have something.
266 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
268 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
269 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
270 att_state
->input_aux_usage
= att_state
->aux_usage
;
272 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
274 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
275 * setting is only allowed if Surface Format supported for Fast
276 * Clear. In addition, if the surface is bound to the sampling
277 * engine, Surface Format must be supported for Render Target
278 * Compression for surfaces bound to the sampling engine."
280 * In other words, we can only sample from a fast-cleared image if it
281 * also supports color compression.
283 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
284 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
286 /* While fast-clear resolves and partial resolves are fairly cheap in the
287 * case where you render to most of the pixels, full resolves are not
288 * because they potentially involve reading and writing the entire
289 * framebuffer. If we can't texture with CCS_E, we should leave it off and
290 * limit ourselves to fast clears.
292 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
293 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
294 anv_perf_warn(device
->instance
, iview
->image
,
295 "Not temporarily enabling CCS_E.");
298 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
302 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
303 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
305 union isl_color_value clear_color
= {};
306 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
308 att_state
->clear_color_is_zero_one
=
309 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
310 att_state
->clear_color_is_zero
=
311 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
313 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
314 /* Start by getting the fast clear type. We use the first subpass
315 * layout here because we don't want to fast-clear if the first subpass
316 * to use the attachment can't handle fast-clears.
318 enum anv_fast_clear_type fast_clear_type
=
319 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
320 VK_IMAGE_ASPECT_COLOR_BIT
,
321 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
322 switch (fast_clear_type
) {
323 case ANV_FAST_CLEAR_NONE
:
324 att_state
->fast_clear
= false;
326 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
327 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
329 case ANV_FAST_CLEAR_ANY
:
330 att_state
->fast_clear
= true;
334 /* Potentially, we could do partial fast-clears but doing so has crazy
335 * alignment restrictions. It's easier to just restrict to full size
336 * fast clears for now.
338 if (render_area
.offset
.x
!= 0 ||
339 render_area
.offset
.y
!= 0 ||
340 render_area
.extent
.width
!= iview
->extent
.width
||
341 render_area
.extent
.height
!= iview
->extent
.height
)
342 att_state
->fast_clear
= false;
344 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
345 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
346 att_state
->fast_clear
= false;
348 /* We only allow fast clears to the first slice of an image (level 0,
349 * layer 0) and only for the entire slice. This guarantees us that, at
350 * any given time, there is only one clear color on any given image at
351 * any given time. At the time of our testing (Jan 17, 2018), there
352 * were no known applications which would benefit from fast-clearing
353 * more than just the first slice.
355 if (att_state
->fast_clear
&&
356 (iview
->planes
[0].isl
.base_level
> 0 ||
357 iview
->planes
[0].isl
.base_array_layer
> 0)) {
358 anv_perf_warn(device
->instance
, iview
->image
,
359 "Rendering with multi-lod or multi-layer framebuffer "
360 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
361 "baseArrayLayer > 0. Not fast clearing.");
362 att_state
->fast_clear
= false;
363 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
364 anv_perf_warn(device
->instance
, iview
->image
,
365 "Rendering to a multi-layer framebuffer with "
366 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
369 if (att_state
->fast_clear
)
370 *fast_clear_color
= clear_color
;
372 att_state
->fast_clear
= false;
377 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
378 struct anv_cmd_state
*cmd_state
,
379 uint32_t att
, VkRect2D render_area
)
381 struct anv_render_pass_attachment
*pass_att
=
382 &cmd_state
->pass
->attachments
[att
];
383 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
384 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
386 /* These will be initialized after the first subpass transition. */
387 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
388 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
391 /* We don't do any HiZ or depth fast-clears on gen7 yet */
392 att_state
->fast_clear
= false;
396 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
397 /* If we're just clearing stencil, we can always HiZ clear */
398 att_state
->fast_clear
= true;
402 /* Default to false for now */
403 att_state
->fast_clear
= false;
405 /* We must have depth in order to have HiZ */
406 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
409 const enum isl_aux_usage first_subpass_aux_usage
=
410 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
411 VK_IMAGE_ASPECT_DEPTH_BIT
,
412 pass_att
->first_subpass_layout
);
413 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
416 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
417 iview
->planes
[0].isl
.format
,
418 iview
->image
->samples
,
419 render_area
.offset
.x
,
420 render_area
.offset
.y
,
421 render_area
.offset
.x
+
422 render_area
.extent
.width
,
423 render_area
.offset
.y
+
424 render_area
.extent
.height
))
427 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
430 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
431 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
432 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
433 * only supports returning 0.0f. Gens prior to gen8 do not support this
439 /* If we got here, then we can fast clear */
440 att_state
->fast_clear
= true;
444 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
446 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
449 /* We only allocate input attachment states for color surfaces. Compression
450 * is not yet enabled for depth textures and stencil doesn't allow
451 * compression so we can just use the texture surface state from the view.
453 return vk_format_is_color(att
->format
);
456 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
457 * the initial layout is undefined, the HiZ buffer and depth buffer will
458 * represent the same data at the end of this operation.
461 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
462 const struct anv_image
*image
,
463 VkImageLayout initial_layout
,
464 VkImageLayout final_layout
)
466 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
467 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
468 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
469 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
470 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
471 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
473 enum isl_aux_op hiz_op
;
474 if (hiz_enabled
&& !enable_hiz
) {
475 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
476 } else if (!hiz_enabled
&& enable_hiz
) {
477 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
479 assert(hiz_enabled
== enable_hiz
);
480 /* If the same buffer will be used, no resolves are necessary. */
481 hiz_op
= ISL_AUX_OP_NONE
;
484 if (hiz_op
!= ISL_AUX_OP_NONE
)
485 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
489 #define MI_PREDICATE_SRC0 0x2400
490 #define MI_PREDICATE_SRC1 0x2408
491 #define MI_PREDICATE_RESULT 0x2418
494 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
495 const struct anv_image
*image
,
496 VkImageAspectFlagBits aspect
,
498 uint32_t base_layer
, uint32_t layer_count
,
501 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
503 /* We only have compression tracking for CCS_E */
504 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
507 for (uint32_t a
= 0; a
< layer_count
; a
++) {
508 uint32_t layer
= base_layer
+ a
;
509 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
510 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
513 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
519 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
520 const struct anv_image
*image
,
521 VkImageAspectFlagBits aspect
,
522 enum anv_fast_clear_type fast_clear
)
524 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
525 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
527 sdi
.ImmediateData
= fast_clear
;
530 /* Whenever we have fast-clear, we consider that slice to be compressed.
531 * This makes building predicates much easier.
533 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
534 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
537 #if GEN_IS_HASWELL || GEN_GEN >= 8
538 static inline uint32_t
539 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
541 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
543 .Operand1
= operand1
,
544 .Operand2
= operand2
,
548 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
554 #define CS_GPR(n) (0x2600 + (n) * 8)
556 /* This is only really practical on haswell and above because it requires
557 * MI math in order to get it correct.
559 #if GEN_GEN >= 8 || GEN_IS_HASWELL
561 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
562 const struct anv_image
*image
,
563 VkImageAspectFlagBits aspect
,
564 uint32_t level
, uint32_t array_layer
,
565 enum isl_aux_op resolve_op
,
566 enum anv_fast_clear_type fast_clear_supported
)
568 struct gen_mi_builder b
;
569 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
571 const struct gen_mi_value fast_clear_type
=
572 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
575 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
576 /* In this case, we're doing a full resolve which means we want the
577 * resolve to happen if any compression (including fast-clears) is
580 * In order to simplify the logic a bit, we make the assumption that,
581 * if the first slice has been fast-cleared, it is also marked as
582 * compressed. See also set_image_fast_clear_state.
584 const struct gen_mi_value compression_state
=
585 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer
->device
,
587 level
, array_layer
));
588 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
590 gen_mi_store(&b
, compression_state
, gen_mi_imm(0));
592 if (level
== 0 && array_layer
== 0) {
593 /* If the predicate is true, we want to write 0 to the fast clear type
594 * and, if it's false, leave it alone. We can do this by writing
596 * clear_type = clear_type & ~predicate;
598 struct gen_mi_value new_fast_clear_type
=
599 gen_mi_iand(&b
, fast_clear_type
,
600 gen_mi_inot(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
)));
601 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
603 } else if (level
== 0 && array_layer
== 0) {
604 /* In this case, we are doing a partial resolve to get rid of fast-clear
605 * colors. We don't care about the compression state but we do care
606 * about how much fast clear is allowed by the final layout.
608 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
609 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
611 /* We need to compute (fast_clear_supported < image->fast_clear) */
612 struct gen_mi_value pred
=
613 gen_mi_ult(&b
, gen_mi_imm(fast_clear_supported
), fast_clear_type
);
614 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
615 gen_mi_value_ref(&b
, pred
));
617 /* If the predicate is true, we want to write 0 to the fast clear type
618 * and, if it's false, leave it alone. We can do this by writing
620 * clear_type = clear_type & ~predicate;
622 struct gen_mi_value new_fast_clear_type
=
623 gen_mi_iand(&b
, fast_clear_type
, gen_mi_inot(&b
, pred
));
624 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
626 /* In this case, we're trying to do a partial resolve on a slice that
627 * doesn't have clear color. There's nothing to do.
629 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
633 /* Set src1 to 0 and use a != condition */
634 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
636 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
637 mip
.LoadOperation
= LOAD_LOADINV
;
638 mip
.CombineOperation
= COMBINE_SET
;
639 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
642 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
646 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
647 const struct anv_image
*image
,
648 VkImageAspectFlagBits aspect
,
649 uint32_t level
, uint32_t array_layer
,
650 enum isl_aux_op resolve_op
,
651 enum anv_fast_clear_type fast_clear_supported
)
653 struct gen_mi_builder b
;
654 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
656 struct gen_mi_value fast_clear_type_mem
=
657 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
660 /* This only works for partial resolves and only when the clear color is
661 * all or nothing. On the upside, this emits less command streamer code
662 * and works on Ivybridge and Bay Trail.
664 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
665 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
667 /* We don't support fast clears on anything other than the first slice. */
668 if (level
> 0 || array_layer
> 0)
671 /* On gen8, we don't have a concept of default clear colors because we
672 * can't sample from CCS surfaces. It's enough to just load the fast clear
673 * state into the predicate register.
675 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), fast_clear_type_mem
);
676 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
677 gen_mi_store(&b
, fast_clear_type_mem
, gen_mi_imm(0));
679 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
680 mip
.LoadOperation
= LOAD_LOADINV
;
681 mip
.CombineOperation
= COMBINE_SET
;
682 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
685 #endif /* GEN_GEN <= 8 */
688 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
689 const struct anv_image
*image
,
690 enum isl_format format
,
691 VkImageAspectFlagBits aspect
,
692 uint32_t level
, uint32_t array_layer
,
693 enum isl_aux_op resolve_op
,
694 enum anv_fast_clear_type fast_clear_supported
)
696 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
699 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
700 aspect
, level
, array_layer
,
701 resolve_op
, fast_clear_supported
);
702 #else /* GEN_GEN <= 8 */
703 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
704 aspect
, level
, array_layer
,
705 resolve_op
, fast_clear_supported
);
708 /* CCS_D only supports full resolves and BLORP will assert on us if we try
709 * to do a partial resolve on a CCS_D surface.
711 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
712 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
713 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
715 anv_image_ccs_op(cmd_buffer
, image
, format
, aspect
, level
,
716 array_layer
, 1, resolve_op
, NULL
, true);
720 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
721 const struct anv_image
*image
,
722 enum isl_format format
,
723 VkImageAspectFlagBits aspect
,
724 uint32_t array_layer
,
725 enum isl_aux_op resolve_op
,
726 enum anv_fast_clear_type fast_clear_supported
)
728 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
729 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
731 #if GEN_GEN >= 8 || GEN_IS_HASWELL
732 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
733 aspect
, 0, array_layer
,
734 resolve_op
, fast_clear_supported
);
736 anv_image_mcs_op(cmd_buffer
, image
, format
, aspect
,
737 array_layer
, 1, resolve_op
, NULL
, true);
739 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
744 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
745 const struct anv_image
*image
,
746 VkImageAspectFlagBits aspect
,
747 enum isl_aux_usage aux_usage
,
750 uint32_t layer_count
)
752 /* The aspect must be exactly one of the image aspects. */
753 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
755 /* The only compression types with more than just fast-clears are MCS,
756 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
757 * track the current fast-clear and compression state. This leaves us
758 * with just MCS and CCS_E.
760 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
761 aux_usage
!= ISL_AUX_USAGE_MCS
)
764 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
765 level
, base_layer
, layer_count
, true);
769 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
770 const struct anv_image
*image
,
771 VkImageAspectFlagBits aspect
)
773 assert(cmd_buffer
&& image
);
774 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
776 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
777 ANV_FAST_CLEAR_NONE
);
779 /* The fast clear value dword(s) will be copied into a surface state object.
780 * Ensure that the restrictions of the fields in the dword(s) are followed.
782 * CCS buffers on SKL+ can have any value set for the clear colors.
784 if (image
->samples
== 1 && GEN_GEN
>= 9)
787 /* Other combinations of auxiliary buffers and platforms require specific
788 * values in the clear value dword(s).
790 struct anv_address addr
=
791 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
794 for (unsigned i
= 0; i
< 4; i
++) {
795 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
797 sdi
.Address
.offset
+= i
* 4;
798 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
799 assert(image
->samples
> 1);
800 sdi
.ImmediateData
= 0;
804 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
806 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
807 /* Pre-SKL, the dword containing the clear values also contains
808 * other fields, so we need to initialize those fields to match the
809 * values that would be in a color attachment.
811 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
812 ISL_CHANNEL_SELECT_GREEN
<< 22 |
813 ISL_CHANNEL_SELECT_BLUE
<< 19 |
814 ISL_CHANNEL_SELECT_ALPHA
<< 16;
815 } else if (GEN_GEN
== 7) {
816 /* On IVB, the dword containing the clear values also contains
817 * other fields that must be zero or can be zero.
819 sdi
.ImmediateData
= 0;
825 /* Copy the fast-clear value dword(s) between a surface state object and an
826 * image's fast clear state buffer.
829 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
830 struct anv_state surface_state
,
831 const struct anv_image
*image
,
832 VkImageAspectFlagBits aspect
,
833 bool copy_from_surface_state
)
835 assert(cmd_buffer
&& image
);
836 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
838 struct anv_address ss_clear_addr
= {
839 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
840 .offset
= surface_state
.offset
+
841 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
843 const struct anv_address entry_addr
=
844 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
845 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
847 if (copy_from_surface_state
) {
848 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, entry_addr
,
849 ss_clear_addr
, copy_size
);
851 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, ss_clear_addr
,
852 entry_addr
, copy_size
);
854 /* Updating a surface state object may require that the state cache be
855 * invalidated. From the SKL PRM, Shared Functions -> State -> State
858 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
859 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
860 * modified [...], the L1 state cache must be invalidated to ensure
861 * the new surface or sampler state is fetched from system memory.
863 * In testing, SKL doesn't actually seem to need this, but HSW does.
865 cmd_buffer
->state
.pending_pipe_bits
|=
866 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
871 * @brief Transitions a color buffer from one layout to another.
873 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
876 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
877 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
878 * this represents the maximum layers to transition at each
879 * specified miplevel.
882 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
883 const struct anv_image
*image
,
884 VkImageAspectFlagBits aspect
,
885 const uint32_t base_level
, uint32_t level_count
,
886 uint32_t base_layer
, uint32_t layer_count
,
887 VkImageLayout initial_layout
,
888 VkImageLayout final_layout
)
890 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
891 /* Validate the inputs. */
893 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
894 /* These values aren't supported for simplicity's sake. */
895 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
896 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
897 /* Ensure the subresource range is valid. */
898 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
899 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
900 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
901 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
902 assert(last_level_num
<= image
->levels
);
903 /* The spec disallows these final layouts. */
904 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
905 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
907 /* No work is necessary if the layout stays the same or if this subresource
908 * range lacks auxiliary data.
910 if (initial_layout
== final_layout
)
913 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
915 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
916 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
917 /* This surface is a linear compressed image with a tiled shadow surface
918 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
919 * we need to ensure the shadow copy is up-to-date.
921 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
922 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
923 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
924 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
926 anv_image_copy_to_shadow(cmd_buffer
, image
,
927 base_level
, level_count
,
928 base_layer
, layer_count
);
931 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
934 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
936 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
937 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
938 /* A subresource in the undefined layout may have been aliased and
939 * populated with any arrangement of bits. Therefore, we must initialize
940 * the related aux buffer and clear buffer entry with desirable values.
941 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
942 * images with VK_IMAGE_TILING_OPTIMAL.
944 * Initialize the relevant clear buffer entries.
946 if (base_level
== 0 && base_layer
== 0)
947 init_fast_clear_color(cmd_buffer
, image
, aspect
);
949 /* Initialize the aux buffers to enable correct rendering. In order to
950 * ensure that things such as storage images work correctly, aux buffers
951 * need to be initialized to valid data.
953 * Having an aux buffer with invalid data is a problem for two reasons:
955 * 1) Having an invalid value in the buffer can confuse the hardware.
956 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
957 * invalid and leads to the hardware doing strange things. It
958 * doesn't hang as far as we can tell but rendering corruption can
961 * 2) If this transition is into the GENERAL layout and we then use the
962 * image as a storage image, then we must have the aux buffer in the
963 * pass-through state so that, if we then go to texture from the
964 * image, we get the results of our storage image writes and not the
965 * fast clear color or other random data.
967 * For CCS both of the problems above are real demonstrable issues. In
968 * that case, the only thing we can do is to perform an ambiguate to
969 * transition the aux surface into the pass-through state.
971 * For MCS, (2) is never an issue because we don't support multisampled
972 * storage images. In theory, issue (1) is a problem with MCS but we've
973 * never seen it in the wild. For 4x and 16x, all bit patters could, in
974 * theory, be interpreted as something but we don't know that all bit
975 * patterns are actually valid. For 2x and 8x, you could easily end up
976 * with the MCS referring to an invalid plane because not all bits of
977 * the MCS value are actually used. Even though we've never seen issues
978 * in the wild, it's best to play it safe and initialize the MCS. We
979 * can use a fast-clear for MCS because we only ever touch from render
980 * and texture (no image load store).
982 if (image
->samples
== 1) {
983 for (uint32_t l
= 0; l
< level_count
; l
++) {
984 const uint32_t level
= base_level
+ l
;
986 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
987 if (base_layer
>= aux_layers
)
988 break; /* We will only get fewer layers as level increases */
989 uint32_t level_layer_count
=
990 MIN2(layer_count
, aux_layers
- base_layer
);
992 anv_image_ccs_op(cmd_buffer
, image
,
993 image
->planes
[plane
].surface
.isl
.format
,
994 aspect
, level
, base_layer
, level_layer_count
,
995 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
997 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
998 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
999 level
, base_layer
, level_layer_count
,
1004 if (image
->samples
== 4 || image
->samples
== 16) {
1005 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1006 "Doing a potentially unnecessary fast-clear to "
1007 "define an MCS buffer.");
1010 assert(base_level
== 0 && level_count
== 1);
1011 anv_image_mcs_op(cmd_buffer
, image
,
1012 image
->planes
[plane
].surface
.isl
.format
,
1013 aspect
, base_layer
, layer_count
,
1014 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1019 const enum isl_aux_usage initial_aux_usage
=
1020 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1021 const enum isl_aux_usage final_aux_usage
=
1022 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1024 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1025 * We can handle transitions between CCS_D/E to and from NONE. What we
1026 * don't yet handle is switching between CCS_E and CCS_D within a given
1027 * image. Doing so in a performant way requires more detailed aux state
1028 * tracking such as what is done in i965. For now, just assume that we
1029 * only have one type of compression.
1031 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1032 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1033 initial_aux_usage
== final_aux_usage
);
1035 /* If initial aux usage is NONE, there is nothing to resolve */
1036 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1039 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1041 /* If the initial layout supports more fast clear than the final layout
1042 * then we need at least a partial resolve.
1044 const enum anv_fast_clear_type initial_fast_clear
=
1045 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1046 const enum anv_fast_clear_type final_fast_clear
=
1047 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1048 if (final_fast_clear
< initial_fast_clear
)
1049 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1051 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1052 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1053 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1055 if (resolve_op
== ISL_AUX_OP_NONE
)
1058 /* Perform a resolve to synchronize data between the main and aux buffer.
1059 * Before we begin, we must satisfy the cache flushing requirement specified
1060 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1062 * Any transition from any value in {Clear, Render, Resolve} to a
1063 * different value in {Clear, Render, Resolve} requires end of pipe
1066 * We perform a flush of the write cache before and after the clear and
1067 * resolve operations to meet this requirement.
1069 * Unlike other drawing, fast clear operations are not properly
1070 * synchronized. The first PIPE_CONTROL here likely ensures that the
1071 * contents of the previous render or clear hit the render target before we
1072 * resolve and the second likely ensures that the resolve is complete before
1073 * we do any more rendering or clearing.
1075 cmd_buffer
->state
.pending_pipe_bits
|=
1076 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1078 for (uint32_t l
= 0; l
< level_count
; l
++) {
1079 uint32_t level
= base_level
+ l
;
1081 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1082 if (base_layer
>= aux_layers
)
1083 break; /* We will only get fewer layers as level increases */
1084 uint32_t level_layer_count
=
1085 MIN2(layer_count
, aux_layers
- base_layer
);
1087 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1088 uint32_t array_layer
= base_layer
+ a
;
1089 if (image
->samples
== 1) {
1090 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1091 image
->planes
[plane
].surface
.isl
.format
,
1092 aspect
, level
, array_layer
, resolve_op
,
1095 /* We only support fast-clear on the first layer so partial
1096 * resolves should not be used on other layers as they will use
1097 * the clear color stored in memory that is only valid for layer0.
1099 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1103 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1104 image
->planes
[plane
].surface
.isl
.format
,
1105 aspect
, array_layer
, resolve_op
,
1111 cmd_buffer
->state
.pending_pipe_bits
|=
1112 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1116 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1119 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1120 struct anv_render_pass
*pass
,
1121 const VkRenderPassBeginInfo
*begin
)
1123 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1124 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1126 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1128 if (pass
->attachment_count
> 0) {
1129 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1130 pass
->attachment_count
*
1131 sizeof(state
->attachments
[0]),
1132 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1133 if (state
->attachments
== NULL
) {
1134 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1135 return anv_batch_set_error(&cmd_buffer
->batch
,
1136 VK_ERROR_OUT_OF_HOST_MEMORY
);
1139 state
->attachments
= NULL
;
1142 /* Reserve one for the NULL state. */
1143 unsigned num_states
= 1;
1144 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1145 if (vk_format_is_color(pass
->attachments
[i
].format
))
1148 if (need_input_attachment_state(&pass
->attachments
[i
]))
1152 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1153 state
->render_pass_states
=
1154 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1155 num_states
* ss_stride
, isl_dev
->ss
.align
);
1157 struct anv_state next_state
= state
->render_pass_states
;
1158 next_state
.alloc_size
= isl_dev
->ss
.size
;
1160 state
->null_surface_state
= next_state
;
1161 next_state
.offset
+= ss_stride
;
1162 next_state
.map
+= ss_stride
;
1164 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1165 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1166 state
->attachments
[i
].color
.state
= next_state
;
1167 next_state
.offset
+= ss_stride
;
1168 next_state
.map
+= ss_stride
;
1171 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1172 state
->attachments
[i
].input
.state
= next_state
;
1173 next_state
.offset
+= ss_stride
;
1174 next_state
.map
+= ss_stride
;
1177 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1178 state
->render_pass_states
.alloc_size
);
1181 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1182 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1184 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1185 isl_extent3d(framebuffer
->width
,
1186 framebuffer
->height
,
1187 framebuffer
->layers
));
1189 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1190 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1191 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1192 VkImageAspectFlags clear_aspects
= 0;
1193 VkImageAspectFlags load_aspects
= 0;
1195 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1196 /* color attachment */
1197 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1198 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1199 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1200 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1203 /* depthstencil attachment */
1204 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1205 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1206 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1207 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1208 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1211 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1212 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1213 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1214 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1215 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1220 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1221 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1222 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1224 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1226 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1227 anv_assert(iview
->vk_format
== att
->format
);
1229 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1230 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1232 union isl_color_value clear_color
= { .u32
= { 0, } };
1233 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1234 anv_assert(iview
->n_planes
== 1);
1235 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1236 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1237 state
, i
, begin
->renderArea
,
1240 anv_image_fill_surface_state(cmd_buffer
->device
,
1242 VK_IMAGE_ASPECT_COLOR_BIT
,
1243 &iview
->planes
[0].isl
,
1244 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1245 state
->attachments
[i
].aux_usage
,
1248 &state
->attachments
[i
].color
,
1251 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1253 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1258 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1259 anv_image_fill_surface_state(cmd_buffer
->device
,
1261 VK_IMAGE_ASPECT_COLOR_BIT
,
1262 &iview
->planes
[0].isl
,
1263 ISL_SURF_USAGE_TEXTURE_BIT
,
1264 state
->attachments
[i
].input_aux_usage
,
1267 &state
->attachments
[i
].input
,
1270 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1279 genX(BeginCommandBuffer
)(
1280 VkCommandBuffer commandBuffer
,
1281 const VkCommandBufferBeginInfo
* pBeginInfo
)
1283 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1285 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1286 * command buffer's state. Otherwise, we must *reset* its state. In both
1287 * cases we reset it.
1289 * From the Vulkan 1.0 spec:
1291 * If a command buffer is in the executable state and the command buffer
1292 * was allocated from a command pool with the
1293 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1294 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1295 * as if vkResetCommandBuffer had been called with
1296 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1297 * the command buffer in the recording state.
1299 anv_cmd_buffer_reset(cmd_buffer
);
1301 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1303 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1304 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1306 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1308 /* We sometimes store vertex data in the dynamic state buffer for blorp
1309 * operations and our dynamic state stream may re-use data from previous
1310 * command buffers. In order to prevent stale cache data, we flush the VF
1311 * cache. We could do this on every blorp call but that's not really
1312 * needed as all of the data will get written by the CPU prior to the GPU
1313 * executing anything. The chances are fairly high that they will use
1314 * blorp at least once per primary command buffer so it shouldn't be
1317 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1318 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1320 /* We send an "Indirect State Pointers Disable" packet at
1321 * EndCommandBuffer, so all push contant packets are ignored during a
1322 * context restore. Documentation says after that command, we need to
1323 * emit push constants again before any rendering operation. So we
1324 * flag them dirty here to make sure they get emitted.
1326 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1328 VkResult result
= VK_SUCCESS
;
1329 if (cmd_buffer
->usage_flags
&
1330 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1331 assert(pBeginInfo
->pInheritanceInfo
);
1332 cmd_buffer
->state
.pass
=
1333 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1334 cmd_buffer
->state
.subpass
=
1335 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1337 /* This is optional in the inheritance info. */
1338 cmd_buffer
->state
.framebuffer
=
1339 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1341 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1342 cmd_buffer
->state
.pass
, NULL
);
1344 /* Record that HiZ is enabled if we can. */
1345 if (cmd_buffer
->state
.framebuffer
) {
1346 const struct anv_image_view
* const iview
=
1347 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1350 VkImageLayout layout
=
1351 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1353 enum isl_aux_usage aux_usage
=
1354 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1355 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1357 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1361 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1364 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1365 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1366 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1367 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1369 /* If secondary buffer supports conditional rendering
1370 * we should emit commands as if conditional rendering is enabled.
1372 cmd_buffer
->state
.conditional_render_enabled
=
1373 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1380 /* From the PRM, Volume 2a:
1382 * "Indirect State Pointers Disable
1384 * At the completion of the post-sync operation associated with this pipe
1385 * control packet, the indirect state pointers in the hardware are
1386 * considered invalid; the indirect pointers are not saved in the context.
1387 * If any new indirect state commands are executed in the command stream
1388 * while the pipe control is pending, the new indirect state commands are
1391 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1392 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1393 * commands are only considered as Indirect State Pointers. Once ISP is
1394 * issued in a context, SW must initialize by programming push constant
1395 * commands for all the shaders (at least to zero length) before attempting
1396 * any rendering operation for the same context."
1398 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1399 * even though they point to a BO that has been already unreferenced at
1400 * the end of the previous batch buffer. This has been fine so far since
1401 * we are protected by these scratch page (every address not covered by
1402 * a BO should be pointing to the scratch page). But on CNL, it is
1403 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1406 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1407 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1408 * context restore, so the mentioned hang doesn't happen. However,
1409 * software must program push constant commands for all stages prior to
1410 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1412 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1413 * constants have been loaded into the EUs prior to disable the push constants
1414 * so that it doesn't hang a previous 3DPRIMITIVE.
1417 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1419 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1420 pc
.StallAtPixelScoreboard
= true;
1421 pc
.CommandStreamerStallEnable
= true;
1423 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1424 pc
.IndirectStatePointersDisable
= true;
1425 pc
.CommandStreamerStallEnable
= true;
1430 genX(EndCommandBuffer
)(
1431 VkCommandBuffer commandBuffer
)
1433 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1435 if (anv_batch_has_error(&cmd_buffer
->batch
))
1436 return cmd_buffer
->batch
.status
;
1438 /* We want every command buffer to start with the PMA fix in a known state,
1439 * so we disable it at the end of the command buffer.
1441 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1443 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1445 emit_isp_disable(cmd_buffer
);
1447 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1453 genX(CmdExecuteCommands
)(
1454 VkCommandBuffer commandBuffer
,
1455 uint32_t commandBufferCount
,
1456 const VkCommandBuffer
* pCmdBuffers
)
1458 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1460 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1462 if (anv_batch_has_error(&primary
->batch
))
1465 /* The secondary command buffers will assume that the PMA fix is disabled
1466 * when they begin executing. Make sure this is true.
1468 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1470 /* The secondary command buffer doesn't know which textures etc. have been
1471 * flushed prior to their execution. Apply those flushes now.
1473 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1475 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1476 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1478 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1479 assert(!anv_batch_has_error(&secondary
->batch
));
1481 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1482 if (secondary
->state
.conditional_render_enabled
) {
1483 if (!primary
->state
.conditional_render_enabled
) {
1484 /* Secondary buffer is constructed as if it will be executed
1485 * with conditional rendering, we should satisfy this dependency
1486 * regardless of conditional rendering being enabled in primary.
1488 emit_lri(&primary
->batch
, CS_GPR(ANV_PREDICATE_RESULT_REG
), UINT32_MAX
);
1489 emit_lri(&primary
->batch
, CS_GPR(ANV_PREDICATE_RESULT_REG
) + 4, UINT32_MAX
);
1494 if (secondary
->usage_flags
&
1495 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1496 /* If we're continuing a render pass from the primary, we need to
1497 * copy the surface states for the current subpass into the storage
1498 * we allocated for them in BeginCommandBuffer.
1500 struct anv_bo
*ss_bo
=
1501 primary
->device
->surface_state_pool
.block_pool
.bo
;
1502 struct anv_state src_state
= primary
->state
.render_pass_states
;
1503 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1504 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1506 genX(cmd_buffer_so_memcpy
)(primary
,
1507 (struct anv_address
) {
1509 .offset
= dst_state
.offset
,
1511 (struct anv_address
) {
1513 .offset
= src_state
.offset
,
1515 src_state
.alloc_size
);
1518 anv_cmd_buffer_add_secondary(primary
, secondary
);
1521 /* The secondary may have selected a different pipeline (3D or compute) and
1522 * may have changed the current L3$ configuration. Reset our tracking
1523 * variables to invalid values to ensure that we re-emit these in the case
1524 * where we do any draws or compute dispatches from the primary after the
1525 * secondary has returned.
1527 primary
->state
.current_pipeline
= UINT32_MAX
;
1528 primary
->state
.current_l3_config
= NULL
;
1530 /* Each of the secondary command buffers will use its own state base
1531 * address. We need to re-emit state base address for the primary after
1532 * all of the secondaries are done.
1534 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1537 genX(cmd_buffer_emit_state_base_address
)(primary
);
1540 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1541 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1542 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1545 * Program the hardware to use the specified L3 configuration.
1548 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1549 const struct gen_l3_config
*cfg
)
1552 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1555 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1556 intel_logd("L3 config transition: ");
1557 gen_dump_l3_config(cfg
, stderr
);
1560 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1562 /* According to the hardware docs, the L3 partitioning can only be changed
1563 * while the pipeline is completely drained and the caches are flushed,
1564 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1566 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1567 pc
.DCFlushEnable
= true;
1568 pc
.PostSyncOperation
= NoWrite
;
1569 pc
.CommandStreamerStallEnable
= true;
1572 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1573 * invalidation of the relevant caches. Note that because RO invalidation
1574 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1575 * command is processed by the CS) we cannot combine it with the previous
1576 * stalling flush as the hardware documentation suggests, because that
1577 * would cause the CS to stall on previous rendering *after* RO
1578 * invalidation and wouldn't prevent the RO caches from being polluted by
1579 * concurrent rendering before the stall completes. This intentionally
1580 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1581 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1582 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1583 * already guarantee that there is no concurrent GPGPU kernel execution
1584 * (see SKL HSD 2132585).
1586 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1587 pc
.TextureCacheInvalidationEnable
= true;
1588 pc
.ConstantCacheInvalidationEnable
= true;
1589 pc
.InstructionCacheInvalidateEnable
= true;
1590 pc
.StateCacheInvalidationEnable
= true;
1591 pc
.PostSyncOperation
= NoWrite
;
1594 /* Now send a third stalling flush to make sure that invalidation is
1595 * complete when the L3 configuration registers are modified.
1597 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1598 pc
.DCFlushEnable
= true;
1599 pc
.PostSyncOperation
= NoWrite
;
1600 pc
.CommandStreamerStallEnable
= true;
1605 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1608 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1609 .SLMEnable
= has_slm
,
1611 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1612 * in L3CNTLREG register. The default setting of the bit is not the
1613 * desirable behavior.
1615 .ErrorDetectionBehaviorControl
= true,
1616 .UseFullWays
= true,
1618 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1619 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1620 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1621 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1623 /* Set up the L3 partitioning. */
1624 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1628 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1629 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1630 cfg
->n
[GEN_L3P_ALL
];
1631 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1632 cfg
->n
[GEN_L3P_ALL
];
1633 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1634 cfg
->n
[GEN_L3P_ALL
];
1636 assert(!cfg
->n
[GEN_L3P_ALL
]);
1638 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1639 * the matching space on the remaining banks has to be allocated to a
1640 * client (URB for all validated configurations) set to the
1641 * lower-bandwidth 2-bank address hashing mode.
1643 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1644 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1645 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1647 /* Minimum number of ways that can be allocated to the URB. */
1648 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1649 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1651 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1652 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1653 .ConvertDC_UC
= !has_dc
,
1654 .ConvertIS_UC
= !has_is
,
1655 .ConvertC_UC
= !has_c
,
1656 .ConvertT_UC
= !has_t
);
1658 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1659 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1660 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1662 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1663 .SLMEnable
= has_slm
,
1664 .URBLowBandwidth
= urb_low_bw
,
1665 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1667 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1669 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1670 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1672 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1673 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1674 .ISLowBandwidth
= 0,
1675 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1677 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1678 .TLowBandwidth
= 0);
1680 /* Set up the L3 partitioning. */
1681 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1682 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1683 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1686 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1687 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1688 * them disabled to avoid crashing the system hard.
1690 uint32_t scratch1
, chicken3
;
1691 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1692 .L3AtomicDisable
= !has_dc
);
1693 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1694 .L3AtomicDisableMask
= true,
1695 .L3AtomicDisable
= !has_dc
);
1696 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1697 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1703 cmd_buffer
->state
.current_l3_config
= cfg
;
1707 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1709 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1711 /* Flushes are pipelined while invalidations are handled immediately.
1712 * Therefore, if we're flushing anything then we need to schedule a stall
1713 * before any invalidations can happen.
1715 if (bits
& ANV_PIPE_FLUSH_BITS
)
1716 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1718 /* If we're going to do an invalidate and we have a pending CS stall that
1719 * has yet to be resolved, we do the CS stall now.
1721 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1722 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1723 bits
|= ANV_PIPE_CS_STALL_BIT
;
1724 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1727 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1728 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1729 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1730 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1731 pipe
.RenderTargetCacheFlushEnable
=
1732 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1734 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1735 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1736 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1739 * According to the Broadwell documentation, any PIPE_CONTROL with the
1740 * "Command Streamer Stall" bit set must also have another bit set,
1741 * with five different options:
1743 * - Render Target Cache Flush
1744 * - Depth Cache Flush
1745 * - Stall at Pixel Scoreboard
1746 * - Post-Sync Operation
1750 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1751 * mesa and it seems to work fine. The choice is fairly arbitrary.
1753 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1754 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1755 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1756 pipe
.StallAtPixelScoreboard
= true;
1759 /* If a render target flush was emitted, then we can toggle off the bit
1760 * saying that render target writes are ongoing.
1762 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
1763 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
1765 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1768 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1769 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1771 * "If the VF Cache Invalidation Enable is set to a 1 in a
1772 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1773 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1774 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1777 * This appears to hang Broadwell, so we restrict it to just gen9.
1779 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1780 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1782 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1783 pipe
.StateCacheInvalidationEnable
=
1784 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1785 pipe
.ConstantCacheInvalidationEnable
=
1786 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1787 pipe
.VFCacheInvalidationEnable
=
1788 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1789 pipe
.TextureCacheInvalidationEnable
=
1790 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1791 pipe
.InstructionCacheInvalidateEnable
=
1792 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1794 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1796 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1797 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1798 * “Write Timestamp”.
1800 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1801 pipe
.PostSyncOperation
= WriteImmediateData
;
1803 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1807 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1810 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1813 void genX(CmdPipelineBarrier
)(
1814 VkCommandBuffer commandBuffer
,
1815 VkPipelineStageFlags srcStageMask
,
1816 VkPipelineStageFlags destStageMask
,
1818 uint32_t memoryBarrierCount
,
1819 const VkMemoryBarrier
* pMemoryBarriers
,
1820 uint32_t bufferMemoryBarrierCount
,
1821 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1822 uint32_t imageMemoryBarrierCount
,
1823 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1825 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1827 /* XXX: Right now, we're really dumb and just flush whatever categories
1828 * the app asks for. One of these days we may make this a bit better
1829 * but right now that's all the hardware allows for in most areas.
1831 VkAccessFlags src_flags
= 0;
1832 VkAccessFlags dst_flags
= 0;
1834 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1835 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1836 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1839 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1840 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1841 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1844 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1845 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1846 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1847 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1848 const VkImageSubresourceRange
*range
=
1849 &pImageMemoryBarriers
[i
].subresourceRange
;
1851 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1852 transition_depth_buffer(cmd_buffer
, image
,
1853 pImageMemoryBarriers
[i
].oldLayout
,
1854 pImageMemoryBarriers
[i
].newLayout
);
1855 } else if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1856 VkImageAspectFlags color_aspects
=
1857 anv_image_expand_aspects(image
, range
->aspectMask
);
1858 uint32_t aspect_bit
;
1860 uint32_t base_layer
, layer_count
;
1861 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1863 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1865 base_layer
= range
->baseArrayLayer
;
1866 layer_count
= anv_get_layerCount(image
, range
);
1869 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1870 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1871 range
->baseMipLevel
,
1872 anv_get_levelCount(image
, range
),
1873 base_layer
, layer_count
,
1874 pImageMemoryBarriers
[i
].oldLayout
,
1875 pImageMemoryBarriers
[i
].newLayout
);
1880 cmd_buffer
->state
.pending_pipe_bits
|=
1881 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1882 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1886 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1888 VkShaderStageFlags stages
=
1889 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1891 /* In order to avoid thrash, we assume that vertex and fragment stages
1892 * always exist. In the rare case where one is missing *and* the other
1893 * uses push concstants, this may be suboptimal. However, avoiding stalls
1894 * seems more important.
1896 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1898 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1902 const unsigned push_constant_kb
= 32;
1903 #elif GEN_IS_HASWELL
1904 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1906 const unsigned push_constant_kb
= 16;
1909 const unsigned num_stages
=
1910 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1911 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1913 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1914 * units of 2KB. Incidentally, these are the same platforms that have
1915 * 32KB worth of push constant space.
1917 if (push_constant_kb
== 32)
1918 size_per_stage
&= ~1u;
1920 uint32_t kb_used
= 0;
1921 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1922 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1923 anv_batch_emit(&cmd_buffer
->batch
,
1924 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1925 alloc
._3DCommandSubOpcode
= 18 + i
;
1926 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1927 alloc
.ConstantBufferSize
= push_size
;
1929 kb_used
+= push_size
;
1932 anv_batch_emit(&cmd_buffer
->batch
,
1933 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1934 alloc
.ConstantBufferOffset
= kb_used
;
1935 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1938 cmd_buffer
->state
.push_constant_stages
= stages
;
1940 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1942 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1943 * the next 3DPRIMITIVE command after programming the
1944 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1946 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1947 * pipeline setup, we need to dirty push constants.
1949 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1952 static const struct anv_descriptor
*
1953 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1954 const struct anv_pipeline_binding
*binding
)
1956 assert(binding
->set
< MAX_SETS
);
1957 const struct anv_descriptor_set
*set
=
1958 pipe_state
->descriptors
[binding
->set
];
1959 const uint32_t offset
=
1960 set
->layout
->binding
[binding
->binding
].descriptor_index
;
1961 return &set
->descriptors
[offset
+ binding
->index
];
1965 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1966 const struct anv_pipeline_binding
*binding
)
1968 assert(binding
->set
< MAX_SETS
);
1969 const struct anv_descriptor_set
*set
=
1970 pipe_state
->descriptors
[binding
->set
];
1972 uint32_t dynamic_offset_idx
=
1973 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
1974 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1977 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
1980 static struct anv_address
1981 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
1982 struct anv_descriptor_set
*set
)
1985 /* This is a normal descriptor set */
1986 return (struct anv_address
) {
1987 .bo
= &set
->pool
->bo
,
1988 .offset
= set
->desc_mem
.offset
,
1991 /* This is a push descriptor set. We have to flag it as used on the GPU
1992 * so that the next time we push descriptors, we grab a new memory.
1994 struct anv_push_descriptor_set
*push_set
=
1995 (struct anv_push_descriptor_set
*)set
;
1996 push_set
->set_used_on_gpu
= true;
1998 return (struct anv_address
) {
1999 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2000 .offset
= set
->desc_mem
.offset
,
2006 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2007 gl_shader_stage stage
,
2008 struct anv_state
*bt_state
)
2010 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
2011 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2012 struct anv_cmd_pipeline_state
*pipe_state
;
2013 struct anv_pipeline
*pipeline
;
2014 uint32_t state_offset
;
2017 case MESA_SHADER_COMPUTE
:
2018 pipe_state
= &cmd_buffer
->state
.compute
.base
;
2021 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
2024 pipeline
= pipe_state
->pipeline
;
2026 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2027 *bt_state
= (struct anv_state
) { 0, };
2031 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2032 if (map
->surface_count
== 0) {
2033 *bt_state
= (struct anv_state
) { 0, };
2037 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2040 uint32_t *bt_map
= bt_state
->map
;
2042 if (bt_state
->map
== NULL
)
2043 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2045 /* We only use push constant space for images before gen9 */
2046 if (map
->image_param_count
> 0) {
2048 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
2049 if (result
!= VK_SUCCESS
)
2052 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
2056 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2057 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2059 struct anv_state surface_state
;
2061 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2062 /* Color attachment binding */
2063 assert(stage
== MESA_SHADER_FRAGMENT
);
2064 assert(binding
->binding
== 0);
2065 if (binding
->index
< subpass
->color_count
) {
2066 const unsigned att
=
2067 subpass
->color_attachments
[binding
->index
].attachment
;
2069 /* From the Vulkan 1.0.46 spec:
2071 * "If any color or depth/stencil attachments are
2072 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2075 if (att
== VK_ATTACHMENT_UNUSED
) {
2076 surface_state
= cmd_buffer
->state
.null_surface_state
;
2078 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2081 surface_state
= cmd_buffer
->state
.null_surface_state
;
2084 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2086 } else if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2087 struct anv_state surface_state
=
2088 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2090 struct anv_address constant_data
= {
2091 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2092 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2094 unsigned constant_data_size
=
2095 pipeline
->shaders
[stage
]->constant_data_size
;
2097 const enum isl_format format
=
2098 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2099 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2100 surface_state
, format
,
2101 constant_data
, constant_data_size
, 1);
2103 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2104 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2106 } else if (binding
->set
== ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
) {
2107 /* This is always the first binding for compute shaders */
2108 assert(stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2109 if (!get_cs_prog_data(pipeline
)->uses_num_work_groups
)
2112 struct anv_state surface_state
=
2113 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2115 const enum isl_format format
=
2116 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2117 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2119 cmd_buffer
->state
.compute
.num_workgroups
,
2121 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2122 add_surface_reloc(cmd_buffer
, surface_state
,
2123 cmd_buffer
->state
.compute
.num_workgroups
);
2125 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2126 /* This is a descriptor set buffer so the set index is actually
2127 * given by binding->binding. (Yes, that's confusing.)
2129 struct anv_descriptor_set
*set
=
2130 pipe_state
->descriptors
[binding
->binding
];
2131 assert(set
->desc_mem
.alloc_size
);
2132 assert(set
->desc_surface_state
.alloc_size
);
2133 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2134 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2135 anv_descriptor_set_address(cmd_buffer
, set
));
2139 const struct anv_descriptor
*desc
=
2140 anv_descriptor_for_binding(pipe_state
, binding
);
2142 switch (desc
->type
) {
2143 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2144 /* Nothing for us to do here */
2147 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2148 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2149 struct anv_surface_state sstate
=
2150 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2151 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2152 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2153 surface_state
= sstate
.state
;
2154 assert(surface_state
.alloc_size
);
2155 add_surface_state_relocs(cmd_buffer
, sstate
);
2158 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2159 assert(stage
== MESA_SHADER_FRAGMENT
);
2160 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2161 /* For depth and stencil input attachments, we treat it like any
2162 * old texture that a user may have bound.
2164 struct anv_surface_state sstate
=
2165 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2166 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2167 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2168 surface_state
= sstate
.state
;
2169 assert(surface_state
.alloc_size
);
2170 add_surface_state_relocs(cmd_buffer
, sstate
);
2172 /* For color input attachments, we create the surface state at
2173 * vkBeginRenderPass time so that we can include aux and clear
2174 * color information.
2176 assert(binding
->input_attachment_index
< subpass
->input_count
);
2177 const unsigned subpass_att
= binding
->input_attachment_index
;
2178 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2179 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2183 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2184 struct anv_surface_state sstate
= (binding
->write_only
)
2185 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2186 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2187 surface_state
= sstate
.state
;
2188 assert(surface_state
.alloc_size
);
2189 add_surface_state_relocs(cmd_buffer
, sstate
);
2190 if (devinfo
->gen
< 9) {
2191 /* We only need the image params on gen8 and earlier. No image
2192 * workarounds that require tiling information are required on
2195 assert(image
< MAX_GEN8_IMAGES
);
2196 struct brw_image_param
*image_param
=
2197 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2200 desc
->image_view
->planes
[binding
->plane
].storage_image_param
;
2205 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2206 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2207 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2208 surface_state
= desc
->buffer_view
->surface_state
;
2209 assert(surface_state
.alloc_size
);
2210 add_surface_reloc(cmd_buffer
, surface_state
,
2211 desc
->buffer_view
->address
);
2214 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2215 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2216 /* Compute the offset within the buffer */
2217 uint32_t dynamic_offset
=
2218 dynamic_offset_for_binding(pipe_state
, binding
);
2219 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2220 /* Clamp to the buffer size */
2221 offset
= MIN2(offset
, desc
->buffer
->size
);
2222 /* Clamp the range to the buffer size */
2223 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2225 struct anv_address address
=
2226 anv_address_add(desc
->buffer
->address
, offset
);
2229 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2230 enum isl_format format
=
2231 anv_isl_format_for_descriptor_type(desc
->type
);
2233 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2234 format
, address
, range
, 1);
2235 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2239 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2240 surface_state
= (binding
->write_only
)
2241 ? desc
->buffer_view
->writeonly_storage_surface_state
2242 : desc
->buffer_view
->storage_surface_state
;
2243 assert(surface_state
.alloc_size
);
2244 add_surface_reloc(cmd_buffer
, surface_state
,
2245 desc
->buffer_view
->address
);
2246 if (devinfo
->gen
< 9) {
2247 assert(image
< MAX_GEN8_IMAGES
);
2248 struct brw_image_param
*image_param
=
2249 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2251 *image_param
= desc
->buffer_view
->storage_image_param
;
2256 assert(!"Invalid descriptor type");
2260 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2262 assert(image
== map
->image_param_count
);
2265 /* The PIPE_CONTROL command description says:
2267 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2268 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2269 * Target Cache Flush by enabling this bit. When render target flush
2270 * is set due to new association of BTI, PS Scoreboard Stall bit must
2271 * be set in this packet."
2273 * FINISHME: Currently we shuffle around the surface states in the binding
2274 * table based on if they are getting used or not. So, we've to do below
2275 * pipe control flush for every binding table upload. Make changes so
2276 * that we do it only when we modify render target surface states.
2278 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2279 pc
.RenderTargetCacheFlushEnable
= true;
2280 pc
.StallAtPixelScoreboard
= true;
2288 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2289 gl_shader_stage stage
,
2290 struct anv_state
*state
)
2292 struct anv_cmd_pipeline_state
*pipe_state
=
2293 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2294 &cmd_buffer
->state
.gfx
.base
;
2295 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2297 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2298 *state
= (struct anv_state
) { 0, };
2302 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2303 if (map
->sampler_count
== 0) {
2304 *state
= (struct anv_state
) { 0, };
2308 uint32_t size
= map
->sampler_count
* 16;
2309 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2311 if (state
->map
== NULL
)
2312 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2314 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2315 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2316 const struct anv_descriptor
*desc
=
2317 anv_descriptor_for_binding(pipe_state
, binding
);
2319 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2320 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2323 struct anv_sampler
*sampler
= desc
->sampler
;
2325 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2326 * happens to be zero.
2328 if (sampler
== NULL
)
2331 memcpy(state
->map
+ (s
* 16),
2332 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2339 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2341 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2343 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2344 pipeline
->active_stages
;
2346 VkResult result
= VK_SUCCESS
;
2347 anv_foreach_stage(s
, dirty
) {
2348 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2349 if (result
!= VK_SUCCESS
)
2351 result
= emit_binding_table(cmd_buffer
, s
,
2352 &cmd_buffer
->state
.binding_tables
[s
]);
2353 if (result
!= VK_SUCCESS
)
2357 if (result
!= VK_SUCCESS
) {
2358 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2360 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2361 if (result
!= VK_SUCCESS
)
2364 /* Re-emit state base addresses so we get the new surface state base
2365 * address before we start emitting binding tables etc.
2367 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2369 /* Re-emit all active binding tables */
2370 dirty
|= pipeline
->active_stages
;
2371 anv_foreach_stage(s
, dirty
) {
2372 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2373 if (result
!= VK_SUCCESS
) {
2374 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2377 result
= emit_binding_table(cmd_buffer
, s
,
2378 &cmd_buffer
->state
.binding_tables
[s
]);
2379 if (result
!= VK_SUCCESS
) {
2380 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2386 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2392 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2395 static const uint32_t sampler_state_opcodes
[] = {
2396 [MESA_SHADER_VERTEX
] = 43,
2397 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2398 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2399 [MESA_SHADER_GEOMETRY
] = 46,
2400 [MESA_SHADER_FRAGMENT
] = 47,
2401 [MESA_SHADER_COMPUTE
] = 0,
2404 static const uint32_t binding_table_opcodes
[] = {
2405 [MESA_SHADER_VERTEX
] = 38,
2406 [MESA_SHADER_TESS_CTRL
] = 39,
2407 [MESA_SHADER_TESS_EVAL
] = 40,
2408 [MESA_SHADER_GEOMETRY
] = 41,
2409 [MESA_SHADER_FRAGMENT
] = 42,
2410 [MESA_SHADER_COMPUTE
] = 0,
2413 anv_foreach_stage(s
, stages
) {
2414 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2415 assert(binding_table_opcodes
[s
] > 0);
2417 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2418 anv_batch_emit(&cmd_buffer
->batch
,
2419 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2420 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2421 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2425 /* Always emit binding table pointers if we're asked to, since on SKL
2426 * this is what flushes push constants. */
2427 anv_batch_emit(&cmd_buffer
->batch
,
2428 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2429 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2430 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2436 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2437 VkShaderStageFlags dirty_stages
)
2439 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2440 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2442 static const uint32_t push_constant_opcodes
[] = {
2443 [MESA_SHADER_VERTEX
] = 21,
2444 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2445 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2446 [MESA_SHADER_GEOMETRY
] = 22,
2447 [MESA_SHADER_FRAGMENT
] = 23,
2448 [MESA_SHADER_COMPUTE
] = 0,
2451 VkShaderStageFlags flushed
= 0;
2453 anv_foreach_stage(stage
, dirty_stages
) {
2454 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2455 assert(push_constant_opcodes
[stage
] > 0);
2457 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2458 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2460 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2461 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2462 const struct brw_stage_prog_data
*prog_data
=
2463 pipeline
->shaders
[stage
]->prog_data
;
2464 const struct anv_pipeline_bind_map
*bind_map
=
2465 &pipeline
->shaders
[stage
]->bind_map
;
2467 /* The Skylake PRM contains the following restriction:
2469 * "The driver must ensure The following case does not occur
2470 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2471 * buffer 3 read length equal to zero committed followed by a
2472 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2475 * To avoid this, we program the buffers in the highest slots.
2476 * This way, slot 0 is only used if slot 3 is also used.
2480 for (int i
= 3; i
>= 0; i
--) {
2481 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2482 if (range
->length
== 0)
2485 const unsigned surface
=
2486 prog_data
->binding_table
.ubo_start
+ range
->block
;
2488 assert(surface
<= bind_map
->surface_count
);
2489 const struct anv_pipeline_binding
*binding
=
2490 &bind_map
->surface_to_descriptor
[surface
];
2492 struct anv_address read_addr
;
2494 if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2495 struct anv_address constant_data
= {
2496 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2497 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2499 unsigned constant_data_size
=
2500 pipeline
->shaders
[stage
]->constant_data_size
;
2502 read_len
= MIN2(range
->length
,
2503 DIV_ROUND_UP(constant_data_size
, 32) - range
->start
);
2504 read_addr
= anv_address_add(constant_data
,
2506 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2507 /* This is a descriptor set buffer so the set index is
2508 * actually given by binding->binding. (Yes, that's
2511 struct anv_descriptor_set
*set
=
2512 gfx_state
->base
.descriptors
[binding
->binding
];
2513 struct anv_address desc_buffer_addr
=
2514 anv_descriptor_set_address(cmd_buffer
, set
);
2515 const unsigned desc_buffer_size
= set
->desc_mem
.alloc_size
;
2517 read_len
= MIN2(range
->length
,
2518 DIV_ROUND_UP(desc_buffer_size
, 32) - range
->start
);
2519 read_addr
= anv_address_add(desc_buffer_addr
,
2522 const struct anv_descriptor
*desc
=
2523 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2525 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2526 read_len
= MIN2(range
->length
,
2527 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2528 read_addr
= anv_address_add(desc
->buffer_view
->address
,
2531 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2533 uint32_t dynamic_offset
=
2534 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2535 uint32_t buf_offset
=
2536 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2537 uint32_t buf_range
=
2538 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2540 read_len
= MIN2(range
->length
,
2541 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2542 read_addr
= anv_address_add(desc
->buffer
->address
,
2543 buf_offset
+ range
->start
* 32);
2548 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2549 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2554 struct anv_state state
=
2555 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2557 if (state
.alloc_size
> 0) {
2558 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2559 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2560 .offset
= state
.offset
,
2562 c
.ConstantBody
.ReadLength
[n
] =
2563 DIV_ROUND_UP(state
.alloc_size
, 32);
2566 /* For Ivy Bridge, the push constants packets have a different
2567 * rule that would require us to iterate in the other direction
2568 * and possibly mess around with dynamic state base address.
2569 * Don't bother; just emit regular push constants at n = 0.
2571 struct anv_state state
=
2572 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2574 if (state
.alloc_size
> 0) {
2575 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2576 c
.ConstantBody
.ReadLength
[0] =
2577 DIV_ROUND_UP(state
.alloc_size
, 32);
2583 flushed
|= mesa_to_vk_shader_stage(stage
);
2586 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2590 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2592 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2595 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2596 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2597 vb_emit
|= pipeline
->vb_used
;
2599 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2601 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2603 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2606 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2607 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2609 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2610 GENX(3DSTATE_VERTEX_BUFFERS
));
2612 for_each_bit(vb
, vb_emit
) {
2613 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2614 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2616 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2617 .VertexBufferIndex
= vb
,
2619 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
2621 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2622 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2625 .AddressModifyEnable
= true,
2626 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2627 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2630 .BufferSize
= buffer
->size
- offset
2632 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2636 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2641 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2644 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
2645 /* We don't need any per-buffer dirty tracking because you're not
2646 * allowed to bind different XFB buffers while XFB is enabled.
2648 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
2649 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
2650 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
2651 sob
.SOBufferIndex
= idx
;
2653 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
2654 sob
.SOBufferEnable
= true;
2655 sob
.MOCS
= cmd_buffer
->device
->default_mocs
,
2656 sob
.StreamOffsetWriteEnable
= false;
2657 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
2659 /* Size is in DWords - 1 */
2660 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
2665 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
2667 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2671 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2672 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2674 /* The exact descriptor layout is pulled from the pipeline, so we need
2675 * to re-emit binding tables on every pipeline change.
2677 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2679 /* If the pipeline changed, we may need to re-allocate push constant
2682 cmd_buffer_alloc_push_constants(cmd_buffer
);
2686 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2687 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2688 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2690 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2691 * stall needs to be sent just prior to any 3DSTATE_VS,
2692 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2693 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2694 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2695 * PIPE_CONTROL needs to be sent before any combination of VS
2696 * associated 3DSTATE."
2698 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2699 pc
.DepthStallEnable
= true;
2700 pc
.PostSyncOperation
= WriteImmediateData
;
2702 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2707 /* Render targets live in the same binding table as fragment descriptors */
2708 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2709 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2711 /* We emit the binding tables and sampler tables first, then emit push
2712 * constants and then finally emit binding table and sampler table
2713 * pointers. It has to happen in this order, since emitting the binding
2714 * tables may change the push constants (in case of storage images). After
2715 * emitting push constants, on SKL+ we have to emit the corresponding
2716 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2719 if (cmd_buffer
->state
.descriptors_dirty
)
2720 dirty
= flush_descriptor_sets(cmd_buffer
);
2722 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2723 /* Because we're pushing UBOs, we have to push whenever either
2724 * descriptors or push constants is dirty.
2726 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2727 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2728 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2732 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2734 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2735 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2737 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2738 ANV_CMD_DIRTY_PIPELINE
)) {
2739 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2740 pipeline
->depth_clamp_enable
);
2743 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2744 ANV_CMD_DIRTY_RENDER_TARGETS
))
2745 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2747 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2749 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2753 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2754 struct anv_address addr
,
2755 uint32_t size
, uint32_t index
)
2757 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2758 GENX(3DSTATE_VERTEX_BUFFERS
));
2760 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2761 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2762 .VertexBufferIndex
= index
,
2763 .AddressModifyEnable
= true,
2765 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
),
2767 .BufferStartingAddress
= addr
,
2770 .BufferStartingAddress
= addr
,
2771 .EndAddress
= anv_address_add(addr
, size
),
2777 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2778 struct anv_address addr
)
2780 emit_vertex_bo(cmd_buffer
, addr
, 8, ANV_SVGS_VB_INDEX
);
2784 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2785 uint32_t base_vertex
, uint32_t base_instance
)
2787 struct anv_state id_state
=
2788 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2790 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2791 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2793 struct anv_address addr
= {
2794 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2795 .offset
= id_state
.offset
,
2798 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2802 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2804 struct anv_state state
=
2805 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2807 ((uint32_t *)state
.map
)[0] = draw_index
;
2809 struct anv_address addr
= {
2810 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2811 .offset
= state
.offset
,
2814 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2818 VkCommandBuffer commandBuffer
,
2819 uint32_t vertexCount
,
2820 uint32_t instanceCount
,
2821 uint32_t firstVertex
,
2822 uint32_t firstInstance
)
2824 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2825 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2826 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2828 if (anv_batch_has_error(&cmd_buffer
->batch
))
2831 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2833 if (cmd_buffer
->state
.conditional_render_enabled
)
2834 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2836 if (vs_prog_data
->uses_firstvertex
||
2837 vs_prog_data
->uses_baseinstance
)
2838 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2839 if (vs_prog_data
->uses_drawid
)
2840 emit_draw_index(cmd_buffer
, 0);
2842 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2843 * different views. We need to multiply instanceCount by the view count.
2845 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2847 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2848 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2849 prim
.VertexAccessType
= SEQUENTIAL
;
2850 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2851 prim
.VertexCountPerInstance
= vertexCount
;
2852 prim
.StartVertexLocation
= firstVertex
;
2853 prim
.InstanceCount
= instanceCount
;
2854 prim
.StartInstanceLocation
= firstInstance
;
2855 prim
.BaseVertexLocation
= 0;
2859 void genX(CmdDrawIndexed
)(
2860 VkCommandBuffer commandBuffer
,
2861 uint32_t indexCount
,
2862 uint32_t instanceCount
,
2863 uint32_t firstIndex
,
2864 int32_t vertexOffset
,
2865 uint32_t firstInstance
)
2867 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2868 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2869 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2871 if (anv_batch_has_error(&cmd_buffer
->batch
))
2874 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2876 if (cmd_buffer
->state
.conditional_render_enabled
)
2877 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2879 if (vs_prog_data
->uses_firstvertex
||
2880 vs_prog_data
->uses_baseinstance
)
2881 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2882 if (vs_prog_data
->uses_drawid
)
2883 emit_draw_index(cmd_buffer
, 0);
2885 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2886 * different views. We need to multiply instanceCount by the view count.
2888 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2890 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2891 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2892 prim
.VertexAccessType
= RANDOM
;
2893 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2894 prim
.VertexCountPerInstance
= indexCount
;
2895 prim
.StartVertexLocation
= firstIndex
;
2896 prim
.InstanceCount
= instanceCount
;
2897 prim
.StartInstanceLocation
= firstInstance
;
2898 prim
.BaseVertexLocation
= vertexOffset
;
2902 /* Auto-Draw / Indirect Registers */
2903 #define GEN7_3DPRIM_END_OFFSET 0x2420
2904 #define GEN7_3DPRIM_START_VERTEX 0x2430
2905 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2906 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2907 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2908 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2910 /* MI_MATH only exists on Haswell+ */
2911 #if GEN_IS_HASWELL || GEN_GEN >= 8
2913 /* Emit dwords to multiply GPR0 by N */
2915 build_alu_multiply_gpr0(uint32_t *dw
, unsigned *dw_count
, uint32_t N
)
2917 VK_OUTARRAY_MAKE(out
, dw
, dw_count
);
2919 #define append_alu(opcode, operand1, operand2) \
2920 vk_outarray_append(&out, alu_dw) *alu_dw = mi_alu(opcode, operand1, operand2)
2923 unsigned top_bit
= 31 - __builtin_clz(N
);
2924 for (int i
= top_bit
- 1; i
>= 0; i
--) {
2925 /* We get our initial data in GPR0 and we write the final data out to
2926 * GPR0 but we use GPR1 as our scratch register.
2928 unsigned src_reg
= i
== top_bit
- 1 ? MI_ALU_REG0
: MI_ALU_REG1
;
2929 unsigned dst_reg
= i
== 0 ? MI_ALU_REG0
: MI_ALU_REG1
;
2931 /* Shift the current value left by 1 */
2932 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, src_reg
);
2933 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, src_reg
);
2934 append_alu(MI_ALU_ADD
, 0, 0);
2937 /* Store ACCU to R1 and add R0 to R1 */
2938 append_alu(MI_ALU_STORE
, MI_ALU_REG1
, MI_ALU_ACCU
);
2939 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
2940 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
2941 append_alu(MI_ALU_ADD
, 0, 0);
2944 append_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2951 emit_mul_gpr0(struct anv_batch
*batch
, uint32_t N
)
2953 uint32_t num_dwords
;
2954 build_alu_multiply_gpr0(NULL
, &num_dwords
, N
);
2956 uint32_t *dw
= anv_batch_emitn(batch
, 1 + num_dwords
, GENX(MI_MATH
));
2957 build_alu_multiply_gpr0(dw
+ 1, &num_dwords
, N
);
2960 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2962 void genX(CmdDrawIndirectByteCountEXT
)(
2963 VkCommandBuffer commandBuffer
,
2964 uint32_t instanceCount
,
2965 uint32_t firstInstance
,
2966 VkBuffer counterBuffer
,
2967 VkDeviceSize counterBufferOffset
,
2968 uint32_t counterOffset
,
2969 uint32_t vertexStride
)
2971 #if GEN_IS_HASWELL || GEN_GEN >= 8
2972 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2973 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
2974 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2975 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2977 /* firstVertex is always zero for this draw function */
2978 const uint32_t firstVertex
= 0;
2980 if (anv_batch_has_error(&cmd_buffer
->batch
))
2983 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2985 if (vs_prog_data
->uses_firstvertex
||
2986 vs_prog_data
->uses_baseinstance
)
2987 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2988 if (vs_prog_data
->uses_drawid
)
2989 emit_draw_index(cmd_buffer
, 0);
2991 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2992 * different views. We need to multiply instanceCount by the view count.
2994 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2996 struct gen_mi_builder b
;
2997 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
2998 struct gen_mi_value count
=
2999 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
3000 counterBufferOffset
));
3002 count
= gen_mi_iadd(&b
, count
, gen_mi_imm(-counterOffset
));
3003 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
3004 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
3006 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3007 gen_mi_imm(firstVertex
));
3008 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
3009 gen_mi_imm(instanceCount
));
3010 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3011 gen_mi_imm(firstInstance
));
3012 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3014 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3015 prim
.IndirectParameterEnable
= true;
3016 prim
.VertexAccessType
= SEQUENTIAL
;
3017 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3019 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3023 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
3024 struct anv_address addr
,
3027 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3029 emit_lrm(batch
, GEN7_3DPRIM_VERTEX_COUNT
, anv_address_add(addr
, 0));
3031 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3032 if (view_count
> 1) {
3033 #if GEN_IS_HASWELL || GEN_GEN >= 8
3034 emit_lrm(batch
, CS_GPR(0), anv_address_add(addr
, 4));
3035 emit_mul_gpr0(batch
, view_count
);
3036 emit_lrr(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, CS_GPR(0));
3038 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3039 "MI_MATH is not supported on Ivy Bridge");
3040 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, anv_address_add(addr
, 4));
3043 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, anv_address_add(addr
, 4));
3046 emit_lrm(batch
, GEN7_3DPRIM_START_VERTEX
, anv_address_add(addr
, 8));
3049 emit_lrm(batch
, GEN7_3DPRIM_BASE_VERTEX
, anv_address_add(addr
, 12));
3050 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, anv_address_add(addr
, 16));
3052 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, anv_address_add(addr
, 12));
3053 emit_lri(batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
3057 void genX(CmdDrawIndirect
)(
3058 VkCommandBuffer commandBuffer
,
3060 VkDeviceSize offset
,
3064 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3065 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3066 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3067 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3069 if (anv_batch_has_error(&cmd_buffer
->batch
))
3072 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3074 if (cmd_buffer
->state
.conditional_render_enabled
)
3075 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3077 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3078 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3080 if (vs_prog_data
->uses_firstvertex
||
3081 vs_prog_data
->uses_baseinstance
)
3082 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3083 if (vs_prog_data
->uses_drawid
)
3084 emit_draw_index(cmd_buffer
, i
);
3086 load_indirect_parameters(cmd_buffer
, draw
, false);
3088 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3089 prim
.IndirectParameterEnable
= true;
3090 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3091 prim
.VertexAccessType
= SEQUENTIAL
;
3092 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3099 void genX(CmdDrawIndexedIndirect
)(
3100 VkCommandBuffer commandBuffer
,
3102 VkDeviceSize offset
,
3106 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3107 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3108 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3109 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3111 if (anv_batch_has_error(&cmd_buffer
->batch
))
3114 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3116 if (cmd_buffer
->state
.conditional_render_enabled
)
3117 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3119 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3120 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3122 /* TODO: We need to stomp base vertex to 0 somehow */
3123 if (vs_prog_data
->uses_firstvertex
||
3124 vs_prog_data
->uses_baseinstance
)
3125 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3126 if (vs_prog_data
->uses_drawid
)
3127 emit_draw_index(cmd_buffer
, i
);
3129 load_indirect_parameters(cmd_buffer
, draw
, true);
3131 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3132 prim
.IndirectParameterEnable
= true;
3133 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3134 prim
.VertexAccessType
= RANDOM
;
3135 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3142 #define TMP_DRAW_COUNT_REG MI_ALU_REG14
3145 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3146 struct anv_address count_address
,
3147 const bool conditional_render_enabled
)
3149 if (conditional_render_enabled
) {
3150 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3151 emit_lrm(&cmd_buffer
->batch
, CS_GPR(TMP_DRAW_COUNT_REG
), count_address
);
3152 emit_lri(&cmd_buffer
->batch
, CS_GPR(TMP_DRAW_COUNT_REG
) + 4, 0);
3155 /* Upload the current draw count from the draw parameters buffer to
3156 * MI_PREDICATE_SRC0.
3158 emit_lrm(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, count_address
);
3159 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
3161 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
3166 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3167 uint32_t draw_index
)
3169 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3170 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, draw_index
);
3172 if (draw_index
== 0) {
3173 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3174 mip
.LoadOperation
= LOAD_LOADINV
;
3175 mip
.CombineOperation
= COMBINE_SET
;
3176 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3179 /* While draw_index < draw_count the predicate's result will be
3180 * (draw_index == draw_count) ^ TRUE = TRUE
3181 * When draw_index == draw_count the result is
3182 * (TRUE) ^ TRUE = FALSE
3183 * After this all results will be:
3184 * (FALSE) ^ FALSE = FALSE
3186 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3187 mip
.LoadOperation
= LOAD_LOAD
;
3188 mip
.CombineOperation
= COMBINE_XOR
;
3189 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3194 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3196 emit_draw_count_predicate_with_conditional_render(
3197 struct anv_cmd_buffer
*cmd_buffer
,
3198 uint32_t draw_index
)
3200 const int draw_index_reg
= MI_ALU_REG0
;
3201 const int tmp_result_reg
= MI_ALU_REG1
;
3203 emit_lri(&cmd_buffer
->batch
, CS_GPR(draw_index_reg
), draw_index
);
3204 emit_lri(&cmd_buffer
->batch
, CS_GPR(draw_index_reg
) + 4, 0);
3207 /* Compute (draw_index < draw_count).
3208 * We do this by subtracting and storing the carry bit.
3210 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 9, GENX(MI_MATH
));
3211 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, draw_index_reg
);
3212 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, TMP_DRAW_COUNT_REG
);
3213 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
3214 dw
[4] = mi_alu(MI_ALU_STORE
, tmp_result_reg
, MI_ALU_CF
);
3216 dw
[5] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, tmp_result_reg
);
3217 dw
[6] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, ANV_PREDICATE_RESULT_REG
);
3218 dw
[7] = mi_alu(MI_ALU_AND
, 0, 0);
3219 dw
[8] = mi_alu(MI_ALU_STORE
, tmp_result_reg
, MI_ALU_ACCU
);
3222 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_RESULT
, CS_GPR(tmp_result_reg
));
3224 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3225 * so we emit MI_PREDICATE to set it.
3228 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(tmp_result_reg
));
3229 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
3230 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
3231 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
3233 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3234 mip
.LoadOperation
= LOAD_LOADINV
;
3235 mip
.CombineOperation
= COMBINE_SET
;
3236 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3242 void genX(CmdDrawIndirectCountKHR
)(
3243 VkCommandBuffer commandBuffer
,
3245 VkDeviceSize offset
,
3246 VkBuffer _countBuffer
,
3247 VkDeviceSize countBufferOffset
,
3248 uint32_t maxDrawCount
,
3251 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3252 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3253 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3254 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3255 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3256 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3258 if (anv_batch_has_error(&cmd_buffer
->batch
))
3261 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3263 struct anv_address count_address
=
3264 anv_address_add(count_buffer
->address
, countBufferOffset
);
3266 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3267 cmd_state
->conditional_render_enabled
);
3269 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3270 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3272 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3273 if (cmd_state
->conditional_render_enabled
) {
3274 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3276 emit_draw_count_predicate(cmd_buffer
, i
);
3279 emit_draw_count_predicate(cmd_buffer
, i
);
3282 if (vs_prog_data
->uses_firstvertex
||
3283 vs_prog_data
->uses_baseinstance
)
3284 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3285 if (vs_prog_data
->uses_drawid
)
3286 emit_draw_index(cmd_buffer
, i
);
3288 load_indirect_parameters(cmd_buffer
, draw
, false);
3290 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3291 prim
.IndirectParameterEnable
= true;
3292 prim
.PredicateEnable
= true;
3293 prim
.VertexAccessType
= SEQUENTIAL
;
3294 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3301 void genX(CmdDrawIndexedIndirectCountKHR
)(
3302 VkCommandBuffer commandBuffer
,
3304 VkDeviceSize offset
,
3305 VkBuffer _countBuffer
,
3306 VkDeviceSize countBufferOffset
,
3307 uint32_t maxDrawCount
,
3310 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3311 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3312 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3313 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3314 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3315 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3317 if (anv_batch_has_error(&cmd_buffer
->batch
))
3320 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3322 struct anv_address count_address
=
3323 anv_address_add(count_buffer
->address
, countBufferOffset
);
3325 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3326 cmd_state
->conditional_render_enabled
);
3328 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3329 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3331 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3332 if (cmd_state
->conditional_render_enabled
) {
3333 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3335 emit_draw_count_predicate(cmd_buffer
, i
);
3338 emit_draw_count_predicate(cmd_buffer
, i
);
3341 /* TODO: We need to stomp base vertex to 0 somehow */
3342 if (vs_prog_data
->uses_firstvertex
||
3343 vs_prog_data
->uses_baseinstance
)
3344 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3345 if (vs_prog_data
->uses_drawid
)
3346 emit_draw_index(cmd_buffer
, i
);
3348 load_indirect_parameters(cmd_buffer
, draw
, true);
3350 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3351 prim
.IndirectParameterEnable
= true;
3352 prim
.PredicateEnable
= true;
3353 prim
.VertexAccessType
= RANDOM
;
3354 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3361 void genX(CmdBeginTransformFeedbackEXT
)(
3362 VkCommandBuffer commandBuffer
,
3363 uint32_t firstCounterBuffer
,
3364 uint32_t counterBufferCount
,
3365 const VkBuffer
* pCounterBuffers
,
3366 const VkDeviceSize
* pCounterBufferOffsets
)
3368 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3370 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3371 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3372 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3374 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3376 * "Ssoftware must ensure that no HW stream output operations can be in
3377 * process or otherwise pending at the point that the MI_LOAD/STORE
3378 * commands are processed. This will likely require a pipeline flush."
3380 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3381 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3383 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3384 /* If we have a counter buffer, this is a resume so we need to load the
3385 * value into the streamout offset register. Otherwise, this is a begin
3386 * and we need to reset it to zero.
3388 if (pCounterBuffers
&&
3389 idx
>= firstCounterBuffer
&&
3390 idx
- firstCounterBuffer
< counterBufferCount
&&
3391 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
3392 uint32_t cb_idx
= idx
- firstCounterBuffer
;
3393 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3394 uint64_t offset
= pCounterBufferOffsets
?
3395 pCounterBufferOffsets
[cb_idx
] : 0;
3397 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3398 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3399 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3403 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
3404 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3410 cmd_buffer
->state
.xfb_enabled
= true;
3411 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3414 void genX(CmdEndTransformFeedbackEXT
)(
3415 VkCommandBuffer commandBuffer
,
3416 uint32_t firstCounterBuffer
,
3417 uint32_t counterBufferCount
,
3418 const VkBuffer
* pCounterBuffers
,
3419 const VkDeviceSize
* pCounterBufferOffsets
)
3421 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3423 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3424 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3425 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3427 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3429 * "Ssoftware must ensure that no HW stream output operations can be in
3430 * process or otherwise pending at the point that the MI_LOAD/STORE
3431 * commands are processed. This will likely require a pipeline flush."
3433 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3434 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3436 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
3437 unsigned idx
= firstCounterBuffer
+ cb_idx
;
3439 /* If we have a counter buffer, this is a resume so we need to load the
3440 * value into the streamout offset register. Otherwise, this is a begin
3441 * and we need to reset it to zero.
3443 if (pCounterBuffers
&&
3444 cb_idx
< counterBufferCount
&&
3445 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
3446 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3447 uint64_t offset
= pCounterBufferOffsets
?
3448 pCounterBufferOffsets
[cb_idx
] : 0;
3450 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
3451 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3453 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3458 cmd_buffer
->state
.xfb_enabled
= false;
3459 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3463 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
3465 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3466 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
3469 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3470 if (result
!= VK_SUCCESS
) {
3471 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3473 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
3474 if (result
!= VK_SUCCESS
)
3477 /* Re-emit state base addresses so we get the new surface state base
3478 * address before we start emitting binding tables etc.
3480 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
3482 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3483 if (result
!= VK_SUCCESS
) {
3484 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3489 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3490 if (result
!= VK_SUCCESS
) {
3491 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3495 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3496 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3497 .BindingTablePointer
= surfaces
.offset
,
3498 .SamplerStatePointer
= samplers
.offset
,
3500 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3502 struct anv_state state
=
3503 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3504 pipeline
->interface_descriptor_data
,
3505 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3508 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3509 anv_batch_emit(&cmd_buffer
->batch
,
3510 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3511 mid
.InterfaceDescriptorTotalLength
= size
;
3512 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3519 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3521 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3522 MAYBE_UNUSED VkResult result
;
3524 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3526 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3528 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3530 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3531 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3533 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3534 * the only bits that are changed are scoreboard related: Scoreboard
3535 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3536 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3539 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3540 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3542 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3545 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3546 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3547 /* FIXME: figure out descriptors for gen7 */
3548 result
= flush_compute_descriptor_set(cmd_buffer
);
3549 if (result
!= VK_SUCCESS
)
3552 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3555 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3556 struct anv_state push_state
=
3557 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3559 if (push_state
.alloc_size
) {
3560 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3561 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3562 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3566 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3569 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3571 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3577 verify_cmd_parser(const struct anv_device
*device
,
3578 int required_version
,
3579 const char *function
)
3581 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3582 return vk_errorf(device
->instance
, device
->instance
,
3583 VK_ERROR_FEATURE_NOT_PRESENT
,
3584 "cmd parser version %d is required for %s",
3585 required_version
, function
);
3594 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3595 uint32_t baseGroupX
,
3596 uint32_t baseGroupY
,
3597 uint32_t baseGroupZ
)
3599 if (anv_batch_has_error(&cmd_buffer
->batch
))
3603 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, MESA_SHADER_COMPUTE
,
3604 base_work_group_id
);
3605 if (result
!= VK_SUCCESS
) {
3606 cmd_buffer
->batch
.status
= result
;
3610 struct anv_push_constants
*push
=
3611 cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3612 if (push
->base_work_group_id
[0] != baseGroupX
||
3613 push
->base_work_group_id
[1] != baseGroupY
||
3614 push
->base_work_group_id
[2] != baseGroupZ
) {
3615 push
->base_work_group_id
[0] = baseGroupX
;
3616 push
->base_work_group_id
[1] = baseGroupY
;
3617 push
->base_work_group_id
[2] = baseGroupZ
;
3619 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3623 void genX(CmdDispatch
)(
3624 VkCommandBuffer commandBuffer
,
3629 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3632 void genX(CmdDispatchBase
)(
3633 VkCommandBuffer commandBuffer
,
3634 uint32_t baseGroupX
,
3635 uint32_t baseGroupY
,
3636 uint32_t baseGroupZ
,
3637 uint32_t groupCountX
,
3638 uint32_t groupCountY
,
3639 uint32_t groupCountZ
)
3641 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3642 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3643 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3645 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3646 baseGroupY
, baseGroupZ
);
3648 if (anv_batch_has_error(&cmd_buffer
->batch
))
3651 if (prog_data
->uses_num_work_groups
) {
3652 struct anv_state state
=
3653 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3654 uint32_t *sizes
= state
.map
;
3655 sizes
[0] = groupCountX
;
3656 sizes
[1] = groupCountY
;
3657 sizes
[2] = groupCountZ
;
3658 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3659 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3660 .offset
= state
.offset
,
3664 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3666 if (cmd_buffer
->state
.conditional_render_enabled
)
3667 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3669 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3670 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3671 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3672 ggw
.ThreadDepthCounterMaximum
= 0;
3673 ggw
.ThreadHeightCounterMaximum
= 0;
3674 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3675 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3676 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3677 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3678 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3679 ggw
.BottomExecutionMask
= 0xffffffff;
3682 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3685 #define GPGPU_DISPATCHDIMX 0x2500
3686 #define GPGPU_DISPATCHDIMY 0x2504
3687 #define GPGPU_DISPATCHDIMZ 0x2508
3689 void genX(CmdDispatchIndirect
)(
3690 VkCommandBuffer commandBuffer
,
3692 VkDeviceSize offset
)
3694 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3695 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3696 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3697 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3698 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3699 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3701 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3704 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3705 * indirect dispatch registers to be written.
3707 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3708 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3712 if (prog_data
->uses_num_work_groups
)
3713 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3715 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3717 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, anv_address_add(addr
, 0));
3718 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, anv_address_add(addr
, 4));
3719 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, anv_address_add(addr
, 8));
3722 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
3723 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
3724 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
3725 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
3727 /* Load compute_dispatch_indirect_x_size into SRC0 */
3728 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 0));
3730 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3731 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3732 mip
.LoadOperation
= LOAD_LOAD
;
3733 mip
.CombineOperation
= COMBINE_SET
;
3734 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3737 /* Load compute_dispatch_indirect_y_size into SRC0 */
3738 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 4));
3740 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3741 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3742 mip
.LoadOperation
= LOAD_LOAD
;
3743 mip
.CombineOperation
= COMBINE_OR
;
3744 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3747 /* Load compute_dispatch_indirect_z_size into SRC0 */
3748 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 8));
3750 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3751 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3752 mip
.LoadOperation
= LOAD_LOAD
;
3753 mip
.CombineOperation
= COMBINE_OR
;
3754 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3757 /* predicate = !predicate; */
3758 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3759 mip
.LoadOperation
= LOAD_LOADINV
;
3760 mip
.CombineOperation
= COMBINE_OR
;
3761 mip
.CompareOperation
= COMPARE_FALSE
;
3765 if (cmd_buffer
->state
.conditional_render_enabled
) {
3766 emit_lrr(batch
, MI_PREDICATE_SRC0
, CS_GPR(ANV_PREDICATE_RESULT_REG
));
3767 /* predicate &= !(conditional_rendering_predicate == 0); */
3768 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3769 mip
.LoadOperation
= LOAD_LOADINV
;
3770 mip
.CombineOperation
= COMBINE_AND
;
3771 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3776 #else /* GEN_GEN > 7 */
3777 if (cmd_buffer
->state
.conditional_render_enabled
)
3778 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3781 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3782 ggw
.IndirectParameterEnable
= true;
3783 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
3784 cmd_buffer
->state
.conditional_render_enabled
;
3785 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3786 ggw
.ThreadDepthCounterMaximum
= 0;
3787 ggw
.ThreadHeightCounterMaximum
= 0;
3788 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3789 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3790 ggw
.BottomExecutionMask
= 0xffffffff;
3793 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3797 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3800 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3802 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3805 #if GEN_GEN >= 8 && GEN_GEN < 10
3806 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3808 * Software must clear the COLOR_CALC_STATE Valid field in
3809 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3810 * with Pipeline Select set to GPGPU.
3812 * The internal hardware docs recommend the same workaround for Gen9
3815 if (pipeline
== GPGPU
)
3816 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3819 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3820 * PIPELINE_SELECT [DevBWR+]":
3824 * Software must ensure all the write caches are flushed through a
3825 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3826 * command to invalidate read only caches prior to programming
3827 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3829 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3830 pc
.RenderTargetCacheFlushEnable
= true;
3831 pc
.DepthCacheFlushEnable
= true;
3832 pc
.DCFlushEnable
= true;
3833 pc
.PostSyncOperation
= NoWrite
;
3834 pc
.CommandStreamerStallEnable
= true;
3837 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3838 pc
.TextureCacheInvalidationEnable
= true;
3839 pc
.ConstantCacheInvalidationEnable
= true;
3840 pc
.StateCacheInvalidationEnable
= true;
3841 pc
.InstructionCacheInvalidateEnable
= true;
3842 pc
.PostSyncOperation
= NoWrite
;
3845 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3849 ps
.PipelineSelection
= pipeline
;
3853 if (devinfo
->is_geminilake
) {
3856 * "This chicken bit works around a hardware issue with barrier logic
3857 * encountered when switching between GPGPU and 3D pipelines. To
3858 * workaround the issue, this mode bit should be set after a pipeline
3862 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3864 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3865 : GLK_BARRIER_MODE_3D_HULL
,
3866 .GLKBarrierModeMask
= 1);
3867 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3871 cmd_buffer
->state
.current_pipeline
= pipeline
;
3875 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3877 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3881 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3883 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3887 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3892 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3894 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3895 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3896 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3897 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3898 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3899 * Depth Flush Bit set, followed by another pipelined depth stall
3900 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3901 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3902 * via a preceding MI_FLUSH)."
3904 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3905 pipe
.DepthStallEnable
= true;
3907 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3908 pipe
.DepthCacheFlushEnable
= true;
3910 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3911 pipe
.DepthStallEnable
= true;
3916 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3918 struct anv_device
*device
= cmd_buffer
->device
;
3919 const struct anv_image_view
*iview
=
3920 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3921 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3923 /* FIXME: Width and Height are wrong */
3925 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3927 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3928 device
->isl_dev
.ds
.size
/ 4);
3932 struct isl_depth_stencil_hiz_emit_info info
= { };
3935 info
.view
= &iview
->planes
[0].isl
;
3937 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3938 uint32_t depth_plane
=
3939 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3940 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
3942 info
.depth_surf
= &surface
->isl
;
3944 info
.depth_address
=
3945 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3946 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
3947 image
->planes
[depth_plane
].address
.bo
,
3948 image
->planes
[depth_plane
].address
.offset
+
3951 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
3954 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
3955 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
3956 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
3957 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
3960 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3961 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
3962 image
->planes
[depth_plane
].address
.bo
,
3963 image
->planes
[depth_plane
].address
.offset
+
3964 image
->planes
[depth_plane
].aux_surface
.offset
);
3966 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
3970 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3971 uint32_t stencil_plane
=
3972 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
3973 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
3975 info
.stencil_surf
= &surface
->isl
;
3977 info
.stencil_address
=
3978 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3979 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
3980 image
->planes
[stencil_plane
].address
.bo
,
3981 image
->planes
[stencil_plane
].address
.offset
+
3984 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
3987 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
3989 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
3993 * This ANDs the view mask of the current subpass with the pending clear
3994 * views in the attachment to get the mask of views active in the subpass
3995 * that still need to be cleared.
3997 static inline uint32_t
3998 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
3999 const struct anv_attachment_state
*att_state
)
4001 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
4005 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
4006 const struct anv_attachment_state
*att_state
)
4008 if (!cmd_state
->subpass
->view_mask
)
4011 uint32_t pending_clear_mask
=
4012 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4014 return pending_clear_mask
& 1;
4018 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
4021 const uint32_t last_subpass_idx
=
4022 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
4023 const struct anv_subpass
*last_subpass
=
4024 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
4025 return last_subpass
== cmd_state
->subpass
;
4029 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
4030 uint32_t subpass_id
)
4032 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4033 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
4034 cmd_state
->subpass
= subpass
;
4036 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
4038 /* Our implementation of VK_KHR_multiview uses instancing to draw the
4039 * different views. If the client asks for instancing, we need to use the
4040 * Instance Data Step Rate to ensure that we repeat the client's
4041 * per-instance data once for each view. Since this bit is in
4042 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
4046 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
4048 /* It is possible to start a render pass with an old pipeline. Because the
4049 * render pass and subpass index are both baked into the pipeline, this is
4050 * highly unlikely. In order to do so, it requires that you have a render
4051 * pass with a single subpass and that you use that render pass twice
4052 * back-to-back and use the same pipeline at the start of the second render
4053 * pass as at the end of the first. In order to avoid unpredictable issues
4054 * with this edge case, we just dirty the pipeline at the start of every
4057 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
4059 /* Accumulate any subpass flushes that need to happen before the subpass */
4060 cmd_buffer
->state
.pending_pipe_bits
|=
4061 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
4063 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4064 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4066 bool is_multiview
= subpass
->view_mask
!= 0;
4068 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4069 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4070 if (a
== VK_ATTACHMENT_UNUSED
)
4073 assert(a
< cmd_state
->pass
->attachment_count
);
4074 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4076 struct anv_image_view
*iview
= fb
->attachments
[a
];
4077 const struct anv_image
*image
= iview
->image
;
4079 /* A resolve is necessary before use as an input attachment if the clear
4080 * color or auxiliary buffer usage isn't supported by the sampler.
4082 const bool input_needs_resolve
=
4083 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
4084 att_state
->input_aux_usage
!= att_state
->aux_usage
;
4086 VkImageLayout target_layout
;
4087 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
4088 !input_needs_resolve
) {
4089 /* Layout transitions before the final only help to enable sampling
4090 * as an input attachment. If the input attachment supports sampling
4091 * using the auxiliary surface, we can skip such transitions by
4092 * making the target layout one that is CCS-aware.
4094 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
4096 target_layout
= subpass
->attachments
[i
].layout
;
4099 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4100 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4102 uint32_t base_layer
, layer_count
;
4103 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4105 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4106 iview
->planes
[0].isl
.base_level
);
4108 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4109 layer_count
= fb
->layers
;
4112 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4113 iview
->planes
[0].isl
.base_level
, 1,
4114 base_layer
, layer_count
,
4115 att_state
->current_layout
, target_layout
);
4116 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4117 transition_depth_buffer(cmd_buffer
, image
,
4118 att_state
->current_layout
, target_layout
);
4119 att_state
->aux_usage
=
4120 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
4121 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
4123 att_state
->current_layout
= target_layout
;
4125 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
4126 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4128 /* Multi-planar images are not supported as attachments */
4129 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4130 assert(image
->n_planes
== 1);
4132 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
4133 uint32_t clear_layer_count
= fb
->layers
;
4135 if (att_state
->fast_clear
&&
4136 do_first_layer_clear(cmd_state
, att_state
)) {
4137 /* We only support fast-clears on the first layer */
4138 assert(iview
->planes
[0].isl
.base_level
== 0);
4139 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4141 union isl_color_value clear_color
= {};
4142 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
4143 if (iview
->image
->samples
== 1) {
4144 anv_image_ccs_op(cmd_buffer
, image
,
4145 iview
->planes
[0].isl
.format
,
4146 VK_IMAGE_ASPECT_COLOR_BIT
,
4147 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4151 anv_image_mcs_op(cmd_buffer
, image
,
4152 iview
->planes
[0].isl
.format
,
4153 VK_IMAGE_ASPECT_COLOR_BIT
,
4154 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4159 clear_layer_count
--;
4161 att_state
->pending_clear_views
&= ~1;
4163 if (att_state
->clear_color_is_zero
) {
4164 /* This image has the auxiliary buffer enabled. We can mark the
4165 * subresource as not needing a resolve because the clear color
4166 * will match what's in every RENDER_SURFACE_STATE object when
4167 * it's being used for sampling.
4169 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4170 VK_IMAGE_ASPECT_COLOR_BIT
,
4171 ANV_FAST_CLEAR_DEFAULT_VALUE
);
4173 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4174 VK_IMAGE_ASPECT_COLOR_BIT
,
4175 ANV_FAST_CLEAR_ANY
);
4179 /* From the VkFramebufferCreateInfo spec:
4181 * "If the render pass uses multiview, then layers must be one and each
4182 * attachment requires a number of layers that is greater than the
4183 * maximum bit index set in the view mask in the subpasses in which it
4186 * So if multiview is active we ignore the number of layers in the
4187 * framebuffer and instead we honor the view mask from the subpass.
4190 assert(image
->n_planes
== 1);
4191 uint32_t pending_clear_mask
=
4192 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4195 for_each_bit(layer_idx
, pending_clear_mask
) {
4197 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4199 anv_image_clear_color(cmd_buffer
, image
,
4200 VK_IMAGE_ASPECT_COLOR_BIT
,
4201 att_state
->aux_usage
,
4202 iview
->planes
[0].isl
.format
,
4203 iview
->planes
[0].isl
.swizzle
,
4204 iview
->planes
[0].isl
.base_level
,
4207 vk_to_isl_color(att_state
->clear_value
.color
));
4210 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4211 } else if (clear_layer_count
> 0) {
4212 assert(image
->n_planes
== 1);
4213 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4214 att_state
->aux_usage
,
4215 iview
->planes
[0].isl
.format
,
4216 iview
->planes
[0].isl
.swizzle
,
4217 iview
->planes
[0].isl
.base_level
,
4218 base_clear_layer
, clear_layer_count
,
4220 vk_to_isl_color(att_state
->clear_value
.color
));
4222 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
4223 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4224 if (att_state
->fast_clear
&& !is_multiview
) {
4225 /* We currently only support HiZ for single-layer images */
4226 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4227 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
4228 assert(iview
->planes
[0].isl
.base_level
== 0);
4229 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4230 assert(fb
->layers
== 1);
4233 anv_image_hiz_clear(cmd_buffer
, image
,
4234 att_state
->pending_clear_aspects
,
4235 iview
->planes
[0].isl
.base_level
,
4236 iview
->planes
[0].isl
.base_array_layer
,
4237 fb
->layers
, render_area
,
4238 att_state
->clear_value
.depthStencil
.stencil
);
4239 } else if (is_multiview
) {
4240 uint32_t pending_clear_mask
=
4241 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4244 for_each_bit(layer_idx
, pending_clear_mask
) {
4246 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4248 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4249 att_state
->pending_clear_aspects
,
4250 att_state
->aux_usage
,
4251 iview
->planes
[0].isl
.base_level
,
4254 att_state
->clear_value
.depthStencil
.depth
,
4255 att_state
->clear_value
.depthStencil
.stencil
);
4258 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4260 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4261 att_state
->pending_clear_aspects
,
4262 att_state
->aux_usage
,
4263 iview
->planes
[0].isl
.base_level
,
4264 iview
->planes
[0].isl
.base_array_layer
,
4265 fb
->layers
, render_area
,
4266 att_state
->clear_value
.depthStencil
.depth
,
4267 att_state
->clear_value
.depthStencil
.stencil
);
4270 assert(att_state
->pending_clear_aspects
== 0);
4274 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4275 image
->planes
[0].aux_surface
.isl
.size_B
> 0 &&
4276 iview
->planes
[0].isl
.base_level
== 0 &&
4277 iview
->planes
[0].isl
.base_array_layer
== 0) {
4278 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
4279 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
4280 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4281 false /* copy to ss */);
4284 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
4285 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
4286 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
4287 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4288 false /* copy to ss */);
4292 if (subpass
->attachments
[i
].usage
==
4293 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
4294 /* We assume that if we're starting a subpass, we're going to do some
4295 * rendering so we may end up with compressed data.
4297 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
4298 VK_IMAGE_ASPECT_COLOR_BIT
,
4299 att_state
->aux_usage
,
4300 iview
->planes
[0].isl
.base_level
,
4301 iview
->planes
[0].isl
.base_array_layer
,
4303 } else if (subpass
->attachments
[i
].usage
==
4304 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
4305 /* We may be writing depth or stencil so we need to mark the surface.
4306 * Unfortunately, there's no way to know at this point whether the
4307 * depth or stencil tests used will actually write to the surface.
4309 * Even though stencil may be plane 1, it always shares a base_level
4312 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
4313 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4314 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4315 VK_IMAGE_ASPECT_DEPTH_BIT
,
4316 att_state
->aux_usage
,
4317 ds_view
->base_level
,
4318 ds_view
->base_array_layer
,
4321 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4322 /* Even though stencil may be plane 1, it always shares a
4323 * base_level with depth.
4325 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4326 VK_IMAGE_ASPECT_STENCIL_BIT
,
4328 ds_view
->base_level
,
4329 ds_view
->base_array_layer
,
4334 /* If multiview is enabled, then we are only done clearing when we no
4335 * longer have pending layers to clear, or when we have processed the
4336 * last subpass that uses this attachment.
4338 if (!is_multiview
||
4339 att_state
->pending_clear_views
== 0 ||
4340 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
4341 att_state
->pending_clear_aspects
= 0;
4344 att_state
->pending_load_aspects
= 0;
4347 cmd_buffer_emit_depth_stencil(cmd_buffer
);
4350 static enum blorp_filter
4351 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
4354 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
4355 return BLORP_FILTER_SAMPLE_0
;
4356 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
4357 return BLORP_FILTER_AVERAGE
;
4358 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
4359 return BLORP_FILTER_MIN_SAMPLE
;
4360 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
4361 return BLORP_FILTER_MAX_SAMPLE
;
4363 return BLORP_FILTER_NONE
;
4368 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
4370 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4371 struct anv_subpass
*subpass
= cmd_state
->subpass
;
4372 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
4373 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4375 if (subpass
->has_color_resolve
) {
4376 /* We are about to do some MSAA resolves. We need to flush so that the
4377 * result of writes to the MSAA color attachments show up in the sampler
4378 * when we blit to the single-sampled resolve target.
4380 cmd_buffer
->state
.pending_pipe_bits
|=
4381 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4382 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
4384 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
4385 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
4386 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
4388 if (dst_att
== VK_ATTACHMENT_UNUSED
)
4391 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4392 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4394 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4395 /* From the Vulkan 1.0 spec:
4397 * If the first use of an attachment in a render pass is as a
4398 * resolve attachment, then the loadOp is effectively ignored
4399 * as the resolve is guaranteed to overwrite all pixels in the
4402 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4405 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
4406 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
4408 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4410 enum isl_aux_usage src_aux_usage
=
4411 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
4412 enum isl_aux_usage dst_aux_usage
=
4413 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
4415 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
4416 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
4418 anv_image_msaa_resolve(cmd_buffer
,
4419 src_iview
->image
, src_aux_usage
,
4420 src_iview
->planes
[0].isl
.base_level
,
4421 src_iview
->planes
[0].isl
.base_array_layer
,
4422 dst_iview
->image
, dst_aux_usage
,
4423 dst_iview
->planes
[0].isl
.base_level
,
4424 dst_iview
->planes
[0].isl
.base_array_layer
,
4425 VK_IMAGE_ASPECT_COLOR_BIT
,
4426 render_area
.offset
.x
, render_area
.offset
.y
,
4427 render_area
.offset
.x
, render_area
.offset
.y
,
4428 render_area
.extent
.width
,
4429 render_area
.extent
.height
,
4430 fb
->layers
, BLORP_FILTER_NONE
);
4434 if (subpass
->ds_resolve_attachment
) {
4435 /* We are about to do some MSAA resolves. We need to flush so that the
4436 * result of writes to the MSAA depth attachments show up in the sampler
4437 * when we blit to the single-sampled resolve target.
4439 cmd_buffer
->state
.pending_pipe_bits
|=
4440 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4441 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
4443 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
4444 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
4446 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4447 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4449 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4450 /* From the Vulkan 1.0 spec:
4452 * If the first use of an attachment in a render pass is as a
4453 * resolve attachment, then the loadOp is effectively ignored
4454 * as the resolve is guaranteed to overwrite all pixels in the
4457 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4460 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
4461 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
4463 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4465 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
4466 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4468 struct anv_attachment_state
*src_state
=
4469 &cmd_state
->attachments
[src_att
];
4470 struct anv_attachment_state
*dst_state
=
4471 &cmd_state
->attachments
[dst_att
];
4473 /* MSAA resolves sample from the source attachment. Transition the
4474 * depth attachment first to get rid of any HiZ that we may not be
4477 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
4478 src_state
->current_layout
,
4479 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4480 src_state
->aux_usage
=
4481 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
4482 VK_IMAGE_ASPECT_DEPTH_BIT
,
4483 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4484 src_state
->current_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
4486 /* MSAA resolves write to the resolve attachment as if it were any
4487 * other transfer op. Transition the resolve attachment accordingly.
4489 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
4491 /* If our render area is the entire size of the image, we're going to
4492 * blow it all away so we can claim the initial layout is UNDEFINED
4493 * and we'll get a HiZ ambiguate instead of a resolve.
4495 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
4496 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
4497 render_area
.extent
.width
== dst_iview
->extent
.width
&&
4498 render_area
.extent
.height
== dst_iview
->extent
.height
)
4499 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
4501 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
4503 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4504 dst_state
->aux_usage
=
4505 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
4506 VK_IMAGE_ASPECT_DEPTH_BIT
,
4507 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4508 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
4510 enum blorp_filter filter
=
4511 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
4513 anv_image_msaa_resolve(cmd_buffer
,
4514 src_iview
->image
, src_state
->aux_usage
,
4515 src_iview
->planes
[0].isl
.base_level
,
4516 src_iview
->planes
[0].isl
.base_array_layer
,
4517 dst_iview
->image
, dst_state
->aux_usage
,
4518 dst_iview
->planes
[0].isl
.base_level
,
4519 dst_iview
->planes
[0].isl
.base_array_layer
,
4520 VK_IMAGE_ASPECT_DEPTH_BIT
,
4521 render_area
.offset
.x
, render_area
.offset
.y
,
4522 render_area
.offset
.x
, render_area
.offset
.y
,
4523 render_area
.extent
.width
,
4524 render_area
.extent
.height
,
4525 fb
->layers
, filter
);
4528 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
4529 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4531 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
4532 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
4534 enum blorp_filter filter
=
4535 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
4537 anv_image_msaa_resolve(cmd_buffer
,
4538 src_iview
->image
, src_aux_usage
,
4539 src_iview
->planes
[0].isl
.base_level
,
4540 src_iview
->planes
[0].isl
.base_array_layer
,
4541 dst_iview
->image
, dst_aux_usage
,
4542 dst_iview
->planes
[0].isl
.base_level
,
4543 dst_iview
->planes
[0].isl
.base_array_layer
,
4544 VK_IMAGE_ASPECT_STENCIL_BIT
,
4545 render_area
.offset
.x
, render_area
.offset
.y
,
4546 render_area
.offset
.x
, render_area
.offset
.y
,
4547 render_area
.extent
.width
,
4548 render_area
.extent
.height
,
4549 fb
->layers
, filter
);
4553 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4554 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4555 if (a
== VK_ATTACHMENT_UNUSED
)
4558 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4561 assert(a
< cmd_state
->pass
->attachment_count
);
4562 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4563 struct anv_image_view
*iview
= fb
->attachments
[a
];
4564 const struct anv_image
*image
= iview
->image
;
4566 if ((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4567 image
->vk_format
!= iview
->vk_format
) {
4568 enum anv_fast_clear_type fast_clear_type
=
4569 anv_layout_to_fast_clear_type(&cmd_buffer
->device
->info
,
4570 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4571 att_state
->current_layout
);
4573 /* If any clear color was used, flush it down the aux surfaces. If we
4574 * don't do it now using the view's format we might use the clear
4575 * color incorrectly in the following resolves (for example with an
4576 * SRGB view & a UNORM image).
4578 if (fast_clear_type
!= ANV_FAST_CLEAR_NONE
) {
4579 anv_perf_warn(cmd_buffer
->device
->instance
, fb
,
4580 "Doing a partial resolve to get rid of clear color at the "
4581 "end of a renderpass due to an image/view format mismatch");
4583 uint32_t base_layer
, layer_count
;
4584 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4586 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4587 iview
->planes
[0].isl
.base_level
);
4589 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4590 layer_count
= fb
->layers
;
4593 for (uint32_t a
= 0; a
< layer_count
; a
++) {
4594 uint32_t array_layer
= base_layer
+ a
;
4595 if (image
->samples
== 1) {
4596 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
4597 iview
->planes
[0].isl
.format
,
4598 VK_IMAGE_ASPECT_COLOR_BIT
,
4599 iview
->planes
[0].isl
.base_level
,
4601 ISL_AUX_OP_PARTIAL_RESOLVE
,
4602 ANV_FAST_CLEAR_NONE
);
4604 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
4605 iview
->planes
[0].isl
.format
,
4606 VK_IMAGE_ASPECT_COLOR_BIT
,
4608 ISL_AUX_OP_PARTIAL_RESOLVE
,
4609 ANV_FAST_CLEAR_NONE
);
4615 /* Transition the image into the final layout for this render pass */
4616 VkImageLayout target_layout
=
4617 cmd_state
->pass
->attachments
[a
].final_layout
;
4619 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4620 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4622 uint32_t base_layer
, layer_count
;
4623 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4625 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4626 iview
->planes
[0].isl
.base_level
);
4628 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4629 layer_count
= fb
->layers
;
4632 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4633 iview
->planes
[0].isl
.base_level
, 1,
4634 base_layer
, layer_count
,
4635 att_state
->current_layout
, target_layout
);
4636 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4637 transition_depth_buffer(cmd_buffer
, image
,
4638 att_state
->current_layout
, target_layout
);
4642 /* Accumulate any subpass flushes that need to happen after the subpass.
4643 * Yes, they do get accumulated twice in the NextSubpass case but since
4644 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
4645 * ORing the bits in twice so it's harmless.
4647 cmd_buffer
->state
.pending_pipe_bits
|=
4648 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
4651 void genX(CmdBeginRenderPass
)(
4652 VkCommandBuffer commandBuffer
,
4653 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4654 VkSubpassContents contents
)
4656 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4657 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4658 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4660 cmd_buffer
->state
.framebuffer
= framebuffer
;
4661 cmd_buffer
->state
.pass
= pass
;
4662 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4664 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
4666 /* If we failed to setup the attachments we should not try to go further */
4667 if (result
!= VK_SUCCESS
) {
4668 assert(anv_batch_has_error(&cmd_buffer
->batch
));
4672 genX(flush_pipeline_select_3d
)(cmd_buffer
);
4674 cmd_buffer_begin_subpass(cmd_buffer
, 0);
4677 void genX(CmdBeginRenderPass2KHR
)(
4678 VkCommandBuffer commandBuffer
,
4679 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4680 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
4682 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
4683 pSubpassBeginInfo
->contents
);
4686 void genX(CmdNextSubpass
)(
4687 VkCommandBuffer commandBuffer
,
4688 VkSubpassContents contents
)
4690 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4692 if (anv_batch_has_error(&cmd_buffer
->batch
))
4695 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4697 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
4698 cmd_buffer_end_subpass(cmd_buffer
);
4699 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4702 void genX(CmdNextSubpass2KHR
)(
4703 VkCommandBuffer commandBuffer
,
4704 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
4705 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4707 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
4710 void genX(CmdEndRenderPass
)(
4711 VkCommandBuffer commandBuffer
)
4713 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4715 if (anv_batch_has_error(&cmd_buffer
->batch
))
4718 cmd_buffer_end_subpass(cmd_buffer
);
4720 cmd_buffer
->state
.hiz_enabled
= false;
4723 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
4726 /* Remove references to render pass specific state. This enables us to
4727 * detect whether or not we're in a renderpass.
4729 cmd_buffer
->state
.framebuffer
= NULL
;
4730 cmd_buffer
->state
.pass
= NULL
;
4731 cmd_buffer
->state
.subpass
= NULL
;
4734 void genX(CmdEndRenderPass2KHR
)(
4735 VkCommandBuffer commandBuffer
,
4736 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4738 genX(CmdEndRenderPass
)(commandBuffer
);
4742 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
4744 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4745 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(ANV_PREDICATE_RESULT_REG
));
4746 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
4747 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
4748 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
4750 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
4751 mip
.LoadOperation
= LOAD_LOADINV
;
4752 mip
.CombineOperation
= COMBINE_SET
;
4753 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4758 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4759 void genX(CmdBeginConditionalRenderingEXT
)(
4760 VkCommandBuffer commandBuffer
,
4761 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
4763 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4764 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
4765 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4766 struct anv_address value_address
=
4767 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
4769 const bool isInverted
= pConditionalRenderingBegin
->flags
&
4770 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
4772 cmd_state
->conditional_render_enabled
= true;
4774 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4776 /* Section 19.4 of the Vulkan 1.1.85 spec says:
4778 * If the value of the predicate in buffer memory changes
4779 * while conditional rendering is active, the rendering commands
4780 * may be discarded in an implementation-dependent way.
4781 * Some implementations may latch the value of the predicate
4782 * upon beginning conditional rendering while others
4783 * may read it before every rendering command.
4785 * So it's perfectly fine to read a value from the buffer once.
4787 emit_lrm(&cmd_buffer
->batch
, CS_GPR(MI_ALU_REG0
), value_address
);
4788 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
4789 emit_lri(&cmd_buffer
->batch
, CS_GPR(MI_ALU_REG0
) + 4, 0);
4791 /* Precompute predicate result, it is necessary to support secondary
4792 * command buffers since it is unknown if conditional rendering is
4793 * inverted when populating them.
4795 uint32_t *dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
4796 dw
[1] = mi_alu(MI_ALU_LOAD0
, MI_ALU_SRCA
, 0);
4797 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG0
);
4798 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
4799 dw
[4] = mi_alu(isInverted
? MI_ALU_STOREINV
: MI_ALU_STORE
,
4800 ANV_PREDICATE_RESULT_REG
, MI_ALU_CF
);
4803 void genX(CmdEndConditionalRenderingEXT
)(
4804 VkCommandBuffer commandBuffer
)
4806 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4807 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4809 cmd_state
->conditional_render_enabled
= false;