2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
31 #include "common/gen_l3_config.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
36 emit_lrm(struct anv_batch
*batch
, uint32_t reg
, struct anv_address addr
)
38 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
39 lrm
.RegisterAddress
= reg
;
40 lrm
.MemoryAddress
= addr
;
45 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
47 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
48 lri
.RegisterOffset
= reg
;
53 #if GEN_IS_HASWELL || GEN_GEN >= 8
55 emit_lrr(struct anv_batch
*batch
, uint32_t dst
, uint32_t src
)
57 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
58 lrr
.SourceRegisterAddress
= src
;
59 lrr
.DestinationRegisterAddress
= dst
;
65 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
67 struct anv_device
*device
= cmd_buffer
->device
;
69 /* If we are emitting a new state base address we probably need to re-emit
72 cmd_buffer
->state
.descriptors_dirty
|= ~0;
74 /* Emit a render target cache flush.
76 * This isn't documented anywhere in the PRM. However, it seems to be
77 * necessary prior to changing the surface state base adress. Without
78 * this, we get GPU hangs when using multi-level command buffers which
79 * clear depth, reset state base address, and then go render stuff.
81 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
82 pc
.DCFlushEnable
= true;
83 pc
.RenderTargetCacheFlushEnable
= true;
84 pc
.CommandStreamerStallEnable
= true;
87 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
88 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
89 sba
.GeneralStateMOCS
= GENX(MOCS
);
90 sba
.GeneralStateBaseAddressModifyEnable
= true;
92 sba
.SurfaceStateBaseAddress
=
93 anv_cmd_buffer_surface_base_address(cmd_buffer
);
94 sba
.SurfaceStateMOCS
= GENX(MOCS
);
95 sba
.SurfaceStateBaseAddressModifyEnable
= true;
97 sba
.DynamicStateBaseAddress
=
98 (struct anv_address
) { &device
->dynamic_state_pool
.block_pool
.bo
, 0 };
99 sba
.DynamicStateMOCS
= GENX(MOCS
);
100 sba
.DynamicStateBaseAddressModifyEnable
= true;
102 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
103 sba
.IndirectObjectMOCS
= GENX(MOCS
);
104 sba
.IndirectObjectBaseAddressModifyEnable
= true;
106 sba
.InstructionBaseAddress
=
107 (struct anv_address
) { &device
->instruction_state_pool
.block_pool
.bo
, 0 };
108 sba
.InstructionMOCS
= GENX(MOCS
);
109 sba
.InstructionBaseAddressModifyEnable
= true;
112 /* Broadwell requires that we specify a buffer size for a bunch of
113 * these fields. However, since we will be growing the BO's live, we
114 * just set them all to the maximum.
116 sba
.GeneralStateBufferSize
= 0xfffff;
117 sba
.GeneralStateBufferSizeModifyEnable
= true;
118 sba
.DynamicStateBufferSize
= 0xfffff;
119 sba
.DynamicStateBufferSizeModifyEnable
= true;
120 sba
.IndirectObjectBufferSize
= 0xfffff;
121 sba
.IndirectObjectBufferSizeModifyEnable
= true;
122 sba
.InstructionBufferSize
= 0xfffff;
123 sba
.InstructionBuffersizeModifyEnable
= true;
126 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
127 sba
.BindlessSurfaceStateMOCS
= GENX(MOCS
);
128 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
129 sba
.BindlessSurfaceStateSize
= 0;
132 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
133 sba
.BindlessSamplerStateMOCS
= GENX(MOCS
);
134 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
135 sba
.BindlessSamplerStateBufferSize
= 0;
139 /* After re-setting the surface state base address, we have to do some
140 * cache flusing so that the sampler engine will pick up the new
141 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
142 * Shared Function > 3D Sampler > State > State Caching (page 96):
144 * Coherency with system memory in the state cache, like the texture
145 * cache is handled partially by software. It is expected that the
146 * command stream or shader will issue Cache Flush operation or
147 * Cache_Flush sampler message to ensure that the L1 cache remains
148 * coherent with system memory.
152 * Whenever the value of the Dynamic_State_Base_Addr,
153 * Surface_State_Base_Addr are altered, the L1 state cache must be
154 * invalidated to ensure the new surface or sampler state is fetched
155 * from system memory.
157 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
158 * which, according the PIPE_CONTROL instruction documentation in the
161 * Setting this bit is independent of any other bit in this packet.
162 * This bit controls the invalidation of the L1 and L2 state caches
163 * at the top of the pipe i.e. at the parsing time.
165 * Unfortunately, experimentation seems to indicate that state cache
166 * invalidation through a PIPE_CONTROL does nothing whatsoever in
167 * regards to surface state and binding tables. In stead, it seems that
168 * invalidating the texture cache is what is actually needed.
170 * XXX: As far as we have been able to determine through
171 * experimentation, shows that flush the texture cache appears to be
172 * sufficient. The theory here is that all of the sampling/rendering
173 * units cache the binding table in the texture cache. However, we have
174 * yet to be able to actually confirm this.
176 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
177 pc
.TextureCacheInvalidationEnable
= true;
178 pc
.ConstantCacheInvalidationEnable
= true;
179 pc
.StateCacheInvalidationEnable
= true;
184 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
185 struct anv_state state
, struct anv_address addr
)
187 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
190 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
191 state
.offset
+ isl_dev
->ss
.addr_offset
,
192 addr
.bo
, addr
.offset
);
193 if (result
!= VK_SUCCESS
)
194 anv_batch_set_error(&cmd_buffer
->batch
, result
);
198 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
199 struct anv_surface_state state
)
201 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
203 assert(!anv_address_is_null(state
.address
));
204 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
206 if (!anv_address_is_null(state
.aux_address
)) {
208 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
209 &cmd_buffer
->pool
->alloc
,
210 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
211 state
.aux_address
.bo
, state
.aux_address
.offset
);
212 if (result
!= VK_SUCCESS
)
213 anv_batch_set_error(&cmd_buffer
->batch
, result
);
216 if (!anv_address_is_null(state
.clear_address
)) {
218 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
219 &cmd_buffer
->pool
->alloc
,
221 isl_dev
->ss
.clear_color_state_offset
,
222 state
.clear_address
.bo
, state
.clear_address
.offset
);
223 if (result
!= VK_SUCCESS
)
224 anv_batch_set_error(&cmd_buffer
->batch
, result
);
229 color_attachment_compute_aux_usage(struct anv_device
* device
,
230 struct anv_cmd_state
* cmd_state
,
231 uint32_t att
, VkRect2D render_area
,
232 union isl_color_value
*fast_clear_color
)
234 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
235 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
237 assert(iview
->n_planes
== 1);
239 if (iview
->planes
[0].isl
.base_array_layer
>=
240 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
241 iview
->planes
[0].isl
.base_level
)) {
242 /* There is no aux buffer which corresponds to the level and layer(s)
245 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
246 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
247 att_state
->fast_clear
= false;
251 att_state
->aux_usage
=
252 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
253 VK_IMAGE_ASPECT_COLOR_BIT
,
254 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
256 /* If we don't have aux, then we should have returned early in the layer
257 * check above. If we got here, we must have something.
259 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
261 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
262 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
263 att_state
->input_aux_usage
= att_state
->aux_usage
;
265 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
267 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
268 * setting is only allowed if Surface Format supported for Fast
269 * Clear. In addition, if the surface is bound to the sampling
270 * engine, Surface Format must be supported for Render Target
271 * Compression for surfaces bound to the sampling engine."
273 * In other words, we can only sample from a fast-cleared image if it
274 * also supports color compression.
276 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
277 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
279 /* While fast-clear resolves and partial resolves are fairly cheap in the
280 * case where you render to most of the pixels, full resolves are not
281 * because they potentially involve reading and writing the entire
282 * framebuffer. If we can't texture with CCS_E, we should leave it off and
283 * limit ourselves to fast clears.
285 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
286 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
287 anv_perf_warn(device
->instance
, iview
->image
,
288 "Not temporarily enabling CCS_E.");
291 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
295 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
296 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
298 union isl_color_value clear_color
= {};
299 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
301 att_state
->clear_color_is_zero_one
=
302 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
303 att_state
->clear_color_is_zero
=
304 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
306 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
307 /* Start by getting the fast clear type. We use the first subpass
308 * layout here because we don't want to fast-clear if the first subpass
309 * to use the attachment can't handle fast-clears.
311 enum anv_fast_clear_type fast_clear_type
=
312 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
313 VK_IMAGE_ASPECT_COLOR_BIT
,
314 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
315 switch (fast_clear_type
) {
316 case ANV_FAST_CLEAR_NONE
:
317 att_state
->fast_clear
= false;
319 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
320 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
322 case ANV_FAST_CLEAR_ANY
:
323 att_state
->fast_clear
= true;
327 /* Potentially, we could do partial fast-clears but doing so has crazy
328 * alignment restrictions. It's easier to just restrict to full size
329 * fast clears for now.
331 if (render_area
.offset
.x
!= 0 ||
332 render_area
.offset
.y
!= 0 ||
333 render_area
.extent
.width
!= iview
->extent
.width
||
334 render_area
.extent
.height
!= iview
->extent
.height
)
335 att_state
->fast_clear
= false;
337 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
338 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
339 att_state
->fast_clear
= false;
341 /* We only allow fast clears to the first slice of an image (level 0,
342 * layer 0) and only for the entire slice. This guarantees us that, at
343 * any given time, there is only one clear color on any given image at
344 * any given time. At the time of our testing (Jan 17, 2018), there
345 * were no known applications which would benefit from fast-clearing
346 * more than just the first slice.
348 if (att_state
->fast_clear
&&
349 (iview
->planes
[0].isl
.base_level
> 0 ||
350 iview
->planes
[0].isl
.base_array_layer
> 0)) {
351 anv_perf_warn(device
->instance
, iview
->image
,
352 "Rendering with multi-lod or multi-layer framebuffer "
353 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
354 "baseArrayLayer > 0. Not fast clearing.");
355 att_state
->fast_clear
= false;
356 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
357 anv_perf_warn(device
->instance
, iview
->image
,
358 "Rendering to a multi-layer framebuffer with "
359 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
362 if (att_state
->fast_clear
)
363 *fast_clear_color
= clear_color
;
365 att_state
->fast_clear
= false;
370 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
371 struct anv_cmd_state
*cmd_state
,
372 uint32_t att
, VkRect2D render_area
)
374 struct anv_render_pass_attachment
*pass_att
=
375 &cmd_state
->pass
->attachments
[att
];
376 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
377 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
379 /* These will be initialized after the first subpass transition. */
380 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
381 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
384 /* We don't do any HiZ or depth fast-clears on gen7 yet */
385 att_state
->fast_clear
= false;
389 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
390 /* If we're just clearing stencil, we can always HiZ clear */
391 att_state
->fast_clear
= true;
395 /* Default to false for now */
396 att_state
->fast_clear
= false;
398 /* We must have depth in order to have HiZ */
399 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
402 const enum isl_aux_usage first_subpass_aux_usage
=
403 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
404 VK_IMAGE_ASPECT_DEPTH_BIT
,
405 pass_att
->first_subpass_layout
);
406 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
409 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
410 iview
->planes
[0].isl
.format
,
411 iview
->image
->samples
,
412 render_area
.offset
.x
,
413 render_area
.offset
.y
,
414 render_area
.offset
.x
+
415 render_area
.extent
.width
,
416 render_area
.offset
.y
+
417 render_area
.extent
.height
))
420 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
423 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
424 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
425 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
426 * only supports returning 0.0f. Gens prior to gen8 do not support this
432 /* If we got here, then we can fast clear */
433 att_state
->fast_clear
= true;
437 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
439 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
442 /* We only allocate input attachment states for color surfaces. Compression
443 * is not yet enabled for depth textures and stencil doesn't allow
444 * compression so we can just use the texture surface state from the view.
446 return vk_format_is_color(att
->format
);
449 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
450 * the initial layout is undefined, the HiZ buffer and depth buffer will
451 * represent the same data at the end of this operation.
454 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
455 const struct anv_image
*image
,
456 VkImageLayout initial_layout
,
457 VkImageLayout final_layout
)
459 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
460 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
461 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
462 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
463 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
464 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
466 enum isl_aux_op hiz_op
;
467 if (hiz_enabled
&& !enable_hiz
) {
468 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
469 } else if (!hiz_enabled
&& enable_hiz
) {
470 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
472 assert(hiz_enabled
== enable_hiz
);
473 /* If the same buffer will be used, no resolves are necessary. */
474 hiz_op
= ISL_AUX_OP_NONE
;
477 if (hiz_op
!= ISL_AUX_OP_NONE
)
478 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
482 #define MI_PREDICATE_SRC0 0x2400
483 #define MI_PREDICATE_SRC1 0x2408
486 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
487 const struct anv_image
*image
,
488 VkImageAspectFlagBits aspect
,
490 uint32_t base_layer
, uint32_t layer_count
,
493 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
495 /* We only have compression tracking for CCS_E */
496 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
499 for (uint32_t a
= 0; a
< layer_count
; a
++) {
500 uint32_t layer
= base_layer
+ a
;
501 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
502 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
505 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
511 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
512 const struct anv_image
*image
,
513 VkImageAspectFlagBits aspect
,
514 enum anv_fast_clear_type fast_clear
)
516 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
517 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
519 sdi
.ImmediateData
= fast_clear
;
522 /* Whenever we have fast-clear, we consider that slice to be compressed.
523 * This makes building predicates much easier.
525 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
526 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
529 #if GEN_IS_HASWELL || GEN_GEN >= 8
530 static inline uint32_t
531 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
533 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
535 .Operand1
= operand1
,
536 .Operand2
= operand2
,
540 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
546 #define CS_GPR(n) (0x2600 + (n) * 8)
548 /* This is only really practical on haswell and above because it requires
549 * MI math in order to get it correct.
551 #if GEN_GEN >= 8 || GEN_IS_HASWELL
553 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
554 const struct anv_image
*image
,
555 VkImageAspectFlagBits aspect
,
556 uint32_t level
, uint32_t array_layer
,
557 enum isl_aux_op resolve_op
,
558 enum anv_fast_clear_type fast_clear_supported
)
560 struct anv_address fast_clear_type_addr
=
561 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
563 /* Name some registers */
564 const int image_fc_reg
= MI_ALU_REG0
;
565 const int fc_imm_reg
= MI_ALU_REG1
;
566 const int pred_reg
= MI_ALU_REG2
;
570 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
571 /* In this case, we're doing a full resolve which means we want the
572 * resolve to happen if any compression (including fast-clears) is
575 * In order to simplify the logic a bit, we make the assumption that,
576 * if the first slice has been fast-cleared, it is also marked as
577 * compressed. See also set_image_fast_clear_state.
579 struct anv_address compression_state_addr
=
580 anv_image_get_compression_state_addr(cmd_buffer
->device
, image
,
581 aspect
, level
, array_layer
);
582 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
583 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
584 lrm
.MemoryAddress
= compression_state_addr
;
586 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
587 sdi
.Address
= compression_state_addr
;
588 sdi
.ImmediateData
= 0;
591 if (level
== 0 && array_layer
== 0) {
592 /* If the predicate is true, we want to write 0 to the fast clear type
593 * and, if it's false, leave it alone. We can do this by writing
595 * clear_type = clear_type & ~predicate;
597 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
598 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
599 lrm
.MemoryAddress
= fast_clear_type_addr
;
601 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
602 lrr
.DestinationRegisterAddress
= CS_GPR(pred_reg
);
603 lrr
.SourceRegisterAddress
= MI_PREDICATE_SRC0
;
606 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
607 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
608 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
609 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
610 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
612 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
613 srm
.MemoryAddress
= fast_clear_type_addr
;
614 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
617 } else if (level
== 0 && array_layer
== 0) {
618 /* In this case, we are doing a partial resolve to get rid of fast-clear
619 * colors. We don't care about the compression state but we do care
620 * about how much fast clear is allowed by the final layout.
622 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
623 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
625 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
626 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
627 lrm
.MemoryAddress
= fast_clear_type_addr
;
629 emit_lri(&cmd_buffer
->batch
, CS_GPR(image_fc_reg
) + 4, 0);
631 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
), fast_clear_supported
);
632 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
) + 4, 0);
634 /* We need to compute (fast_clear_supported < image->fast_clear).
635 * We do this by subtracting and storing the carry bit.
637 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
638 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, fc_imm_reg
);
639 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, image_fc_reg
);
640 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
641 dw
[4] = mi_alu(MI_ALU_STORE
, pred_reg
, MI_ALU_CF
);
643 /* Store the predicate */
644 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(pred_reg
));
646 /* If the predicate is true, we want to write 0 to the fast clear type
647 * and, if it's false, leave it alone. We can do this by writing
649 * clear_type = clear_type & ~predicate;
651 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
652 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
653 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
654 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
655 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
657 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
658 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
659 srm
.MemoryAddress
= fast_clear_type_addr
;
662 /* In this case, we're trying to do a partial resolve on a slice that
663 * doesn't have clear color. There's nothing to do.
665 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
669 /* We use the first half of src0 for the actual predicate. Set the second
670 * half of src0 and all of src1 to 0 as the predicate operation will be
671 * doing an implicit src0 != src1.
673 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
674 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
675 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
677 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
678 mip
.LoadOperation
= LOAD_LOADINV
;
679 mip
.CombineOperation
= COMBINE_SET
;
680 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
683 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
687 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
688 const struct anv_image
*image
,
689 VkImageAspectFlagBits aspect
,
690 uint32_t level
, uint32_t array_layer
,
691 enum isl_aux_op resolve_op
,
692 enum anv_fast_clear_type fast_clear_supported
)
694 struct anv_address fast_clear_type_addr
=
695 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
697 /* This only works for partial resolves and only when the clear color is
698 * all or nothing. On the upside, this emits less command streamer code
699 * and works on Ivybridge and Bay Trail.
701 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
702 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
704 /* We don't support fast clears on anything other than the first slice. */
705 if (level
> 0 || array_layer
> 0)
708 /* On gen8, we don't have a concept of default clear colors because we
709 * can't sample from CCS surfaces. It's enough to just load the fast clear
710 * state into the predicate register.
712 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
713 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
714 lrm
.MemoryAddress
= fast_clear_type_addr
;
716 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
717 sdi
.Address
= fast_clear_type_addr
;
718 sdi
.ImmediateData
= 0;
721 /* We use the first half of src0 for the actual predicate. Set the second
722 * half of src0 and all of src1 to 0 as the predicate operation will be
723 * doing an implicit src0 != src1.
725 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
726 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
727 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
729 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
730 mip
.LoadOperation
= LOAD_LOADINV
;
731 mip
.CombineOperation
= COMBINE_SET
;
732 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
735 #endif /* GEN_GEN <= 8 */
738 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
739 const struct anv_image
*image
,
740 VkImageAspectFlagBits aspect
,
741 uint32_t level
, uint32_t array_layer
,
742 enum isl_aux_op resolve_op
,
743 enum anv_fast_clear_type fast_clear_supported
)
745 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
748 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
749 aspect
, level
, array_layer
,
750 resolve_op
, fast_clear_supported
);
751 #else /* GEN_GEN <= 8 */
752 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
753 aspect
, level
, array_layer
,
754 resolve_op
, fast_clear_supported
);
757 /* CCS_D only supports full resolves and BLORP will assert on us if we try
758 * to do a partial resolve on a CCS_D surface.
760 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
761 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
762 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
764 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
765 array_layer
, 1, resolve_op
, NULL
, true);
769 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
770 const struct anv_image
*image
,
771 VkImageAspectFlagBits aspect
,
772 uint32_t array_layer
,
773 enum isl_aux_op resolve_op
,
774 enum anv_fast_clear_type fast_clear_supported
)
776 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
777 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
779 #if GEN_GEN >= 8 || GEN_IS_HASWELL
780 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
781 aspect
, 0, array_layer
,
782 resolve_op
, fast_clear_supported
);
784 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
785 array_layer
, 1, resolve_op
, NULL
, true);
787 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
792 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
793 const struct anv_image
*image
,
794 VkImageAspectFlagBits aspect
,
795 enum isl_aux_usage aux_usage
,
798 uint32_t layer_count
)
800 /* The aspect must be exactly one of the image aspects. */
801 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
803 /* The only compression types with more than just fast-clears are MCS,
804 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
805 * track the current fast-clear and compression state. This leaves us
806 * with just MCS and CCS_E.
808 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
809 aux_usage
!= ISL_AUX_USAGE_MCS
)
812 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
813 level
, base_layer
, layer_count
, true);
817 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
818 const struct anv_image
*image
,
819 VkImageAspectFlagBits aspect
)
821 assert(cmd_buffer
&& image
);
822 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
824 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
825 ANV_FAST_CLEAR_NONE
);
827 /* The fast clear value dword(s) will be copied into a surface state object.
828 * Ensure that the restrictions of the fields in the dword(s) are followed.
830 * CCS buffers on SKL+ can have any value set for the clear colors.
832 if (image
->samples
== 1 && GEN_GEN
>= 9)
835 /* Other combinations of auxiliary buffers and platforms require specific
836 * values in the clear value dword(s).
838 struct anv_address addr
=
839 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
842 for (unsigned i
= 0; i
< 4; i
++) {
843 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
845 sdi
.Address
.offset
+= i
* 4;
846 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
847 assert(image
->samples
> 1);
848 sdi
.ImmediateData
= 0;
852 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
854 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
855 /* Pre-SKL, the dword containing the clear values also contains
856 * other fields, so we need to initialize those fields to match the
857 * values that would be in a color attachment.
859 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
860 ISL_CHANNEL_SELECT_GREEN
<< 22 |
861 ISL_CHANNEL_SELECT_BLUE
<< 19 |
862 ISL_CHANNEL_SELECT_ALPHA
<< 16;
863 } else if (GEN_GEN
== 7) {
864 /* On IVB, the dword containing the clear values also contains
865 * other fields that must be zero or can be zero.
867 sdi
.ImmediateData
= 0;
873 /* Copy the fast-clear value dword(s) between a surface state object and an
874 * image's fast clear state buffer.
877 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
878 struct anv_state surface_state
,
879 const struct anv_image
*image
,
880 VkImageAspectFlagBits aspect
,
881 bool copy_from_surface_state
)
883 assert(cmd_buffer
&& image
);
884 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
886 struct anv_address ss_clear_addr
= {
887 .bo
= &cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
888 .offset
= surface_state
.offset
+
889 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
891 const struct anv_address entry_addr
=
892 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
893 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
895 if (copy_from_surface_state
) {
896 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, entry_addr
,
897 ss_clear_addr
, copy_size
);
899 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, ss_clear_addr
,
900 entry_addr
, copy_size
);
902 /* Updating a surface state object may require that the state cache be
903 * invalidated. From the SKL PRM, Shared Functions -> State -> State
906 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
907 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
908 * modified [...], the L1 state cache must be invalidated to ensure
909 * the new surface or sampler state is fetched from system memory.
911 * In testing, SKL doesn't actually seem to need this, but HSW does.
913 cmd_buffer
->state
.pending_pipe_bits
|=
914 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
919 * @brief Transitions a color buffer from one layout to another.
921 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
924 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
925 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
926 * this represents the maximum layers to transition at each
927 * specified miplevel.
930 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
931 const struct anv_image
*image
,
932 VkImageAspectFlagBits aspect
,
933 const uint32_t base_level
, uint32_t level_count
,
934 uint32_t base_layer
, uint32_t layer_count
,
935 VkImageLayout initial_layout
,
936 VkImageLayout final_layout
)
938 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
939 /* Validate the inputs. */
941 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
942 /* These values aren't supported for simplicity's sake. */
943 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
944 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
945 /* Ensure the subresource range is valid. */
946 uint64_t last_level_num
= base_level
+ level_count
;
947 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
948 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
949 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
950 assert(last_level_num
<= image
->levels
);
951 /* The spec disallows these final layouts. */
952 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
953 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
955 /* No work is necessary if the layout stays the same or if this subresource
956 * range lacks auxiliary data.
958 if (initial_layout
== final_layout
)
961 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
963 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
964 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
965 /* This surface is a linear compressed image with a tiled shadow surface
966 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
967 * we need to ensure the shadow copy is up-to-date.
969 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
970 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
971 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
972 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
974 anv_image_copy_to_shadow(cmd_buffer
, image
,
975 base_level
, level_count
,
976 base_layer
, layer_count
);
979 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
982 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
984 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
985 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
986 /* A subresource in the undefined layout may have been aliased and
987 * populated with any arrangement of bits. Therefore, we must initialize
988 * the related aux buffer and clear buffer entry with desirable values.
989 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
990 * images with VK_IMAGE_TILING_OPTIMAL.
992 * Initialize the relevant clear buffer entries.
994 if (base_level
== 0 && base_layer
== 0)
995 init_fast_clear_color(cmd_buffer
, image
, aspect
);
997 /* Initialize the aux buffers to enable correct rendering. In order to
998 * ensure that things such as storage images work correctly, aux buffers
999 * need to be initialized to valid data.
1001 * Having an aux buffer with invalid data is a problem for two reasons:
1003 * 1) Having an invalid value in the buffer can confuse the hardware.
1004 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1005 * invalid and leads to the hardware doing strange things. It
1006 * doesn't hang as far as we can tell but rendering corruption can
1009 * 2) If this transition is into the GENERAL layout and we then use the
1010 * image as a storage image, then we must have the aux buffer in the
1011 * pass-through state so that, if we then go to texture from the
1012 * image, we get the results of our storage image writes and not the
1013 * fast clear color or other random data.
1015 * For CCS both of the problems above are real demonstrable issues. In
1016 * that case, the only thing we can do is to perform an ambiguate to
1017 * transition the aux surface into the pass-through state.
1019 * For MCS, (2) is never an issue because we don't support multisampled
1020 * storage images. In theory, issue (1) is a problem with MCS but we've
1021 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1022 * theory, be interpreted as something but we don't know that all bit
1023 * patterns are actually valid. For 2x and 8x, you could easily end up
1024 * with the MCS referring to an invalid plane because not all bits of
1025 * the MCS value are actually used. Even though we've never seen issues
1026 * in the wild, it's best to play it safe and initialize the MCS. We
1027 * can use a fast-clear for MCS because we only ever touch from render
1028 * and texture (no image load store).
1030 if (image
->samples
== 1) {
1031 for (uint32_t l
= 0; l
< level_count
; l
++) {
1032 const uint32_t level
= base_level
+ l
;
1034 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1035 if (base_layer
>= aux_layers
)
1036 break; /* We will only get fewer layers as level increases */
1037 uint32_t level_layer_count
=
1038 MIN2(layer_count
, aux_layers
- base_layer
);
1040 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
1041 base_layer
, level_layer_count
,
1042 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1044 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1045 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1046 level
, base_layer
, level_layer_count
,
1051 if (image
->samples
== 4 || image
->samples
== 16) {
1052 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1053 "Doing a potentially unnecessary fast-clear to "
1054 "define an MCS buffer.");
1057 assert(base_level
== 0 && level_count
== 1);
1058 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
1059 base_layer
, layer_count
,
1060 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1065 const enum isl_aux_usage initial_aux_usage
=
1066 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1067 const enum isl_aux_usage final_aux_usage
=
1068 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1070 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1071 * We can handle transitions between CCS_D/E to and from NONE. What we
1072 * don't yet handle is switching between CCS_E and CCS_D within a given
1073 * image. Doing so in a performant way requires more detailed aux state
1074 * tracking such as what is done in i965. For now, just assume that we
1075 * only have one type of compression.
1077 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1078 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1079 initial_aux_usage
== final_aux_usage
);
1081 /* If initial aux usage is NONE, there is nothing to resolve */
1082 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1085 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1087 /* If the initial layout supports more fast clear than the final layout
1088 * then we need at least a partial resolve.
1090 const enum anv_fast_clear_type initial_fast_clear
=
1091 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1092 const enum anv_fast_clear_type final_fast_clear
=
1093 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1094 if (final_fast_clear
< initial_fast_clear
)
1095 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1097 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1098 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1099 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1101 if (resolve_op
== ISL_AUX_OP_NONE
)
1104 /* Perform a resolve to synchronize data between the main and aux buffer.
1105 * Before we begin, we must satisfy the cache flushing requirement specified
1106 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1108 * Any transition from any value in {Clear, Render, Resolve} to a
1109 * different value in {Clear, Render, Resolve} requires end of pipe
1112 * We perform a flush of the write cache before and after the clear and
1113 * resolve operations to meet this requirement.
1115 * Unlike other drawing, fast clear operations are not properly
1116 * synchronized. The first PIPE_CONTROL here likely ensures that the
1117 * contents of the previous render or clear hit the render target before we
1118 * resolve and the second likely ensures that the resolve is complete before
1119 * we do any more rendering or clearing.
1121 cmd_buffer
->state
.pending_pipe_bits
|=
1122 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1124 for (uint32_t l
= 0; l
< level_count
; l
++) {
1125 uint32_t level
= base_level
+ l
;
1127 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1128 if (base_layer
>= aux_layers
)
1129 break; /* We will only get fewer layers as level increases */
1130 uint32_t level_layer_count
=
1131 MIN2(layer_count
, aux_layers
- base_layer
);
1133 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1134 uint32_t array_layer
= base_layer
+ a
;
1135 if (image
->samples
== 1) {
1136 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
, aspect
,
1137 level
, array_layer
, resolve_op
,
1140 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
, aspect
,
1141 array_layer
, resolve_op
,
1147 cmd_buffer
->state
.pending_pipe_bits
|=
1148 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1152 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1155 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1156 struct anv_render_pass
*pass
,
1157 const VkRenderPassBeginInfo
*begin
)
1159 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1160 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1162 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1164 if (pass
->attachment_count
> 0) {
1165 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1166 pass
->attachment_count
*
1167 sizeof(state
->attachments
[0]),
1168 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1169 if (state
->attachments
== NULL
) {
1170 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1171 return anv_batch_set_error(&cmd_buffer
->batch
,
1172 VK_ERROR_OUT_OF_HOST_MEMORY
);
1175 state
->attachments
= NULL
;
1178 /* Reserve one for the NULL state. */
1179 unsigned num_states
= 1;
1180 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1181 if (vk_format_is_color(pass
->attachments
[i
].format
))
1184 if (need_input_attachment_state(&pass
->attachments
[i
]))
1188 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1189 state
->render_pass_states
=
1190 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1191 num_states
* ss_stride
, isl_dev
->ss
.align
);
1193 struct anv_state next_state
= state
->render_pass_states
;
1194 next_state
.alloc_size
= isl_dev
->ss
.size
;
1196 state
->null_surface_state
= next_state
;
1197 next_state
.offset
+= ss_stride
;
1198 next_state
.map
+= ss_stride
;
1200 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1201 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1202 state
->attachments
[i
].color
.state
= next_state
;
1203 next_state
.offset
+= ss_stride
;
1204 next_state
.map
+= ss_stride
;
1207 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1208 state
->attachments
[i
].input
.state
= next_state
;
1209 next_state
.offset
+= ss_stride
;
1210 next_state
.map
+= ss_stride
;
1213 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1214 state
->render_pass_states
.alloc_size
);
1217 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1218 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1220 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1221 isl_extent3d(framebuffer
->width
,
1222 framebuffer
->height
,
1223 framebuffer
->layers
));
1225 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1226 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1227 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1228 VkImageAspectFlags clear_aspects
= 0;
1229 VkImageAspectFlags load_aspects
= 0;
1231 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1232 /* color attachment */
1233 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1234 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1235 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1236 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1239 /* depthstencil attachment */
1240 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1241 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1242 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1243 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1244 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1247 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1248 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1249 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1250 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1251 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1256 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1257 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1258 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1260 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1262 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1263 anv_assert(iview
->vk_format
== att
->format
);
1265 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1266 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1268 union isl_color_value clear_color
= { .u32
= { 0, } };
1269 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1270 anv_assert(iview
->n_planes
== 1);
1271 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1272 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1273 state
, i
, begin
->renderArea
,
1276 anv_image_fill_surface_state(cmd_buffer
->device
,
1278 VK_IMAGE_ASPECT_COLOR_BIT
,
1279 &iview
->planes
[0].isl
,
1280 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1281 state
->attachments
[i
].aux_usage
,
1284 &state
->attachments
[i
].color
,
1287 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1289 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1294 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1295 anv_image_fill_surface_state(cmd_buffer
->device
,
1297 VK_IMAGE_ASPECT_COLOR_BIT
,
1298 &iview
->planes
[0].isl
,
1299 ISL_SURF_USAGE_TEXTURE_BIT
,
1300 state
->attachments
[i
].input_aux_usage
,
1303 &state
->attachments
[i
].input
,
1306 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1315 genX(BeginCommandBuffer
)(
1316 VkCommandBuffer commandBuffer
,
1317 const VkCommandBufferBeginInfo
* pBeginInfo
)
1319 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1321 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1322 * command buffer's state. Otherwise, we must *reset* its state. In both
1323 * cases we reset it.
1325 * From the Vulkan 1.0 spec:
1327 * If a command buffer is in the executable state and the command buffer
1328 * was allocated from a command pool with the
1329 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1330 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1331 * as if vkResetCommandBuffer had been called with
1332 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1333 * the command buffer in the recording state.
1335 anv_cmd_buffer_reset(cmd_buffer
);
1337 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1339 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1340 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1342 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1344 /* We sometimes store vertex data in the dynamic state buffer for blorp
1345 * operations and our dynamic state stream may re-use data from previous
1346 * command buffers. In order to prevent stale cache data, we flush the VF
1347 * cache. We could do this on every blorp call but that's not really
1348 * needed as all of the data will get written by the CPU prior to the GPU
1349 * executing anything. The chances are fairly high that they will use
1350 * blorp at least once per primary command buffer so it shouldn't be
1353 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1354 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1356 /* We send an "Indirect State Pointers Disable" packet at
1357 * EndCommandBuffer, so all push contant packets are ignored during a
1358 * context restore. Documentation says after that command, we need to
1359 * emit push constants again before any rendering operation. So we
1360 * flag them dirty here to make sure they get emitted.
1362 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1364 VkResult result
= VK_SUCCESS
;
1365 if (cmd_buffer
->usage_flags
&
1366 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1367 assert(pBeginInfo
->pInheritanceInfo
);
1368 cmd_buffer
->state
.pass
=
1369 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1370 cmd_buffer
->state
.subpass
=
1371 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1373 /* This is optional in the inheritance info. */
1374 cmd_buffer
->state
.framebuffer
=
1375 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1377 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1378 cmd_buffer
->state
.pass
, NULL
);
1380 /* Record that HiZ is enabled if we can. */
1381 if (cmd_buffer
->state
.framebuffer
) {
1382 const struct anv_image_view
* const iview
=
1383 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1386 VkImageLayout layout
=
1387 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1389 enum isl_aux_usage aux_usage
=
1390 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1391 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1393 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1397 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1403 /* From the PRM, Volume 2a:
1405 * "Indirect State Pointers Disable
1407 * At the completion of the post-sync operation associated with this pipe
1408 * control packet, the indirect state pointers in the hardware are
1409 * considered invalid; the indirect pointers are not saved in the context.
1410 * If any new indirect state commands are executed in the command stream
1411 * while the pipe control is pending, the new indirect state commands are
1414 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1415 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1416 * commands are only considered as Indirect State Pointers. Once ISP is
1417 * issued in a context, SW must initialize by programming push constant
1418 * commands for all the shaders (at least to zero length) before attempting
1419 * any rendering operation for the same context."
1421 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1422 * even though they point to a BO that has been already unreferenced at
1423 * the end of the previous batch buffer. This has been fine so far since
1424 * we are protected by these scratch page (every address not covered by
1425 * a BO should be pointing to the scratch page). But on CNL, it is
1426 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1429 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1430 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1431 * context restore, so the mentioned hang doesn't happen. However,
1432 * software must program push constant commands for all stages prior to
1433 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1435 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1436 * constants have been loaded into the EUs prior to disable the push constants
1437 * so that it doesn't hang a previous 3DPRIMITIVE.
1440 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1442 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1443 pc
.StallAtPixelScoreboard
= true;
1444 pc
.CommandStreamerStallEnable
= true;
1446 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1447 pc
.IndirectStatePointersDisable
= true;
1448 pc
.CommandStreamerStallEnable
= true;
1453 genX(EndCommandBuffer
)(
1454 VkCommandBuffer commandBuffer
)
1456 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1458 if (anv_batch_has_error(&cmd_buffer
->batch
))
1459 return cmd_buffer
->batch
.status
;
1461 /* We want every command buffer to start with the PMA fix in a known state,
1462 * so we disable it at the end of the command buffer.
1464 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1466 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1468 emit_isp_disable(cmd_buffer
);
1470 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1476 genX(CmdExecuteCommands
)(
1477 VkCommandBuffer commandBuffer
,
1478 uint32_t commandBufferCount
,
1479 const VkCommandBuffer
* pCmdBuffers
)
1481 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1483 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1485 if (anv_batch_has_error(&primary
->batch
))
1488 /* The secondary command buffers will assume that the PMA fix is disabled
1489 * when they begin executing. Make sure this is true.
1491 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1493 /* The secondary command buffer doesn't know which textures etc. have been
1494 * flushed prior to their execution. Apply those flushes now.
1496 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1498 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1499 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1501 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1502 assert(!anv_batch_has_error(&secondary
->batch
));
1504 if (secondary
->usage_flags
&
1505 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1506 /* If we're continuing a render pass from the primary, we need to
1507 * copy the surface states for the current subpass into the storage
1508 * we allocated for them in BeginCommandBuffer.
1510 struct anv_bo
*ss_bo
=
1511 &primary
->device
->surface_state_pool
.block_pool
.bo
;
1512 struct anv_state src_state
= primary
->state
.render_pass_states
;
1513 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1514 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1516 genX(cmd_buffer_so_memcpy
)(primary
,
1517 (struct anv_address
) {
1519 .offset
= dst_state
.offset
,
1521 (struct anv_address
) {
1523 .offset
= src_state
.offset
,
1525 src_state
.alloc_size
);
1528 anv_cmd_buffer_add_secondary(primary
, secondary
);
1531 /* The secondary may have selected a different pipeline (3D or compute) and
1532 * may have changed the current L3$ configuration. Reset our tracking
1533 * variables to invalid values to ensure that we re-emit these in the case
1534 * where we do any draws or compute dispatches from the primary after the
1535 * secondary has returned.
1537 primary
->state
.current_pipeline
= UINT32_MAX
;
1538 primary
->state
.current_l3_config
= NULL
;
1540 /* Each of the secondary command buffers will use its own state base
1541 * address. We need to re-emit state base address for the primary after
1542 * all of the secondaries are done.
1544 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1547 genX(cmd_buffer_emit_state_base_address
)(primary
);
1550 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1551 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1552 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1555 * Program the hardware to use the specified L3 configuration.
1558 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1559 const struct gen_l3_config
*cfg
)
1562 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1565 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1566 intel_logd("L3 config transition: ");
1567 gen_dump_l3_config(cfg
, stderr
);
1570 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1572 /* According to the hardware docs, the L3 partitioning can only be changed
1573 * while the pipeline is completely drained and the caches are flushed,
1574 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1576 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1577 pc
.DCFlushEnable
= true;
1578 pc
.PostSyncOperation
= NoWrite
;
1579 pc
.CommandStreamerStallEnable
= true;
1582 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1583 * invalidation of the relevant caches. Note that because RO invalidation
1584 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1585 * command is processed by the CS) we cannot combine it with the previous
1586 * stalling flush as the hardware documentation suggests, because that
1587 * would cause the CS to stall on previous rendering *after* RO
1588 * invalidation and wouldn't prevent the RO caches from being polluted by
1589 * concurrent rendering before the stall completes. This intentionally
1590 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1591 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1592 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1593 * already guarantee that there is no concurrent GPGPU kernel execution
1594 * (see SKL HSD 2132585).
1596 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1597 pc
.TextureCacheInvalidationEnable
= true;
1598 pc
.ConstantCacheInvalidationEnable
= true;
1599 pc
.InstructionCacheInvalidateEnable
= true;
1600 pc
.StateCacheInvalidationEnable
= true;
1601 pc
.PostSyncOperation
= NoWrite
;
1604 /* Now send a third stalling flush to make sure that invalidation is
1605 * complete when the L3 configuration registers are modified.
1607 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1608 pc
.DCFlushEnable
= true;
1609 pc
.PostSyncOperation
= NoWrite
;
1610 pc
.CommandStreamerStallEnable
= true;
1615 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1618 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1619 .SLMEnable
= has_slm
,
1621 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1622 * in L3CNTLREG register. The default setting of the bit is not the
1623 * desirable behavior.
1625 .ErrorDetectionBehaviorControl
= true,
1626 .UseFullWays
= true,
1628 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1629 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1630 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1631 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1633 /* Set up the L3 partitioning. */
1634 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1638 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1639 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1640 cfg
->n
[GEN_L3P_ALL
];
1641 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1642 cfg
->n
[GEN_L3P_ALL
];
1643 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1644 cfg
->n
[GEN_L3P_ALL
];
1646 assert(!cfg
->n
[GEN_L3P_ALL
]);
1648 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1649 * the matching space on the remaining banks has to be allocated to a
1650 * client (URB for all validated configurations) set to the
1651 * lower-bandwidth 2-bank address hashing mode.
1653 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1654 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1655 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1657 /* Minimum number of ways that can be allocated to the URB. */
1658 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1659 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1661 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1662 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1663 .ConvertDC_UC
= !has_dc
,
1664 .ConvertIS_UC
= !has_is
,
1665 .ConvertC_UC
= !has_c
,
1666 .ConvertT_UC
= !has_t
);
1668 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1669 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1670 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1672 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1673 .SLMEnable
= has_slm
,
1674 .URBLowBandwidth
= urb_low_bw
,
1675 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1677 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1679 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1680 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1682 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1683 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1684 .ISLowBandwidth
= 0,
1685 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1687 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1688 .TLowBandwidth
= 0);
1690 /* Set up the L3 partitioning. */
1691 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1692 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1693 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1696 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1697 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1698 * them disabled to avoid crashing the system hard.
1700 uint32_t scratch1
, chicken3
;
1701 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1702 .L3AtomicDisable
= !has_dc
);
1703 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1704 .L3AtomicDisableMask
= true,
1705 .L3AtomicDisable
= !has_dc
);
1706 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1707 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1713 cmd_buffer
->state
.current_l3_config
= cfg
;
1717 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1719 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1721 /* Flushes are pipelined while invalidations are handled immediately.
1722 * Therefore, if we're flushing anything then we need to schedule a stall
1723 * before any invalidations can happen.
1725 if (bits
& ANV_PIPE_FLUSH_BITS
)
1726 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1728 /* If we're going to do an invalidate and we have a pending CS stall that
1729 * has yet to be resolved, we do the CS stall now.
1731 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1732 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1733 bits
|= ANV_PIPE_CS_STALL_BIT
;
1734 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1737 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1738 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1739 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1740 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1741 pipe
.RenderTargetCacheFlushEnable
=
1742 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1744 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1745 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1746 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1749 * According to the Broadwell documentation, any PIPE_CONTROL with the
1750 * "Command Streamer Stall" bit set must also have another bit set,
1751 * with five different options:
1753 * - Render Target Cache Flush
1754 * - Depth Cache Flush
1755 * - Stall at Pixel Scoreboard
1756 * - Post-Sync Operation
1760 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1761 * mesa and it seems to work fine. The choice is fairly arbitrary.
1763 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1764 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1765 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1766 pipe
.StallAtPixelScoreboard
= true;
1769 /* If a render target flush was emitted, then we can toggle off the bit
1770 * saying that render target writes are ongoing.
1772 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
1773 bits
&= ~(ANV_PIPE_RENDER_TARGET_WRITES
);
1775 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1778 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1779 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1781 * "If the VF Cache Invalidation Enable is set to a 1 in a
1782 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1783 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1784 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1787 * This appears to hang Broadwell, so we restrict it to just gen9.
1789 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1790 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1792 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1793 pipe
.StateCacheInvalidationEnable
=
1794 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1795 pipe
.ConstantCacheInvalidationEnable
=
1796 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1797 pipe
.VFCacheInvalidationEnable
=
1798 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1799 pipe
.TextureCacheInvalidationEnable
=
1800 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1801 pipe
.InstructionCacheInvalidateEnable
=
1802 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1804 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1806 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1807 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1808 * “Write Timestamp”.
1810 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1811 pipe
.PostSyncOperation
= WriteImmediateData
;
1813 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1817 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1820 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1823 void genX(CmdPipelineBarrier
)(
1824 VkCommandBuffer commandBuffer
,
1825 VkPipelineStageFlags srcStageMask
,
1826 VkPipelineStageFlags destStageMask
,
1828 uint32_t memoryBarrierCount
,
1829 const VkMemoryBarrier
* pMemoryBarriers
,
1830 uint32_t bufferMemoryBarrierCount
,
1831 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1832 uint32_t imageMemoryBarrierCount
,
1833 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1835 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1837 /* XXX: Right now, we're really dumb and just flush whatever categories
1838 * the app asks for. One of these days we may make this a bit better
1839 * but right now that's all the hardware allows for in most areas.
1841 VkAccessFlags src_flags
= 0;
1842 VkAccessFlags dst_flags
= 0;
1844 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1845 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1846 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1849 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1850 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1851 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1854 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1855 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1856 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1857 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1858 const VkImageSubresourceRange
*range
=
1859 &pImageMemoryBarriers
[i
].subresourceRange
;
1861 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1862 transition_depth_buffer(cmd_buffer
, image
,
1863 pImageMemoryBarriers
[i
].oldLayout
,
1864 pImageMemoryBarriers
[i
].newLayout
);
1865 } else if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1866 VkImageAspectFlags color_aspects
=
1867 anv_image_expand_aspects(image
, range
->aspectMask
);
1868 uint32_t aspect_bit
;
1870 uint32_t base_layer
, layer_count
;
1871 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1873 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1875 base_layer
= range
->baseArrayLayer
;
1876 layer_count
= anv_get_layerCount(image
, range
);
1879 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1880 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1881 range
->baseMipLevel
,
1882 anv_get_levelCount(image
, range
),
1883 base_layer
, layer_count
,
1884 pImageMemoryBarriers
[i
].oldLayout
,
1885 pImageMemoryBarriers
[i
].newLayout
);
1890 cmd_buffer
->state
.pending_pipe_bits
|=
1891 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1892 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1896 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1898 VkShaderStageFlags stages
=
1899 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1901 /* In order to avoid thrash, we assume that vertex and fragment stages
1902 * always exist. In the rare case where one is missing *and* the other
1903 * uses push concstants, this may be suboptimal. However, avoiding stalls
1904 * seems more important.
1906 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1908 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1912 const unsigned push_constant_kb
= 32;
1913 #elif GEN_IS_HASWELL
1914 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1916 const unsigned push_constant_kb
= 16;
1919 const unsigned num_stages
=
1920 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1921 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1923 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1924 * units of 2KB. Incidentally, these are the same platforms that have
1925 * 32KB worth of push constant space.
1927 if (push_constant_kb
== 32)
1928 size_per_stage
&= ~1u;
1930 uint32_t kb_used
= 0;
1931 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1932 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1933 anv_batch_emit(&cmd_buffer
->batch
,
1934 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1935 alloc
._3DCommandSubOpcode
= 18 + i
;
1936 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1937 alloc
.ConstantBufferSize
= push_size
;
1939 kb_used
+= push_size
;
1942 anv_batch_emit(&cmd_buffer
->batch
,
1943 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1944 alloc
.ConstantBufferOffset
= kb_used
;
1945 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1948 cmd_buffer
->state
.push_constant_stages
= stages
;
1950 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1952 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1953 * the next 3DPRIMITIVE command after programming the
1954 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1956 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1957 * pipeline setup, we need to dirty push constants.
1959 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1962 static const struct anv_descriptor
*
1963 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1964 const struct anv_pipeline_binding
*binding
)
1966 assert(binding
->set
< MAX_SETS
);
1967 const struct anv_descriptor_set
*set
=
1968 pipe_state
->descriptors
[binding
->set
];
1969 const uint32_t offset
=
1970 set
->layout
->binding
[binding
->binding
].descriptor_index
;
1971 return &set
->descriptors
[offset
+ binding
->index
];
1975 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1976 const struct anv_pipeline_binding
*binding
)
1978 assert(binding
->set
< MAX_SETS
);
1979 const struct anv_descriptor_set
*set
=
1980 pipe_state
->descriptors
[binding
->set
];
1982 uint32_t dynamic_offset_idx
=
1983 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
1984 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1987 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
1991 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1992 gl_shader_stage stage
,
1993 struct anv_state
*bt_state
)
1995 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1996 struct anv_cmd_pipeline_state
*pipe_state
;
1997 struct anv_pipeline
*pipeline
;
1998 uint32_t bias
, state_offset
;
2001 case MESA_SHADER_COMPUTE
:
2002 pipe_state
= &cmd_buffer
->state
.compute
.base
;
2006 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
2010 pipeline
= pipe_state
->pipeline
;
2012 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2013 *bt_state
= (struct anv_state
) { 0, };
2017 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2018 if (bias
+ map
->surface_count
== 0) {
2019 *bt_state
= (struct anv_state
) { 0, };
2023 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2024 bias
+ map
->surface_count
,
2026 uint32_t *bt_map
= bt_state
->map
;
2028 if (bt_state
->map
== NULL
)
2029 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2031 if (stage
== MESA_SHADER_COMPUTE
&&
2032 get_cs_prog_data(pipeline
)->uses_num_work_groups
) {
2033 struct anv_state surface_state
;
2035 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2037 const enum isl_format format
=
2038 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2039 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2041 cmd_buffer
->state
.compute
.num_workgroups
,
2044 bt_map
[0] = surface_state
.offset
+ state_offset
;
2045 add_surface_reloc(cmd_buffer
, surface_state
,
2046 cmd_buffer
->state
.compute
.num_workgroups
);
2049 if (map
->surface_count
== 0)
2052 if (map
->image_count
> 0) {
2054 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
2055 if (result
!= VK_SUCCESS
)
2058 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
2062 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2063 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2065 struct anv_state surface_state
;
2067 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2068 /* Color attachment binding */
2069 assert(stage
== MESA_SHADER_FRAGMENT
);
2070 assert(binding
->binding
== 0);
2071 if (binding
->index
< subpass
->color_count
) {
2072 const unsigned att
=
2073 subpass
->color_attachments
[binding
->index
].attachment
;
2075 /* From the Vulkan 1.0.46 spec:
2077 * "If any color or depth/stencil attachments are
2078 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2081 if (att
== VK_ATTACHMENT_UNUSED
) {
2082 surface_state
= cmd_buffer
->state
.null_surface_state
;
2084 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2087 surface_state
= cmd_buffer
->state
.null_surface_state
;
2090 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2092 } else if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2093 struct anv_state surface_state
=
2094 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2096 struct anv_address constant_data
= {
2097 .bo
= &pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2098 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2100 unsigned constant_data_size
=
2101 pipeline
->shaders
[stage
]->constant_data_size
;
2103 const enum isl_format format
=
2104 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2105 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2106 surface_state
, format
,
2107 constant_data
, constant_data_size
, 1);
2109 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2110 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2114 const struct anv_descriptor
*desc
=
2115 anv_descriptor_for_binding(pipe_state
, binding
);
2117 switch (desc
->type
) {
2118 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2119 /* Nothing for us to do here */
2122 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2123 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2124 struct anv_surface_state sstate
=
2125 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2126 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2127 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2128 surface_state
= sstate
.state
;
2129 assert(surface_state
.alloc_size
);
2130 add_surface_state_relocs(cmd_buffer
, sstate
);
2133 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2134 assert(stage
== MESA_SHADER_FRAGMENT
);
2135 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2136 /* For depth and stencil input attachments, we treat it like any
2137 * old texture that a user may have bound.
2139 struct anv_surface_state sstate
=
2140 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2141 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2142 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2143 surface_state
= sstate
.state
;
2144 assert(surface_state
.alloc_size
);
2145 add_surface_state_relocs(cmd_buffer
, sstate
);
2147 /* For color input attachments, we create the surface state at
2148 * vkBeginRenderPass time so that we can include aux and clear
2149 * color information.
2151 assert(binding
->input_attachment_index
< subpass
->input_count
);
2152 const unsigned subpass_att
= binding
->input_attachment_index
;
2153 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2154 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2158 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2159 struct anv_surface_state sstate
= (binding
->write_only
)
2160 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2161 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2162 surface_state
= sstate
.state
;
2163 assert(surface_state
.alloc_size
);
2164 add_surface_state_relocs(cmd_buffer
, sstate
);
2166 struct brw_image_param
*image_param
=
2167 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2169 *image_param
= desc
->image_view
->planes
[binding
->plane
].storage_image_param
;
2173 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2174 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2175 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2176 surface_state
= desc
->buffer_view
->surface_state
;
2177 assert(surface_state
.alloc_size
);
2178 add_surface_reloc(cmd_buffer
, surface_state
,
2179 desc
->buffer_view
->address
);
2182 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2183 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2184 /* Compute the offset within the buffer */
2185 uint32_t dynamic_offset
=
2186 dynamic_offset_for_binding(pipe_state
, binding
);
2187 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2188 /* Clamp to the buffer size */
2189 offset
= MIN2(offset
, desc
->buffer
->size
);
2190 /* Clamp the range to the buffer size */
2191 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2193 struct anv_address address
=
2194 anv_address_add(desc
->buffer
->address
, offset
);
2197 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2198 enum isl_format format
=
2199 anv_isl_format_for_descriptor_type(desc
->type
);
2201 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2202 format
, address
, range
, 1);
2203 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2207 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2208 surface_state
= (binding
->write_only
)
2209 ? desc
->buffer_view
->writeonly_storage_surface_state
2210 : desc
->buffer_view
->storage_surface_state
;
2211 assert(surface_state
.alloc_size
);
2212 add_surface_reloc(cmd_buffer
, surface_state
,
2213 desc
->buffer_view
->address
);
2215 struct brw_image_param
*image_param
=
2216 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2218 *image_param
= desc
->buffer_view
->storage_image_param
;
2222 assert(!"Invalid descriptor type");
2226 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2228 assert(image
== map
->image_count
);
2231 anv_state_flush(cmd_buffer
->device
, *bt_state
);
2234 /* The PIPE_CONTROL command description says:
2236 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2237 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2238 * Target Cache Flush by enabling this bit. When render target flush
2239 * is set due to new association of BTI, PS Scoreboard Stall bit must
2240 * be set in this packet."
2242 * FINISHME: Currently we shuffle around the surface states in the binding
2243 * table based on if they are getting used or not. So, we've to do below
2244 * pipe control flush for every binding table upload. Make changes so
2245 * that we do it only when we modify render target surface states.
2247 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2248 pc
.RenderTargetCacheFlushEnable
= true;
2249 pc
.StallAtPixelScoreboard
= true;
2257 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2258 gl_shader_stage stage
,
2259 struct anv_state
*state
)
2261 struct anv_cmd_pipeline_state
*pipe_state
=
2262 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2263 &cmd_buffer
->state
.gfx
.base
;
2264 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2266 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2267 *state
= (struct anv_state
) { 0, };
2271 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2272 if (map
->sampler_count
== 0) {
2273 *state
= (struct anv_state
) { 0, };
2277 uint32_t size
= map
->sampler_count
* 16;
2278 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2280 if (state
->map
== NULL
)
2281 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2283 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2284 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2285 const struct anv_descriptor
*desc
=
2286 anv_descriptor_for_binding(pipe_state
, binding
);
2288 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2289 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2292 struct anv_sampler
*sampler
= desc
->sampler
;
2294 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2295 * happens to be zero.
2297 if (sampler
== NULL
)
2300 memcpy(state
->map
+ (s
* 16),
2301 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2304 anv_state_flush(cmd_buffer
->device
, *state
);
2310 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2312 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2314 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2315 pipeline
->active_stages
;
2317 VkResult result
= VK_SUCCESS
;
2318 anv_foreach_stage(s
, dirty
) {
2319 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2320 if (result
!= VK_SUCCESS
)
2322 result
= emit_binding_table(cmd_buffer
, s
,
2323 &cmd_buffer
->state
.binding_tables
[s
]);
2324 if (result
!= VK_SUCCESS
)
2328 if (result
!= VK_SUCCESS
) {
2329 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2331 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2332 if (result
!= VK_SUCCESS
)
2335 /* Re-emit state base addresses so we get the new surface state base
2336 * address before we start emitting binding tables etc.
2338 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2340 /* Re-emit all active binding tables */
2341 dirty
|= pipeline
->active_stages
;
2342 anv_foreach_stage(s
, dirty
) {
2343 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2344 if (result
!= VK_SUCCESS
) {
2345 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2348 result
= emit_binding_table(cmd_buffer
, s
,
2349 &cmd_buffer
->state
.binding_tables
[s
]);
2350 if (result
!= VK_SUCCESS
) {
2351 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2357 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2363 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2366 static const uint32_t sampler_state_opcodes
[] = {
2367 [MESA_SHADER_VERTEX
] = 43,
2368 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2369 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2370 [MESA_SHADER_GEOMETRY
] = 46,
2371 [MESA_SHADER_FRAGMENT
] = 47,
2372 [MESA_SHADER_COMPUTE
] = 0,
2375 static const uint32_t binding_table_opcodes
[] = {
2376 [MESA_SHADER_VERTEX
] = 38,
2377 [MESA_SHADER_TESS_CTRL
] = 39,
2378 [MESA_SHADER_TESS_EVAL
] = 40,
2379 [MESA_SHADER_GEOMETRY
] = 41,
2380 [MESA_SHADER_FRAGMENT
] = 42,
2381 [MESA_SHADER_COMPUTE
] = 0,
2384 anv_foreach_stage(s
, stages
) {
2385 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2386 assert(binding_table_opcodes
[s
] > 0);
2388 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2389 anv_batch_emit(&cmd_buffer
->batch
,
2390 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2391 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2392 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2396 /* Always emit binding table pointers if we're asked to, since on SKL
2397 * this is what flushes push constants. */
2398 anv_batch_emit(&cmd_buffer
->batch
,
2399 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2400 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2401 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2407 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2408 VkShaderStageFlags dirty_stages
)
2410 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2411 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2413 static const uint32_t push_constant_opcodes
[] = {
2414 [MESA_SHADER_VERTEX
] = 21,
2415 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2416 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2417 [MESA_SHADER_GEOMETRY
] = 22,
2418 [MESA_SHADER_FRAGMENT
] = 23,
2419 [MESA_SHADER_COMPUTE
] = 0,
2422 VkShaderStageFlags flushed
= 0;
2424 anv_foreach_stage(stage
, dirty_stages
) {
2425 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2426 assert(push_constant_opcodes
[stage
] > 0);
2428 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2429 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2431 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2432 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2433 const struct brw_stage_prog_data
*prog_data
=
2434 pipeline
->shaders
[stage
]->prog_data
;
2435 const struct anv_pipeline_bind_map
*bind_map
=
2436 &pipeline
->shaders
[stage
]->bind_map
;
2438 /* The Skylake PRM contains the following restriction:
2440 * "The driver must ensure The following case does not occur
2441 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2442 * buffer 3 read length equal to zero committed followed by a
2443 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2446 * To avoid this, we program the buffers in the highest slots.
2447 * This way, slot 0 is only used if slot 3 is also used.
2451 for (int i
= 3; i
>= 0; i
--) {
2452 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2453 if (range
->length
== 0)
2456 const unsigned surface
=
2457 prog_data
->binding_table
.ubo_start
+ range
->block
;
2459 assert(surface
<= bind_map
->surface_count
);
2460 const struct anv_pipeline_binding
*binding
=
2461 &bind_map
->surface_to_descriptor
[surface
];
2463 struct anv_address read_addr
;
2465 if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2466 struct anv_address constant_data
= {
2467 .bo
= &pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2468 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2470 unsigned constant_data_size
=
2471 pipeline
->shaders
[stage
]->constant_data_size
;
2473 read_len
= MIN2(range
->length
,
2474 DIV_ROUND_UP(constant_data_size
, 32) - range
->start
);
2475 read_addr
= anv_address_add(constant_data
,
2478 const struct anv_descriptor
*desc
=
2479 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2481 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2482 read_len
= MIN2(range
->length
,
2483 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2484 read_addr
= anv_address_add(desc
->buffer_view
->address
,
2487 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2489 uint32_t dynamic_offset
=
2490 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2491 uint32_t buf_offset
=
2492 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2493 uint32_t buf_range
=
2494 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2496 read_len
= MIN2(range
->length
,
2497 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2498 read_addr
= anv_address_add(desc
->buffer
->address
,
2499 buf_offset
+ range
->start
* 32);
2504 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2505 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2510 struct anv_state state
=
2511 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2513 if (state
.alloc_size
> 0) {
2514 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2515 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2516 .offset
= state
.offset
,
2518 c
.ConstantBody
.ReadLength
[n
] =
2519 DIV_ROUND_UP(state
.alloc_size
, 32);
2522 /* For Ivy Bridge, the push constants packets have a different
2523 * rule that would require us to iterate in the other direction
2524 * and possibly mess around with dynamic state base address.
2525 * Don't bother; just emit regular push constants at n = 0.
2527 struct anv_state state
=
2528 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2530 if (state
.alloc_size
> 0) {
2531 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2532 c
.ConstantBody
.ReadLength
[0] =
2533 DIV_ROUND_UP(state
.alloc_size
, 32);
2539 flushed
|= mesa_to_vk_shader_stage(stage
);
2542 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2546 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2548 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2551 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2552 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2553 vb_emit
|= pipeline
->vb_used
;
2555 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2557 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2559 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2562 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2563 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2565 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2566 GENX(3DSTATE_VERTEX_BUFFERS
));
2568 for_each_bit(vb
, vb_emit
) {
2569 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2570 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2572 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2573 .VertexBufferIndex
= vb
,
2575 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
2577 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2578 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2581 .AddressModifyEnable
= true,
2582 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2583 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2586 .BufferSize
= buffer
->size
- offset
2588 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2592 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2597 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2599 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2600 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2602 /* The exact descriptor layout is pulled from the pipeline, so we need
2603 * to re-emit binding tables on every pipeline change.
2605 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2607 /* If the pipeline changed, we may need to re-allocate push constant
2610 cmd_buffer_alloc_push_constants(cmd_buffer
);
2614 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2615 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2616 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2618 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2619 * stall needs to be sent just prior to any 3DSTATE_VS,
2620 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2621 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2622 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2623 * PIPE_CONTROL needs to be sent before any combination of VS
2624 * associated 3DSTATE."
2626 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2627 pc
.DepthStallEnable
= true;
2628 pc
.PostSyncOperation
= WriteImmediateData
;
2630 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2635 /* Render targets live in the same binding table as fragment descriptors */
2636 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2637 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2639 /* We emit the binding tables and sampler tables first, then emit push
2640 * constants and then finally emit binding table and sampler table
2641 * pointers. It has to happen in this order, since emitting the binding
2642 * tables may change the push constants (in case of storage images). After
2643 * emitting push constants, on SKL+ we have to emit the corresponding
2644 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2647 if (cmd_buffer
->state
.descriptors_dirty
)
2648 dirty
= flush_descriptor_sets(cmd_buffer
);
2650 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2651 /* Because we're pushing UBOs, we have to push whenever either
2652 * descriptors or push constants is dirty.
2654 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2655 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2656 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2660 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2662 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2663 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2665 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2666 ANV_CMD_DIRTY_PIPELINE
)) {
2667 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2668 pipeline
->depth_clamp_enable
);
2671 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2672 ANV_CMD_DIRTY_RENDER_TARGETS
))
2673 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2675 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2677 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2681 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2682 struct anv_address addr
,
2683 uint32_t size
, uint32_t index
)
2685 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2686 GENX(3DSTATE_VERTEX_BUFFERS
));
2688 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2689 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2690 .VertexBufferIndex
= index
,
2691 .AddressModifyEnable
= true,
2693 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
),
2695 .BufferStartingAddress
= addr
,
2698 .BufferStartingAddress
= addr
,
2699 .EndAddress
= anv_address_add(addr
, size
),
2705 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2706 struct anv_address addr
)
2708 emit_vertex_bo(cmd_buffer
, addr
, 8, ANV_SVGS_VB_INDEX
);
2712 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2713 uint32_t base_vertex
, uint32_t base_instance
)
2715 struct anv_state id_state
=
2716 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2718 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2719 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2721 anv_state_flush(cmd_buffer
->device
, id_state
);
2723 struct anv_address addr
= {
2724 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2725 .offset
= id_state
.offset
,
2728 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2732 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2734 struct anv_state state
=
2735 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2737 ((uint32_t *)state
.map
)[0] = draw_index
;
2739 anv_state_flush(cmd_buffer
->device
, state
);
2741 struct anv_address addr
= {
2742 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2743 .offset
= state
.offset
,
2746 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2750 VkCommandBuffer commandBuffer
,
2751 uint32_t vertexCount
,
2752 uint32_t instanceCount
,
2753 uint32_t firstVertex
,
2754 uint32_t firstInstance
)
2756 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2757 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2758 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2760 if (anv_batch_has_error(&cmd_buffer
->batch
))
2763 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2765 if (vs_prog_data
->uses_firstvertex
||
2766 vs_prog_data
->uses_baseinstance
)
2767 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2768 if (vs_prog_data
->uses_drawid
)
2769 emit_draw_index(cmd_buffer
, 0);
2771 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2772 * different views. We need to multiply instanceCount by the view count.
2774 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2776 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2777 prim
.VertexAccessType
= SEQUENTIAL
;
2778 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2779 prim
.VertexCountPerInstance
= vertexCount
;
2780 prim
.StartVertexLocation
= firstVertex
;
2781 prim
.InstanceCount
= instanceCount
;
2782 prim
.StartInstanceLocation
= firstInstance
;
2783 prim
.BaseVertexLocation
= 0;
2786 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_RENDER_TARGET_WRITES
;
2789 void genX(CmdDrawIndexed
)(
2790 VkCommandBuffer commandBuffer
,
2791 uint32_t indexCount
,
2792 uint32_t instanceCount
,
2793 uint32_t firstIndex
,
2794 int32_t vertexOffset
,
2795 uint32_t firstInstance
)
2797 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2798 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2799 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2801 if (anv_batch_has_error(&cmd_buffer
->batch
))
2804 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2806 if (vs_prog_data
->uses_firstvertex
||
2807 vs_prog_data
->uses_baseinstance
)
2808 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2809 if (vs_prog_data
->uses_drawid
)
2810 emit_draw_index(cmd_buffer
, 0);
2812 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2813 * different views. We need to multiply instanceCount by the view count.
2815 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2817 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2818 prim
.VertexAccessType
= RANDOM
;
2819 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2820 prim
.VertexCountPerInstance
= indexCount
;
2821 prim
.StartVertexLocation
= firstIndex
;
2822 prim
.InstanceCount
= instanceCount
;
2823 prim
.StartInstanceLocation
= firstInstance
;
2824 prim
.BaseVertexLocation
= vertexOffset
;
2827 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_RENDER_TARGET_WRITES
;
2830 /* Auto-Draw / Indirect Registers */
2831 #define GEN7_3DPRIM_END_OFFSET 0x2420
2832 #define GEN7_3DPRIM_START_VERTEX 0x2430
2833 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2834 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2835 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2836 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2838 /* MI_MATH only exists on Haswell+ */
2839 #if GEN_IS_HASWELL || GEN_GEN >= 8
2841 /* Emit dwords to multiply GPR0 by N */
2843 build_alu_multiply_gpr0(uint32_t *dw
, unsigned *dw_count
, uint32_t N
)
2845 VK_OUTARRAY_MAKE(out
, dw
, dw_count
);
2847 #define append_alu(opcode, operand1, operand2) \
2848 vk_outarray_append(&out, alu_dw) *alu_dw = mi_alu(opcode, operand1, operand2)
2851 unsigned top_bit
= 31 - __builtin_clz(N
);
2852 for (int i
= top_bit
- 1; i
>= 0; i
--) {
2853 /* We get our initial data in GPR0 and we write the final data out to
2854 * GPR0 but we use GPR1 as our scratch register.
2856 unsigned src_reg
= i
== top_bit
- 1 ? MI_ALU_REG0
: MI_ALU_REG1
;
2857 unsigned dst_reg
= i
== 0 ? MI_ALU_REG0
: MI_ALU_REG1
;
2859 /* Shift the current value left by 1 */
2860 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, src_reg
);
2861 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, src_reg
);
2862 append_alu(MI_ALU_ADD
, 0, 0);
2865 /* Store ACCU to R1 and add R0 to R1 */
2866 append_alu(MI_ALU_STORE
, MI_ALU_REG1
, MI_ALU_ACCU
);
2867 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
2868 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
2869 append_alu(MI_ALU_ADD
, 0, 0);
2872 append_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2879 emit_mul_gpr0(struct anv_batch
*batch
, uint32_t N
)
2881 uint32_t num_dwords
;
2882 build_alu_multiply_gpr0(NULL
, &num_dwords
, N
);
2884 uint32_t *dw
= anv_batch_emitn(batch
, 1 + num_dwords
, GENX(MI_MATH
));
2885 build_alu_multiply_gpr0(dw
+ 1, &num_dwords
, N
);
2888 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2891 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2892 struct anv_address addr
,
2895 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2897 emit_lrm(batch
, GEN7_3DPRIM_VERTEX_COUNT
, anv_address_add(addr
, 0));
2899 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2900 if (view_count
> 1) {
2901 #if GEN_IS_HASWELL || GEN_GEN >= 8
2902 emit_lrm(batch
, CS_GPR(0), anv_address_add(addr
, 4));
2903 emit_mul_gpr0(batch
, view_count
);
2904 emit_lrr(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, CS_GPR(0));
2906 anv_finishme("Multiview + indirect draw requires MI_MATH; "
2907 "MI_MATH is not supported on Ivy Bridge");
2908 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, anv_address_add(addr
, 4));
2911 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, anv_address_add(addr
, 4));
2914 emit_lrm(batch
, GEN7_3DPRIM_START_VERTEX
, anv_address_add(addr
, 8));
2917 emit_lrm(batch
, GEN7_3DPRIM_BASE_VERTEX
, anv_address_add(addr
, 12));
2918 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, anv_address_add(addr
, 16));
2920 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, anv_address_add(addr
, 12));
2921 emit_lri(batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
2925 void genX(CmdDrawIndirect
)(
2926 VkCommandBuffer commandBuffer
,
2928 VkDeviceSize offset
,
2932 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2933 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2934 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2935 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2937 if (anv_batch_has_error(&cmd_buffer
->batch
))
2940 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2942 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2943 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
2945 if (vs_prog_data
->uses_firstvertex
||
2946 vs_prog_data
->uses_baseinstance
)
2947 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
2948 if (vs_prog_data
->uses_drawid
)
2949 emit_draw_index(cmd_buffer
, i
);
2951 load_indirect_parameters(cmd_buffer
, draw
, false);
2953 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2954 prim
.IndirectParameterEnable
= true;
2955 prim
.VertexAccessType
= SEQUENTIAL
;
2956 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2962 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_RENDER_TARGET_WRITES
;
2965 void genX(CmdDrawIndexedIndirect
)(
2966 VkCommandBuffer commandBuffer
,
2968 VkDeviceSize offset
,
2972 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2973 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2974 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2975 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2977 if (anv_batch_has_error(&cmd_buffer
->batch
))
2980 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2982 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2983 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
2985 /* TODO: We need to stomp base vertex to 0 somehow */
2986 if (vs_prog_data
->uses_firstvertex
||
2987 vs_prog_data
->uses_baseinstance
)
2988 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
2989 if (vs_prog_data
->uses_drawid
)
2990 emit_draw_index(cmd_buffer
, i
);
2992 load_indirect_parameters(cmd_buffer
, draw
, true);
2994 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2995 prim
.IndirectParameterEnable
= true;
2996 prim
.VertexAccessType
= RANDOM
;
2997 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3003 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_RENDER_TARGET_WRITES
;
3007 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
3009 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3010 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
3013 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3014 if (result
!= VK_SUCCESS
) {
3015 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3017 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
3018 if (result
!= VK_SUCCESS
)
3021 /* Re-emit state base addresses so we get the new surface state base
3022 * address before we start emitting binding tables etc.
3024 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
3026 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3027 if (result
!= VK_SUCCESS
) {
3028 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3033 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3034 if (result
!= VK_SUCCESS
) {
3035 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3039 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3040 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3041 .BindingTablePointer
= surfaces
.offset
,
3042 .SamplerStatePointer
= samplers
.offset
,
3044 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3046 struct anv_state state
=
3047 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3048 pipeline
->interface_descriptor_data
,
3049 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3052 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3053 anv_batch_emit(&cmd_buffer
->batch
,
3054 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3055 mid
.InterfaceDescriptorTotalLength
= size
;
3056 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3063 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3065 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3066 MAYBE_UNUSED VkResult result
;
3068 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3070 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3072 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3074 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3075 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3077 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3078 * the only bits that are changed are scoreboard related: Scoreboard
3079 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3080 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3083 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3084 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3086 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3089 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3090 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3091 /* FIXME: figure out descriptors for gen7 */
3092 result
= flush_compute_descriptor_set(cmd_buffer
);
3093 if (result
!= VK_SUCCESS
)
3096 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3099 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3100 struct anv_state push_state
=
3101 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3103 if (push_state
.alloc_size
) {
3104 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3105 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3106 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3110 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3113 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3115 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3121 verify_cmd_parser(const struct anv_device
*device
,
3122 int required_version
,
3123 const char *function
)
3125 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3126 return vk_errorf(device
->instance
, device
->instance
,
3127 VK_ERROR_FEATURE_NOT_PRESENT
,
3128 "cmd parser version %d is required for %s",
3129 required_version
, function
);
3138 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3139 uint32_t baseGroupX
,
3140 uint32_t baseGroupY
,
3141 uint32_t baseGroupZ
)
3143 if (anv_batch_has_error(&cmd_buffer
->batch
))
3147 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, MESA_SHADER_COMPUTE
,
3148 base_work_group_id
);
3149 if (result
!= VK_SUCCESS
) {
3150 cmd_buffer
->batch
.status
= result
;
3154 struct anv_push_constants
*push
=
3155 cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3156 if (push
->base_work_group_id
[0] != baseGroupX
||
3157 push
->base_work_group_id
[1] != baseGroupY
||
3158 push
->base_work_group_id
[2] != baseGroupZ
) {
3159 push
->base_work_group_id
[0] = baseGroupX
;
3160 push
->base_work_group_id
[1] = baseGroupY
;
3161 push
->base_work_group_id
[2] = baseGroupZ
;
3163 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3167 void genX(CmdDispatch
)(
3168 VkCommandBuffer commandBuffer
,
3173 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3176 void genX(CmdDispatchBase
)(
3177 VkCommandBuffer commandBuffer
,
3178 uint32_t baseGroupX
,
3179 uint32_t baseGroupY
,
3180 uint32_t baseGroupZ
,
3181 uint32_t groupCountX
,
3182 uint32_t groupCountY
,
3183 uint32_t groupCountZ
)
3185 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3186 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3187 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3189 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3190 baseGroupY
, baseGroupZ
);
3192 if (anv_batch_has_error(&cmd_buffer
->batch
))
3195 if (prog_data
->uses_num_work_groups
) {
3196 struct anv_state state
=
3197 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3198 uint32_t *sizes
= state
.map
;
3199 sizes
[0] = groupCountX
;
3200 sizes
[1] = groupCountY
;
3201 sizes
[2] = groupCountZ
;
3202 anv_state_flush(cmd_buffer
->device
, state
);
3203 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3204 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3205 .offset
= state
.offset
,
3209 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3211 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3212 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3213 ggw
.ThreadDepthCounterMaximum
= 0;
3214 ggw
.ThreadHeightCounterMaximum
= 0;
3215 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3216 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3217 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3218 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3219 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3220 ggw
.BottomExecutionMask
= 0xffffffff;
3223 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3226 #define GPGPU_DISPATCHDIMX 0x2500
3227 #define GPGPU_DISPATCHDIMY 0x2504
3228 #define GPGPU_DISPATCHDIMZ 0x2508
3230 void genX(CmdDispatchIndirect
)(
3231 VkCommandBuffer commandBuffer
,
3233 VkDeviceSize offset
)
3235 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3236 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3237 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3238 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3239 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3240 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3242 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3245 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3246 * indirect dispatch registers to be written.
3248 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3249 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3253 if (prog_data
->uses_num_work_groups
)
3254 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3256 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3258 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, anv_address_add(addr
, 0));
3259 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, anv_address_add(addr
, 4));
3260 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, anv_address_add(addr
, 8));
3263 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
3264 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
3265 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
3266 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
3268 /* Load compute_dispatch_indirect_x_size into SRC0 */
3269 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 0));
3271 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3272 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3273 mip
.LoadOperation
= LOAD_LOAD
;
3274 mip
.CombineOperation
= COMBINE_SET
;
3275 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3278 /* Load compute_dispatch_indirect_y_size into SRC0 */
3279 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 4));
3281 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3282 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3283 mip
.LoadOperation
= LOAD_LOAD
;
3284 mip
.CombineOperation
= COMBINE_OR
;
3285 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3288 /* Load compute_dispatch_indirect_z_size into SRC0 */
3289 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 8));
3291 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3292 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3293 mip
.LoadOperation
= LOAD_LOAD
;
3294 mip
.CombineOperation
= COMBINE_OR
;
3295 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3298 /* predicate = !predicate; */
3299 #define COMPARE_FALSE 1
3300 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3301 mip
.LoadOperation
= LOAD_LOADINV
;
3302 mip
.CombineOperation
= COMBINE_OR
;
3303 mip
.CompareOperation
= COMPARE_FALSE
;
3307 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3308 ggw
.IndirectParameterEnable
= true;
3309 ggw
.PredicateEnable
= GEN_GEN
<= 7;
3310 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3311 ggw
.ThreadDepthCounterMaximum
= 0;
3312 ggw
.ThreadHeightCounterMaximum
= 0;
3313 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3314 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3315 ggw
.BottomExecutionMask
= 0xffffffff;
3318 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3322 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3325 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3327 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3330 #if GEN_GEN >= 8 && GEN_GEN < 10
3331 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3333 * Software must clear the COLOR_CALC_STATE Valid field in
3334 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3335 * with Pipeline Select set to GPGPU.
3337 * The internal hardware docs recommend the same workaround for Gen9
3340 if (pipeline
== GPGPU
)
3341 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3344 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3345 * PIPELINE_SELECT [DevBWR+]":
3349 * Software must ensure all the write caches are flushed through a
3350 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3351 * command to invalidate read only caches prior to programming
3352 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3354 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3355 pc
.RenderTargetCacheFlushEnable
= true;
3356 pc
.DepthCacheFlushEnable
= true;
3357 pc
.DCFlushEnable
= true;
3358 pc
.PostSyncOperation
= NoWrite
;
3359 pc
.CommandStreamerStallEnable
= true;
3362 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3363 pc
.TextureCacheInvalidationEnable
= true;
3364 pc
.ConstantCacheInvalidationEnable
= true;
3365 pc
.StateCacheInvalidationEnable
= true;
3366 pc
.InstructionCacheInvalidateEnable
= true;
3367 pc
.PostSyncOperation
= NoWrite
;
3370 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3374 ps
.PipelineSelection
= pipeline
;
3378 if (devinfo
->is_geminilake
) {
3381 * "This chicken bit works around a hardware issue with barrier logic
3382 * encountered when switching between GPGPU and 3D pipelines. To
3383 * workaround the issue, this mode bit should be set after a pipeline
3387 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3389 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3390 : GLK_BARRIER_MODE_3D_HULL
,
3391 .GLKBarrierModeMask
= 1);
3392 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3396 cmd_buffer
->state
.current_pipeline
= pipeline
;
3400 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3402 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3406 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3408 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3412 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3417 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3419 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3420 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3421 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3422 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3423 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3424 * Depth Flush Bit set, followed by another pipelined depth stall
3425 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3426 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3427 * via a preceding MI_FLUSH)."
3429 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3430 pipe
.DepthStallEnable
= true;
3432 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3433 pipe
.DepthCacheFlushEnable
= true;
3435 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3436 pipe
.DepthStallEnable
= true;
3441 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3443 struct anv_device
*device
= cmd_buffer
->device
;
3444 const struct anv_image_view
*iview
=
3445 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3446 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3448 /* FIXME: Width and Height are wrong */
3450 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3452 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3453 device
->isl_dev
.ds
.size
/ 4);
3457 struct isl_depth_stencil_hiz_emit_info info
= { };
3460 info
.view
= &iview
->planes
[0].isl
;
3462 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3463 uint32_t depth_plane
=
3464 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3465 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
3467 info
.depth_surf
= &surface
->isl
;
3469 info
.depth_address
=
3470 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3471 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
3472 image
->planes
[depth_plane
].address
.bo
,
3473 image
->planes
[depth_plane
].address
.offset
+
3476 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
3479 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
3480 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
3481 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
3482 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
3485 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3486 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
3487 image
->planes
[depth_plane
].address
.bo
,
3488 image
->planes
[depth_plane
].address
.offset
+
3489 image
->planes
[depth_plane
].aux_surface
.offset
);
3491 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
3495 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3496 uint32_t stencil_plane
=
3497 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
3498 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
3500 info
.stencil_surf
= &surface
->isl
;
3502 info
.stencil_address
=
3503 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3504 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
3505 image
->planes
[stencil_plane
].address
.bo
,
3506 image
->planes
[stencil_plane
].address
.offset
+
3509 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
3512 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
3514 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
3518 * This ANDs the view mask of the current subpass with the pending clear
3519 * views in the attachment to get the mask of views active in the subpass
3520 * that still need to be cleared.
3522 static inline uint32_t
3523 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
3524 const struct anv_attachment_state
*att_state
)
3526 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
3530 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
3531 const struct anv_attachment_state
*att_state
)
3533 if (!cmd_state
->subpass
->view_mask
)
3536 uint32_t pending_clear_mask
=
3537 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3539 return pending_clear_mask
& 1;
3543 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
3546 const uint32_t last_subpass_idx
=
3547 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
3548 const struct anv_subpass
*last_subpass
=
3549 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
3550 return last_subpass
== cmd_state
->subpass
;
3554 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
3555 uint32_t subpass_id
)
3557 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3558 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
3559 cmd_state
->subpass
= subpass
;
3561 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
3563 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3564 * different views. If the client asks for instancing, we need to use the
3565 * Instance Data Step Rate to ensure that we repeat the client's
3566 * per-instance data once for each view. Since this bit is in
3567 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
3571 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
3573 /* It is possible to start a render pass with an old pipeline. Because the
3574 * render pass and subpass index are both baked into the pipeline, this is
3575 * highly unlikely. In order to do so, it requires that you have a render
3576 * pass with a single subpass and that you use that render pass twice
3577 * back-to-back and use the same pipeline at the start of the second render
3578 * pass as at the end of the first. In order to avoid unpredictable issues
3579 * with this edge case, we just dirty the pipeline at the start of every
3582 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
3584 /* Accumulate any subpass flushes that need to happen before the subpass */
3585 cmd_buffer
->state
.pending_pipe_bits
|=
3586 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
3588 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
3589 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3591 bool is_multiview
= subpass
->view_mask
!= 0;
3593 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3594 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3595 if (a
== VK_ATTACHMENT_UNUSED
)
3598 assert(a
< cmd_state
->pass
->attachment_count
);
3599 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3601 struct anv_image_view
*iview
= fb
->attachments
[a
];
3602 const struct anv_image
*image
= iview
->image
;
3604 /* A resolve is necessary before use as an input attachment if the clear
3605 * color or auxiliary buffer usage isn't supported by the sampler.
3607 const bool input_needs_resolve
=
3608 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
3609 att_state
->input_aux_usage
!= att_state
->aux_usage
;
3611 VkImageLayout target_layout
;
3612 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
3613 !input_needs_resolve
) {
3614 /* Layout transitions before the final only help to enable sampling
3615 * as an input attachment. If the input attachment supports sampling
3616 * using the auxiliary surface, we can skip such transitions by
3617 * making the target layout one that is CCS-aware.
3619 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
3621 target_layout
= subpass
->attachments
[i
].layout
;
3624 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3625 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3627 uint32_t base_layer
, layer_count
;
3628 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3630 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3631 iview
->planes
[0].isl
.base_level
);
3633 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3634 layer_count
= fb
->layers
;
3637 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3638 iview
->planes
[0].isl
.base_level
, 1,
3639 base_layer
, layer_count
,
3640 att_state
->current_layout
, target_layout
);
3641 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3642 transition_depth_buffer(cmd_buffer
, image
,
3643 att_state
->current_layout
, target_layout
);
3644 att_state
->aux_usage
=
3645 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
3646 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
3648 att_state
->current_layout
= target_layout
;
3650 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
3651 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3653 /* Multi-planar images are not supported as attachments */
3654 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3655 assert(image
->n_planes
== 1);
3657 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
3658 uint32_t clear_layer_count
= fb
->layers
;
3660 if (att_state
->fast_clear
&&
3661 do_first_layer_clear(cmd_state
, att_state
)) {
3662 /* We only support fast-clears on the first layer */
3663 assert(iview
->planes
[0].isl
.base_level
== 0);
3664 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3666 union isl_color_value clear_color
= {};
3667 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
3668 if (iview
->image
->samples
== 1) {
3669 anv_image_ccs_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3670 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
3674 anv_image_mcs_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3675 0, 1, ISL_AUX_OP_FAST_CLEAR
,
3680 clear_layer_count
--;
3682 att_state
->pending_clear_views
&= ~1;
3684 if (att_state
->clear_color_is_zero
) {
3685 /* This image has the auxiliary buffer enabled. We can mark the
3686 * subresource as not needing a resolve because the clear color
3687 * will match what's in every RENDER_SURFACE_STATE object when
3688 * it's being used for sampling.
3690 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3691 VK_IMAGE_ASPECT_COLOR_BIT
,
3692 ANV_FAST_CLEAR_DEFAULT_VALUE
);
3694 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3695 VK_IMAGE_ASPECT_COLOR_BIT
,
3696 ANV_FAST_CLEAR_ANY
);
3700 /* From the VkFramebufferCreateInfo spec:
3702 * "If the render pass uses multiview, then layers must be one and each
3703 * attachment requires a number of layers that is greater than the
3704 * maximum bit index set in the view mask in the subpasses in which it
3707 * So if multiview is active we ignore the number of layers in the
3708 * framebuffer and instead we honor the view mask from the subpass.
3711 assert(image
->n_planes
== 1);
3712 uint32_t pending_clear_mask
=
3713 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3716 for_each_bit(layer_idx
, pending_clear_mask
) {
3718 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
3720 anv_image_clear_color(cmd_buffer
, image
,
3721 VK_IMAGE_ASPECT_COLOR_BIT
,
3722 att_state
->aux_usage
,
3723 iview
->planes
[0].isl
.format
,
3724 iview
->planes
[0].isl
.swizzle
,
3725 iview
->planes
[0].isl
.base_level
,
3728 vk_to_isl_color(att_state
->clear_value
.color
));
3731 att_state
->pending_clear_views
&= ~pending_clear_mask
;
3732 } else if (clear_layer_count
> 0) {
3733 assert(image
->n_planes
== 1);
3734 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3735 att_state
->aux_usage
,
3736 iview
->planes
[0].isl
.format
,
3737 iview
->planes
[0].isl
.swizzle
,
3738 iview
->planes
[0].isl
.base_level
,
3739 base_clear_layer
, clear_layer_count
,
3741 vk_to_isl_color(att_state
->clear_value
.color
));
3743 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
3744 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3745 if (att_state
->fast_clear
&& !is_multiview
) {
3746 /* We currently only support HiZ for single-layer images */
3747 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3748 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
3749 assert(iview
->planes
[0].isl
.base_level
== 0);
3750 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3751 assert(fb
->layers
== 1);
3754 anv_image_hiz_clear(cmd_buffer
, image
,
3755 att_state
->pending_clear_aspects
,
3756 iview
->planes
[0].isl
.base_level
,
3757 iview
->planes
[0].isl
.base_array_layer
,
3758 fb
->layers
, render_area
,
3759 att_state
->clear_value
.depthStencil
.stencil
);
3760 } else if (is_multiview
) {
3761 uint32_t pending_clear_mask
=
3762 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3765 for_each_bit(layer_idx
, pending_clear_mask
) {
3767 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
3769 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3770 att_state
->pending_clear_aspects
,
3771 att_state
->aux_usage
,
3772 iview
->planes
[0].isl
.base_level
,
3775 att_state
->clear_value
.depthStencil
.depth
,
3776 att_state
->clear_value
.depthStencil
.stencil
);
3779 att_state
->pending_clear_views
&= ~pending_clear_mask
;
3781 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3782 att_state
->pending_clear_aspects
,
3783 att_state
->aux_usage
,
3784 iview
->planes
[0].isl
.base_level
,
3785 iview
->planes
[0].isl
.base_array_layer
,
3786 fb
->layers
, render_area
,
3787 att_state
->clear_value
.depthStencil
.depth
,
3788 att_state
->clear_value
.depthStencil
.stencil
);
3791 assert(att_state
->pending_clear_aspects
== 0);
3795 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
3796 image
->planes
[0].aux_surface
.isl
.size_B
> 0 &&
3797 iview
->planes
[0].isl
.base_level
== 0 &&
3798 iview
->planes
[0].isl
.base_array_layer
== 0) {
3799 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
3800 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
3801 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3802 false /* copy to ss */);
3805 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
3806 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
3807 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
3808 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3809 false /* copy to ss */);
3813 if (subpass
->attachments
[i
].usage
==
3814 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
3815 /* We assume that if we're starting a subpass, we're going to do some
3816 * rendering so we may end up with compressed data.
3818 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
3819 VK_IMAGE_ASPECT_COLOR_BIT
,
3820 att_state
->aux_usage
,
3821 iview
->planes
[0].isl
.base_level
,
3822 iview
->planes
[0].isl
.base_array_layer
,
3824 } else if (subpass
->attachments
[i
].usage
==
3825 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
3826 /* We may be writing depth or stencil so we need to mark the surface.
3827 * Unfortunately, there's no way to know at this point whether the
3828 * depth or stencil tests used will actually write to the surface.
3830 * Even though stencil may be plane 1, it always shares a base_level
3833 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
3834 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3835 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3836 VK_IMAGE_ASPECT_DEPTH_BIT
,
3837 att_state
->aux_usage
,
3838 ds_view
->base_level
,
3839 ds_view
->base_array_layer
,
3842 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
3843 /* Even though stencil may be plane 1, it always shares a
3844 * base_level with depth.
3846 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3847 VK_IMAGE_ASPECT_STENCIL_BIT
,
3849 ds_view
->base_level
,
3850 ds_view
->base_array_layer
,
3855 /* If multiview is enabled, then we are only done clearing when we no
3856 * longer have pending layers to clear, or when we have processed the
3857 * last subpass that uses this attachment.
3859 if (!is_multiview
||
3860 att_state
->pending_clear_views
== 0 ||
3861 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
3862 att_state
->pending_clear_aspects
= 0;
3865 att_state
->pending_load_aspects
= 0;
3868 cmd_buffer_emit_depth_stencil(cmd_buffer
);
3872 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
3874 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3875 struct anv_subpass
*subpass
= cmd_state
->subpass
;
3876 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
3878 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
3880 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3881 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3882 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3883 if (a
== VK_ATTACHMENT_UNUSED
)
3886 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
3889 assert(a
< cmd_state
->pass
->attachment_count
);
3890 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3891 struct anv_image_view
*iview
= fb
->attachments
[a
];
3892 const struct anv_image
*image
= iview
->image
;
3894 /* Transition the image into the final layout for this render pass */
3895 VkImageLayout target_layout
=
3896 cmd_state
->pass
->attachments
[a
].final_layout
;
3898 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3899 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3901 uint32_t base_layer
, layer_count
;
3902 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3904 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3905 iview
->planes
[0].isl
.base_level
);
3907 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3908 layer_count
= fb
->layers
;
3911 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3912 iview
->planes
[0].isl
.base_level
, 1,
3913 base_layer
, layer_count
,
3914 att_state
->current_layout
, target_layout
);
3915 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3916 transition_depth_buffer(cmd_buffer
, image
,
3917 att_state
->current_layout
, target_layout
);
3921 /* Accumulate any subpass flushes that need to happen after the subpass.
3922 * Yes, they do get accumulated twice in the NextSubpass case but since
3923 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
3924 * ORing the bits in twice so it's harmless.
3926 cmd_buffer
->state
.pending_pipe_bits
|=
3927 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
3930 void genX(CmdBeginRenderPass
)(
3931 VkCommandBuffer commandBuffer
,
3932 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3933 VkSubpassContents contents
)
3935 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3936 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3937 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3939 cmd_buffer
->state
.framebuffer
= framebuffer
;
3940 cmd_buffer
->state
.pass
= pass
;
3941 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3943 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
3945 /* If we failed to setup the attachments we should not try to go further */
3946 if (result
!= VK_SUCCESS
) {
3947 assert(anv_batch_has_error(&cmd_buffer
->batch
));
3951 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3953 cmd_buffer_begin_subpass(cmd_buffer
, 0);
3956 void genX(CmdBeginRenderPass2KHR
)(
3957 VkCommandBuffer commandBuffer
,
3958 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
3959 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
3961 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
3962 pSubpassBeginInfo
->contents
);
3965 void genX(CmdNextSubpass
)(
3966 VkCommandBuffer commandBuffer
,
3967 VkSubpassContents contents
)
3969 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3971 if (anv_batch_has_error(&cmd_buffer
->batch
))
3974 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3976 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
3977 cmd_buffer_end_subpass(cmd_buffer
);
3978 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
3981 void genX(CmdNextSubpass2KHR
)(
3982 VkCommandBuffer commandBuffer
,
3983 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
3984 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
3986 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
3989 void genX(CmdEndRenderPass
)(
3990 VkCommandBuffer commandBuffer
)
3992 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3994 if (anv_batch_has_error(&cmd_buffer
->batch
))
3997 cmd_buffer_end_subpass(cmd_buffer
);
3999 cmd_buffer
->state
.hiz_enabled
= false;
4002 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
4005 /* Remove references to render pass specific state. This enables us to
4006 * detect whether or not we're in a renderpass.
4008 cmd_buffer
->state
.framebuffer
= NULL
;
4009 cmd_buffer
->state
.pass
= NULL
;
4010 cmd_buffer
->state
.subpass
= NULL
;
4013 void genX(CmdEndRenderPass2KHR
)(
4014 VkCommandBuffer commandBuffer
,
4015 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4017 genX(CmdEndRenderPass
)(commandBuffer
);