2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
29 #include "genxml/gen_macros.h"
30 #include "genxml/genX_pack.h"
33 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
35 struct anv_device
*device
= cmd_buffer
->device
;
36 struct anv_bo
*scratch_bo
= NULL
;
38 cmd_buffer
->state
.scratch_size
=
39 anv_block_pool_size(&device
->scratch_block_pool
);
40 if (cmd_buffer
->state
.scratch_size
> 0)
41 scratch_bo
= &device
->scratch_block_pool
.bo
;
43 /* XXX: Do we need this on more than just BDW? */
45 /* Emit a render target cache flush.
47 * This isn't documented anywhere in the PRM. However, it seems to be
48 * necessary prior to changing the surface state base adress. Without
49 * this, we get GPU hangs when using multi-level command buffers which
50 * clear depth, reset state base address, and then go render stuff.
52 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
53 .RenderTargetCacheFlushEnable
= true);
56 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
),
57 .GeneralStateBaseAddress
= { scratch_bo
, 0 },
58 .GeneralStateMemoryObjectControlState
= GENX(MOCS
),
59 .GeneralStateBaseAddressModifyEnable
= true,
61 .SurfaceStateBaseAddress
= anv_cmd_buffer_surface_base_address(cmd_buffer
),
62 .SurfaceStateMemoryObjectControlState
= GENX(MOCS
),
63 .SurfaceStateBaseAddressModifyEnable
= true,
65 .DynamicStateBaseAddress
= { &device
->dynamic_state_block_pool
.bo
, 0 },
66 .DynamicStateMemoryObjectControlState
= GENX(MOCS
),
67 .DynamicStateBaseAddressModifyEnable
= true,
69 .IndirectObjectBaseAddress
= { NULL
, 0 },
70 .IndirectObjectMemoryObjectControlState
= GENX(MOCS
),
71 .IndirectObjectBaseAddressModifyEnable
= true,
73 .InstructionBaseAddress
= { &device
->instruction_block_pool
.bo
, 0 },
74 .InstructionMemoryObjectControlState
= GENX(MOCS
),
75 .InstructionBaseAddressModifyEnable
= true,
78 /* Broadwell requires that we specify a buffer size for a bunch of
79 * these fields. However, since we will be growing the BO's live, we
80 * just set them all to the maximum.
82 .GeneralStateBufferSize
= 0xfffff,
83 .GeneralStateBufferSizeModifyEnable
= true,
84 .DynamicStateBufferSize
= 0xfffff,
85 .DynamicStateBufferSizeModifyEnable
= true,
86 .IndirectObjectBufferSize
= 0xfffff,
87 .IndirectObjectBufferSizeModifyEnable
= true,
88 .InstructionBufferSize
= 0xfffff,
89 .InstructionBuffersizeModifyEnable
= true,
93 /* After re-setting the surface state base address, we have to do some
94 * cache flusing so that the sampler engine will pick up the new
95 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
96 * Shared Function > 3D Sampler > State > State Caching (page 96):
98 * Coherency with system memory in the state cache, like the texture
99 * cache is handled partially by software. It is expected that the
100 * command stream or shader will issue Cache Flush operation or
101 * Cache_Flush sampler message to ensure that the L1 cache remains
102 * coherent with system memory.
106 * Whenever the value of the Dynamic_State_Base_Addr,
107 * Surface_State_Base_Addr are altered, the L1 state cache must be
108 * invalidated to ensure the new surface or sampler state is fetched
109 * from system memory.
111 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
112 * which, according the PIPE_CONTROL instruction documentation in the
115 * Setting this bit is independent of any other bit in this packet.
116 * This bit controls the invalidation of the L1 and L2 state caches
117 * at the top of the pipe i.e. at the parsing time.
119 * Unfortunately, experimentation seems to indicate that state cache
120 * invalidation through a PIPE_CONTROL does nothing whatsoever in
121 * regards to surface state and binding tables. In stead, it seems that
122 * invalidating the texture cache is what is actually needed.
124 * XXX: As far as we have been able to determine through
125 * experimentation, shows that flush the texture cache appears to be
126 * sufficient. The theory here is that all of the sampling/rendering
127 * units cache the binding table in the texture cache. However, we have
128 * yet to be able to actually confirm this.
130 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
131 .TextureCacheInvalidationEnable
= true);
134 void genX(CmdPipelineBarrier
)(
135 VkCommandBuffer commandBuffer
,
136 VkPipelineStageFlags srcStageMask
,
137 VkPipelineStageFlags destStageMask
,
139 uint32_t memoryBarrierCount
,
140 const VkMemoryBarrier
* pMemoryBarriers
,
141 uint32_t bufferMemoryBarrierCount
,
142 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
143 uint32_t imageMemoryBarrierCount
,
144 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
146 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
149 /* XXX: Right now, we're really dumb and just flush whatever categories
150 * the app asks for. One of these days we may make this a bit better
151 * but right now that's all the hardware allows for in most areas.
153 VkAccessFlags src_flags
= 0;
154 VkAccessFlags dst_flags
= 0;
156 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
157 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
158 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
161 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
162 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
163 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
166 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
167 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
168 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
171 /* Mask out the Source access flags we care about */
172 const uint32_t src_mask
=
173 VK_ACCESS_SHADER_WRITE_BIT
|
174 VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
|
175 VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
|
176 VK_ACCESS_TRANSFER_WRITE_BIT
;
178 src_flags
= src_flags
& src_mask
;
180 /* Mask out the destination access flags we care about */
181 const uint32_t dst_mask
=
182 VK_ACCESS_INDIRECT_COMMAND_READ_BIT
|
183 VK_ACCESS_INDEX_READ_BIT
|
184 VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
|
185 VK_ACCESS_UNIFORM_READ_BIT
|
186 VK_ACCESS_SHADER_READ_BIT
|
187 VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
|
188 VK_ACCESS_TRANSFER_READ_BIT
;
190 dst_flags
= dst_flags
& dst_mask
;
192 /* The src flags represent how things were used previously. This is
193 * what we use for doing flushes.
195 struct GENX(PIPE_CONTROL
) flush_cmd
= {
196 GENX(PIPE_CONTROL_header
),
197 .PostSyncOperation
= NoWrite
,
200 for_each_bit(b
, src_flags
) {
201 switch ((VkAccessFlagBits
)(1 << b
)) {
202 case VK_ACCESS_SHADER_WRITE_BIT
:
203 flush_cmd
.DCFlushEnable
= true;
205 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
206 flush_cmd
.RenderTargetCacheFlushEnable
= true;
208 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
209 flush_cmd
.DepthCacheFlushEnable
= true;
211 case VK_ACCESS_TRANSFER_WRITE_BIT
:
212 flush_cmd
.RenderTargetCacheFlushEnable
= true;
213 flush_cmd
.DepthCacheFlushEnable
= true;
216 unreachable("should've masked this out by now");
220 /* If we end up doing two PIPE_CONTROLs, the first, flusing one also has to
221 * stall and wait for the flushing to finish, so we don't re-dirty the
222 * caches with in-flight rendering after the second PIPE_CONTROL
227 flush_cmd
.CommandStreamerStallEnable
= true;
229 if (src_flags
&& dst_flags
) {
230 dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
, GENX(PIPE_CONTROL_length
));
231 GENX(PIPE_CONTROL_pack
)(&cmd_buffer
->batch
, dw
, &flush_cmd
);
234 /* The dst flags represent how things will be used in the future. This
235 * is what we use for doing cache invalidations.
237 struct GENX(PIPE_CONTROL
) invalidate_cmd
= {
238 GENX(PIPE_CONTROL_header
),
239 .PostSyncOperation
= NoWrite
,
242 for_each_bit(b
, dst_flags
) {
243 switch ((VkAccessFlagBits
)(1 << b
)) {
244 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
245 case VK_ACCESS_INDEX_READ_BIT
:
246 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
247 invalidate_cmd
.VFCacheInvalidationEnable
= true;
249 case VK_ACCESS_UNIFORM_READ_BIT
:
250 invalidate_cmd
.ConstantCacheInvalidationEnable
= true;
252 case VK_ACCESS_SHADER_READ_BIT
:
253 invalidate_cmd
.TextureCacheInvalidationEnable
= true;
255 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
256 invalidate_cmd
.TextureCacheInvalidationEnable
= true;
258 case VK_ACCESS_TRANSFER_READ_BIT
:
259 invalidate_cmd
.TextureCacheInvalidationEnable
= true;
262 unreachable("should've masked this out by now");
267 dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
, GENX(PIPE_CONTROL_length
));
268 GENX(PIPE_CONTROL_pack
)(&cmd_buffer
->batch
, dw
, &invalidate_cmd
);
273 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
274 struct anv_bo
*bo
, uint32_t offset
)
276 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
277 GENX(3DSTATE_VERTEX_BUFFERS
));
279 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
280 &(struct GENX(VERTEX_BUFFER_STATE
)) {
281 .VertexBufferIndex
= 32, /* Reserved for this */
282 .AddressModifyEnable
= true,
285 .MemoryObjectControlState
= GENX(MOCS
),
286 .BufferStartingAddress
= { bo
, offset
},
289 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
290 .BufferStartingAddress
= { bo
, offset
},
291 .EndAddress
= { bo
, offset
+ 8 },
297 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
298 uint32_t base_vertex
, uint32_t base_instance
)
300 struct anv_state id_state
=
301 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
303 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
304 ((uint32_t *)id_state
.map
)[1] = base_instance
;
306 if (!cmd_buffer
->device
->info
.has_llc
)
307 anv_state_clflush(id_state
);
309 emit_base_vertex_instance_bo(cmd_buffer
,
310 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, id_state
.offset
);
314 VkCommandBuffer commandBuffer
,
315 uint32_t vertexCount
,
316 uint32_t instanceCount
,
317 uint32_t firstVertex
,
318 uint32_t firstInstance
)
320 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
321 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
322 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
324 genX(cmd_buffer_flush_state
)(cmd_buffer
);
326 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
327 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
329 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
),
330 .VertexAccessType
= SEQUENTIAL
,
331 .PrimitiveTopologyType
= pipeline
->topology
,
332 .VertexCountPerInstance
= vertexCount
,
333 .StartVertexLocation
= firstVertex
,
334 .InstanceCount
= instanceCount
,
335 .StartInstanceLocation
= firstInstance
,
336 .BaseVertexLocation
= 0);
339 void genX(CmdDrawIndexed
)(
340 VkCommandBuffer commandBuffer
,
342 uint32_t instanceCount
,
344 int32_t vertexOffset
,
345 uint32_t firstInstance
)
347 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
348 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
349 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
351 genX(cmd_buffer_flush_state
)(cmd_buffer
);
353 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
354 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
356 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
),
357 .VertexAccessType
= RANDOM
,
358 .PrimitiveTopologyType
= pipeline
->topology
,
359 .VertexCountPerInstance
= indexCount
,
360 .StartVertexLocation
= firstIndex
,
361 .InstanceCount
= instanceCount
,
362 .StartInstanceLocation
= firstInstance
,
363 .BaseVertexLocation
= vertexOffset
);
366 /* Auto-Draw / Indirect Registers */
367 #define GEN7_3DPRIM_END_OFFSET 0x2420
368 #define GEN7_3DPRIM_START_VERTEX 0x2430
369 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
370 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
371 #define GEN7_3DPRIM_START_INSTANCE 0x243C
372 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
375 emit_lrm(struct anv_batch
*batch
,
376 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
378 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
),
379 .RegisterAddress
= reg
,
380 .MemoryAddress
= { bo
, offset
});
384 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
386 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
),
387 .RegisterOffset
= reg
,
391 void genX(CmdDrawIndirect
)(
392 VkCommandBuffer commandBuffer
,
398 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
399 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
400 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
401 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
402 struct anv_bo
*bo
= buffer
->bo
;
403 uint32_t bo_offset
= buffer
->offset
+ offset
;
405 genX(cmd_buffer_flush_state
)(cmd_buffer
);
407 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
408 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
410 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
411 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
412 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
413 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
414 emit_lri(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
416 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
),
417 .IndirectParameterEnable
= true,
418 .VertexAccessType
= SEQUENTIAL
,
419 .PrimitiveTopologyType
= pipeline
->topology
);
422 void genX(CmdDrawIndexedIndirect
)(
423 VkCommandBuffer commandBuffer
,
429 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
430 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
431 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
432 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
433 struct anv_bo
*bo
= buffer
->bo
;
434 uint32_t bo_offset
= buffer
->offset
+ offset
;
436 genX(cmd_buffer_flush_state
)(cmd_buffer
);
438 /* TODO: We need to stomp base vertex to 0 somehow */
439 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
440 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
442 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
443 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
444 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
445 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
446 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
448 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
),
449 .IndirectParameterEnable
= true,
450 .VertexAccessType
= RANDOM
,
451 .PrimitiveTopologyType
= pipeline
->topology
);
455 void genX(CmdDispatch
)(
456 VkCommandBuffer commandBuffer
,
461 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
462 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
463 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
465 if (prog_data
->uses_num_work_groups
) {
466 struct anv_state state
=
467 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
468 uint32_t *sizes
= state
.map
;
472 if (!cmd_buffer
->device
->info
.has_llc
)
473 anv_state_clflush(state
);
474 cmd_buffer
->state
.num_workgroups_offset
= state
.offset
;
475 cmd_buffer
->state
.num_workgroups_bo
=
476 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
;
479 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
481 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
),
482 .SIMDSize
= prog_data
->simd_size
/ 16,
483 .ThreadDepthCounterMaximum
= 0,
484 .ThreadHeightCounterMaximum
= 0,
485 .ThreadWidthCounterMaximum
= pipeline
->cs_thread_width_max
- 1,
486 .ThreadGroupIDXDimension
= x
,
487 .ThreadGroupIDYDimension
= y
,
488 .ThreadGroupIDZDimension
= z
,
489 .RightExecutionMask
= pipeline
->cs_right_mask
,
490 .BottomExecutionMask
= 0xffffffff);
492 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
));
495 #define GPGPU_DISPATCHDIMX 0x2500
496 #define GPGPU_DISPATCHDIMY 0x2504
497 #define GPGPU_DISPATCHDIMZ 0x2508
499 #define MI_PREDICATE_SRC0 0x2400
500 #define MI_PREDICATE_SRC1 0x2408
502 void genX(CmdDispatchIndirect
)(
503 VkCommandBuffer commandBuffer
,
507 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
508 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
509 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
510 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
511 struct anv_bo
*bo
= buffer
->bo
;
512 uint32_t bo_offset
= buffer
->offset
+ offset
;
513 struct anv_batch
*batch
= &cmd_buffer
->batch
;
515 if (prog_data
->uses_num_work_groups
) {
516 cmd_buffer
->state
.num_workgroups_offset
= bo_offset
;
517 cmd_buffer
->state
.num_workgroups_bo
= bo
;
520 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
522 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
523 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
524 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
527 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
528 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
529 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
530 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
532 /* Load compute_dispatch_indirect_x_size into SRC0 */
533 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
535 /* predicate = (compute_dispatch_indirect_x_size == 0); */
536 anv_batch_emit(batch
, GENX(MI_PREDICATE
),
537 .LoadOperation
= LOAD_LOAD
,
538 .CombineOperation
= COMBINE_SET
,
539 .CompareOperation
= COMPARE_SRCS_EQUAL
);
541 /* Load compute_dispatch_indirect_y_size into SRC0 */
542 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
544 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
545 anv_batch_emit(batch
, GENX(MI_PREDICATE
),
546 .LoadOperation
= LOAD_LOAD
,
547 .CombineOperation
= COMBINE_OR
,
548 .CompareOperation
= COMPARE_SRCS_EQUAL
);
550 /* Load compute_dispatch_indirect_z_size into SRC0 */
551 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
553 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
554 anv_batch_emit(batch
, GENX(MI_PREDICATE
),
555 .LoadOperation
= LOAD_LOAD
,
556 .CombineOperation
= COMBINE_OR
,
557 .CompareOperation
= COMPARE_SRCS_EQUAL
);
559 /* predicate = !predicate; */
560 #define COMPARE_FALSE 1
561 anv_batch_emit(batch
, GENX(MI_PREDICATE
),
562 .LoadOperation
= LOAD_LOADINV
,
563 .CombineOperation
= COMBINE_OR
,
564 .CompareOperation
= COMPARE_FALSE
);
567 anv_batch_emit(batch
, GENX(GPGPU_WALKER
),
568 .IndirectParameterEnable
= true,
569 .PredicateEnable
= GEN_GEN
<= 7,
570 .SIMDSize
= prog_data
->simd_size
/ 16,
571 .ThreadDepthCounterMaximum
= 0,
572 .ThreadHeightCounterMaximum
= 0,
573 .ThreadWidthCounterMaximum
= pipeline
->cs_thread_width_max
- 1,
574 .RightExecutionMask
= pipeline
->cs_right_mask
,
575 .BottomExecutionMask
= 0xffffffff);
577 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
));
581 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
583 if (cmd_buffer
->state
.current_pipeline
!= _3D
) {
584 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
),
588 .PipelineSelection
= _3D
);
589 cmd_buffer
->state
.current_pipeline
= _3D
;
594 genX(cmd_buffer_alloc_null_surface_state
)(struct anv_cmd_buffer
*cmd_buffer
,
595 struct anv_framebuffer
*fb
)
597 struct anv_state state
=
598 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
600 struct GENX(RENDER_SURFACE_STATE
) null_ss
= {
601 .SurfaceType
= SURFTYPE_NULL
,
602 .SurfaceArray
= fb
->layers
> 0,
603 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
607 .TiledSurface
= true,
609 .Width
= fb
->width
- 1,
610 .Height
= fb
->height
- 1,
611 .Depth
= fb
->layers
- 1,
612 .RenderTargetViewExtent
= fb
->layers
- 1,
615 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
.map
, &null_ss
);
617 if (!cmd_buffer
->device
->info
.has_llc
)
618 anv_state_clflush(state
);
624 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
626 struct anv_device
*device
= cmd_buffer
->device
;
627 const struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
628 const struct anv_image_view
*iview
=
629 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
630 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
631 const struct anv_format
*anv_format
=
632 iview
? anv_format_for_vk_format(iview
->vk_format
) : NULL
;
633 const bool has_depth
= iview
&& anv_format
->has_depth
;
634 const bool has_stencil
= iview
&& anv_format
->has_stencil
;
636 /* FIXME: Implement the PMA stall W/A */
637 /* FIXME: Width and Height are wrong */
639 /* Emit 3DSTATE_DEPTH_BUFFER */
641 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
),
642 .SurfaceType
= SURFTYPE_2D
,
643 .DepthWriteEnable
= true,
644 .StencilWriteEnable
= has_stencil
,
645 .HierarchicalDepthBufferEnable
= false,
646 .SurfaceFormat
= isl_surf_get_depth_format(&device
->isl_dev
,
647 &image
->depth_surface
.isl
),
648 .SurfacePitch
= image
->depth_surface
.isl
.row_pitch
- 1,
649 .SurfaceBaseAddress
= {
651 .offset
= image
->offset
+ image
->depth_surface
.offset
,
653 .Height
= fb
->height
- 1,
654 .Width
= fb
->width
- 1,
657 .MinimumArrayElement
= 0,
658 .DepthBufferObjectControlState
= GENX(MOCS
),
660 .SurfaceQPitch
= isl_surf_get_array_pitch_el_rows(&image
->depth_surface
.isl
) >> 2,
662 .RenderTargetViewExtent
= 1 - 1);
664 /* Even when no depth buffer is present, the hardware requires that
665 * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
667 * If a null depth buffer is bound, the driver must instead bind depth as:
668 * 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
669 * 3DSTATE_DEPTH.Width = 1
670 * 3DSTATE_DEPTH.Height = 1
671 * 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
672 * 3DSTATE_DEPTH.SurfaceBaseAddress = 0
673 * 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
674 * 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
675 * 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
677 * The PRM is wrong, though. The width and height must be programmed to
678 * actual framebuffer's width and height, even when neither depth buffer
679 * nor stencil buffer is present. Also, D16_UNORM is not allowed to
680 * be combined with a stencil buffer so we use D32_FLOAT instead.
682 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
),
683 .SurfaceType
= SURFTYPE_2D
,
684 .SurfaceFormat
= D32_FLOAT
,
685 .Width
= fb
->width
- 1,
686 .Height
= fb
->height
- 1,
687 .StencilWriteEnable
= has_stencil
);
690 /* Emit 3DSTATE_STENCIL_BUFFER */
692 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
),
693 #if GEN_GEN >= 8 || GEN_IS_HASWELL
694 .StencilBufferEnable
= true,
696 .StencilBufferObjectControlState
= GENX(MOCS
),
698 /* Stencil buffers have strange pitch. The PRM says:
700 * The pitch must be set to 2x the value computed based on width,
701 * as the stencil buffer is stored with two rows interleaved.
703 .SurfacePitch
= 2 * image
->stencil_surface
.isl
.row_pitch
- 1,
706 .SurfaceQPitch
= isl_surf_get_array_pitch_el_rows(&image
->stencil_surface
.isl
) >> 2,
708 .SurfaceBaseAddress
= {
710 .offset
= image
->offset
+ image
->stencil_surface
.offset
,
713 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
));
716 /* Disable hierarchial depth buffers. */
717 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
));
719 /* Clear the clear params. */
720 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CLEAR_PARAMS
));
724 * @see anv_cmd_buffer_set_subpass()
727 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
728 struct anv_subpass
*subpass
)
730 cmd_buffer
->state
.subpass
= subpass
;
732 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
734 cmd_buffer_emit_depth_stencil(cmd_buffer
);
737 void genX(CmdBeginRenderPass
)(
738 VkCommandBuffer commandBuffer
,
739 const VkRenderPassBeginInfo
* pRenderPassBegin
,
740 VkSubpassContents contents
)
742 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
743 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
744 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
746 cmd_buffer
->state
.framebuffer
= framebuffer
;
747 cmd_buffer
->state
.pass
= pass
;
748 anv_cmd_state_setup_attachments(cmd_buffer
, pRenderPassBegin
);
750 genX(flush_pipeline_select_3d
)(cmd_buffer
);
752 const VkRect2D
*render_area
= &pRenderPassBegin
->renderArea
;
754 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DRAWING_RECTANGLE
),
755 .ClippedDrawingRectangleYMin
= MAX2(render_area
->offset
.y
, 0),
756 .ClippedDrawingRectangleXMin
= MAX2(render_area
->offset
.x
, 0),
757 .ClippedDrawingRectangleYMax
=
758 render_area
->offset
.y
+ render_area
->extent
.height
- 1,
759 .ClippedDrawingRectangleXMax
=
760 render_area
->offset
.x
+ render_area
->extent
.width
- 1,
761 .DrawingRectangleOriginY
= 0,
762 .DrawingRectangleOriginX
= 0);
764 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
765 anv_cmd_buffer_clear_subpass(cmd_buffer
);
768 void genX(CmdNextSubpass
)(
769 VkCommandBuffer commandBuffer
,
770 VkSubpassContents contents
)
772 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
774 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
776 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
777 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
778 anv_cmd_buffer_clear_subpass(cmd_buffer
);
781 void genX(CmdEndRenderPass
)(
782 VkCommandBuffer commandBuffer
)
784 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
786 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
790 emit_ps_depth_count(struct anv_batch
*batch
,
791 struct anv_bo
*bo
, uint32_t offset
)
793 anv_batch_emit(batch
, GENX(PIPE_CONTROL
),
794 .DestinationAddressType
= DAT_PPGTT
,
795 .PostSyncOperation
= WritePSDepthCount
,
796 .DepthStallEnable
= true,
797 .Address
= { bo
, offset
});
801 emit_query_availability(struct anv_batch
*batch
,
802 struct anv_bo
*bo
, uint32_t offset
)
804 anv_batch_emit(batch
, GENX(PIPE_CONTROL
),
805 .DestinationAddressType
= DAT_PPGTT
,
806 .PostSyncOperation
= WriteImmediateData
,
807 .Address
= { bo
, offset
},
811 void genX(CmdBeginQuery
)(
812 VkCommandBuffer commandBuffer
,
813 VkQueryPool queryPool
,
815 VkQueryControlFlags flags
)
817 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
818 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
820 /* Workaround: When meta uses the pipeline with the VS disabled, it seems
821 * that the pipelining of the depth write breaks. What we see is that
822 * samples from the render pass clear leaks into the first query
823 * immediately after the clear. Doing a pipecontrol with a post-sync
824 * operation and DepthStallEnable seems to work around the issue.
826 if (cmd_buffer
->state
.need_query_wa
) {
827 cmd_buffer
->state
.need_query_wa
= false;
828 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
829 .DepthCacheFlushEnable
= true,
830 .DepthStallEnable
= true);
833 switch (pool
->type
) {
834 case VK_QUERY_TYPE_OCCLUSION
:
835 emit_ps_depth_count(&cmd_buffer
->batch
, &pool
->bo
,
836 query
* sizeof(struct anv_query_pool_slot
));
839 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
845 void genX(CmdEndQuery
)(
846 VkCommandBuffer commandBuffer
,
847 VkQueryPool queryPool
,
850 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
851 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
853 switch (pool
->type
) {
854 case VK_QUERY_TYPE_OCCLUSION
:
855 emit_ps_depth_count(&cmd_buffer
->batch
, &pool
->bo
,
856 query
* sizeof(struct anv_query_pool_slot
) + 8);
858 emit_query_availability(&cmd_buffer
->batch
, &pool
->bo
,
859 query
* sizeof(struct anv_query_pool_slot
) + 16);
862 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
868 #define TIMESTAMP 0x2358
870 void genX(CmdWriteTimestamp
)(
871 VkCommandBuffer commandBuffer
,
872 VkPipelineStageFlagBits pipelineStage
,
873 VkQueryPool queryPool
,
876 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
877 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
878 uint32_t offset
= query
* sizeof(struct anv_query_pool_slot
);
880 assert(pool
->type
== VK_QUERY_TYPE_TIMESTAMP
);
882 switch (pipelineStage
) {
883 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
:
884 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
),
885 .RegisterAddress
= TIMESTAMP
,
886 .MemoryAddress
= { &pool
->bo
, offset
});
887 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
),
888 .RegisterAddress
= TIMESTAMP
+ 4,
889 .MemoryAddress
= { &pool
->bo
, offset
+ 4 });
893 /* Everything else is bottom-of-pipe */
894 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
895 .DestinationAddressType
= DAT_PPGTT
,
896 .PostSyncOperation
= WriteTimestamp
,
897 .Address
= { &pool
->bo
, offset
});
901 emit_query_availability(&cmd_buffer
->batch
, &pool
->bo
, query
+ 16);
904 #if GEN_GEN > 7 || GEN_IS_HASWELL
906 #define alu_opcode(v) __gen_uint((v), 20, 31)
907 #define alu_operand1(v) __gen_uint((v), 10, 19)
908 #define alu_operand2(v) __gen_uint((v), 0, 9)
909 #define alu(opcode, operand1, operand2) \
910 alu_opcode(opcode) | alu_operand1(operand1) | alu_operand2(operand2)
912 #define OPCODE_NOOP 0x000
913 #define OPCODE_LOAD 0x080
914 #define OPCODE_LOADINV 0x480
915 #define OPCODE_LOAD0 0x081
916 #define OPCODE_LOAD1 0x481
917 #define OPCODE_ADD 0x100
918 #define OPCODE_SUB 0x101
919 #define OPCODE_AND 0x102
920 #define OPCODE_OR 0x103
921 #define OPCODE_XOR 0x104
922 #define OPCODE_STORE 0x180
923 #define OPCODE_STOREINV 0x580
925 #define OPERAND_R0 0x00
926 #define OPERAND_R1 0x01
927 #define OPERAND_R2 0x02
928 #define OPERAND_R3 0x03
929 #define OPERAND_R4 0x04
930 #define OPERAND_SRCA 0x20
931 #define OPERAND_SRCB 0x21
932 #define OPERAND_ACCU 0x31
933 #define OPERAND_ZF 0x32
934 #define OPERAND_CF 0x33
936 #define CS_GPR(n) (0x2600 + (n) * 8)
939 emit_load_alu_reg_u64(struct anv_batch
*batch
, uint32_t reg
,
940 struct anv_bo
*bo
, uint32_t offset
)
942 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
),
943 .RegisterAddress
= reg
,
944 .MemoryAddress
= { bo
, offset
});
945 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
),
946 .RegisterAddress
= reg
+ 4,
947 .MemoryAddress
= { bo
, offset
+ 4 });
951 store_query_result(struct anv_batch
*batch
, uint32_t reg
,
952 struct anv_bo
*bo
, uint32_t offset
, VkQueryResultFlags flags
)
954 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
),
955 .RegisterAddress
= reg
,
956 .MemoryAddress
= { bo
, offset
});
958 if (flags
& VK_QUERY_RESULT_64_BIT
)
959 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
),
960 .RegisterAddress
= reg
+ 4,
961 .MemoryAddress
= { bo
, offset
+ 4 });
964 void genX(CmdCopyQueryPoolResults
)(
965 VkCommandBuffer commandBuffer
,
966 VkQueryPool queryPool
,
970 VkDeviceSize destOffset
,
971 VkDeviceSize destStride
,
972 VkQueryResultFlags flags
)
974 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
975 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
976 ANV_FROM_HANDLE(anv_buffer
, buffer
, destBuffer
);
977 uint32_t slot_offset
, dst_offset
;
979 if (flags
& VK_QUERY_RESULT_WAIT_BIT
)
980 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
981 .CommandStreamerStallEnable
= true,
982 .StallAtPixelScoreboard
= true);
984 dst_offset
= buffer
->offset
+ destOffset
;
985 for (uint32_t i
= 0; i
< queryCount
; i
++) {
987 slot_offset
= (firstQuery
+ i
) * sizeof(struct anv_query_pool_slot
);
988 switch (pool
->type
) {
989 case VK_QUERY_TYPE_OCCLUSION
:
990 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
991 CS_GPR(0), &pool
->bo
, slot_offset
);
992 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
993 CS_GPR(1), &pool
->bo
, slot_offset
+ 8);
995 /* FIXME: We need to clamp the result for 32 bit. */
997 uint32_t *dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
998 dw
[1] = alu(OPCODE_LOAD
, OPERAND_SRCA
, OPERAND_R1
);
999 dw
[2] = alu(OPCODE_LOAD
, OPERAND_SRCB
, OPERAND_R0
);
1000 dw
[3] = alu(OPCODE_SUB
, 0, 0);
1001 dw
[4] = alu(OPCODE_STORE
, OPERAND_R2
, OPERAND_ACCU
);
1004 case VK_QUERY_TYPE_TIMESTAMP
:
1005 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
1006 CS_GPR(2), &pool
->bo
, slot_offset
);
1010 unreachable("unhandled query type");
1013 store_query_result(&cmd_buffer
->batch
,
1014 CS_GPR(2), buffer
->bo
, dst_offset
, flags
);
1016 if (flags
& VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
) {
1017 emit_load_alu_reg_u64(&cmd_buffer
->batch
, CS_GPR(0),
1018 &pool
->bo
, slot_offset
+ 16);
1019 if (flags
& VK_QUERY_RESULT_64_BIT
)
1020 store_query_result(&cmd_buffer
->batch
,
1021 CS_GPR(0), buffer
->bo
, dst_offset
+ 8, flags
);
1023 store_query_result(&cmd_buffer
->batch
,
1024 CS_GPR(0), buffer
->bo
, dst_offset
+ 4, flags
);
1027 dst_offset
+= destStride
;