2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "common/gen_l3_config.h"
31 #include "genxml/gen_macros.h"
32 #include "genxml/genX_pack.h"
35 emit_lrm(struct anv_batch
*batch
,
36 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
38 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
39 lrm
.RegisterAddress
= reg
;
40 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
45 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
47 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
48 lri
.RegisterOffset
= reg
;
54 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
56 struct anv_device
*device
= cmd_buffer
->device
;
58 /* Emit a render target cache flush.
60 * This isn't documented anywhere in the PRM. However, it seems to be
61 * necessary prior to changing the surface state base adress. Without
62 * this, we get GPU hangs when using multi-level command buffers which
63 * clear depth, reset state base address, and then go render stuff.
65 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
66 pc
.DCFlushEnable
= true;
67 pc
.RenderTargetCacheFlushEnable
= true;
68 pc
.CommandStreamerStallEnable
= true;
71 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
72 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
73 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
74 sba
.GeneralStateBaseAddressModifyEnable
= true;
76 sba
.SurfaceStateBaseAddress
=
77 anv_cmd_buffer_surface_base_address(cmd_buffer
);
78 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
79 sba
.SurfaceStateBaseAddressModifyEnable
= true;
81 sba
.DynamicStateBaseAddress
=
82 (struct anv_address
) { &device
->dynamic_state_block_pool
.bo
, 0 };
83 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
84 sba
.DynamicStateBaseAddressModifyEnable
= true;
86 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
87 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
88 sba
.IndirectObjectBaseAddressModifyEnable
= true;
90 sba
.InstructionBaseAddress
=
91 (struct anv_address
) { &device
->instruction_block_pool
.bo
, 0 };
92 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
93 sba
.InstructionBaseAddressModifyEnable
= true;
96 /* Broadwell requires that we specify a buffer size for a bunch of
97 * these fields. However, since we will be growing the BO's live, we
98 * just set them all to the maximum.
100 sba
.GeneralStateBufferSize
= 0xfffff;
101 sba
.GeneralStateBufferSizeModifyEnable
= true;
102 sba
.DynamicStateBufferSize
= 0xfffff;
103 sba
.DynamicStateBufferSizeModifyEnable
= true;
104 sba
.IndirectObjectBufferSize
= 0xfffff;
105 sba
.IndirectObjectBufferSizeModifyEnable
= true;
106 sba
.InstructionBufferSize
= 0xfffff;
107 sba
.InstructionBuffersizeModifyEnable
= true;
111 /* After re-setting the surface state base address, we have to do some
112 * cache flusing so that the sampler engine will pick up the new
113 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
114 * Shared Function > 3D Sampler > State > State Caching (page 96):
116 * Coherency with system memory in the state cache, like the texture
117 * cache is handled partially by software. It is expected that the
118 * command stream or shader will issue Cache Flush operation or
119 * Cache_Flush sampler message to ensure that the L1 cache remains
120 * coherent with system memory.
124 * Whenever the value of the Dynamic_State_Base_Addr,
125 * Surface_State_Base_Addr are altered, the L1 state cache must be
126 * invalidated to ensure the new surface or sampler state is fetched
127 * from system memory.
129 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
130 * which, according the PIPE_CONTROL instruction documentation in the
133 * Setting this bit is independent of any other bit in this packet.
134 * This bit controls the invalidation of the L1 and L2 state caches
135 * at the top of the pipe i.e. at the parsing time.
137 * Unfortunately, experimentation seems to indicate that state cache
138 * invalidation through a PIPE_CONTROL does nothing whatsoever in
139 * regards to surface state and binding tables. In stead, it seems that
140 * invalidating the texture cache is what is actually needed.
142 * XXX: As far as we have been able to determine through
143 * experimentation, shows that flush the texture cache appears to be
144 * sufficient. The theory here is that all of the sampling/rendering
145 * units cache the binding table in the texture cache. However, we have
146 * yet to be able to actually confirm this.
148 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
149 pc
.TextureCacheInvalidationEnable
= true;
150 pc
.ConstantCacheInvalidationEnable
= true;
151 pc
.StateCacheInvalidationEnable
= true;
156 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
157 struct anv_state state
,
158 struct anv_bo
*bo
, uint32_t offset
)
160 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
162 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
163 state
.offset
+ isl_dev
->ss
.addr_offset
, bo
, offset
);
167 add_image_view_relocs(struct anv_cmd_buffer
*cmd_buffer
,
168 const struct anv_image_view
*iview
,
169 enum isl_aux_usage aux_usage
,
170 struct anv_state state
)
172 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
174 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
175 state
.offset
+ isl_dev
->ss
.addr_offset
,
176 iview
->bo
, iview
->offset
);
178 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
179 uint32_t aux_offset
= iview
->offset
+ iview
->image
->aux_surface
.offset
;
181 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
182 * used to store other information. This should be ok, however, because
183 * surface buffer addresses are always 4K page alinged.
185 assert((aux_offset
& 0xfff) == 0);
186 uint32_t *aux_addr_dw
= state
.map
+ isl_dev
->ss
.aux_addr_offset
;
187 aux_offset
+= *aux_addr_dw
& 0xfff;
189 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
190 state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
191 iview
->bo
, aux_offset
);
196 color_is_zero_one(VkClearColorValue value
, enum isl_format format
)
198 if (isl_format_has_int_channel(format
)) {
199 for (unsigned i
= 0; i
< 4; i
++) {
200 if (value
.int32
[i
] != 0 && value
.int32
[i
] != 1)
204 for (unsigned i
= 0; i
< 4; i
++) {
205 if (value
.float32
[i
] != 0.0f
&& value
.float32
[i
] != 1.0f
)
214 color_attachment_compute_aux_usage(struct anv_device
*device
,
215 struct anv_attachment_state
*att_state
,
216 struct anv_image_view
*iview
,
217 VkRect2D render_area
,
218 union isl_color_value
*fast_clear_color
)
220 if (iview
->image
->aux_surface
.isl
.size
== 0) {
221 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
222 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
223 att_state
->fast_clear
= false;
227 assert(iview
->image
->aux_surface
.isl
.usage
& ISL_SURF_USAGE_CCS_BIT
);
229 att_state
->clear_color_is_zero_one
=
230 color_is_zero_one(att_state
->clear_value
.color
, iview
->isl
.format
);
232 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
233 /* Start off assuming fast clears are possible */
234 att_state
->fast_clear
= true;
236 /* Potentially, we could do partial fast-clears but doing so has crazy
237 * alignment restrictions. It's easier to just restrict to full size
238 * fast clears for now.
240 if (render_area
.offset
.x
!= 0 ||
241 render_area
.offset
.y
!= 0 ||
242 render_area
.extent
.width
!= iview
->extent
.width
||
243 render_area
.extent
.height
!= iview
->extent
.height
)
244 att_state
->fast_clear
= false;
247 /* On gen7, we can't do multi-LOD or multi-layer fast-clears. We
248 * technically can, but it comes with crazy restrictions that we
249 * don't want to deal with now.
251 if (iview
->isl
.base_level
> 0 ||
252 iview
->isl
.base_array_layer
> 0 ||
253 iview
->isl
.array_len
> 1)
254 att_state
->fast_clear
= false;
257 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
258 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
259 att_state
->fast_clear
= false;
261 if (att_state
->fast_clear
) {
262 memcpy(fast_clear_color
->u32
, att_state
->clear_value
.color
.uint32
,
263 sizeof(fast_clear_color
->u32
));
266 att_state
->fast_clear
= false;
269 if (isl_format_supports_lossless_compression(&device
->info
,
270 iview
->isl
.format
)) {
271 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
272 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_E
;
273 } else if (att_state
->fast_clear
) {
274 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
276 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
278 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
279 * setting is only allowed if Surface Format supported for Fast
280 * Clear. In addition, if the surface is bound to the sampling
281 * engine, Surface Format must be supported for Render Target
282 * Compression for surfaces bound to the sampling engine."
284 * In other words, we can't sample from a fast-cleared image if it
285 * doesn't also support color compression.
287 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
288 } else if (GEN_GEN
== 8) {
289 /* Broadwell can sample from fast-cleared images */
290 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
292 /* Ivy Bridge and Haswell cannot */
293 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
296 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
297 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
302 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
304 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
307 /* We only allocate input attachment states for color surfaces. Compression
308 * is not yet enabled for depth textures and stencil doesn't allow
309 * compression so we can just use the texture surface state from the view.
311 return vk_format_is_color(att
->format
);
314 static enum isl_aux_usage
315 layout_to_hiz_usage(VkImageLayout layout
, uint8_t samples
)
318 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
:
319 return ISL_AUX_USAGE_HIZ
;
320 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL
:
321 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
:
322 if (anv_can_sample_with_hiz(GEN_GEN
, samples
))
323 return ISL_AUX_USAGE_HIZ
;
325 case VK_IMAGE_LAYOUT_GENERAL
:
326 /* This buffer could be used as a source or destination in a transfer
327 * operation. Transfer operations current don't perform HiZ-enabled reads
331 return ISL_AUX_USAGE_NONE
;
335 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
336 * the initial layout is undefined, the HiZ buffer and depth buffer will
337 * represent the same data at the end of this operation.
340 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
341 const struct anv_image
*image
,
342 VkImageLayout initial_layout
,
343 VkImageLayout final_layout
)
347 if (image
->aux_usage
!= ISL_AUX_USAGE_HIZ
|| final_layout
== initial_layout
)
350 const bool hiz_enabled
= layout_to_hiz_usage(initial_layout
, image
->samples
) ==
352 const bool enable_hiz
= layout_to_hiz_usage(final_layout
, image
->samples
) ==
355 enum blorp_hiz_op hiz_op
;
356 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
357 /* We've already initialized the aux HiZ buffer at BindImageMemory time,
358 * so there's no need to perform a HIZ resolve or clear to avoid GPU hangs.
359 * This initial layout indicates that the user doesn't care about the data
360 * that's currently in the buffer, so resolves are not necessary except
361 * for the special case noted below.
363 hiz_op
= BLORP_HIZ_OP_NONE
;
364 } else if (hiz_enabled
&& !enable_hiz
) {
365 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
366 } else if (!hiz_enabled
&& enable_hiz
) {
367 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
369 assert(hiz_enabled
== enable_hiz
);
370 /* If the same buffer will be used, no resolves are necessary except for
371 * the special case noted below.
373 hiz_op
= BLORP_HIZ_OP_NONE
;
376 if (hiz_op
!= BLORP_HIZ_OP_NONE
)
377 anv_gen8_hiz_op_resolve(cmd_buffer
, image
, hiz_op
);
379 /* Images that have sampling with HiZ enabled cause all shader sampling to
380 * load data with the HiZ buffer. Therefore, in the case of transitioning to
381 * the general layout - which currently routes all writes to the depth
382 * buffer - we must ensure that the HiZ buffer remains consistent with the
383 * depth buffer by performing an additional HIZ resolve if the operation
384 * required by this transition was not already a HiZ resolve.
386 if (final_layout
== VK_IMAGE_LAYOUT_GENERAL
&&
387 anv_can_sample_with_hiz(GEN_GEN
, image
->samples
) &&
388 hiz_op
!= BLORP_HIZ_OP_HIZ_RESOLVE
) {
389 anv_gen8_hiz_op_resolve(cmd_buffer
, image
, BLORP_HIZ_OP_HIZ_RESOLVE
);
395 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
398 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
399 struct anv_render_pass
*pass
,
400 const VkRenderPassBeginInfo
*begin
)
402 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
403 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
405 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
407 if (pass
->attachment_count
== 0) {
408 state
->attachments
= NULL
;
412 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
413 pass
->attachment_count
*
414 sizeof(state
->attachments
[0]),
415 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
416 if (state
->attachments
== NULL
) {
417 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
421 bool need_null_state
= false;
422 unsigned num_states
= 0;
423 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
424 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
427 /* We need a null state for any depth-stencil-only subpasses.
428 * Importantly, this includes depth/stencil clears so we create one
429 * whenever we have depth or stencil
431 need_null_state
= true;
434 if (need_input_attachment_state(&pass
->attachments
[i
]))
437 num_states
+= need_null_state
;
439 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
440 state
->render_pass_states
=
441 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
442 num_states
* ss_stride
, isl_dev
->ss
.align
);
444 struct anv_state next_state
= state
->render_pass_states
;
445 next_state
.alloc_size
= isl_dev
->ss
.size
;
447 if (need_null_state
) {
448 state
->null_surface_state
= next_state
;
449 next_state
.offset
+= ss_stride
;
450 next_state
.map
+= ss_stride
;
453 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
454 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
455 state
->attachments
[i
].color_rt_state
= next_state
;
456 next_state
.offset
+= ss_stride
;
457 next_state
.map
+= ss_stride
;
460 if (need_input_attachment_state(&pass
->attachments
[i
])) {
461 state
->attachments
[i
].input_att_state
= next_state
;
462 next_state
.offset
+= ss_stride
;
463 next_state
.map
+= ss_stride
;
466 assert(next_state
.offset
== state
->render_pass_states
.offset
+
467 state
->render_pass_states
.alloc_size
);
470 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
471 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
473 if (need_null_state
) {
474 struct GENX(RENDER_SURFACE_STATE
) null_ss
= {
475 .SurfaceType
= SURFTYPE_NULL
,
476 .SurfaceArray
= framebuffer
->layers
> 0,
477 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
481 .TiledSurface
= true,
483 .Width
= framebuffer
->width
- 1,
484 .Height
= framebuffer
->height
- 1,
485 .Depth
= framebuffer
->layers
- 1,
486 .RenderTargetViewExtent
= framebuffer
->layers
- 1,
488 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
->null_surface_state
.map
,
492 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
493 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
494 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
495 VkImageAspectFlags clear_aspects
= 0;
497 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
498 /* color attachment */
499 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
500 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
503 /* depthstencil attachment */
504 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
505 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
506 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
508 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
509 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
510 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
514 state
->attachments
[i
].current_layout
= att
->initial_layout
;
515 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
517 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
519 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
520 assert(iview
->vk_format
== att
->format
);
522 union isl_color_value clear_color
= { .u32
= { 0, } };
523 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
524 color_attachment_compute_aux_usage(cmd_buffer
->device
,
525 &state
->attachments
[i
],
526 iview
, begin
->renderArea
,
529 struct isl_view view
= iview
->isl
;
530 view
.usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
531 view
.swizzle
= anv_swizzle_for_render(view
.swizzle
);
532 isl_surf_fill_state(isl_dev
,
533 state
->attachments
[i
].color_rt_state
.map
,
534 .surf
= &iview
->image
->color_surface
.isl
,
536 .aux_surf
= &iview
->image
->aux_surface
.isl
,
537 .aux_usage
= state
->attachments
[i
].aux_usage
,
538 .clear_color
= clear_color
,
539 .mocs
= cmd_buffer
->device
->default_mocs
);
541 add_image_view_relocs(cmd_buffer
, iview
,
542 state
->attachments
[i
].aux_usage
,
543 state
->attachments
[i
].color_rt_state
);
545 if (iview
->image
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
546 state
->attachments
[i
].aux_usage
=
547 layout_to_hiz_usage(att
->initial_layout
, iview
->image
->samples
);
549 state
->attachments
[i
].aux_usage
= ISL_AUX_USAGE_NONE
;
551 state
->attachments
[i
].input_aux_usage
= ISL_AUX_USAGE_NONE
;
554 if (need_input_attachment_state(&pass
->attachments
[i
])) {
555 struct isl_view view
= iview
->isl
;
556 view
.usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
557 isl_surf_fill_state(isl_dev
,
558 state
->attachments
[i
].input_att_state
.map
,
559 .surf
= &iview
->image
->color_surface
.isl
,
561 .aux_surf
= &iview
->image
->aux_surface
.isl
,
562 .aux_usage
= state
->attachments
[i
].input_aux_usage
,
563 .clear_color
= clear_color
,
564 .mocs
= cmd_buffer
->device
->default_mocs
);
566 add_image_view_relocs(cmd_buffer
, iview
,
567 state
->attachments
[i
].input_aux_usage
,
568 state
->attachments
[i
].input_att_state
);
572 if (!cmd_buffer
->device
->info
.has_llc
)
573 anv_state_clflush(state
->render_pass_states
);
578 genX(BeginCommandBuffer
)(
579 VkCommandBuffer commandBuffer
,
580 const VkCommandBufferBeginInfo
* pBeginInfo
)
582 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
584 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
585 * command buffer's state. Otherwise, we must *reset* its state. In both
588 * From the Vulkan 1.0 spec:
590 * If a command buffer is in the executable state and the command buffer
591 * was allocated from a command pool with the
592 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
593 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
594 * as if vkResetCommandBuffer had been called with
595 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
596 * the command buffer in the recording state.
598 anv_cmd_buffer_reset(cmd_buffer
);
600 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
602 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
603 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
605 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
607 if (cmd_buffer
->usage_flags
&
608 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
609 cmd_buffer
->state
.pass
=
610 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
611 cmd_buffer
->state
.subpass
=
612 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
613 cmd_buffer
->state
.framebuffer
= NULL
;
615 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, cmd_buffer
->state
.pass
,
618 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
625 genX(EndCommandBuffer
)(
626 VkCommandBuffer commandBuffer
)
628 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
630 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
632 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
638 genX(CmdExecuteCommands
)(
639 VkCommandBuffer commandBuffer
,
640 uint32_t commandBufferCount
,
641 const VkCommandBuffer
* pCmdBuffers
)
643 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
645 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
647 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
648 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
650 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
652 if (secondary
->usage_flags
&
653 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
654 /* If we're continuing a render pass from the primary, we need to
655 * copy the surface states for the current subpass into the storage
656 * we allocated for them in BeginCommandBuffer.
658 struct anv_bo
*ss_bo
= &primary
->device
->surface_state_block_pool
.bo
;
659 struct anv_state src_state
= primary
->state
.render_pass_states
;
660 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
661 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
663 genX(cmd_buffer_gpu_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
664 ss_bo
, src_state
.offset
,
665 src_state
.alloc_size
);
668 anv_cmd_buffer_add_secondary(primary
, secondary
);
671 /* Each of the secondary command buffers will use its own state base
672 * address. We need to re-emit state base address for the primary after
673 * all of the secondaries are done.
675 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
678 genX(cmd_buffer_emit_state_base_address
)(primary
);
681 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
682 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
683 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
686 * Program the hardware to use the specified L3 configuration.
689 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
690 const struct gen_l3_config
*cfg
)
693 if (cfg
== cmd_buffer
->state
.current_l3_config
)
696 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
697 fprintf(stderr
, "L3 config transition: ");
698 gen_dump_l3_config(cfg
, stderr
);
701 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
703 /* According to the hardware docs, the L3 partitioning can only be changed
704 * while the pipeline is completely drained and the caches are flushed,
705 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
707 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
708 pc
.DCFlushEnable
= true;
709 pc
.PostSyncOperation
= NoWrite
;
710 pc
.CommandStreamerStallEnable
= true;
713 /* ...followed by a second pipelined PIPE_CONTROL that initiates
714 * invalidation of the relevant caches. Note that because RO invalidation
715 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
716 * command is processed by the CS) we cannot combine it with the previous
717 * stalling flush as the hardware documentation suggests, because that
718 * would cause the CS to stall on previous rendering *after* RO
719 * invalidation and wouldn't prevent the RO caches from being polluted by
720 * concurrent rendering before the stall completes. This intentionally
721 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
722 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
723 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
724 * already guarantee that there is no concurrent GPGPU kernel execution
725 * (see SKL HSD 2132585).
727 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
728 pc
.TextureCacheInvalidationEnable
= true;
729 pc
.ConstantCacheInvalidationEnable
= true;
730 pc
.InstructionCacheInvalidateEnable
= true;
731 pc
.StateCacheInvalidationEnable
= true;
732 pc
.PostSyncOperation
= NoWrite
;
735 /* Now send a third stalling flush to make sure that invalidation is
736 * complete when the L3 configuration registers are modified.
738 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
739 pc
.DCFlushEnable
= true;
740 pc
.PostSyncOperation
= NoWrite
;
741 pc
.CommandStreamerStallEnable
= true;
746 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
749 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
750 .SLMEnable
= has_slm
,
751 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
752 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
753 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
754 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
756 /* Set up the L3 partitioning. */
757 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
761 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
762 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
764 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
766 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
769 assert(!cfg
->n
[GEN_L3P_ALL
]);
771 /* When enabled SLM only uses a portion of the L3 on half of the banks,
772 * the matching space on the remaining banks has to be allocated to a
773 * client (URB for all validated configurations) set to the
774 * lower-bandwidth 2-bank address hashing mode.
776 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
777 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
778 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
780 /* Minimum number of ways that can be allocated to the URB. */
781 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
782 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
784 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
785 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
786 .ConvertDC_UC
= !has_dc
,
787 .ConvertIS_UC
= !has_is
,
788 .ConvertC_UC
= !has_c
,
789 .ConvertT_UC
= !has_t
);
791 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
792 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
793 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
795 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
796 .SLMEnable
= has_slm
,
797 .URBLowBandwidth
= urb_low_bw
,
798 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
800 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
802 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
803 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
805 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
806 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
808 .CAllocation
= cfg
->n
[GEN_L3P_C
],
810 .TAllocation
= cfg
->n
[GEN_L3P_T
],
813 /* Set up the L3 partitioning. */
814 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
815 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
816 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
819 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
820 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
821 * them disabled to avoid crashing the system hard.
823 uint32_t scratch1
, chicken3
;
824 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
825 .L3AtomicDisable
= !has_dc
);
826 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
827 .L3AtomicDisableMask
= true,
828 .L3AtomicDisable
= !has_dc
);
829 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
830 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
836 cmd_buffer
->state
.current_l3_config
= cfg
;
840 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
842 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
844 /* Flushes are pipelined while invalidations are handled immediately.
845 * Therefore, if we're flushing anything then we need to schedule a stall
846 * before any invalidations can happen.
848 if (bits
& ANV_PIPE_FLUSH_BITS
)
849 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
851 /* If we're going to do an invalidate and we have a pending CS stall that
852 * has yet to be resolved, we do the CS stall now.
854 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
855 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
856 bits
|= ANV_PIPE_CS_STALL_BIT
;
857 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
860 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
861 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
862 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
863 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
864 pipe
.RenderTargetCacheFlushEnable
=
865 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
867 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
868 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
869 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
872 * According to the Broadwell documentation, any PIPE_CONTROL with the
873 * "Command Streamer Stall" bit set must also have another bit set,
874 * with five different options:
876 * - Render Target Cache Flush
877 * - Depth Cache Flush
878 * - Stall at Pixel Scoreboard
879 * - Post-Sync Operation
883 * I chose "Stall at Pixel Scoreboard" since that's what we use in
884 * mesa and it seems to work fine. The choice is fairly arbitrary.
886 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
887 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
888 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
889 pipe
.StallAtPixelScoreboard
= true;
892 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
895 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
896 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
897 pipe
.StateCacheInvalidationEnable
=
898 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
899 pipe
.ConstantCacheInvalidationEnable
=
900 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
901 pipe
.VFCacheInvalidationEnable
=
902 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
903 pipe
.TextureCacheInvalidationEnable
=
904 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
905 pipe
.InstructionCacheInvalidateEnable
=
906 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
909 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
912 cmd_buffer
->state
.pending_pipe_bits
= bits
;
915 void genX(CmdPipelineBarrier
)(
916 VkCommandBuffer commandBuffer
,
917 VkPipelineStageFlags srcStageMask
,
918 VkPipelineStageFlags destStageMask
,
920 uint32_t memoryBarrierCount
,
921 const VkMemoryBarrier
* pMemoryBarriers
,
922 uint32_t bufferMemoryBarrierCount
,
923 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
924 uint32_t imageMemoryBarrierCount
,
925 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
927 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
930 /* XXX: Right now, we're really dumb and just flush whatever categories
931 * the app asks for. One of these days we may make this a bit better
932 * but right now that's all the hardware allows for in most areas.
934 VkAccessFlags src_flags
= 0;
935 VkAccessFlags dst_flags
= 0;
937 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
938 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
939 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
942 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
943 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
944 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
947 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
948 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
949 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
950 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
951 if (pImageMemoryBarriers
[i
].subresourceRange
.aspectMask
&
952 VK_IMAGE_ASPECT_DEPTH_BIT
) {
953 transition_depth_buffer(cmd_buffer
, image
,
954 pImageMemoryBarriers
[i
].oldLayout
,
955 pImageMemoryBarriers
[i
].newLayout
);
959 enum anv_pipe_bits pipe_bits
= 0;
961 for_each_bit(b
, src_flags
) {
962 switch ((VkAccessFlagBits
)(1 << b
)) {
963 case VK_ACCESS_SHADER_WRITE_BIT
:
964 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
966 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
967 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
969 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
970 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
972 case VK_ACCESS_TRANSFER_WRITE_BIT
:
973 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
974 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
977 break; /* Nothing to do */
981 for_each_bit(b
, dst_flags
) {
982 switch ((VkAccessFlagBits
)(1 << b
)) {
983 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
984 case VK_ACCESS_INDEX_READ_BIT
:
985 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
986 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
988 case VK_ACCESS_UNIFORM_READ_BIT
:
989 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
990 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
992 case VK_ACCESS_SHADER_READ_BIT
:
993 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
994 case VK_ACCESS_TRANSFER_READ_BIT
:
995 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
998 break; /* Nothing to do */
1002 cmd_buffer
->state
.pending_pipe_bits
|= pipe_bits
;
1006 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1008 VkShaderStageFlags stages
= cmd_buffer
->state
.pipeline
->active_stages
;
1010 /* In order to avoid thrash, we assume that vertex and fragment stages
1011 * always exist. In the rare case where one is missing *and* the other
1012 * uses push concstants, this may be suboptimal. However, avoiding stalls
1013 * seems more important.
1015 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1017 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1021 const unsigned push_constant_kb
= 32;
1022 #elif GEN_IS_HASWELL
1023 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1025 const unsigned push_constant_kb
= 16;
1028 const unsigned num_stages
=
1029 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1030 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1032 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1033 * units of 2KB. Incidentally, these are the same platforms that have
1034 * 32KB worth of push constant space.
1036 if (push_constant_kb
== 32)
1037 size_per_stage
&= ~1u;
1039 uint32_t kb_used
= 0;
1040 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1041 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1042 anv_batch_emit(&cmd_buffer
->batch
,
1043 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1044 alloc
._3DCommandSubOpcode
= 18 + i
;
1045 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1046 alloc
.ConstantBufferSize
= push_size
;
1048 kb_used
+= push_size
;
1051 anv_batch_emit(&cmd_buffer
->batch
,
1052 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1053 alloc
.ConstantBufferOffset
= kb_used
;
1054 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1057 cmd_buffer
->state
.push_constant_stages
= stages
;
1059 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1061 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1062 * the next 3DPRIMITIVE command after programming the
1063 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1065 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1066 * pipeline setup, we need to dirty push constants.
1068 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1072 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1073 gl_shader_stage stage
,
1074 struct anv_state
*bt_state
)
1076 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1077 struct anv_pipeline
*pipeline
;
1078 uint32_t bias
, state_offset
;
1081 case MESA_SHADER_COMPUTE
:
1082 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1086 pipeline
= cmd_buffer
->state
.pipeline
;
1091 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1092 *bt_state
= (struct anv_state
) { 0, };
1096 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1097 if (bias
+ map
->surface_count
== 0) {
1098 *bt_state
= (struct anv_state
) { 0, };
1102 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
1103 bias
+ map
->surface_count
,
1105 uint32_t *bt_map
= bt_state
->map
;
1107 if (bt_state
->map
== NULL
)
1108 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1110 if (stage
== MESA_SHADER_COMPUTE
&&
1111 get_cs_prog_data(cmd_buffer
->state
.compute_pipeline
)->uses_num_work_groups
) {
1112 struct anv_bo
*bo
= cmd_buffer
->state
.num_workgroups_bo
;
1113 uint32_t bo_offset
= cmd_buffer
->state
.num_workgroups_offset
;
1115 struct anv_state surface_state
;
1117 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
1119 const enum isl_format format
=
1120 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
1121 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1122 format
, bo_offset
, 12, 1);
1124 bt_map
[0] = surface_state
.offset
+ state_offset
;
1125 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
1128 if (map
->surface_count
== 0)
1131 if (map
->image_count
> 0) {
1133 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
1134 if (result
!= VK_SUCCESS
)
1137 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
1141 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
1142 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
1144 struct anv_state surface_state
;
1146 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
1147 /* Color attachment binding */
1148 assert(stage
== MESA_SHADER_FRAGMENT
);
1149 assert(binding
->binding
== 0);
1150 if (binding
->index
< subpass
->color_count
) {
1151 const unsigned att
= subpass
->color_attachments
[binding
->index
];
1152 surface_state
= cmd_buffer
->state
.attachments
[att
].color_rt_state
;
1154 surface_state
= cmd_buffer
->state
.null_surface_state
;
1157 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1161 struct anv_descriptor_set
*set
=
1162 cmd_buffer
->state
.descriptors
[binding
->set
];
1163 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1164 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1166 switch (desc
->type
) {
1167 case VK_DESCRIPTOR_TYPE_SAMPLER
:
1168 /* Nothing for us to do here */
1171 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
1172 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
1173 surface_state
= desc
->image_view
->sampler_surface_state
;
1174 assert(surface_state
.alloc_size
);
1175 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1176 desc
->image_view
->image
->aux_usage
,
1180 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
1181 assert(stage
== MESA_SHADER_FRAGMENT
);
1182 if (desc
->image_view
->aspect_mask
!= VK_IMAGE_ASPECT_COLOR_BIT
) {
1183 /* For depth and stencil input attachments, we treat it like any
1184 * old texture that a user may have bound.
1186 surface_state
= desc
->image_view
->sampler_surface_state
;
1187 assert(surface_state
.alloc_size
);
1188 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1189 desc
->image_view
->image
->aux_usage
,
1192 /* For color input attachments, we create the surface state at
1193 * vkBeginRenderPass time so that we can include aux and clear
1194 * color information.
1196 assert(binding
->input_attachment_index
< subpass
->input_count
);
1197 const unsigned subpass_att
= binding
->input_attachment_index
;
1198 const unsigned att
= subpass
->input_attachments
[subpass_att
];
1199 surface_state
= cmd_buffer
->state
.attachments
[att
].input_att_state
;
1203 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
1204 surface_state
= desc
->image_view
->storage_surface_state
;
1205 assert(surface_state
.alloc_size
);
1206 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1207 desc
->image_view
->image
->aux_usage
,
1210 struct brw_image_param
*image_param
=
1211 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1213 *image_param
= desc
->image_view
->storage_image_param
;
1214 image_param
->surface_idx
= bias
+ s
;
1218 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
1219 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
1220 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
1221 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
1222 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
1223 surface_state
= desc
->buffer_view
->surface_state
;
1224 assert(surface_state
.alloc_size
);
1225 add_surface_state_reloc(cmd_buffer
, surface_state
,
1226 desc
->buffer_view
->bo
,
1227 desc
->buffer_view
->offset
);
1230 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
1231 surface_state
= desc
->buffer_view
->storage_surface_state
;
1232 assert(surface_state
.alloc_size
);
1233 add_surface_state_reloc(cmd_buffer
, surface_state
,
1234 desc
->buffer_view
->bo
,
1235 desc
->buffer_view
->offset
);
1237 struct brw_image_param
*image_param
=
1238 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1240 *image_param
= desc
->buffer_view
->storage_image_param
;
1241 image_param
->surface_idx
= bias
+ s
;
1245 assert(!"Invalid descriptor type");
1249 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1251 assert(image
== map
->image_count
);
1254 if (!cmd_buffer
->device
->info
.has_llc
)
1255 anv_state_clflush(*bt_state
);
1261 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
1262 gl_shader_stage stage
,
1263 struct anv_state
*state
)
1265 struct anv_pipeline
*pipeline
;
1267 if (stage
== MESA_SHADER_COMPUTE
)
1268 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1270 pipeline
= cmd_buffer
->state
.pipeline
;
1272 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1273 *state
= (struct anv_state
) { 0, };
1277 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1278 if (map
->sampler_count
== 0) {
1279 *state
= (struct anv_state
) { 0, };
1283 uint32_t size
= map
->sampler_count
* 16;
1284 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
1286 if (state
->map
== NULL
)
1287 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1289 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
1290 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
1291 struct anv_descriptor_set
*set
=
1292 cmd_buffer
->state
.descriptors
[binding
->set
];
1293 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1294 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1296 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
1297 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
1300 struct anv_sampler
*sampler
= desc
->sampler
;
1302 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
1303 * happens to be zero.
1305 if (sampler
== NULL
)
1308 memcpy(state
->map
+ (s
* 16),
1309 sampler
->state
, sizeof(sampler
->state
));
1312 if (!cmd_buffer
->device
->info
.has_llc
)
1313 anv_state_clflush(*state
);
1319 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
1321 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
1322 cmd_buffer
->state
.pipeline
->active_stages
;
1324 VkResult result
= VK_SUCCESS
;
1325 anv_foreach_stage(s
, dirty
) {
1326 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1327 if (result
!= VK_SUCCESS
)
1329 result
= emit_binding_table(cmd_buffer
, s
,
1330 &cmd_buffer
->state
.binding_tables
[s
]);
1331 if (result
!= VK_SUCCESS
)
1335 if (result
!= VK_SUCCESS
) {
1336 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1338 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1339 assert(result
== VK_SUCCESS
);
1341 /* Re-emit state base addresses so we get the new surface state base
1342 * address before we start emitting binding tables etc.
1344 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1346 /* Re-emit all active binding tables */
1347 dirty
|= cmd_buffer
->state
.pipeline
->active_stages
;
1348 anv_foreach_stage(s
, dirty
) {
1349 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1350 if (result
!= VK_SUCCESS
)
1352 result
= emit_binding_table(cmd_buffer
, s
,
1353 &cmd_buffer
->state
.binding_tables
[s
]);
1354 if (result
!= VK_SUCCESS
)
1359 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
1365 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
1368 static const uint32_t sampler_state_opcodes
[] = {
1369 [MESA_SHADER_VERTEX
] = 43,
1370 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
1371 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
1372 [MESA_SHADER_GEOMETRY
] = 46,
1373 [MESA_SHADER_FRAGMENT
] = 47,
1374 [MESA_SHADER_COMPUTE
] = 0,
1377 static const uint32_t binding_table_opcodes
[] = {
1378 [MESA_SHADER_VERTEX
] = 38,
1379 [MESA_SHADER_TESS_CTRL
] = 39,
1380 [MESA_SHADER_TESS_EVAL
] = 40,
1381 [MESA_SHADER_GEOMETRY
] = 41,
1382 [MESA_SHADER_FRAGMENT
] = 42,
1383 [MESA_SHADER_COMPUTE
] = 0,
1386 anv_foreach_stage(s
, stages
) {
1387 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
1388 anv_batch_emit(&cmd_buffer
->batch
,
1389 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
1390 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
1391 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
1395 /* Always emit binding table pointers if we're asked to, since on SKL
1396 * this is what flushes push constants. */
1397 anv_batch_emit(&cmd_buffer
->batch
,
1398 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
1399 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
1400 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
1406 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1408 static const uint32_t push_constant_opcodes
[] = {
1409 [MESA_SHADER_VERTEX
] = 21,
1410 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
1411 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
1412 [MESA_SHADER_GEOMETRY
] = 22,
1413 [MESA_SHADER_FRAGMENT
] = 23,
1414 [MESA_SHADER_COMPUTE
] = 0,
1417 VkShaderStageFlags flushed
= 0;
1419 anv_foreach_stage(stage
, cmd_buffer
->state
.push_constants_dirty
) {
1420 if (stage
== MESA_SHADER_COMPUTE
)
1423 struct anv_state state
= anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
1425 if (state
.offset
== 0) {
1426 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
)
1427 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
1429 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
1430 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
],
1431 c
.ConstantBody
= (struct GENX(3DSTATE_CONSTANT_BODY
)) {
1433 .PointerToConstantBuffer2
= { &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, state
.offset
},
1434 .ConstantBuffer2ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1436 .PointerToConstantBuffer0
= { .offset
= state
.offset
},
1437 .ConstantBuffer0ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1443 flushed
|= mesa_to_vk_shader_stage(stage
);
1446 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_ALL_GRAPHICS
;
1452 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1454 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1457 uint32_t vb_emit
= cmd_buffer
->state
.vb_dirty
& pipeline
->vb_used
;
1459 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
1461 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1463 genX(flush_pipeline_select_3d
)(cmd_buffer
);
1466 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
1467 const uint32_t num_dwords
= 1 + num_buffers
* 4;
1469 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
1470 GENX(3DSTATE_VERTEX_BUFFERS
));
1472 for_each_bit(vb
, vb_emit
) {
1473 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1474 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
1476 struct GENX(VERTEX_BUFFER_STATE
) state
= {
1477 .VertexBufferIndex
= vb
,
1480 .MemoryObjectControlState
= GENX(MOCS
),
1482 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
1483 .InstanceDataStepRate
= 1,
1484 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1487 .AddressModifyEnable
= true,
1488 .BufferPitch
= pipeline
->binding_stride
[vb
],
1489 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
1492 .BufferSize
= buffer
->size
- offset
1494 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
1498 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
1503 cmd_buffer
->state
.vb_dirty
&= ~vb_emit
;
1505 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1506 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1508 /* The exact descriptor layout is pulled from the pipeline, so we need
1509 * to re-emit binding tables on every pipeline change.
1511 cmd_buffer
->state
.descriptors_dirty
|=
1512 cmd_buffer
->state
.pipeline
->active_stages
;
1514 /* If the pipeline changed, we may need to re-allocate push constant
1517 cmd_buffer_alloc_push_constants(cmd_buffer
);
1521 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
1522 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
1523 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
1525 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
1526 * stall needs to be sent just prior to any 3DSTATE_VS,
1527 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
1528 * 3DSTATE_BINDING_TABLE_POINTER_VS,
1529 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
1530 * PIPE_CONTROL needs to be sent before any combination of VS
1531 * associated 3DSTATE."
1533 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1534 pc
.DepthStallEnable
= true;
1535 pc
.PostSyncOperation
= WriteImmediateData
;
1537 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1542 /* Render targets live in the same binding table as fragment descriptors */
1543 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
1544 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
1546 /* We emit the binding tables and sampler tables first, then emit push
1547 * constants and then finally emit binding table and sampler table
1548 * pointers. It has to happen in this order, since emitting the binding
1549 * tables may change the push constants (in case of storage images). After
1550 * emitting push constants, on SKL+ we have to emit the corresponding
1551 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
1554 if (cmd_buffer
->state
.descriptors_dirty
)
1555 dirty
= flush_descriptor_sets(cmd_buffer
);
1557 if (cmd_buffer
->state
.push_constants_dirty
) {
1559 /* On Sky Lake and later, the binding table pointers commands are
1560 * what actually flush the changes to push constant state so we need
1561 * to dirty them so they get re-emitted below.
1563 dirty
|= cmd_buffer_flush_push_constants(cmd_buffer
);
1565 cmd_buffer_flush_push_constants(cmd_buffer
);
1570 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
1572 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
1573 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
1575 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
1576 ANV_CMD_DIRTY_PIPELINE
)) {
1577 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
1578 pipeline
->depth_clamp_enable
);
1581 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
1582 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
1584 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
1586 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1590 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
1591 struct anv_bo
*bo
, uint32_t offset
)
1593 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
1594 GENX(3DSTATE_VERTEX_BUFFERS
));
1596 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
1597 &(struct GENX(VERTEX_BUFFER_STATE
)) {
1598 .VertexBufferIndex
= ANV_SVGS_VB_INDEX
, /* Reserved for this */
1599 .AddressModifyEnable
= true,
1602 .MemoryObjectControlState
= GENX(MOCS
),
1603 .BufferStartingAddress
= { bo
, offset
},
1606 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1607 .BufferStartingAddress
= { bo
, offset
},
1608 .EndAddress
= { bo
, offset
+ 8 },
1614 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
1615 uint32_t base_vertex
, uint32_t base_instance
)
1617 struct anv_state id_state
=
1618 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
1620 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
1621 ((uint32_t *)id_state
.map
)[1] = base_instance
;
1623 if (!cmd_buffer
->device
->info
.has_llc
)
1624 anv_state_clflush(id_state
);
1626 emit_base_vertex_instance_bo(cmd_buffer
,
1627 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, id_state
.offset
);
1631 VkCommandBuffer commandBuffer
,
1632 uint32_t vertexCount
,
1633 uint32_t instanceCount
,
1634 uint32_t firstVertex
,
1635 uint32_t firstInstance
)
1637 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1638 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1639 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1641 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1643 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1644 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
1646 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1647 prim
.VertexAccessType
= SEQUENTIAL
;
1648 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1649 prim
.VertexCountPerInstance
= vertexCount
;
1650 prim
.StartVertexLocation
= firstVertex
;
1651 prim
.InstanceCount
= instanceCount
;
1652 prim
.StartInstanceLocation
= firstInstance
;
1653 prim
.BaseVertexLocation
= 0;
1657 void genX(CmdDrawIndexed
)(
1658 VkCommandBuffer commandBuffer
,
1659 uint32_t indexCount
,
1660 uint32_t instanceCount
,
1661 uint32_t firstIndex
,
1662 int32_t vertexOffset
,
1663 uint32_t firstInstance
)
1665 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1666 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1667 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1669 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1671 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1672 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
1674 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1675 prim
.VertexAccessType
= RANDOM
;
1676 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1677 prim
.VertexCountPerInstance
= indexCount
;
1678 prim
.StartVertexLocation
= firstIndex
;
1679 prim
.InstanceCount
= instanceCount
;
1680 prim
.StartInstanceLocation
= firstInstance
;
1681 prim
.BaseVertexLocation
= vertexOffset
;
1685 /* Auto-Draw / Indirect Registers */
1686 #define GEN7_3DPRIM_END_OFFSET 0x2420
1687 #define GEN7_3DPRIM_START_VERTEX 0x2430
1688 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
1689 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
1690 #define GEN7_3DPRIM_START_INSTANCE 0x243C
1691 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
1693 void genX(CmdDrawIndirect
)(
1694 VkCommandBuffer commandBuffer
,
1696 VkDeviceSize offset
,
1700 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1701 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1702 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1703 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1704 struct anv_bo
*bo
= buffer
->bo
;
1705 uint32_t bo_offset
= buffer
->offset
+ offset
;
1707 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1709 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1710 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
1712 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1713 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1714 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1715 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
1716 emit_lri(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
1718 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1719 prim
.IndirectParameterEnable
= true;
1720 prim
.VertexAccessType
= SEQUENTIAL
;
1721 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1725 void genX(CmdDrawIndexedIndirect
)(
1726 VkCommandBuffer commandBuffer
,
1728 VkDeviceSize offset
,
1732 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1733 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1734 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1735 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1736 struct anv_bo
*bo
= buffer
->bo
;
1737 uint32_t bo_offset
= buffer
->offset
+ offset
;
1739 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1741 /* TODO: We need to stomp base vertex to 0 somehow */
1742 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1743 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
1745 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1746 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1747 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1748 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
1749 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
1751 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1752 prim
.IndirectParameterEnable
= true;
1753 prim
.VertexAccessType
= RANDOM
;
1754 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1759 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
1761 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1762 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
1765 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1766 if (result
!= VK_SUCCESS
) {
1767 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1768 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1769 assert(result
== VK_SUCCESS
);
1771 /* Re-emit state base addresses so we get the new surface state base
1772 * address before we start emitting binding tables etc.
1774 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1776 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1777 assert(result
== VK_SUCCESS
);
1780 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
1781 assert(result
== VK_SUCCESS
);
1783 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
1784 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
1785 .BindingTablePointer
= surfaces
.offset
,
1786 .SamplerStatePointer
= samplers
.offset
,
1788 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
1790 struct anv_state state
=
1791 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
1792 pipeline
->interface_descriptor_data
,
1793 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
1796 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
1797 anv_batch_emit(&cmd_buffer
->batch
,
1798 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
1799 mid
.InterfaceDescriptorTotalLength
= size
;
1800 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
1807 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1809 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1810 MAYBE_UNUSED VkResult result
;
1812 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
1814 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1816 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
1818 if (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1819 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
1821 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
1822 * the only bits that are changed are scoreboard related: Scoreboard
1823 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
1824 * these scoreboard related states, a MEDIA_STATE_FLUSH is
1827 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
1828 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1830 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1833 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
1834 (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)) {
1835 /* FIXME: figure out descriptors for gen7 */
1836 result
= flush_compute_descriptor_set(cmd_buffer
);
1837 assert(result
== VK_SUCCESS
);
1838 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
1841 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
1842 struct anv_state push_state
=
1843 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
1845 if (push_state
.alloc_size
) {
1846 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
1847 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
1848 curbe
.CURBEDataStartAddress
= push_state
.offset
;
1853 cmd_buffer
->state
.compute_dirty
= 0;
1855 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1861 verify_cmd_parser(const struct anv_device
*device
,
1862 int required_version
,
1863 const char *function
)
1865 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
1866 vk_errorf(VK_ERROR_FEATURE_NOT_PRESENT
,
1867 "cmd parser version %d is required for %s",
1868 required_version
, function
);
1877 void genX(CmdDispatch
)(
1878 VkCommandBuffer commandBuffer
,
1883 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1884 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1885 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1887 if (prog_data
->uses_num_work_groups
) {
1888 struct anv_state state
=
1889 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
1890 uint32_t *sizes
= state
.map
;
1894 if (!cmd_buffer
->device
->info
.has_llc
)
1895 anv_state_clflush(state
);
1896 cmd_buffer
->state
.num_workgroups_offset
= state
.offset
;
1897 cmd_buffer
->state
.num_workgroups_bo
=
1898 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
;
1901 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1903 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
1904 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
1905 ggw
.ThreadDepthCounterMaximum
= 0;
1906 ggw
.ThreadHeightCounterMaximum
= 0;
1907 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
1908 ggw
.ThreadGroupIDXDimension
= x
;
1909 ggw
.ThreadGroupIDYDimension
= y
;
1910 ggw
.ThreadGroupIDZDimension
= z
;
1911 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
1912 ggw
.BottomExecutionMask
= 0xffffffff;
1915 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
1918 #define GPGPU_DISPATCHDIMX 0x2500
1919 #define GPGPU_DISPATCHDIMY 0x2504
1920 #define GPGPU_DISPATCHDIMZ 0x2508
1922 #define MI_PREDICATE_SRC0 0x2400
1923 #define MI_PREDICATE_SRC1 0x2408
1925 void genX(CmdDispatchIndirect
)(
1926 VkCommandBuffer commandBuffer
,
1928 VkDeviceSize offset
)
1930 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1931 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1932 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1933 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1934 struct anv_bo
*bo
= buffer
->bo
;
1935 uint32_t bo_offset
= buffer
->offset
+ offset
;
1936 struct anv_batch
*batch
= &cmd_buffer
->batch
;
1939 /* Linux 4.4 added command parser version 5 which allows the GPGPU
1940 * indirect dispatch registers to be written.
1942 if (!verify_cmd_parser(cmd_buffer
->device
, 5, "vkCmdDispatchIndirect"))
1946 if (prog_data
->uses_num_work_groups
) {
1947 cmd_buffer
->state
.num_workgroups_offset
= bo_offset
;
1948 cmd_buffer
->state
.num_workgroups_bo
= bo
;
1951 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1953 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
1954 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
1955 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
1958 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
1959 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
1960 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
1961 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
1963 /* Load compute_dispatch_indirect_x_size into SRC0 */
1964 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
1966 /* predicate = (compute_dispatch_indirect_x_size == 0); */
1967 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1968 mip
.LoadOperation
= LOAD_LOAD
;
1969 mip
.CombineOperation
= COMBINE_SET
;
1970 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1973 /* Load compute_dispatch_indirect_y_size into SRC0 */
1974 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
1976 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
1977 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1978 mip
.LoadOperation
= LOAD_LOAD
;
1979 mip
.CombineOperation
= COMBINE_OR
;
1980 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1983 /* Load compute_dispatch_indirect_z_size into SRC0 */
1984 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
1986 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
1987 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1988 mip
.LoadOperation
= LOAD_LOAD
;
1989 mip
.CombineOperation
= COMBINE_OR
;
1990 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1993 /* predicate = !predicate; */
1994 #define COMPARE_FALSE 1
1995 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1996 mip
.LoadOperation
= LOAD_LOADINV
;
1997 mip
.CombineOperation
= COMBINE_OR
;
1998 mip
.CompareOperation
= COMPARE_FALSE
;
2002 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
2003 ggw
.IndirectParameterEnable
= true;
2004 ggw
.PredicateEnable
= GEN_GEN
<= 7;
2005 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
2006 ggw
.ThreadDepthCounterMaximum
= 0;
2007 ggw
.ThreadHeightCounterMaximum
= 0;
2008 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
2009 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
2010 ggw
.BottomExecutionMask
= 0xffffffff;
2013 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
2017 flush_pipeline_before_pipeline_select(struct anv_cmd_buffer
*cmd_buffer
,
2020 #if GEN_GEN >= 8 && GEN_GEN < 10
2021 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
2023 * Software must clear the COLOR_CALC_STATE Valid field in
2024 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
2025 * with Pipeline Select set to GPGPU.
2027 * The internal hardware docs recommend the same workaround for Gen9
2030 if (pipeline
== GPGPU
)
2031 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
2033 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
2034 * PIPELINE_SELECT [DevBWR+]":
2038 * Software must ensure all the write caches are flushed through a
2039 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
2040 * command to invalidate read only caches prior to programming
2041 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
2043 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2044 pc
.RenderTargetCacheFlushEnable
= true;
2045 pc
.DepthCacheFlushEnable
= true;
2046 pc
.DCFlushEnable
= true;
2047 pc
.PostSyncOperation
= NoWrite
;
2048 pc
.CommandStreamerStallEnable
= true;
2051 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2052 pc
.TextureCacheInvalidationEnable
= true;
2053 pc
.ConstantCacheInvalidationEnable
= true;
2054 pc
.StateCacheInvalidationEnable
= true;
2055 pc
.InstructionCacheInvalidateEnable
= true;
2056 pc
.PostSyncOperation
= NoWrite
;
2062 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
2064 if (cmd_buffer
->state
.current_pipeline
!= _3D
) {
2065 flush_pipeline_before_pipeline_select(cmd_buffer
, _3D
);
2067 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
2071 ps
.PipelineSelection
= _3D
;
2074 cmd_buffer
->state
.current_pipeline
= _3D
;
2079 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
2081 if (cmd_buffer
->state
.current_pipeline
!= GPGPU
) {
2082 flush_pipeline_before_pipeline_select(cmd_buffer
, GPGPU
);
2084 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
2088 ps
.PipelineSelection
= GPGPU
;
2091 cmd_buffer
->state
.current_pipeline
= GPGPU
;
2096 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
2101 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
2103 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
2104 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
2105 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
2106 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
2107 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
2108 * Depth Flush Bit set, followed by another pipelined depth stall
2109 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
2110 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
2111 * via a preceding MI_FLUSH)."
2113 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2114 pipe
.DepthStallEnable
= true;
2116 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2117 pipe
.DepthCacheFlushEnable
= true;
2119 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2120 pipe
.DepthStallEnable
= true;
2125 depth_stencil_surface_type(enum isl_surf_dim dim
)
2128 case ISL_SURF_DIM_1D
:
2130 /* From the Sky Lake PRM, 3DSTATAE_DEPTH_BUFFER::SurfaceType
2132 * Programming Notes:
2133 * The Surface Type of the depth buffer must be the same as the
2134 * Surface Type of the render target(s) (defined in
2135 * SURFACE_STATE), unless either the depth buffer or render
2136 * targets are SURFTYPE_NULL (see exception below for SKL). 1D
2137 * surface type not allowed for depth surface and stencil surface.
2140 * If depth/stencil is enabled with 1D render target,
2141 * depth/stencil surface type needs to be set to 2D surface type
2142 * and height set to 1. Depth will use (legacy) TileY and stencil
2143 * will use TileW. For this case only, the Surface Type of the
2144 * depth buffer can be 2D while the Surface Type of the render
2145 * target(s) are 1D, representing an exception to a programming
2152 case ISL_SURF_DIM_2D
:
2154 case ISL_SURF_DIM_3D
:
2156 /* The Sky Lake docs list the value for 3D as "Reserved". However,
2157 * they have the exact same layout as 2D arrays on gen9+, so we can
2165 unreachable("Invalid surface dimension");
2170 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
2172 struct anv_device
*device
= cmd_buffer
->device
;
2173 const struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
2174 const struct anv_image_view
*iview
=
2175 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2176 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
2177 const bool has_depth
= image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
2178 const uint32_t ds
= cmd_buffer
->state
.subpass
->depth_stencil_attachment
;
2179 const bool has_hiz
= image
!= NULL
&&
2180 cmd_buffer
->state
.attachments
[ds
].aux_usage
== ISL_AUX_USAGE_HIZ
;
2181 const bool has_stencil
=
2182 image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
2184 /* FIXME: Implement the PMA stall W/A */
2185 /* FIXME: Width and Height are wrong */
2187 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
2189 /* Emit 3DSTATE_DEPTH_BUFFER */
2191 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
2193 depth_stencil_surface_type(image
->depth_surface
.isl
.dim
);
2194 db
.DepthWriteEnable
= true;
2195 db
.StencilWriteEnable
= has_stencil
;
2196 db
.HierarchicalDepthBufferEnable
= has_hiz
;
2198 db
.SurfaceFormat
= isl_surf_get_depth_format(&device
->isl_dev
,
2199 &image
->depth_surface
.isl
);
2201 db
.SurfaceBaseAddress
= (struct anv_address
) {
2203 .offset
= image
->offset
+ image
->depth_surface
.offset
,
2205 db
.DepthBufferObjectControlState
= GENX(MOCS
);
2207 db
.SurfacePitch
= image
->depth_surface
.isl
.row_pitch
- 1;
2208 db
.Height
= image
->extent
.height
- 1;
2209 db
.Width
= image
->extent
.width
- 1;
2210 db
.LOD
= iview
->isl
.base_level
;
2211 db
.MinimumArrayElement
= iview
->isl
.base_array_layer
;
2213 assert(image
->depth_surface
.isl
.dim
!= ISL_SURF_DIM_3D
);
2215 db
.RenderTargetViewExtent
=
2216 iview
->isl
.array_len
- iview
->isl
.base_array_layer
- 1;
2220 isl_surf_get_array_pitch_el_rows(&image
->depth_surface
.isl
) >> 2;
2224 /* Even when no depth buffer is present, the hardware requires that
2225 * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
2227 * If a null depth buffer is bound, the driver must instead bind depth as:
2228 * 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
2229 * 3DSTATE_DEPTH.Width = 1
2230 * 3DSTATE_DEPTH.Height = 1
2231 * 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
2232 * 3DSTATE_DEPTH.SurfaceBaseAddress = 0
2233 * 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
2234 * 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
2235 * 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
2237 * The PRM is wrong, though. The width and height must be programmed to
2238 * actual framebuffer's width and height, even when neither depth buffer
2239 * nor stencil buffer is present. Also, D16_UNORM is not allowed to
2240 * be combined with a stencil buffer so we use D32_FLOAT instead.
2242 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
2245 depth_stencil_surface_type(image
->stencil_surface
.isl
.dim
);
2247 db
.SurfaceType
= SURFTYPE_2D
;
2249 db
.SurfaceFormat
= D32_FLOAT
;
2250 db
.Width
= MAX2(fb
->width
, 1) - 1;
2251 db
.Height
= MAX2(fb
->height
, 1) - 1;
2252 db
.StencilWriteEnable
= has_stencil
;
2257 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
) {
2258 hdb
.HierarchicalDepthBufferObjectControlState
= GENX(MOCS
);
2259 hdb
.SurfacePitch
= image
->aux_surface
.isl
.row_pitch
- 1;
2260 hdb
.SurfaceBaseAddress
= (struct anv_address
) {
2262 .offset
= image
->offset
+ image
->aux_surface
.offset
,
2265 /* From the SKL PRM Vol2a:
2267 * The interpretation of this field is dependent on Surface Type
2269 * - SURFTYPE_1D: distance in pixels between array slices
2270 * - SURFTYPE_2D/CUBE: distance in rows between array slices
2271 * - SURFTYPE_3D: distance in rows between R - slices
2273 * Unfortunately, the docs aren't 100% accurate here. They fail to
2274 * mention that the 1-D rule only applies to linear 1-D images.
2275 * Since depth and HiZ buffers are always tiled, they are treated as
2276 * 2-D images. Prior to Sky Lake, this field is always in rows.
2279 isl_surf_get_array_pitch_sa_rows(&image
->aux_surface
.isl
) >> 2;
2283 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
);
2286 /* Emit 3DSTATE_STENCIL_BUFFER */
2288 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
) {
2289 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2290 sb
.StencilBufferEnable
= true;
2292 sb
.StencilBufferObjectControlState
= GENX(MOCS
);
2294 sb
.SurfacePitch
= image
->stencil_surface
.isl
.row_pitch
- 1;
2297 sb
.SurfaceQPitch
= isl_surf_get_array_pitch_el_rows(&image
->stencil_surface
.isl
) >> 2;
2299 sb
.SurfaceBaseAddress
= (struct anv_address
) {
2301 .offset
= image
->offset
+ image
->stencil_surface
.offset
,
2305 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
);
2308 /* From the IVB PRM Vol2P1, 11.5.5.4 3DSTATE_CLEAR_PARAMS:
2310 * 3DSTATE_CLEAR_PARAMS must always be programmed in the along with
2311 * the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER,
2312 * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER)
2314 * Testing also shows that some variant of this restriction may exist HSW+.
2315 * On BDW+, it is not possible to emit 2 of these packets consecutively when
2316 * both have DepthClearValueValid set. An analysis of such state programming
2317 * on SKL showed that the GPU doesn't register the latter packet's clear
2320 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CLEAR_PARAMS
), cp
) {
2322 cp
.DepthClearValueValid
= true;
2323 cp
.DepthClearValue
= ANV_HZ_FC_VAL
;
2329 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
2330 struct anv_subpass
*subpass
)
2332 cmd_buffer
->state
.subpass
= subpass
;
2334 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
2336 const struct anv_image_view
*iview
=
2337 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2339 if (iview
&& iview
->image
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
2340 const uint32_t ds
= subpass
->depth_stencil_attachment
;
2341 transition_depth_buffer(cmd_buffer
, iview
->image
,
2342 cmd_buffer
->state
.attachments
[ds
].current_layout
,
2343 cmd_buffer
->state
.subpass
->depth_stencil_layout
);
2344 cmd_buffer
->state
.attachments
[ds
].current_layout
=
2345 cmd_buffer
->state
.subpass
->depth_stencil_layout
;
2346 cmd_buffer
->state
.attachments
[ds
].aux_usage
=
2347 layout_to_hiz_usage(cmd_buffer
->state
.subpass
->depth_stencil_layout
,
2348 iview
->image
->samples
);
2351 cmd_buffer_emit_depth_stencil(cmd_buffer
);
2353 anv_cmd_buffer_clear_subpass(cmd_buffer
);
2356 void genX(CmdBeginRenderPass
)(
2357 VkCommandBuffer commandBuffer
,
2358 const VkRenderPassBeginInfo
* pRenderPassBegin
,
2359 VkSubpassContents contents
)
2361 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2362 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2363 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
2365 cmd_buffer
->state
.framebuffer
= framebuffer
;
2366 cmd_buffer
->state
.pass
= pass
;
2367 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
2368 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
2370 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2372 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
2375 void genX(CmdNextSubpass
)(
2376 VkCommandBuffer commandBuffer
,
2377 VkSubpassContents contents
)
2379 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2381 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
2383 const struct anv_image_view
*iview
=
2384 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2386 if (iview
&& iview
->image
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
2387 const uint32_t ds
= cmd_buffer
->state
.subpass
->depth_stencil_attachment
;
2389 if (cmd_buffer
->state
.subpass
- cmd_buffer
->state
.pass
->subpasses
==
2390 cmd_buffer
->state
.pass
->attachments
[ds
].last_subpass_idx
) {
2391 transition_depth_buffer(cmd_buffer
, iview
->image
,
2392 cmd_buffer
->state
.attachments
[ds
].current_layout
,
2393 cmd_buffer
->state
.pass
->attachments
[ds
].final_layout
);
2397 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2398 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
2401 void genX(CmdEndRenderPass
)(
2402 VkCommandBuffer commandBuffer
)
2404 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2406 const struct anv_image_view
*iview
=
2407 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2409 if (iview
&& iview
->image
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
2410 const uint32_t ds
= cmd_buffer
->state
.subpass
->depth_stencil_attachment
;
2412 if (cmd_buffer
->state
.subpass
- cmd_buffer
->state
.pass
->subpasses
==
2413 cmd_buffer
->state
.pass
->attachments
[ds
].last_subpass_idx
) {
2414 transition_depth_buffer(cmd_buffer
, iview
->image
,
2415 cmd_buffer
->state
.attachments
[ds
].current_layout
,
2416 cmd_buffer
->state
.pass
->attachments
[ds
].final_layout
);
2420 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2423 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
2428 emit_ps_depth_count(struct anv_cmd_buffer
*cmd_buffer
,
2429 struct anv_bo
*bo
, uint32_t offset
)
2431 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2432 pc
.DestinationAddressType
= DAT_PPGTT
;
2433 pc
.PostSyncOperation
= WritePSDepthCount
;
2434 pc
.DepthStallEnable
= true;
2435 pc
.Address
= (struct anv_address
) { bo
, offset
};
2437 if (GEN_GEN
== 9 && cmd_buffer
->device
->info
.gt
== 4)
2438 pc
.CommandStreamerStallEnable
= true;
2443 emit_query_availability(struct anv_cmd_buffer
*cmd_buffer
,
2444 struct anv_bo
*bo
, uint32_t offset
)
2446 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2447 pc
.DestinationAddressType
= DAT_PPGTT
;
2448 pc
.PostSyncOperation
= WriteImmediateData
;
2449 pc
.Address
= (struct anv_address
) { bo
, offset
};
2450 pc
.ImmediateData
= 1;
2454 void genX(CmdBeginQuery
)(
2455 VkCommandBuffer commandBuffer
,
2456 VkQueryPool queryPool
,
2458 VkQueryControlFlags flags
)
2460 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2461 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2463 /* Workaround: When meta uses the pipeline with the VS disabled, it seems
2464 * that the pipelining of the depth write breaks. What we see is that
2465 * samples from the render pass clear leaks into the first query
2466 * immediately after the clear. Doing a pipecontrol with a post-sync
2467 * operation and DepthStallEnable seems to work around the issue.
2469 if (cmd_buffer
->state
.need_query_wa
) {
2470 cmd_buffer
->state
.need_query_wa
= false;
2471 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2472 pc
.DepthCacheFlushEnable
= true;
2473 pc
.DepthStallEnable
= true;
2477 switch (pool
->type
) {
2478 case VK_QUERY_TYPE_OCCLUSION
:
2479 emit_ps_depth_count(cmd_buffer
, &pool
->bo
,
2480 query
* sizeof(struct anv_query_pool_slot
));
2483 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
2489 void genX(CmdEndQuery
)(
2490 VkCommandBuffer commandBuffer
,
2491 VkQueryPool queryPool
,
2494 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2495 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2497 switch (pool
->type
) {
2498 case VK_QUERY_TYPE_OCCLUSION
:
2499 emit_ps_depth_count(cmd_buffer
, &pool
->bo
,
2500 query
* sizeof(struct anv_query_pool_slot
) + 8);
2502 emit_query_availability(cmd_buffer
, &pool
->bo
,
2503 query
* sizeof(struct anv_query_pool_slot
) + 16);
2506 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
2512 #define TIMESTAMP 0x2358
2514 void genX(CmdWriteTimestamp
)(
2515 VkCommandBuffer commandBuffer
,
2516 VkPipelineStageFlagBits pipelineStage
,
2517 VkQueryPool queryPool
,
2520 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2521 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2522 uint32_t offset
= query
* sizeof(struct anv_query_pool_slot
);
2524 assert(pool
->type
== VK_QUERY_TYPE_TIMESTAMP
);
2526 switch (pipelineStage
) {
2527 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
:
2528 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2529 srm
.RegisterAddress
= TIMESTAMP
;
2530 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
};
2532 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2533 srm
.RegisterAddress
= TIMESTAMP
+ 4;
2534 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
+ 4 };
2539 /* Everything else is bottom-of-pipe */
2540 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2541 pc
.DestinationAddressType
= DAT_PPGTT
;
2542 pc
.PostSyncOperation
= WriteTimestamp
;
2543 pc
.Address
= (struct anv_address
) { &pool
->bo
, offset
};
2545 if (GEN_GEN
== 9 && cmd_buffer
->device
->info
.gt
== 4)
2546 pc
.CommandStreamerStallEnable
= true;
2551 emit_query_availability(cmd_buffer
, &pool
->bo
, query
+ 16);
2554 #if GEN_GEN > 7 || GEN_IS_HASWELL
2556 #define alu_opcode(v) __gen_uint((v), 20, 31)
2557 #define alu_operand1(v) __gen_uint((v), 10, 19)
2558 #define alu_operand2(v) __gen_uint((v), 0, 9)
2559 #define alu(opcode, operand1, operand2) \
2560 alu_opcode(opcode) | alu_operand1(operand1) | alu_operand2(operand2)
2562 #define OPCODE_NOOP 0x000
2563 #define OPCODE_LOAD 0x080
2564 #define OPCODE_LOADINV 0x480
2565 #define OPCODE_LOAD0 0x081
2566 #define OPCODE_LOAD1 0x481
2567 #define OPCODE_ADD 0x100
2568 #define OPCODE_SUB 0x101
2569 #define OPCODE_AND 0x102
2570 #define OPCODE_OR 0x103
2571 #define OPCODE_XOR 0x104
2572 #define OPCODE_STORE 0x180
2573 #define OPCODE_STOREINV 0x580
2575 #define OPERAND_R0 0x00
2576 #define OPERAND_R1 0x01
2577 #define OPERAND_R2 0x02
2578 #define OPERAND_R3 0x03
2579 #define OPERAND_R4 0x04
2580 #define OPERAND_SRCA 0x20
2581 #define OPERAND_SRCB 0x21
2582 #define OPERAND_ACCU 0x31
2583 #define OPERAND_ZF 0x32
2584 #define OPERAND_CF 0x33
2586 #define CS_GPR(n) (0x2600 + (n) * 8)
2589 emit_load_alu_reg_u64(struct anv_batch
*batch
, uint32_t reg
,
2590 struct anv_bo
*bo
, uint32_t offset
)
2592 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2593 lrm
.RegisterAddress
= reg
,
2594 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
2596 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2597 lrm
.RegisterAddress
= reg
+ 4;
2598 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
2603 store_query_result(struct anv_batch
*batch
, uint32_t reg
,
2604 struct anv_bo
*bo
, uint32_t offset
, VkQueryResultFlags flags
)
2606 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2607 srm
.RegisterAddress
= reg
;
2608 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
2611 if (flags
& VK_QUERY_RESULT_64_BIT
) {
2612 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2613 srm
.RegisterAddress
= reg
+ 4;
2614 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
2619 void genX(CmdCopyQueryPoolResults
)(
2620 VkCommandBuffer commandBuffer
,
2621 VkQueryPool queryPool
,
2622 uint32_t firstQuery
,
2623 uint32_t queryCount
,
2624 VkBuffer destBuffer
,
2625 VkDeviceSize destOffset
,
2626 VkDeviceSize destStride
,
2627 VkQueryResultFlags flags
)
2629 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2630 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2631 ANV_FROM_HANDLE(anv_buffer
, buffer
, destBuffer
);
2632 uint32_t slot_offset
, dst_offset
;
2634 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
2635 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2636 pc
.CommandStreamerStallEnable
= true;
2637 pc
.StallAtPixelScoreboard
= true;
2641 dst_offset
= buffer
->offset
+ destOffset
;
2642 for (uint32_t i
= 0; i
< queryCount
; i
++) {
2644 slot_offset
= (firstQuery
+ i
) * sizeof(struct anv_query_pool_slot
);
2645 switch (pool
->type
) {
2646 case VK_QUERY_TYPE_OCCLUSION
:
2647 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2648 CS_GPR(0), &pool
->bo
, slot_offset
);
2649 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2650 CS_GPR(1), &pool
->bo
, slot_offset
+ 8);
2652 /* FIXME: We need to clamp the result for 32 bit. */
2654 uint32_t *dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
2655 dw
[1] = alu(OPCODE_LOAD
, OPERAND_SRCA
, OPERAND_R1
);
2656 dw
[2] = alu(OPCODE_LOAD
, OPERAND_SRCB
, OPERAND_R0
);
2657 dw
[3] = alu(OPCODE_SUB
, 0, 0);
2658 dw
[4] = alu(OPCODE_STORE
, OPERAND_R2
, OPERAND_ACCU
);
2661 case VK_QUERY_TYPE_TIMESTAMP
:
2662 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2663 CS_GPR(2), &pool
->bo
, slot_offset
);
2667 unreachable("unhandled query type");
2670 store_query_result(&cmd_buffer
->batch
,
2671 CS_GPR(2), buffer
->bo
, dst_offset
, flags
);
2673 if (flags
& VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
) {
2674 emit_load_alu_reg_u64(&cmd_buffer
->batch
, CS_GPR(0),
2675 &pool
->bo
, slot_offset
+ 16);
2676 if (flags
& VK_QUERY_RESULT_64_BIT
)
2677 store_query_result(&cmd_buffer
->batch
,
2678 CS_GPR(0), buffer
->bo
, dst_offset
+ 8, flags
);
2680 store_query_result(&cmd_buffer
->batch
,
2681 CS_GPR(0), buffer
->bo
, dst_offset
+ 4, flags
);
2684 dst_offset
+= destStride
;
2689 void genX(CmdCopyQueryPoolResults
)(
2690 VkCommandBuffer commandBuffer
,
2691 VkQueryPool queryPool
,
2692 uint32_t firstQuery
,
2693 uint32_t queryCount
,
2694 VkBuffer destBuffer
,
2695 VkDeviceSize destOffset
,
2696 VkDeviceSize destStride
,
2697 VkQueryResultFlags flags
)
2699 anv_finishme("Queries not yet supported on Ivy Bridge");