2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_l3_config.h"
33 #include "genxml/gen_macros.h"
34 #include "genxml/genX_pack.h"
36 /* We reserve GPR 14 and 15 for conditional rendering */
37 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
38 #define __gen_get_batch_dwords anv_batch_emit_dwords
39 #define __gen_address_offset anv_address_add
40 #include "common/gen_mi_builder.h"
43 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
45 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
46 lri
.RegisterOffset
= reg
;
52 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
54 struct anv_device
*device
= cmd_buffer
->device
;
56 /* If we are emitting a new state base address we probably need to re-emit
59 cmd_buffer
->state
.descriptors_dirty
|= ~0;
61 /* Emit a render target cache flush.
63 * This isn't documented anywhere in the PRM. However, it seems to be
64 * necessary prior to changing the surface state base adress. Without
65 * this, we get GPU hangs when using multi-level command buffers which
66 * clear depth, reset state base address, and then go render stuff.
68 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
69 pc
.DCFlushEnable
= true;
70 pc
.RenderTargetCacheFlushEnable
= true;
71 pc
.CommandStreamerStallEnable
= true;
74 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
75 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
76 sba
.GeneralStateMOCS
= GENX(MOCS
);
77 sba
.GeneralStateBaseAddressModifyEnable
= true;
79 sba
.SurfaceStateBaseAddress
=
80 anv_cmd_buffer_surface_base_address(cmd_buffer
);
81 sba
.SurfaceStateMOCS
= GENX(MOCS
);
82 sba
.SurfaceStateBaseAddressModifyEnable
= true;
84 sba
.DynamicStateBaseAddress
=
85 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
86 sba
.DynamicStateMOCS
= GENX(MOCS
);
87 sba
.DynamicStateBaseAddressModifyEnable
= true;
89 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
90 sba
.IndirectObjectMOCS
= GENX(MOCS
);
91 sba
.IndirectObjectBaseAddressModifyEnable
= true;
93 sba
.InstructionBaseAddress
=
94 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
95 sba
.InstructionMOCS
= GENX(MOCS
);
96 sba
.InstructionBaseAddressModifyEnable
= true;
99 /* Broadwell requires that we specify a buffer size for a bunch of
100 * these fields. However, since we will be growing the BO's live, we
101 * just set them all to the maximum.
103 sba
.GeneralStateBufferSize
= 0xfffff;
104 sba
.GeneralStateBufferSizeModifyEnable
= true;
105 sba
.DynamicStateBufferSize
= 0xfffff;
106 sba
.DynamicStateBufferSizeModifyEnable
= true;
107 sba
.IndirectObjectBufferSize
= 0xfffff;
108 sba
.IndirectObjectBufferSizeModifyEnable
= true;
109 sba
.InstructionBufferSize
= 0xfffff;
110 sba
.InstructionBuffersizeModifyEnable
= true;
113 if (cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
) {
114 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) {
115 .bo
= device
->surface_state_pool
.block_pool
.bo
,
118 sba
.BindlessSurfaceStateSize
= (1 << 20) - 1;
120 sba
.BindlessSurfaceStateBaseAddress
= ANV_NULL_ADDRESS
;
121 sba
.BindlessSurfaceStateSize
= 0;
123 sba
.BindlessSurfaceStateMOCS
= GENX(MOCS
);
124 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
127 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
128 sba
.BindlessSamplerStateMOCS
= GENX(MOCS
);
129 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
130 sba
.BindlessSamplerStateBufferSize
= 0;
134 /* After re-setting the surface state base address, we have to do some
135 * cache flusing so that the sampler engine will pick up the new
136 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
137 * Shared Function > 3D Sampler > State > State Caching (page 96):
139 * Coherency with system memory in the state cache, like the texture
140 * cache is handled partially by software. It is expected that the
141 * command stream or shader will issue Cache Flush operation or
142 * Cache_Flush sampler message to ensure that the L1 cache remains
143 * coherent with system memory.
147 * Whenever the value of the Dynamic_State_Base_Addr,
148 * Surface_State_Base_Addr are altered, the L1 state cache must be
149 * invalidated to ensure the new surface or sampler state is fetched
150 * from system memory.
152 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
153 * which, according the PIPE_CONTROL instruction documentation in the
156 * Setting this bit is independent of any other bit in this packet.
157 * This bit controls the invalidation of the L1 and L2 state caches
158 * at the top of the pipe i.e. at the parsing time.
160 * Unfortunately, experimentation seems to indicate that state cache
161 * invalidation through a PIPE_CONTROL does nothing whatsoever in
162 * regards to surface state and binding tables. In stead, it seems that
163 * invalidating the texture cache is what is actually needed.
165 * XXX: As far as we have been able to determine through
166 * experimentation, shows that flush the texture cache appears to be
167 * sufficient. The theory here is that all of the sampling/rendering
168 * units cache the binding table in the texture cache. However, we have
169 * yet to be able to actually confirm this.
171 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
172 pc
.TextureCacheInvalidationEnable
= true;
173 pc
.ConstantCacheInvalidationEnable
= true;
174 pc
.StateCacheInvalidationEnable
= true;
179 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
180 struct anv_state state
, struct anv_address addr
)
182 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
185 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
186 state
.offset
+ isl_dev
->ss
.addr_offset
,
187 addr
.bo
, addr
.offset
);
188 if (result
!= VK_SUCCESS
)
189 anv_batch_set_error(&cmd_buffer
->batch
, result
);
193 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
194 struct anv_surface_state state
)
196 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
198 assert(!anv_address_is_null(state
.address
));
199 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
201 if (!anv_address_is_null(state
.aux_address
)) {
203 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
204 &cmd_buffer
->pool
->alloc
,
205 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
206 state
.aux_address
.bo
, state
.aux_address
.offset
);
207 if (result
!= VK_SUCCESS
)
208 anv_batch_set_error(&cmd_buffer
->batch
, result
);
211 if (!anv_address_is_null(state
.clear_address
)) {
213 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
214 &cmd_buffer
->pool
->alloc
,
216 isl_dev
->ss
.clear_color_state_offset
,
217 state
.clear_address
.bo
, state
.clear_address
.offset
);
218 if (result
!= VK_SUCCESS
)
219 anv_batch_set_error(&cmd_buffer
->batch
, result
);
224 color_attachment_compute_aux_usage(struct anv_device
* device
,
225 struct anv_cmd_state
* cmd_state
,
226 uint32_t att
, VkRect2D render_area
,
227 union isl_color_value
*fast_clear_color
)
229 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
230 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
232 assert(iview
->n_planes
== 1);
234 if (iview
->planes
[0].isl
.base_array_layer
>=
235 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
236 iview
->planes
[0].isl
.base_level
)) {
237 /* There is no aux buffer which corresponds to the level and layer(s)
240 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
241 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
242 att_state
->fast_clear
= false;
246 att_state
->aux_usage
=
247 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
248 VK_IMAGE_ASPECT_COLOR_BIT
,
249 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
251 /* If we don't have aux, then we should have returned early in the layer
252 * check above. If we got here, we must have something.
254 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
256 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
257 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
258 att_state
->input_aux_usage
= att_state
->aux_usage
;
260 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
262 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
263 * setting is only allowed if Surface Format supported for Fast
264 * Clear. In addition, if the surface is bound to the sampling
265 * engine, Surface Format must be supported for Render Target
266 * Compression for surfaces bound to the sampling engine."
268 * In other words, we can only sample from a fast-cleared image if it
269 * also supports color compression.
271 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
272 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
274 /* While fast-clear resolves and partial resolves are fairly cheap in the
275 * case where you render to most of the pixels, full resolves are not
276 * because they potentially involve reading and writing the entire
277 * framebuffer. If we can't texture with CCS_E, we should leave it off and
278 * limit ourselves to fast clears.
280 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
281 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
282 anv_perf_warn(device
->instance
, iview
->image
,
283 "Not temporarily enabling CCS_E.");
286 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
290 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
291 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
293 union isl_color_value clear_color
= {};
294 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
296 att_state
->clear_color_is_zero_one
=
297 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
298 att_state
->clear_color_is_zero
=
299 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
301 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
302 /* Start by getting the fast clear type. We use the first subpass
303 * layout here because we don't want to fast-clear if the first subpass
304 * to use the attachment can't handle fast-clears.
306 enum anv_fast_clear_type fast_clear_type
=
307 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
308 VK_IMAGE_ASPECT_COLOR_BIT
,
309 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
310 switch (fast_clear_type
) {
311 case ANV_FAST_CLEAR_NONE
:
312 att_state
->fast_clear
= false;
314 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
315 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
317 case ANV_FAST_CLEAR_ANY
:
318 att_state
->fast_clear
= true;
322 /* Potentially, we could do partial fast-clears but doing so has crazy
323 * alignment restrictions. It's easier to just restrict to full size
324 * fast clears for now.
326 if (render_area
.offset
.x
!= 0 ||
327 render_area
.offset
.y
!= 0 ||
328 render_area
.extent
.width
!= iview
->extent
.width
||
329 render_area
.extent
.height
!= iview
->extent
.height
)
330 att_state
->fast_clear
= false;
332 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
333 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
334 att_state
->fast_clear
= false;
336 /* We only allow fast clears to the first slice of an image (level 0,
337 * layer 0) and only for the entire slice. This guarantees us that, at
338 * any given time, there is only one clear color on any given image at
339 * any given time. At the time of our testing (Jan 17, 2018), there
340 * were no known applications which would benefit from fast-clearing
341 * more than just the first slice.
343 if (att_state
->fast_clear
&&
344 (iview
->planes
[0].isl
.base_level
> 0 ||
345 iview
->planes
[0].isl
.base_array_layer
> 0)) {
346 anv_perf_warn(device
->instance
, iview
->image
,
347 "Rendering with multi-lod or multi-layer framebuffer "
348 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
349 "baseArrayLayer > 0. Not fast clearing.");
350 att_state
->fast_clear
= false;
351 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
352 anv_perf_warn(device
->instance
, iview
->image
,
353 "Rendering to a multi-layer framebuffer with "
354 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
357 if (att_state
->fast_clear
)
358 *fast_clear_color
= clear_color
;
360 att_state
->fast_clear
= false;
365 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
366 struct anv_cmd_state
*cmd_state
,
367 uint32_t att
, VkRect2D render_area
)
369 struct anv_render_pass_attachment
*pass_att
=
370 &cmd_state
->pass
->attachments
[att
];
371 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
372 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
374 /* These will be initialized after the first subpass transition. */
375 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
376 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
379 /* We don't do any HiZ or depth fast-clears on gen7 yet */
380 att_state
->fast_clear
= false;
384 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
385 /* If we're just clearing stencil, we can always HiZ clear */
386 att_state
->fast_clear
= true;
390 /* Default to false for now */
391 att_state
->fast_clear
= false;
393 /* We must have depth in order to have HiZ */
394 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
397 const enum isl_aux_usage first_subpass_aux_usage
=
398 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
399 VK_IMAGE_ASPECT_DEPTH_BIT
,
400 pass_att
->first_subpass_layout
);
401 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
404 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
405 iview
->planes
[0].isl
.format
,
406 iview
->image
->samples
,
407 render_area
.offset
.x
,
408 render_area
.offset
.y
,
409 render_area
.offset
.x
+
410 render_area
.extent
.width
,
411 render_area
.offset
.y
+
412 render_area
.extent
.height
))
415 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
418 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
419 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
420 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
421 * only supports returning 0.0f. Gens prior to gen8 do not support this
427 /* If we got here, then we can fast clear */
428 att_state
->fast_clear
= true;
432 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
434 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
437 /* We only allocate input attachment states for color surfaces. Compression
438 * is not yet enabled for depth textures and stencil doesn't allow
439 * compression so we can just use the texture surface state from the view.
441 return vk_format_is_color(att
->format
);
444 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
445 * the initial layout is undefined, the HiZ buffer and depth buffer will
446 * represent the same data at the end of this operation.
449 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
450 const struct anv_image
*image
,
451 VkImageLayout initial_layout
,
452 VkImageLayout final_layout
)
454 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
455 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
456 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
457 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
458 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
459 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
461 enum isl_aux_op hiz_op
;
462 if (hiz_enabled
&& !enable_hiz
) {
463 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
464 } else if (!hiz_enabled
&& enable_hiz
) {
465 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
467 assert(hiz_enabled
== enable_hiz
);
468 /* If the same buffer will be used, no resolves are necessary. */
469 hiz_op
= ISL_AUX_OP_NONE
;
472 if (hiz_op
!= ISL_AUX_OP_NONE
)
473 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
477 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
478 * the initial layout is undefined, the HiZ buffer and depth buffer will
479 * represent the same data at the end of this operation.
482 transition_stencil_buffer(struct anv_cmd_buffer
*cmd_buffer
,
483 const struct anv_image
*image
,
484 uint32_t base_level
, uint32_t level_count
,
485 uint32_t base_layer
, uint32_t layer_count
,
486 VkImageLayout initial_layout
,
487 VkImageLayout final_layout
)
491 #define MI_PREDICATE_SRC0 0x2400
492 #define MI_PREDICATE_SRC1 0x2408
493 #define MI_PREDICATE_RESULT 0x2418
496 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
497 const struct anv_image
*image
,
498 VkImageAspectFlagBits aspect
,
500 uint32_t base_layer
, uint32_t layer_count
,
503 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
505 /* We only have compression tracking for CCS_E */
506 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
509 for (uint32_t a
= 0; a
< layer_count
; a
++) {
510 uint32_t layer
= base_layer
+ a
;
511 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
512 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
515 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
521 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
522 const struct anv_image
*image
,
523 VkImageAspectFlagBits aspect
,
524 enum anv_fast_clear_type fast_clear
)
526 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
527 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
529 sdi
.ImmediateData
= fast_clear
;
532 /* Whenever we have fast-clear, we consider that slice to be compressed.
533 * This makes building predicates much easier.
535 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
536 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
539 #if GEN_IS_HASWELL || GEN_GEN >= 8
540 static inline uint32_t
541 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
543 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
545 .Operand1
= operand1
,
546 .Operand2
= operand2
,
550 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
556 /* This is only really practical on haswell and above because it requires
557 * MI math in order to get it correct.
559 #if GEN_GEN >= 8 || GEN_IS_HASWELL
561 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
562 const struct anv_image
*image
,
563 VkImageAspectFlagBits aspect
,
564 uint32_t level
, uint32_t array_layer
,
565 enum isl_aux_op resolve_op
,
566 enum anv_fast_clear_type fast_clear_supported
)
568 struct gen_mi_builder b
;
569 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
571 const struct gen_mi_value fast_clear_type
=
572 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
575 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
576 /* In this case, we're doing a full resolve which means we want the
577 * resolve to happen if any compression (including fast-clears) is
580 * In order to simplify the logic a bit, we make the assumption that,
581 * if the first slice has been fast-cleared, it is also marked as
582 * compressed. See also set_image_fast_clear_state.
584 const struct gen_mi_value compression_state
=
585 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer
->device
,
587 level
, array_layer
));
588 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
590 gen_mi_store(&b
, compression_state
, gen_mi_imm(0));
592 if (level
== 0 && array_layer
== 0) {
593 /* If the predicate is true, we want to write 0 to the fast clear type
594 * and, if it's false, leave it alone. We can do this by writing
596 * clear_type = clear_type & ~predicate;
598 struct gen_mi_value new_fast_clear_type
=
599 gen_mi_iand(&b
, fast_clear_type
,
600 gen_mi_inot(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
)));
601 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
603 } else if (level
== 0 && array_layer
== 0) {
604 /* In this case, we are doing a partial resolve to get rid of fast-clear
605 * colors. We don't care about the compression state but we do care
606 * about how much fast clear is allowed by the final layout.
608 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
609 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
611 /* We need to compute (fast_clear_supported < image->fast_clear) */
612 struct gen_mi_value pred
=
613 gen_mi_ult(&b
, gen_mi_imm(fast_clear_supported
), fast_clear_type
);
614 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
615 gen_mi_value_ref(&b
, pred
));
617 /* If the predicate is true, we want to write 0 to the fast clear type
618 * and, if it's false, leave it alone. We can do this by writing
620 * clear_type = clear_type & ~predicate;
622 struct gen_mi_value new_fast_clear_type
=
623 gen_mi_iand(&b
, fast_clear_type
, gen_mi_inot(&b
, pred
));
624 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
626 /* In this case, we're trying to do a partial resolve on a slice that
627 * doesn't have clear color. There's nothing to do.
629 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
633 /* Set src1 to 0 and use a != condition */
634 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
636 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
637 mip
.LoadOperation
= LOAD_LOADINV
;
638 mip
.CombineOperation
= COMBINE_SET
;
639 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
642 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
646 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
647 const struct anv_image
*image
,
648 VkImageAspectFlagBits aspect
,
649 uint32_t level
, uint32_t array_layer
,
650 enum isl_aux_op resolve_op
,
651 enum anv_fast_clear_type fast_clear_supported
)
653 struct gen_mi_builder b
;
654 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
656 struct gen_mi_value fast_clear_type_mem
=
657 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
660 /* This only works for partial resolves and only when the clear color is
661 * all or nothing. On the upside, this emits less command streamer code
662 * and works on Ivybridge and Bay Trail.
664 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
665 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
667 /* We don't support fast clears on anything other than the first slice. */
668 if (level
> 0 || array_layer
> 0)
671 /* On gen8, we don't have a concept of default clear colors because we
672 * can't sample from CCS surfaces. It's enough to just load the fast clear
673 * state into the predicate register.
675 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), fast_clear_type_mem
);
676 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
677 gen_mi_store(&b
, fast_clear_type_mem
, gen_mi_imm(0));
679 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
680 mip
.LoadOperation
= LOAD_LOADINV
;
681 mip
.CombineOperation
= COMBINE_SET
;
682 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
685 #endif /* GEN_GEN <= 8 */
688 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
689 const struct anv_image
*image
,
690 enum isl_format format
,
691 VkImageAspectFlagBits aspect
,
692 uint32_t level
, uint32_t array_layer
,
693 enum isl_aux_op resolve_op
,
694 enum anv_fast_clear_type fast_clear_supported
)
696 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
699 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
700 aspect
, level
, array_layer
,
701 resolve_op
, fast_clear_supported
);
702 #else /* GEN_GEN <= 8 */
703 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
704 aspect
, level
, array_layer
,
705 resolve_op
, fast_clear_supported
);
708 /* CCS_D only supports full resolves and BLORP will assert on us if we try
709 * to do a partial resolve on a CCS_D surface.
711 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
712 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
713 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
715 anv_image_ccs_op(cmd_buffer
, image
, format
, aspect
, level
,
716 array_layer
, 1, resolve_op
, NULL
, true);
720 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
721 const struct anv_image
*image
,
722 enum isl_format format
,
723 VkImageAspectFlagBits aspect
,
724 uint32_t array_layer
,
725 enum isl_aux_op resolve_op
,
726 enum anv_fast_clear_type fast_clear_supported
)
728 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
729 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
731 #if GEN_GEN >= 8 || GEN_IS_HASWELL
732 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
733 aspect
, 0, array_layer
,
734 resolve_op
, fast_clear_supported
);
736 anv_image_mcs_op(cmd_buffer
, image
, format
, aspect
,
737 array_layer
, 1, resolve_op
, NULL
, true);
739 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
744 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
745 const struct anv_image
*image
,
746 VkImageAspectFlagBits aspect
,
747 enum isl_aux_usage aux_usage
,
750 uint32_t layer_count
)
752 /* The aspect must be exactly one of the image aspects. */
753 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
755 /* The only compression types with more than just fast-clears are MCS,
756 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
757 * track the current fast-clear and compression state. This leaves us
758 * with just MCS and CCS_E.
760 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
761 aux_usage
!= ISL_AUX_USAGE_MCS
)
764 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
765 level
, base_layer
, layer_count
, true);
769 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
770 const struct anv_image
*image
,
771 VkImageAspectFlagBits aspect
)
773 assert(cmd_buffer
&& image
);
774 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
776 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
777 ANV_FAST_CLEAR_NONE
);
779 /* Initialize the struct fields that are accessed for fast-clears so that
780 * the HW restrictions on the field values are satisfied.
782 struct anv_address addr
=
783 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
786 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
787 const unsigned num_dwords
= GEN_GEN
>= 10 ?
788 isl_dev
->ss
.clear_color_state_size
/ 4 :
789 isl_dev
->ss
.clear_value_size
/ 4;
790 for (unsigned i
= 0; i
< num_dwords
; i
++) {
791 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
793 sdi
.Address
.offset
+= i
* 4;
794 sdi
.ImmediateData
= 0;
798 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
800 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
801 /* Pre-SKL, the dword containing the clear values also contains
802 * other fields, so we need to initialize those fields to match the
803 * values that would be in a color attachment.
805 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
806 ISL_CHANNEL_SELECT_GREEN
<< 22 |
807 ISL_CHANNEL_SELECT_BLUE
<< 19 |
808 ISL_CHANNEL_SELECT_ALPHA
<< 16;
809 } else if (GEN_GEN
== 7) {
810 /* On IVB, the dword containing the clear values also contains
811 * other fields that must be zero or can be zero.
813 sdi
.ImmediateData
= 0;
819 /* Copy the fast-clear value dword(s) between a surface state object and an
820 * image's fast clear state buffer.
823 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
824 struct anv_state surface_state
,
825 const struct anv_image
*image
,
826 VkImageAspectFlagBits aspect
,
827 bool copy_from_surface_state
)
829 assert(cmd_buffer
&& image
);
830 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
832 struct anv_address ss_clear_addr
= {
833 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
834 .offset
= surface_state
.offset
+
835 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
837 const struct anv_address entry_addr
=
838 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
839 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
842 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
843 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
844 * in-flight when they are issued even if the memory touched is not
845 * currently active for rendering. The weird bit is that it is not the
846 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
847 * rendering hangs such that the next stalling command after the
848 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
850 * It is unclear exactly why this hang occurs. Both MI commands come with
851 * warnings about the 3D pipeline but that doesn't seem to fully explain
852 * it. My (Jason's) best theory is that it has something to do with the
853 * fact that we're using a GPU state register as our temporary and that
854 * something with reading/writing it is causing problems.
856 * In order to work around this issue, we emit a PIPE_CONTROL with the
857 * command streamer stall bit set.
859 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
860 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
863 struct gen_mi_builder b
;
864 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
866 if (copy_from_surface_state
) {
867 gen_mi_memcpy(&b
, entry_addr
, ss_clear_addr
, copy_size
);
869 gen_mi_memcpy(&b
, ss_clear_addr
, entry_addr
, copy_size
);
871 /* Updating a surface state object may require that the state cache be
872 * invalidated. From the SKL PRM, Shared Functions -> State -> State
875 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
876 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
877 * modified [...], the L1 state cache must be invalidated to ensure
878 * the new surface or sampler state is fetched from system memory.
880 * In testing, SKL doesn't actually seem to need this, but HSW does.
882 cmd_buffer
->state
.pending_pipe_bits
|=
883 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
888 * @brief Transitions a color buffer from one layout to another.
890 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
893 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
894 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
895 * this represents the maximum layers to transition at each
896 * specified miplevel.
899 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
900 const struct anv_image
*image
,
901 VkImageAspectFlagBits aspect
,
902 const uint32_t base_level
, uint32_t level_count
,
903 uint32_t base_layer
, uint32_t layer_count
,
904 VkImageLayout initial_layout
,
905 VkImageLayout final_layout
)
907 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
908 /* Validate the inputs. */
910 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
911 /* These values aren't supported for simplicity's sake. */
912 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
913 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
914 /* Ensure the subresource range is valid. */
915 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
916 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
917 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
918 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
919 assert(last_level_num
<= image
->levels
);
920 /* The spec disallows these final layouts. */
921 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
922 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
924 /* No work is necessary if the layout stays the same or if this subresource
925 * range lacks auxiliary data.
927 if (initial_layout
== final_layout
)
930 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
932 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
933 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
934 /* This surface is a linear compressed image with a tiled shadow surface
935 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
936 * we need to ensure the shadow copy is up-to-date.
938 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
939 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
940 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
941 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
943 anv_image_copy_to_shadow(cmd_buffer
, image
,
944 VK_IMAGE_ASPECT_COLOR_BIT
,
945 base_level
, level_count
,
946 base_layer
, layer_count
);
949 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
952 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
954 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
955 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
956 /* A subresource in the undefined layout may have been aliased and
957 * populated with any arrangement of bits. Therefore, we must initialize
958 * the related aux buffer and clear buffer entry with desirable values.
959 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
960 * images with VK_IMAGE_TILING_OPTIMAL.
962 * Initialize the relevant clear buffer entries.
964 if (base_level
== 0 && base_layer
== 0)
965 init_fast_clear_color(cmd_buffer
, image
, aspect
);
967 /* Initialize the aux buffers to enable correct rendering. In order to
968 * ensure that things such as storage images work correctly, aux buffers
969 * need to be initialized to valid data.
971 * Having an aux buffer with invalid data is a problem for two reasons:
973 * 1) Having an invalid value in the buffer can confuse the hardware.
974 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
975 * invalid and leads to the hardware doing strange things. It
976 * doesn't hang as far as we can tell but rendering corruption can
979 * 2) If this transition is into the GENERAL layout and we then use the
980 * image as a storage image, then we must have the aux buffer in the
981 * pass-through state so that, if we then go to texture from the
982 * image, we get the results of our storage image writes and not the
983 * fast clear color or other random data.
985 * For CCS both of the problems above are real demonstrable issues. In
986 * that case, the only thing we can do is to perform an ambiguate to
987 * transition the aux surface into the pass-through state.
989 * For MCS, (2) is never an issue because we don't support multisampled
990 * storage images. In theory, issue (1) is a problem with MCS but we've
991 * never seen it in the wild. For 4x and 16x, all bit patters could, in
992 * theory, be interpreted as something but we don't know that all bit
993 * patterns are actually valid. For 2x and 8x, you could easily end up
994 * with the MCS referring to an invalid plane because not all bits of
995 * the MCS value are actually used. Even though we've never seen issues
996 * in the wild, it's best to play it safe and initialize the MCS. We
997 * can use a fast-clear for MCS because we only ever touch from render
998 * and texture (no image load store).
1000 if (image
->samples
== 1) {
1001 for (uint32_t l
= 0; l
< level_count
; l
++) {
1002 const uint32_t level
= base_level
+ l
;
1004 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1005 if (base_layer
>= aux_layers
)
1006 break; /* We will only get fewer layers as level increases */
1007 uint32_t level_layer_count
=
1008 MIN2(layer_count
, aux_layers
- base_layer
);
1010 anv_image_ccs_op(cmd_buffer
, image
,
1011 image
->planes
[plane
].surface
.isl
.format
,
1012 aspect
, level
, base_layer
, level_layer_count
,
1013 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1015 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1016 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1017 level
, base_layer
, level_layer_count
,
1022 if (image
->samples
== 4 || image
->samples
== 16) {
1023 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1024 "Doing a potentially unnecessary fast-clear to "
1025 "define an MCS buffer.");
1028 assert(base_level
== 0 && level_count
== 1);
1029 anv_image_mcs_op(cmd_buffer
, image
,
1030 image
->planes
[plane
].surface
.isl
.format
,
1031 aspect
, base_layer
, layer_count
,
1032 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1037 const enum isl_aux_usage initial_aux_usage
=
1038 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1039 const enum isl_aux_usage final_aux_usage
=
1040 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1042 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1043 * We can handle transitions between CCS_D/E to and from NONE. What we
1044 * don't yet handle is switching between CCS_E and CCS_D within a given
1045 * image. Doing so in a performant way requires more detailed aux state
1046 * tracking such as what is done in i965. For now, just assume that we
1047 * only have one type of compression.
1049 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1050 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1051 initial_aux_usage
== final_aux_usage
);
1053 /* If initial aux usage is NONE, there is nothing to resolve */
1054 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1057 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1059 /* If the initial layout supports more fast clear than the final layout
1060 * then we need at least a partial resolve.
1062 const enum anv_fast_clear_type initial_fast_clear
=
1063 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1064 const enum anv_fast_clear_type final_fast_clear
=
1065 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1066 if (final_fast_clear
< initial_fast_clear
)
1067 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1069 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1070 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1071 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1073 if (resolve_op
== ISL_AUX_OP_NONE
)
1076 /* Perform a resolve to synchronize data between the main and aux buffer.
1077 * Before we begin, we must satisfy the cache flushing requirement specified
1078 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1080 * Any transition from any value in {Clear, Render, Resolve} to a
1081 * different value in {Clear, Render, Resolve} requires end of pipe
1084 * We perform a flush of the write cache before and after the clear and
1085 * resolve operations to meet this requirement.
1087 * Unlike other drawing, fast clear operations are not properly
1088 * synchronized. The first PIPE_CONTROL here likely ensures that the
1089 * contents of the previous render or clear hit the render target before we
1090 * resolve and the second likely ensures that the resolve is complete before
1091 * we do any more rendering or clearing.
1093 cmd_buffer
->state
.pending_pipe_bits
|=
1094 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1096 for (uint32_t l
= 0; l
< level_count
; l
++) {
1097 uint32_t level
= base_level
+ l
;
1099 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1100 if (base_layer
>= aux_layers
)
1101 break; /* We will only get fewer layers as level increases */
1102 uint32_t level_layer_count
=
1103 MIN2(layer_count
, aux_layers
- base_layer
);
1105 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1106 uint32_t array_layer
= base_layer
+ a
;
1107 if (image
->samples
== 1) {
1108 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1109 image
->planes
[plane
].surface
.isl
.format
,
1110 aspect
, level
, array_layer
, resolve_op
,
1113 /* We only support fast-clear on the first layer so partial
1114 * resolves should not be used on other layers as they will use
1115 * the clear color stored in memory that is only valid for layer0.
1117 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1121 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1122 image
->planes
[plane
].surface
.isl
.format
,
1123 aspect
, array_layer
, resolve_op
,
1129 cmd_buffer
->state
.pending_pipe_bits
|=
1130 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1134 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1137 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1138 struct anv_render_pass
*pass
,
1139 const VkRenderPassBeginInfo
*begin
)
1141 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1142 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1144 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1146 if (pass
->attachment_count
> 0) {
1147 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1148 pass
->attachment_count
*
1149 sizeof(state
->attachments
[0]),
1150 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1151 if (state
->attachments
== NULL
) {
1152 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1153 return anv_batch_set_error(&cmd_buffer
->batch
,
1154 VK_ERROR_OUT_OF_HOST_MEMORY
);
1157 state
->attachments
= NULL
;
1160 /* Reserve one for the NULL state. */
1161 unsigned num_states
= 1;
1162 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1163 if (vk_format_is_color(pass
->attachments
[i
].format
))
1166 if (need_input_attachment_state(&pass
->attachments
[i
]))
1170 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1171 state
->render_pass_states
=
1172 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1173 num_states
* ss_stride
, isl_dev
->ss
.align
);
1175 struct anv_state next_state
= state
->render_pass_states
;
1176 next_state
.alloc_size
= isl_dev
->ss
.size
;
1178 state
->null_surface_state
= next_state
;
1179 next_state
.offset
+= ss_stride
;
1180 next_state
.map
+= ss_stride
;
1182 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1183 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1184 state
->attachments
[i
].color
.state
= next_state
;
1185 next_state
.offset
+= ss_stride
;
1186 next_state
.map
+= ss_stride
;
1189 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1190 state
->attachments
[i
].input
.state
= next_state
;
1191 next_state
.offset
+= ss_stride
;
1192 next_state
.map
+= ss_stride
;
1195 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1196 state
->render_pass_states
.alloc_size
);
1199 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1200 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1202 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1203 isl_extent3d(framebuffer
->width
,
1204 framebuffer
->height
,
1205 framebuffer
->layers
));
1207 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1208 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1209 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1210 VkImageAspectFlags clear_aspects
= 0;
1211 VkImageAspectFlags load_aspects
= 0;
1213 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1214 /* color attachment */
1215 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1216 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1217 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1218 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1221 /* depthstencil attachment */
1222 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1223 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1224 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1225 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1226 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1229 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1230 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1231 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1232 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1233 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1238 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1239 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1240 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1242 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1244 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1245 anv_assert(iview
->vk_format
== att
->format
);
1247 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1248 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1250 union isl_color_value clear_color
= { .u32
= { 0, } };
1251 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1252 anv_assert(iview
->n_planes
== 1);
1253 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1254 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1255 state
, i
, begin
->renderArea
,
1258 anv_image_fill_surface_state(cmd_buffer
->device
,
1260 VK_IMAGE_ASPECT_COLOR_BIT
,
1261 &iview
->planes
[0].isl
,
1262 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1263 state
->attachments
[i
].aux_usage
,
1266 &state
->attachments
[i
].color
,
1269 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1271 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1276 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1277 anv_image_fill_surface_state(cmd_buffer
->device
,
1279 VK_IMAGE_ASPECT_COLOR_BIT
,
1280 &iview
->planes
[0].isl
,
1281 ISL_SURF_USAGE_TEXTURE_BIT
,
1282 state
->attachments
[i
].input_aux_usage
,
1285 &state
->attachments
[i
].input
,
1288 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1297 genX(BeginCommandBuffer
)(
1298 VkCommandBuffer commandBuffer
,
1299 const VkCommandBufferBeginInfo
* pBeginInfo
)
1301 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1303 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1304 * command buffer's state. Otherwise, we must *reset* its state. In both
1305 * cases we reset it.
1307 * From the Vulkan 1.0 spec:
1309 * If a command buffer is in the executable state and the command buffer
1310 * was allocated from a command pool with the
1311 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1312 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1313 * as if vkResetCommandBuffer had been called with
1314 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1315 * the command buffer in the recording state.
1317 anv_cmd_buffer_reset(cmd_buffer
);
1319 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1321 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1322 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1324 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1326 /* We sometimes store vertex data in the dynamic state buffer for blorp
1327 * operations and our dynamic state stream may re-use data from previous
1328 * command buffers. In order to prevent stale cache data, we flush the VF
1329 * cache. We could do this on every blorp call but that's not really
1330 * needed as all of the data will get written by the CPU prior to the GPU
1331 * executing anything. The chances are fairly high that they will use
1332 * blorp at least once per primary command buffer so it shouldn't be
1335 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1336 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1338 /* We send an "Indirect State Pointers Disable" packet at
1339 * EndCommandBuffer, so all push contant packets are ignored during a
1340 * context restore. Documentation says after that command, we need to
1341 * emit push constants again before any rendering operation. So we
1342 * flag them dirty here to make sure they get emitted.
1344 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1346 VkResult result
= VK_SUCCESS
;
1347 if (cmd_buffer
->usage_flags
&
1348 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1349 assert(pBeginInfo
->pInheritanceInfo
);
1350 cmd_buffer
->state
.pass
=
1351 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1352 cmd_buffer
->state
.subpass
=
1353 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1355 /* This is optional in the inheritance info. */
1356 cmd_buffer
->state
.framebuffer
=
1357 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1359 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1360 cmd_buffer
->state
.pass
, NULL
);
1362 /* Record that HiZ is enabled if we can. */
1363 if (cmd_buffer
->state
.framebuffer
) {
1364 const struct anv_image_view
* const iview
=
1365 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1368 VkImageLayout layout
=
1369 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1371 enum isl_aux_usage aux_usage
=
1372 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1373 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1375 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1379 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1382 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1383 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1384 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1385 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1387 /* If secondary buffer supports conditional rendering
1388 * we should emit commands as if conditional rendering is enabled.
1390 cmd_buffer
->state
.conditional_render_enabled
=
1391 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1398 /* From the PRM, Volume 2a:
1400 * "Indirect State Pointers Disable
1402 * At the completion of the post-sync operation associated with this pipe
1403 * control packet, the indirect state pointers in the hardware are
1404 * considered invalid; the indirect pointers are not saved in the context.
1405 * If any new indirect state commands are executed in the command stream
1406 * while the pipe control is pending, the new indirect state commands are
1409 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1410 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1411 * commands are only considered as Indirect State Pointers. Once ISP is
1412 * issued in a context, SW must initialize by programming push constant
1413 * commands for all the shaders (at least to zero length) before attempting
1414 * any rendering operation for the same context."
1416 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1417 * even though they point to a BO that has been already unreferenced at
1418 * the end of the previous batch buffer. This has been fine so far since
1419 * we are protected by these scratch page (every address not covered by
1420 * a BO should be pointing to the scratch page). But on CNL, it is
1421 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1424 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1425 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1426 * context restore, so the mentioned hang doesn't happen. However,
1427 * software must program push constant commands for all stages prior to
1428 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1430 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1431 * constants have been loaded into the EUs prior to disable the push constants
1432 * so that it doesn't hang a previous 3DPRIMITIVE.
1435 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1437 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1438 pc
.StallAtPixelScoreboard
= true;
1439 pc
.CommandStreamerStallEnable
= true;
1441 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1442 pc
.IndirectStatePointersDisable
= true;
1443 pc
.CommandStreamerStallEnable
= true;
1448 genX(EndCommandBuffer
)(
1449 VkCommandBuffer commandBuffer
)
1451 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1453 if (anv_batch_has_error(&cmd_buffer
->batch
))
1454 return cmd_buffer
->batch
.status
;
1456 /* We want every command buffer to start with the PMA fix in a known state,
1457 * so we disable it at the end of the command buffer.
1459 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1461 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1463 emit_isp_disable(cmd_buffer
);
1465 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1471 genX(CmdExecuteCommands
)(
1472 VkCommandBuffer commandBuffer
,
1473 uint32_t commandBufferCount
,
1474 const VkCommandBuffer
* pCmdBuffers
)
1476 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1478 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1480 if (anv_batch_has_error(&primary
->batch
))
1483 /* The secondary command buffers will assume that the PMA fix is disabled
1484 * when they begin executing. Make sure this is true.
1486 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1488 /* The secondary command buffer doesn't know which textures etc. have been
1489 * flushed prior to their execution. Apply those flushes now.
1491 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1493 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1494 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1496 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1497 assert(!anv_batch_has_error(&secondary
->batch
));
1499 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1500 if (secondary
->state
.conditional_render_enabled
) {
1501 if (!primary
->state
.conditional_render_enabled
) {
1502 /* Secondary buffer is constructed as if it will be executed
1503 * with conditional rendering, we should satisfy this dependency
1504 * regardless of conditional rendering being enabled in primary.
1506 struct gen_mi_builder b
;
1507 gen_mi_builder_init(&b
, &primary
->batch
);
1508 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
1509 gen_mi_imm(UINT64_MAX
));
1514 if (secondary
->usage_flags
&
1515 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1516 /* If we're continuing a render pass from the primary, we need to
1517 * copy the surface states for the current subpass into the storage
1518 * we allocated for them in BeginCommandBuffer.
1520 struct anv_bo
*ss_bo
=
1521 primary
->device
->surface_state_pool
.block_pool
.bo
;
1522 struct anv_state src_state
= primary
->state
.render_pass_states
;
1523 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1524 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1526 genX(cmd_buffer_so_memcpy
)(primary
,
1527 (struct anv_address
) {
1529 .offset
= dst_state
.offset
,
1531 (struct anv_address
) {
1533 .offset
= src_state
.offset
,
1535 src_state
.alloc_size
);
1538 anv_cmd_buffer_add_secondary(primary
, secondary
);
1541 /* The secondary may have selected a different pipeline (3D or compute) and
1542 * may have changed the current L3$ configuration. Reset our tracking
1543 * variables to invalid values to ensure that we re-emit these in the case
1544 * where we do any draws or compute dispatches from the primary after the
1545 * secondary has returned.
1547 primary
->state
.current_pipeline
= UINT32_MAX
;
1548 primary
->state
.current_l3_config
= NULL
;
1550 /* Each of the secondary command buffers will use its own state base
1551 * address. We need to re-emit state base address for the primary after
1552 * all of the secondaries are done.
1554 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1557 genX(cmd_buffer_emit_state_base_address
)(primary
);
1560 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1561 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1562 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1565 * Program the hardware to use the specified L3 configuration.
1568 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1569 const struct gen_l3_config
*cfg
)
1572 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1575 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1576 intel_logd("L3 config transition: ");
1577 gen_dump_l3_config(cfg
, stderr
);
1580 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1582 /* According to the hardware docs, the L3 partitioning can only be changed
1583 * while the pipeline is completely drained and the caches are flushed,
1584 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1586 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1587 pc
.DCFlushEnable
= true;
1588 pc
.PostSyncOperation
= NoWrite
;
1589 pc
.CommandStreamerStallEnable
= true;
1592 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1593 * invalidation of the relevant caches. Note that because RO invalidation
1594 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1595 * command is processed by the CS) we cannot combine it with the previous
1596 * stalling flush as the hardware documentation suggests, because that
1597 * would cause the CS to stall on previous rendering *after* RO
1598 * invalidation and wouldn't prevent the RO caches from being polluted by
1599 * concurrent rendering before the stall completes. This intentionally
1600 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1601 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1602 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1603 * already guarantee that there is no concurrent GPGPU kernel execution
1604 * (see SKL HSD 2132585).
1606 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1607 pc
.TextureCacheInvalidationEnable
= true;
1608 pc
.ConstantCacheInvalidationEnable
= true;
1609 pc
.InstructionCacheInvalidateEnable
= true;
1610 pc
.StateCacheInvalidationEnable
= true;
1611 pc
.PostSyncOperation
= NoWrite
;
1614 /* Now send a third stalling flush to make sure that invalidation is
1615 * complete when the L3 configuration registers are modified.
1617 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1618 pc
.DCFlushEnable
= true;
1619 pc
.PostSyncOperation
= NoWrite
;
1620 pc
.CommandStreamerStallEnable
= true;
1625 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1628 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1629 .SLMEnable
= has_slm
,
1631 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1632 * in L3CNTLREG register. The default setting of the bit is not the
1633 * desirable behavior.
1635 .ErrorDetectionBehaviorControl
= true,
1636 .UseFullWays
= true,
1638 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1639 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1640 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1641 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1643 /* Set up the L3 partitioning. */
1644 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1648 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1649 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1650 cfg
->n
[GEN_L3P_ALL
];
1651 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1652 cfg
->n
[GEN_L3P_ALL
];
1653 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1654 cfg
->n
[GEN_L3P_ALL
];
1656 assert(!cfg
->n
[GEN_L3P_ALL
]);
1658 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1659 * the matching space on the remaining banks has to be allocated to a
1660 * client (URB for all validated configurations) set to the
1661 * lower-bandwidth 2-bank address hashing mode.
1663 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1664 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1665 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1667 /* Minimum number of ways that can be allocated to the URB. */
1668 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1669 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1671 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1672 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1673 .ConvertDC_UC
= !has_dc
,
1674 .ConvertIS_UC
= !has_is
,
1675 .ConvertC_UC
= !has_c
,
1676 .ConvertT_UC
= !has_t
);
1678 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1679 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1680 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1682 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1683 .SLMEnable
= has_slm
,
1684 .URBLowBandwidth
= urb_low_bw
,
1685 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1687 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1689 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1690 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1692 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1693 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1694 .ISLowBandwidth
= 0,
1695 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1697 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1698 .TLowBandwidth
= 0);
1700 /* Set up the L3 partitioning. */
1701 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1702 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1703 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1706 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1707 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1708 * them disabled to avoid crashing the system hard.
1710 uint32_t scratch1
, chicken3
;
1711 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1712 .L3AtomicDisable
= !has_dc
);
1713 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1714 .L3AtomicDisableMask
= true,
1715 .L3AtomicDisable
= !has_dc
);
1716 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1717 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1723 cmd_buffer
->state
.current_l3_config
= cfg
;
1727 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1729 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1731 /* Flushes are pipelined while invalidations are handled immediately.
1732 * Therefore, if we're flushing anything then we need to schedule a stall
1733 * before any invalidations can happen.
1735 if (bits
& ANV_PIPE_FLUSH_BITS
)
1736 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1738 /* If we're going to do an invalidate and we have a pending CS stall that
1739 * has yet to be resolved, we do the CS stall now.
1741 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1742 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1743 bits
|= ANV_PIPE_CS_STALL_BIT
;
1744 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1747 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1748 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1749 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1750 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1751 pipe
.RenderTargetCacheFlushEnable
=
1752 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1754 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1755 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1756 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1759 * According to the Broadwell documentation, any PIPE_CONTROL with the
1760 * "Command Streamer Stall" bit set must also have another bit set,
1761 * with five different options:
1763 * - Render Target Cache Flush
1764 * - Depth Cache Flush
1765 * - Stall at Pixel Scoreboard
1766 * - Post-Sync Operation
1770 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1771 * mesa and it seems to work fine. The choice is fairly arbitrary.
1773 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1774 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1775 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1776 pipe
.StallAtPixelScoreboard
= true;
1779 /* If a render target flush was emitted, then we can toggle off the bit
1780 * saying that render target writes are ongoing.
1782 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
1783 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
1785 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1788 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1789 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1791 * "If the VF Cache Invalidation Enable is set to a 1 in a
1792 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1793 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1794 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1797 * This appears to hang Broadwell, so we restrict it to just gen9.
1799 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1800 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1802 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1803 pipe
.StateCacheInvalidationEnable
=
1804 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1805 pipe
.ConstantCacheInvalidationEnable
=
1806 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1807 pipe
.VFCacheInvalidationEnable
=
1808 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1809 pipe
.TextureCacheInvalidationEnable
=
1810 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1811 pipe
.InstructionCacheInvalidateEnable
=
1812 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1814 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1816 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1817 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1818 * “Write Timestamp”.
1820 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1821 pipe
.PostSyncOperation
= WriteImmediateData
;
1823 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1827 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1830 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1833 void genX(CmdPipelineBarrier
)(
1834 VkCommandBuffer commandBuffer
,
1835 VkPipelineStageFlags srcStageMask
,
1836 VkPipelineStageFlags destStageMask
,
1838 uint32_t memoryBarrierCount
,
1839 const VkMemoryBarrier
* pMemoryBarriers
,
1840 uint32_t bufferMemoryBarrierCount
,
1841 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1842 uint32_t imageMemoryBarrierCount
,
1843 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1845 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1847 /* XXX: Right now, we're really dumb and just flush whatever categories
1848 * the app asks for. One of these days we may make this a bit better
1849 * but right now that's all the hardware allows for in most areas.
1851 VkAccessFlags src_flags
= 0;
1852 VkAccessFlags dst_flags
= 0;
1854 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1855 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1856 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1859 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1860 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1861 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1864 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1865 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1866 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1867 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1868 const VkImageSubresourceRange
*range
=
1869 &pImageMemoryBarriers
[i
].subresourceRange
;
1871 uint32_t base_layer
, layer_count
;
1872 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1874 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1876 base_layer
= range
->baseArrayLayer
;
1877 layer_count
= anv_get_layerCount(image
, range
);
1880 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1881 transition_depth_buffer(cmd_buffer
, image
,
1882 pImageMemoryBarriers
[i
].oldLayout
,
1883 pImageMemoryBarriers
[i
].newLayout
);
1886 if (range
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1887 transition_stencil_buffer(cmd_buffer
, image
,
1888 range
->baseMipLevel
,
1889 anv_get_levelCount(image
, range
),
1890 base_layer
, layer_count
,
1891 pImageMemoryBarriers
[i
].oldLayout
,
1892 pImageMemoryBarriers
[i
].newLayout
);
1895 if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1896 VkImageAspectFlags color_aspects
=
1897 anv_image_expand_aspects(image
, range
->aspectMask
);
1898 uint32_t aspect_bit
;
1899 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1900 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1901 range
->baseMipLevel
,
1902 anv_get_levelCount(image
, range
),
1903 base_layer
, layer_count
,
1904 pImageMemoryBarriers
[i
].oldLayout
,
1905 pImageMemoryBarriers
[i
].newLayout
);
1910 cmd_buffer
->state
.pending_pipe_bits
|=
1911 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1912 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1916 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1918 VkShaderStageFlags stages
=
1919 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1921 /* In order to avoid thrash, we assume that vertex and fragment stages
1922 * always exist. In the rare case where one is missing *and* the other
1923 * uses push concstants, this may be suboptimal. However, avoiding stalls
1924 * seems more important.
1926 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1928 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1932 const unsigned push_constant_kb
= 32;
1933 #elif GEN_IS_HASWELL
1934 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1936 const unsigned push_constant_kb
= 16;
1939 const unsigned num_stages
=
1940 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1941 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1943 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1944 * units of 2KB. Incidentally, these are the same platforms that have
1945 * 32KB worth of push constant space.
1947 if (push_constant_kb
== 32)
1948 size_per_stage
&= ~1u;
1950 uint32_t kb_used
= 0;
1951 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1952 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1953 anv_batch_emit(&cmd_buffer
->batch
,
1954 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1955 alloc
._3DCommandSubOpcode
= 18 + i
;
1956 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1957 alloc
.ConstantBufferSize
= push_size
;
1959 kb_used
+= push_size
;
1962 anv_batch_emit(&cmd_buffer
->batch
,
1963 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1964 alloc
.ConstantBufferOffset
= kb_used
;
1965 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1968 cmd_buffer
->state
.push_constant_stages
= stages
;
1970 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1972 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1973 * the next 3DPRIMITIVE command after programming the
1974 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1976 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1977 * pipeline setup, we need to dirty push constants.
1979 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1982 static const struct anv_descriptor
*
1983 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1984 const struct anv_pipeline_binding
*binding
)
1986 assert(binding
->set
< MAX_SETS
);
1987 const struct anv_descriptor_set
*set
=
1988 pipe_state
->descriptors
[binding
->set
];
1989 const uint32_t offset
=
1990 set
->layout
->binding
[binding
->binding
].descriptor_index
;
1991 return &set
->descriptors
[offset
+ binding
->index
];
1995 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1996 const struct anv_pipeline_binding
*binding
)
1998 assert(binding
->set
< MAX_SETS
);
1999 const struct anv_descriptor_set
*set
=
2000 pipe_state
->descriptors
[binding
->set
];
2002 uint32_t dynamic_offset_idx
=
2003 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
2004 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
2007 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
2010 static struct anv_address
2011 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
2012 struct anv_descriptor_set
*set
)
2015 /* This is a normal descriptor set */
2016 return (struct anv_address
) {
2017 .bo
= &set
->pool
->bo
,
2018 .offset
= set
->desc_mem
.offset
,
2021 /* This is a push descriptor set. We have to flag it as used on the GPU
2022 * so that the next time we push descriptors, we grab a new memory.
2024 struct anv_push_descriptor_set
*push_set
=
2025 (struct anv_push_descriptor_set
*)set
;
2026 push_set
->set_used_on_gpu
= true;
2028 return (struct anv_address
) {
2029 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2030 .offset
= set
->desc_mem
.offset
,
2036 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2037 gl_shader_stage stage
,
2038 struct anv_state
*bt_state
)
2040 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2041 struct anv_cmd_pipeline_state
*pipe_state
;
2042 struct anv_pipeline
*pipeline
;
2043 uint32_t state_offset
;
2046 case MESA_SHADER_COMPUTE
:
2047 pipe_state
= &cmd_buffer
->state
.compute
.base
;
2050 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
2053 pipeline
= pipe_state
->pipeline
;
2055 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2056 *bt_state
= (struct anv_state
) { 0, };
2060 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2061 if (map
->surface_count
== 0) {
2062 *bt_state
= (struct anv_state
) { 0, };
2066 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2069 uint32_t *bt_map
= bt_state
->map
;
2071 if (bt_state
->map
== NULL
)
2072 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2074 /* We only need to emit relocs if we're not using softpin. If we are using
2075 * softpin then we always keep all user-allocated memory objects resident.
2077 const bool need_client_mem_relocs
=
2078 !cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
;
2080 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2081 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2083 struct anv_state surface_state
;
2085 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2086 /* Color attachment binding */
2087 assert(stage
== MESA_SHADER_FRAGMENT
);
2088 assert(binding
->binding
== 0);
2089 if (binding
->index
< subpass
->color_count
) {
2090 const unsigned att
=
2091 subpass
->color_attachments
[binding
->index
].attachment
;
2093 /* From the Vulkan 1.0.46 spec:
2095 * "If any color or depth/stencil attachments are
2096 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2099 if (att
== VK_ATTACHMENT_UNUSED
) {
2100 surface_state
= cmd_buffer
->state
.null_surface_state
;
2102 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2105 surface_state
= cmd_buffer
->state
.null_surface_state
;
2108 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2110 } else if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2111 struct anv_state surface_state
=
2112 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2114 struct anv_address constant_data
= {
2115 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2116 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2118 unsigned constant_data_size
=
2119 pipeline
->shaders
[stage
]->constant_data_size
;
2121 const enum isl_format format
=
2122 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2123 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2124 surface_state
, format
,
2125 constant_data
, constant_data_size
, 1);
2127 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2128 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2130 } else if (binding
->set
== ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
) {
2131 /* This is always the first binding for compute shaders */
2132 assert(stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2133 if (!get_cs_prog_data(pipeline
)->uses_num_work_groups
)
2136 struct anv_state surface_state
=
2137 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2139 const enum isl_format format
=
2140 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2141 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2143 cmd_buffer
->state
.compute
.num_workgroups
,
2145 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2146 if (need_client_mem_relocs
) {
2147 add_surface_reloc(cmd_buffer
, surface_state
,
2148 cmd_buffer
->state
.compute
.num_workgroups
);
2151 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2152 /* This is a descriptor set buffer so the set index is actually
2153 * given by binding->binding. (Yes, that's confusing.)
2155 struct anv_descriptor_set
*set
=
2156 pipe_state
->descriptors
[binding
->binding
];
2157 assert(set
->desc_mem
.alloc_size
);
2158 assert(set
->desc_surface_state
.alloc_size
);
2159 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2160 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2161 anv_descriptor_set_address(cmd_buffer
, set
));
2165 const struct anv_descriptor
*desc
=
2166 anv_descriptor_for_binding(pipe_state
, binding
);
2168 switch (desc
->type
) {
2169 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2170 /* Nothing for us to do here */
2173 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2174 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2175 struct anv_surface_state sstate
=
2176 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2177 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2178 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2179 surface_state
= sstate
.state
;
2180 assert(surface_state
.alloc_size
);
2181 if (need_client_mem_relocs
)
2182 add_surface_state_relocs(cmd_buffer
, sstate
);
2185 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2186 assert(stage
== MESA_SHADER_FRAGMENT
);
2187 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2188 /* For depth and stencil input attachments, we treat it like any
2189 * old texture that a user may have bound.
2191 struct anv_surface_state sstate
=
2192 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2193 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2194 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2195 surface_state
= sstate
.state
;
2196 assert(surface_state
.alloc_size
);
2197 if (need_client_mem_relocs
)
2198 add_surface_state_relocs(cmd_buffer
, sstate
);
2200 /* For color input attachments, we create the surface state at
2201 * vkBeginRenderPass time so that we can include aux and clear
2202 * color information.
2204 assert(binding
->input_attachment_index
< subpass
->input_count
);
2205 const unsigned subpass_att
= binding
->input_attachment_index
;
2206 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2207 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2211 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2212 struct anv_surface_state sstate
= (binding
->write_only
)
2213 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2214 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2215 surface_state
= sstate
.state
;
2216 assert(surface_state
.alloc_size
);
2217 if (need_client_mem_relocs
)
2218 add_surface_state_relocs(cmd_buffer
, sstate
);
2222 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2223 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2224 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2225 surface_state
= desc
->buffer_view
->surface_state
;
2226 assert(surface_state
.alloc_size
);
2227 if (need_client_mem_relocs
) {
2228 add_surface_reloc(cmd_buffer
, surface_state
,
2229 desc
->buffer_view
->address
);
2233 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2234 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2235 /* Compute the offset within the buffer */
2236 uint32_t dynamic_offset
=
2237 dynamic_offset_for_binding(pipe_state
, binding
);
2238 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2239 /* Clamp to the buffer size */
2240 offset
= MIN2(offset
, desc
->buffer
->size
);
2241 /* Clamp the range to the buffer size */
2242 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2244 struct anv_address address
=
2245 anv_address_add(desc
->buffer
->address
, offset
);
2248 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2249 enum isl_format format
=
2250 anv_isl_format_for_descriptor_type(desc
->type
);
2252 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2253 format
, address
, range
, 1);
2254 if (need_client_mem_relocs
)
2255 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2259 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2260 surface_state
= (binding
->write_only
)
2261 ? desc
->buffer_view
->writeonly_storage_surface_state
2262 : desc
->buffer_view
->storage_surface_state
;
2263 assert(surface_state
.alloc_size
);
2264 if (need_client_mem_relocs
) {
2265 add_surface_reloc(cmd_buffer
, surface_state
,
2266 desc
->buffer_view
->address
);
2271 assert(!"Invalid descriptor type");
2275 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2279 /* The PIPE_CONTROL command description says:
2281 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2282 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2283 * Target Cache Flush by enabling this bit. When render target flush
2284 * is set due to new association of BTI, PS Scoreboard Stall bit must
2285 * be set in this packet."
2287 * FINISHME: Currently we shuffle around the surface states in the binding
2288 * table based on if they are getting used or not. So, we've to do below
2289 * pipe control flush for every binding table upload. Make changes so
2290 * that we do it only when we modify render target surface states.
2292 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2293 pc
.RenderTargetCacheFlushEnable
= true;
2294 pc
.StallAtPixelScoreboard
= true;
2302 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2303 gl_shader_stage stage
,
2304 struct anv_state
*state
)
2306 struct anv_cmd_pipeline_state
*pipe_state
=
2307 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2308 &cmd_buffer
->state
.gfx
.base
;
2309 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2311 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2312 *state
= (struct anv_state
) { 0, };
2316 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2317 if (map
->sampler_count
== 0) {
2318 *state
= (struct anv_state
) { 0, };
2322 uint32_t size
= map
->sampler_count
* 16;
2323 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2325 if (state
->map
== NULL
)
2326 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2328 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2329 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2330 const struct anv_descriptor
*desc
=
2331 anv_descriptor_for_binding(pipe_state
, binding
);
2333 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2334 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2337 struct anv_sampler
*sampler
= desc
->sampler
;
2339 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2340 * happens to be zero.
2342 if (sampler
== NULL
)
2345 memcpy(state
->map
+ (s
* 16),
2346 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2353 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2355 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2357 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2358 pipeline
->active_stages
;
2360 VkResult result
= VK_SUCCESS
;
2361 anv_foreach_stage(s
, dirty
) {
2362 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2363 if (result
!= VK_SUCCESS
)
2365 result
= emit_binding_table(cmd_buffer
, s
,
2366 &cmd_buffer
->state
.binding_tables
[s
]);
2367 if (result
!= VK_SUCCESS
)
2371 if (result
!= VK_SUCCESS
) {
2372 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2374 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2375 if (result
!= VK_SUCCESS
)
2378 /* Re-emit state base addresses so we get the new surface state base
2379 * address before we start emitting binding tables etc.
2381 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2383 /* Re-emit all active binding tables */
2384 dirty
|= pipeline
->active_stages
;
2385 anv_foreach_stage(s
, dirty
) {
2386 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2387 if (result
!= VK_SUCCESS
) {
2388 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2391 result
= emit_binding_table(cmd_buffer
, s
,
2392 &cmd_buffer
->state
.binding_tables
[s
]);
2393 if (result
!= VK_SUCCESS
) {
2394 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2400 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2406 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2409 static const uint32_t sampler_state_opcodes
[] = {
2410 [MESA_SHADER_VERTEX
] = 43,
2411 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2412 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2413 [MESA_SHADER_GEOMETRY
] = 46,
2414 [MESA_SHADER_FRAGMENT
] = 47,
2415 [MESA_SHADER_COMPUTE
] = 0,
2418 static const uint32_t binding_table_opcodes
[] = {
2419 [MESA_SHADER_VERTEX
] = 38,
2420 [MESA_SHADER_TESS_CTRL
] = 39,
2421 [MESA_SHADER_TESS_EVAL
] = 40,
2422 [MESA_SHADER_GEOMETRY
] = 41,
2423 [MESA_SHADER_FRAGMENT
] = 42,
2424 [MESA_SHADER_COMPUTE
] = 0,
2427 anv_foreach_stage(s
, stages
) {
2428 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2429 assert(binding_table_opcodes
[s
] > 0);
2431 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2432 anv_batch_emit(&cmd_buffer
->batch
,
2433 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2434 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2435 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2439 /* Always emit binding table pointers if we're asked to, since on SKL
2440 * this is what flushes push constants. */
2441 anv_batch_emit(&cmd_buffer
->batch
,
2442 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2443 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2444 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2450 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2451 VkShaderStageFlags dirty_stages
)
2453 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2454 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2456 static const uint32_t push_constant_opcodes
[] = {
2457 [MESA_SHADER_VERTEX
] = 21,
2458 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2459 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2460 [MESA_SHADER_GEOMETRY
] = 22,
2461 [MESA_SHADER_FRAGMENT
] = 23,
2462 [MESA_SHADER_COMPUTE
] = 0,
2465 VkShaderStageFlags flushed
= 0;
2467 anv_foreach_stage(stage
, dirty_stages
) {
2468 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2469 assert(push_constant_opcodes
[stage
] > 0);
2471 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2472 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2474 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2475 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2476 const struct brw_stage_prog_data
*prog_data
=
2477 pipeline
->shaders
[stage
]->prog_data
;
2478 const struct anv_pipeline_bind_map
*bind_map
=
2479 &pipeline
->shaders
[stage
]->bind_map
;
2481 /* The Skylake PRM contains the following restriction:
2483 * "The driver must ensure The following case does not occur
2484 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2485 * buffer 3 read length equal to zero committed followed by a
2486 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2489 * To avoid this, we program the buffers in the highest slots.
2490 * This way, slot 0 is only used if slot 3 is also used.
2494 for (int i
= 3; i
>= 0; i
--) {
2495 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2496 if (range
->length
== 0)
2499 const unsigned surface
=
2500 prog_data
->binding_table
.ubo_start
+ range
->block
;
2502 assert(surface
<= bind_map
->surface_count
);
2503 const struct anv_pipeline_binding
*binding
=
2504 &bind_map
->surface_to_descriptor
[surface
];
2506 struct anv_address read_addr
;
2508 if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2509 struct anv_address constant_data
= {
2510 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2511 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2513 unsigned constant_data_size
=
2514 pipeline
->shaders
[stage
]->constant_data_size
;
2516 read_len
= MIN2(range
->length
,
2517 DIV_ROUND_UP(constant_data_size
, 32) - range
->start
);
2518 read_addr
= anv_address_add(constant_data
,
2520 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2521 /* This is a descriptor set buffer so the set index is
2522 * actually given by binding->binding. (Yes, that's
2525 struct anv_descriptor_set
*set
=
2526 gfx_state
->base
.descriptors
[binding
->binding
];
2527 struct anv_address desc_buffer_addr
=
2528 anv_descriptor_set_address(cmd_buffer
, set
);
2529 const unsigned desc_buffer_size
= set
->desc_mem
.alloc_size
;
2531 read_len
= MIN2(range
->length
,
2532 DIV_ROUND_UP(desc_buffer_size
, 32) - range
->start
);
2533 read_addr
= anv_address_add(desc_buffer_addr
,
2536 const struct anv_descriptor
*desc
=
2537 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2539 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2540 read_len
= MIN2(range
->length
,
2541 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2542 read_addr
= anv_address_add(desc
->buffer_view
->address
,
2545 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2547 uint32_t dynamic_offset
=
2548 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2549 uint32_t buf_offset
=
2550 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2551 uint32_t buf_range
=
2552 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2554 read_len
= MIN2(range
->length
,
2555 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2556 read_addr
= anv_address_add(desc
->buffer
->address
,
2557 buf_offset
+ range
->start
* 32);
2562 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2563 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2568 struct anv_state state
=
2569 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2571 if (state
.alloc_size
> 0) {
2572 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2573 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2574 .offset
= state
.offset
,
2576 c
.ConstantBody
.ReadLength
[n
] =
2577 DIV_ROUND_UP(state
.alloc_size
, 32);
2580 /* For Ivy Bridge, the push constants packets have a different
2581 * rule that would require us to iterate in the other direction
2582 * and possibly mess around with dynamic state base address.
2583 * Don't bother; just emit regular push constants at n = 0.
2585 struct anv_state state
=
2586 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2588 if (state
.alloc_size
> 0) {
2589 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2590 c
.ConstantBody
.ReadLength
[0] =
2591 DIV_ROUND_UP(state
.alloc_size
, 32);
2597 flushed
|= mesa_to_vk_shader_stage(stage
);
2600 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2604 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2606 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2609 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2610 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2611 vb_emit
|= pipeline
->vb_used
;
2613 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2615 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2617 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2620 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2621 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2623 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2624 GENX(3DSTATE_VERTEX_BUFFERS
));
2626 for_each_bit(vb
, vb_emit
) {
2627 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2628 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2630 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2631 .VertexBufferIndex
= vb
,
2633 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
2635 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2636 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2639 .AddressModifyEnable
= true,
2640 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2641 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2644 .BufferSize
= buffer
->size
- offset
2646 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2650 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2655 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2658 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
2659 /* We don't need any per-buffer dirty tracking because you're not
2660 * allowed to bind different XFB buffers while XFB is enabled.
2662 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
2663 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
2664 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
2665 sob
.SOBufferIndex
= idx
;
2667 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
2668 sob
.SOBufferEnable
= true;
2669 sob
.MOCS
= cmd_buffer
->device
->default_mocs
,
2670 sob
.StreamOffsetWriteEnable
= false;
2671 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
2673 /* Size is in DWords - 1 */
2674 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
2679 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
2681 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2685 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2686 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2688 /* The exact descriptor layout is pulled from the pipeline, so we need
2689 * to re-emit binding tables on every pipeline change.
2691 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2693 /* If the pipeline changed, we may need to re-allocate push constant
2696 cmd_buffer_alloc_push_constants(cmd_buffer
);
2700 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2701 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2702 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2704 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2705 * stall needs to be sent just prior to any 3DSTATE_VS,
2706 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2707 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2708 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2709 * PIPE_CONTROL needs to be sent before any combination of VS
2710 * associated 3DSTATE."
2712 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2713 pc
.DepthStallEnable
= true;
2714 pc
.PostSyncOperation
= WriteImmediateData
;
2716 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2721 /* Render targets live in the same binding table as fragment descriptors */
2722 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2723 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2725 /* We emit the binding tables and sampler tables first, then emit push
2726 * constants and then finally emit binding table and sampler table
2727 * pointers. It has to happen in this order, since emitting the binding
2728 * tables may change the push constants (in case of storage images). After
2729 * emitting push constants, on SKL+ we have to emit the corresponding
2730 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2733 if (cmd_buffer
->state
.descriptors_dirty
)
2734 dirty
= flush_descriptor_sets(cmd_buffer
);
2736 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2737 /* Because we're pushing UBOs, we have to push whenever either
2738 * descriptors or push constants is dirty.
2740 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2741 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2742 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2746 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2748 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2749 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2751 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2752 ANV_CMD_DIRTY_PIPELINE
)) {
2753 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2754 pipeline
->depth_clamp_enable
);
2757 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2758 ANV_CMD_DIRTY_RENDER_TARGETS
))
2759 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2761 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2763 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2767 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2768 struct anv_address addr
,
2769 uint32_t size
, uint32_t index
)
2771 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2772 GENX(3DSTATE_VERTEX_BUFFERS
));
2774 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2775 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2776 .VertexBufferIndex
= index
,
2777 .AddressModifyEnable
= true,
2779 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
),
2781 .BufferStartingAddress
= addr
,
2784 .BufferStartingAddress
= addr
,
2785 .EndAddress
= anv_address_add(addr
, size
),
2791 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2792 struct anv_address addr
)
2794 emit_vertex_bo(cmd_buffer
, addr
, 8, ANV_SVGS_VB_INDEX
);
2798 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2799 uint32_t base_vertex
, uint32_t base_instance
)
2801 struct anv_state id_state
=
2802 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2804 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2805 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2807 struct anv_address addr
= {
2808 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2809 .offset
= id_state
.offset
,
2812 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2816 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2818 struct anv_state state
=
2819 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2821 ((uint32_t *)state
.map
)[0] = draw_index
;
2823 struct anv_address addr
= {
2824 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2825 .offset
= state
.offset
,
2828 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2832 VkCommandBuffer commandBuffer
,
2833 uint32_t vertexCount
,
2834 uint32_t instanceCount
,
2835 uint32_t firstVertex
,
2836 uint32_t firstInstance
)
2838 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2839 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2840 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2842 if (anv_batch_has_error(&cmd_buffer
->batch
))
2845 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2847 if (cmd_buffer
->state
.conditional_render_enabled
)
2848 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2850 if (vs_prog_data
->uses_firstvertex
||
2851 vs_prog_data
->uses_baseinstance
)
2852 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2853 if (vs_prog_data
->uses_drawid
)
2854 emit_draw_index(cmd_buffer
, 0);
2856 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2857 * different views. We need to multiply instanceCount by the view count.
2859 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2861 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2862 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2863 prim
.VertexAccessType
= SEQUENTIAL
;
2864 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2865 prim
.VertexCountPerInstance
= vertexCount
;
2866 prim
.StartVertexLocation
= firstVertex
;
2867 prim
.InstanceCount
= instanceCount
;
2868 prim
.StartInstanceLocation
= firstInstance
;
2869 prim
.BaseVertexLocation
= 0;
2873 void genX(CmdDrawIndexed
)(
2874 VkCommandBuffer commandBuffer
,
2875 uint32_t indexCount
,
2876 uint32_t instanceCount
,
2877 uint32_t firstIndex
,
2878 int32_t vertexOffset
,
2879 uint32_t firstInstance
)
2881 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2882 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2883 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2885 if (anv_batch_has_error(&cmd_buffer
->batch
))
2888 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2890 if (cmd_buffer
->state
.conditional_render_enabled
)
2891 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2893 if (vs_prog_data
->uses_firstvertex
||
2894 vs_prog_data
->uses_baseinstance
)
2895 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2896 if (vs_prog_data
->uses_drawid
)
2897 emit_draw_index(cmd_buffer
, 0);
2899 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2900 * different views. We need to multiply instanceCount by the view count.
2902 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2904 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2905 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2906 prim
.VertexAccessType
= RANDOM
;
2907 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2908 prim
.VertexCountPerInstance
= indexCount
;
2909 prim
.StartVertexLocation
= firstIndex
;
2910 prim
.InstanceCount
= instanceCount
;
2911 prim
.StartInstanceLocation
= firstInstance
;
2912 prim
.BaseVertexLocation
= vertexOffset
;
2916 /* Auto-Draw / Indirect Registers */
2917 #define GEN7_3DPRIM_END_OFFSET 0x2420
2918 #define GEN7_3DPRIM_START_VERTEX 0x2430
2919 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2920 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2921 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2922 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2924 void genX(CmdDrawIndirectByteCountEXT
)(
2925 VkCommandBuffer commandBuffer
,
2926 uint32_t instanceCount
,
2927 uint32_t firstInstance
,
2928 VkBuffer counterBuffer
,
2929 VkDeviceSize counterBufferOffset
,
2930 uint32_t counterOffset
,
2931 uint32_t vertexStride
)
2933 #if GEN_IS_HASWELL || GEN_GEN >= 8
2934 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2935 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
2936 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2937 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2939 /* firstVertex is always zero for this draw function */
2940 const uint32_t firstVertex
= 0;
2942 if (anv_batch_has_error(&cmd_buffer
->batch
))
2945 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2947 if (vs_prog_data
->uses_firstvertex
||
2948 vs_prog_data
->uses_baseinstance
)
2949 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2950 if (vs_prog_data
->uses_drawid
)
2951 emit_draw_index(cmd_buffer
, 0);
2953 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2954 * different views. We need to multiply instanceCount by the view count.
2956 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2958 struct gen_mi_builder b
;
2959 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
2960 struct gen_mi_value count
=
2961 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
2962 counterBufferOffset
));
2964 count
= gen_mi_isub(&b
, count
, gen_mi_imm(counterOffset
));
2965 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
2966 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
2968 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
2969 gen_mi_imm(firstVertex
));
2970 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
2971 gen_mi_imm(instanceCount
));
2972 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
2973 gen_mi_imm(firstInstance
));
2974 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
2976 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2977 prim
.IndirectParameterEnable
= true;
2978 prim
.VertexAccessType
= SEQUENTIAL
;
2979 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2981 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2985 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2986 struct anv_address addr
,
2989 struct gen_mi_builder b
;
2990 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
2992 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
),
2993 gen_mi_mem32(anv_address_add(addr
, 0)));
2995 struct gen_mi_value instance_count
= gen_mi_mem32(anv_address_add(addr
, 4));
2996 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2997 if (view_count
> 1) {
2998 #if GEN_IS_HASWELL || GEN_GEN >= 8
2999 instance_count
= gen_mi_imul_imm(&b
, instance_count
, view_count
);
3001 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3002 "MI_MATH is not supported on Ivy Bridge");
3005 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
), instance_count
);
3007 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3008 gen_mi_mem32(anv_address_add(addr
, 8)));
3011 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
),
3012 gen_mi_mem32(anv_address_add(addr
, 12)));
3013 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3014 gen_mi_mem32(anv_address_add(addr
, 16)));
3016 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3017 gen_mi_mem32(anv_address_add(addr
, 12)));
3018 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3022 void genX(CmdDrawIndirect
)(
3023 VkCommandBuffer commandBuffer
,
3025 VkDeviceSize offset
,
3029 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3030 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3031 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3032 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3034 if (anv_batch_has_error(&cmd_buffer
->batch
))
3037 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3039 if (cmd_buffer
->state
.conditional_render_enabled
)
3040 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3042 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3043 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3045 if (vs_prog_data
->uses_firstvertex
||
3046 vs_prog_data
->uses_baseinstance
)
3047 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3048 if (vs_prog_data
->uses_drawid
)
3049 emit_draw_index(cmd_buffer
, i
);
3051 load_indirect_parameters(cmd_buffer
, draw
, false);
3053 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3054 prim
.IndirectParameterEnable
= true;
3055 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3056 prim
.VertexAccessType
= SEQUENTIAL
;
3057 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3064 void genX(CmdDrawIndexedIndirect
)(
3065 VkCommandBuffer commandBuffer
,
3067 VkDeviceSize offset
,
3071 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3072 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3073 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3074 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3076 if (anv_batch_has_error(&cmd_buffer
->batch
))
3079 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3081 if (cmd_buffer
->state
.conditional_render_enabled
)
3082 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3084 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3085 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3087 /* TODO: We need to stomp base vertex to 0 somehow */
3088 if (vs_prog_data
->uses_firstvertex
||
3089 vs_prog_data
->uses_baseinstance
)
3090 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3091 if (vs_prog_data
->uses_drawid
)
3092 emit_draw_index(cmd_buffer
, i
);
3094 load_indirect_parameters(cmd_buffer
, draw
, true);
3096 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3097 prim
.IndirectParameterEnable
= true;
3098 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3099 prim
.VertexAccessType
= RANDOM
;
3100 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3107 #define TMP_DRAW_COUNT_REG 0x2670 /* MI_ALU_REG14 */
3110 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3111 struct anv_address count_address
,
3112 const bool conditional_render_enabled
)
3114 struct gen_mi_builder b
;
3115 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3117 if (conditional_render_enabled
) {
3118 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3119 gen_mi_store(&b
, gen_mi_reg64(TMP_DRAW_COUNT_REG
),
3120 gen_mi_mem32(count_address
));
3123 /* Upload the current draw count from the draw parameters buffer to
3124 * MI_PREDICATE_SRC0.
3126 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
3127 gen_mi_mem32(count_address
));
3129 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
+ 4), gen_mi_imm(0));
3134 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3135 uint32_t draw_index
)
3137 struct gen_mi_builder b
;
3138 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3140 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3141 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
), gen_mi_imm(draw_index
));
3143 if (draw_index
== 0) {
3144 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3145 mip
.LoadOperation
= LOAD_LOADINV
;
3146 mip
.CombineOperation
= COMBINE_SET
;
3147 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3150 /* While draw_index < draw_count the predicate's result will be
3151 * (draw_index == draw_count) ^ TRUE = TRUE
3152 * When draw_index == draw_count the result is
3153 * (TRUE) ^ TRUE = FALSE
3154 * After this all results will be:
3155 * (FALSE) ^ FALSE = FALSE
3157 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3158 mip
.LoadOperation
= LOAD_LOAD
;
3159 mip
.CombineOperation
= COMBINE_XOR
;
3160 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3165 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3167 emit_draw_count_predicate_with_conditional_render(
3168 struct anv_cmd_buffer
*cmd_buffer
,
3169 uint32_t draw_index
)
3171 struct gen_mi_builder b
;
3172 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3174 struct gen_mi_value pred
= gen_mi_ult(&b
, gen_mi_imm(draw_index
),
3175 gen_mi_reg64(TMP_DRAW_COUNT_REG
));
3176 pred
= gen_mi_iand(&b
, pred
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
));
3179 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_RESULT
), pred
);
3181 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3182 * so we emit MI_PREDICATE to set it.
3185 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), pred
);
3186 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3188 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3189 mip
.LoadOperation
= LOAD_LOADINV
;
3190 mip
.CombineOperation
= COMBINE_SET
;
3191 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3197 void genX(CmdDrawIndirectCountKHR
)(
3198 VkCommandBuffer commandBuffer
,
3200 VkDeviceSize offset
,
3201 VkBuffer _countBuffer
,
3202 VkDeviceSize countBufferOffset
,
3203 uint32_t maxDrawCount
,
3206 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3207 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3208 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3209 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3210 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3211 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3213 if (anv_batch_has_error(&cmd_buffer
->batch
))
3216 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3218 struct anv_address count_address
=
3219 anv_address_add(count_buffer
->address
, countBufferOffset
);
3221 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3222 cmd_state
->conditional_render_enabled
);
3224 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3225 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3227 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3228 if (cmd_state
->conditional_render_enabled
) {
3229 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3231 emit_draw_count_predicate(cmd_buffer
, i
);
3234 emit_draw_count_predicate(cmd_buffer
, i
);
3237 if (vs_prog_data
->uses_firstvertex
||
3238 vs_prog_data
->uses_baseinstance
)
3239 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3240 if (vs_prog_data
->uses_drawid
)
3241 emit_draw_index(cmd_buffer
, i
);
3243 load_indirect_parameters(cmd_buffer
, draw
, false);
3245 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3246 prim
.IndirectParameterEnable
= true;
3247 prim
.PredicateEnable
= true;
3248 prim
.VertexAccessType
= SEQUENTIAL
;
3249 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3256 void genX(CmdDrawIndexedIndirectCountKHR
)(
3257 VkCommandBuffer commandBuffer
,
3259 VkDeviceSize offset
,
3260 VkBuffer _countBuffer
,
3261 VkDeviceSize countBufferOffset
,
3262 uint32_t maxDrawCount
,
3265 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3266 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3267 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3268 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3269 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3270 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3272 if (anv_batch_has_error(&cmd_buffer
->batch
))
3275 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3277 struct anv_address count_address
=
3278 anv_address_add(count_buffer
->address
, countBufferOffset
);
3280 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3281 cmd_state
->conditional_render_enabled
);
3283 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3284 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3286 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3287 if (cmd_state
->conditional_render_enabled
) {
3288 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3290 emit_draw_count_predicate(cmd_buffer
, i
);
3293 emit_draw_count_predicate(cmd_buffer
, i
);
3296 /* TODO: We need to stomp base vertex to 0 somehow */
3297 if (vs_prog_data
->uses_firstvertex
||
3298 vs_prog_data
->uses_baseinstance
)
3299 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3300 if (vs_prog_data
->uses_drawid
)
3301 emit_draw_index(cmd_buffer
, i
);
3303 load_indirect_parameters(cmd_buffer
, draw
, true);
3305 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3306 prim
.IndirectParameterEnable
= true;
3307 prim
.PredicateEnable
= true;
3308 prim
.VertexAccessType
= RANDOM
;
3309 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3316 void genX(CmdBeginTransformFeedbackEXT
)(
3317 VkCommandBuffer commandBuffer
,
3318 uint32_t firstCounterBuffer
,
3319 uint32_t counterBufferCount
,
3320 const VkBuffer
* pCounterBuffers
,
3321 const VkDeviceSize
* pCounterBufferOffsets
)
3323 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3325 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3326 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3327 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3329 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3331 * "Ssoftware must ensure that no HW stream output operations can be in
3332 * process or otherwise pending at the point that the MI_LOAD/STORE
3333 * commands are processed. This will likely require a pipeline flush."
3335 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3336 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3338 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3339 /* If we have a counter buffer, this is a resume so we need to load the
3340 * value into the streamout offset register. Otherwise, this is a begin
3341 * and we need to reset it to zero.
3343 if (pCounterBuffers
&&
3344 idx
>= firstCounterBuffer
&&
3345 idx
- firstCounterBuffer
< counterBufferCount
&&
3346 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
3347 uint32_t cb_idx
= idx
- firstCounterBuffer
;
3348 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3349 uint64_t offset
= pCounterBufferOffsets
?
3350 pCounterBufferOffsets
[cb_idx
] : 0;
3352 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3353 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3354 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3358 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
3359 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3365 cmd_buffer
->state
.xfb_enabled
= true;
3366 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3369 void genX(CmdEndTransformFeedbackEXT
)(
3370 VkCommandBuffer commandBuffer
,
3371 uint32_t firstCounterBuffer
,
3372 uint32_t counterBufferCount
,
3373 const VkBuffer
* pCounterBuffers
,
3374 const VkDeviceSize
* pCounterBufferOffsets
)
3376 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3378 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3379 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3380 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3382 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3384 * "Ssoftware must ensure that no HW stream output operations can be in
3385 * process or otherwise pending at the point that the MI_LOAD/STORE
3386 * commands are processed. This will likely require a pipeline flush."
3388 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3389 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3391 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
3392 unsigned idx
= firstCounterBuffer
+ cb_idx
;
3394 /* If we have a counter buffer, this is a resume so we need to load the
3395 * value into the streamout offset register. Otherwise, this is a begin
3396 * and we need to reset it to zero.
3398 if (pCounterBuffers
&&
3399 cb_idx
< counterBufferCount
&&
3400 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
3401 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3402 uint64_t offset
= pCounterBufferOffsets
?
3403 pCounterBufferOffsets
[cb_idx
] : 0;
3405 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
3406 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3408 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3413 cmd_buffer
->state
.xfb_enabled
= false;
3414 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3418 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
3420 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3421 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
3424 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3425 if (result
!= VK_SUCCESS
) {
3426 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3428 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
3429 if (result
!= VK_SUCCESS
)
3432 /* Re-emit state base addresses so we get the new surface state base
3433 * address before we start emitting binding tables etc.
3435 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
3437 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3438 if (result
!= VK_SUCCESS
) {
3439 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3444 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3445 if (result
!= VK_SUCCESS
) {
3446 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3450 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3451 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3452 .BindingTablePointer
= surfaces
.offset
,
3453 .SamplerStatePointer
= samplers
.offset
,
3455 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3457 struct anv_state state
=
3458 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3459 pipeline
->interface_descriptor_data
,
3460 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3463 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3464 anv_batch_emit(&cmd_buffer
->batch
,
3465 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3466 mid
.InterfaceDescriptorTotalLength
= size
;
3467 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3474 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3476 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3477 MAYBE_UNUSED VkResult result
;
3479 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3481 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3483 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3485 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3486 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3488 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3489 * the only bits that are changed are scoreboard related: Scoreboard
3490 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3491 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3494 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3495 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3497 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3500 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3501 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3502 /* FIXME: figure out descriptors for gen7 */
3503 result
= flush_compute_descriptor_set(cmd_buffer
);
3504 if (result
!= VK_SUCCESS
)
3507 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3510 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3511 struct anv_state push_state
=
3512 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3514 if (push_state
.alloc_size
) {
3515 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3516 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3517 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3521 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3524 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3526 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3532 verify_cmd_parser(const struct anv_device
*device
,
3533 int required_version
,
3534 const char *function
)
3536 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3537 return vk_errorf(device
->instance
, device
->instance
,
3538 VK_ERROR_FEATURE_NOT_PRESENT
,
3539 "cmd parser version %d is required for %s",
3540 required_version
, function
);
3549 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3550 uint32_t baseGroupX
,
3551 uint32_t baseGroupY
,
3552 uint32_t baseGroupZ
)
3554 if (anv_batch_has_error(&cmd_buffer
->batch
))
3557 struct anv_push_constants
*push
=
3558 &cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3559 if (push
->base_work_group_id
[0] != baseGroupX
||
3560 push
->base_work_group_id
[1] != baseGroupY
||
3561 push
->base_work_group_id
[2] != baseGroupZ
) {
3562 push
->base_work_group_id
[0] = baseGroupX
;
3563 push
->base_work_group_id
[1] = baseGroupY
;
3564 push
->base_work_group_id
[2] = baseGroupZ
;
3566 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3570 void genX(CmdDispatch
)(
3571 VkCommandBuffer commandBuffer
,
3576 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3579 void genX(CmdDispatchBase
)(
3580 VkCommandBuffer commandBuffer
,
3581 uint32_t baseGroupX
,
3582 uint32_t baseGroupY
,
3583 uint32_t baseGroupZ
,
3584 uint32_t groupCountX
,
3585 uint32_t groupCountY
,
3586 uint32_t groupCountZ
)
3588 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3589 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3590 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3592 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3593 baseGroupY
, baseGroupZ
);
3595 if (anv_batch_has_error(&cmd_buffer
->batch
))
3598 if (prog_data
->uses_num_work_groups
) {
3599 struct anv_state state
=
3600 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3601 uint32_t *sizes
= state
.map
;
3602 sizes
[0] = groupCountX
;
3603 sizes
[1] = groupCountY
;
3604 sizes
[2] = groupCountZ
;
3605 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3606 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3607 .offset
= state
.offset
,
3611 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3613 if (cmd_buffer
->state
.conditional_render_enabled
)
3614 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3616 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3617 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3618 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3619 ggw
.ThreadDepthCounterMaximum
= 0;
3620 ggw
.ThreadHeightCounterMaximum
= 0;
3621 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3622 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3623 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3624 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3625 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3626 ggw
.BottomExecutionMask
= 0xffffffff;
3629 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3632 #define GPGPU_DISPATCHDIMX 0x2500
3633 #define GPGPU_DISPATCHDIMY 0x2504
3634 #define GPGPU_DISPATCHDIMZ 0x2508
3636 void genX(CmdDispatchIndirect
)(
3637 VkCommandBuffer commandBuffer
,
3639 VkDeviceSize offset
)
3641 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3642 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3643 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3644 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3645 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3646 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3648 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3651 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3652 * indirect dispatch registers to be written.
3654 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3655 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3659 if (prog_data
->uses_num_work_groups
)
3660 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3662 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3664 struct gen_mi_builder b
;
3665 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3667 struct gen_mi_value size_x
= gen_mi_mem32(anv_address_add(addr
, 0));
3668 struct gen_mi_value size_y
= gen_mi_mem32(anv_address_add(addr
, 4));
3669 struct gen_mi_value size_z
= gen_mi_mem32(anv_address_add(addr
, 8));
3671 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMX
), size_x
);
3672 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMY
), size_y
);
3673 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMZ
), size_z
);
3676 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3677 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), size_x
);
3678 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3679 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3680 mip
.LoadOperation
= LOAD_LOAD
;
3681 mip
.CombineOperation
= COMBINE_SET
;
3682 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3685 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3686 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_y
);
3687 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3688 mip
.LoadOperation
= LOAD_LOAD
;
3689 mip
.CombineOperation
= COMBINE_OR
;
3690 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3693 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3694 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_z
);
3695 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3696 mip
.LoadOperation
= LOAD_LOAD
;
3697 mip
.CombineOperation
= COMBINE_OR
;
3698 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3701 /* predicate = !predicate; */
3702 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3703 mip
.LoadOperation
= LOAD_LOADINV
;
3704 mip
.CombineOperation
= COMBINE_OR
;
3705 mip
.CompareOperation
= COMPARE_FALSE
;
3709 if (cmd_buffer
->state
.conditional_render_enabled
) {
3710 /* predicate &= !(conditional_rendering_predicate == 0); */
3711 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
),
3712 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
3713 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3714 mip
.LoadOperation
= LOAD_LOADINV
;
3715 mip
.CombineOperation
= COMBINE_AND
;
3716 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3721 #else /* GEN_GEN > 7 */
3722 if (cmd_buffer
->state
.conditional_render_enabled
)
3723 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3726 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3727 ggw
.IndirectParameterEnable
= true;
3728 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
3729 cmd_buffer
->state
.conditional_render_enabled
;
3730 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3731 ggw
.ThreadDepthCounterMaximum
= 0;
3732 ggw
.ThreadHeightCounterMaximum
= 0;
3733 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3734 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3735 ggw
.BottomExecutionMask
= 0xffffffff;
3738 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3742 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3745 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3747 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3750 #if GEN_GEN >= 8 && GEN_GEN < 10
3751 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3753 * Software must clear the COLOR_CALC_STATE Valid field in
3754 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3755 * with Pipeline Select set to GPGPU.
3757 * The internal hardware docs recommend the same workaround for Gen9
3760 if (pipeline
== GPGPU
)
3761 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3764 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3765 * PIPELINE_SELECT [DevBWR+]":
3769 * Software must ensure all the write caches are flushed through a
3770 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3771 * command to invalidate read only caches prior to programming
3772 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3774 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3775 pc
.RenderTargetCacheFlushEnable
= true;
3776 pc
.DepthCacheFlushEnable
= true;
3777 pc
.DCFlushEnable
= true;
3778 pc
.PostSyncOperation
= NoWrite
;
3779 pc
.CommandStreamerStallEnable
= true;
3782 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3783 pc
.TextureCacheInvalidationEnable
= true;
3784 pc
.ConstantCacheInvalidationEnable
= true;
3785 pc
.StateCacheInvalidationEnable
= true;
3786 pc
.InstructionCacheInvalidateEnable
= true;
3787 pc
.PostSyncOperation
= NoWrite
;
3790 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3794 ps
.PipelineSelection
= pipeline
;
3798 if (devinfo
->is_geminilake
) {
3801 * "This chicken bit works around a hardware issue with barrier logic
3802 * encountered when switching between GPGPU and 3D pipelines. To
3803 * workaround the issue, this mode bit should be set after a pipeline
3807 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3809 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3810 : GLK_BARRIER_MODE_3D_HULL
,
3811 .GLKBarrierModeMask
= 1);
3812 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3816 cmd_buffer
->state
.current_pipeline
= pipeline
;
3820 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3822 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3826 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3828 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3832 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3837 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3839 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3840 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3841 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3842 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3843 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3844 * Depth Flush Bit set, followed by another pipelined depth stall
3845 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3846 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3847 * via a preceding MI_FLUSH)."
3849 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3850 pipe
.DepthStallEnable
= true;
3852 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3853 pipe
.DepthCacheFlushEnable
= true;
3855 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3856 pipe
.DepthStallEnable
= true;
3861 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3863 struct anv_device
*device
= cmd_buffer
->device
;
3864 const struct anv_image_view
*iview
=
3865 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3866 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3868 /* FIXME: Width and Height are wrong */
3870 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3872 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3873 device
->isl_dev
.ds
.size
/ 4);
3877 struct isl_depth_stencil_hiz_emit_info info
= { };
3880 info
.view
= &iview
->planes
[0].isl
;
3882 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3883 uint32_t depth_plane
=
3884 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3885 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
3887 info
.depth_surf
= &surface
->isl
;
3889 info
.depth_address
=
3890 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3891 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
3892 image
->planes
[depth_plane
].address
.bo
,
3893 image
->planes
[depth_plane
].address
.offset
+
3896 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
3899 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
3900 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
3901 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
3902 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
3905 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3906 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
3907 image
->planes
[depth_plane
].address
.bo
,
3908 image
->planes
[depth_plane
].address
.offset
+
3909 image
->planes
[depth_plane
].aux_surface
.offset
);
3911 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
3915 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3916 uint32_t stencil_plane
=
3917 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
3918 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
3920 info
.stencil_surf
= &surface
->isl
;
3922 info
.stencil_address
=
3923 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3924 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
3925 image
->planes
[stencil_plane
].address
.bo
,
3926 image
->planes
[stencil_plane
].address
.offset
+
3929 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
3932 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
3934 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
3938 * This ANDs the view mask of the current subpass with the pending clear
3939 * views in the attachment to get the mask of views active in the subpass
3940 * that still need to be cleared.
3942 static inline uint32_t
3943 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
3944 const struct anv_attachment_state
*att_state
)
3946 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
3950 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
3951 const struct anv_attachment_state
*att_state
)
3953 if (!cmd_state
->subpass
->view_mask
)
3956 uint32_t pending_clear_mask
=
3957 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3959 return pending_clear_mask
& 1;
3963 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
3966 const uint32_t last_subpass_idx
=
3967 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
3968 const struct anv_subpass
*last_subpass
=
3969 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
3970 return last_subpass
== cmd_state
->subpass
;
3974 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
3975 uint32_t subpass_id
)
3977 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3978 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
3979 cmd_state
->subpass
= subpass
;
3981 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
3983 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3984 * different views. If the client asks for instancing, we need to use the
3985 * Instance Data Step Rate to ensure that we repeat the client's
3986 * per-instance data once for each view. Since this bit is in
3987 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
3991 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
3993 /* It is possible to start a render pass with an old pipeline. Because the
3994 * render pass and subpass index are both baked into the pipeline, this is
3995 * highly unlikely. In order to do so, it requires that you have a render
3996 * pass with a single subpass and that you use that render pass twice
3997 * back-to-back and use the same pipeline at the start of the second render
3998 * pass as at the end of the first. In order to avoid unpredictable issues
3999 * with this edge case, we just dirty the pipeline at the start of every
4002 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
4004 /* Accumulate any subpass flushes that need to happen before the subpass */
4005 cmd_buffer
->state
.pending_pipe_bits
|=
4006 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
4008 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4009 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4011 bool is_multiview
= subpass
->view_mask
!= 0;
4013 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4014 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4015 if (a
== VK_ATTACHMENT_UNUSED
)
4018 assert(a
< cmd_state
->pass
->attachment_count
);
4019 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4021 struct anv_image_view
*iview
= fb
->attachments
[a
];
4022 const struct anv_image
*image
= iview
->image
;
4024 /* A resolve is necessary before use as an input attachment if the clear
4025 * color or auxiliary buffer usage isn't supported by the sampler.
4027 const bool input_needs_resolve
=
4028 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
4029 att_state
->input_aux_usage
!= att_state
->aux_usage
;
4031 VkImageLayout target_layout
;
4032 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
4033 !input_needs_resolve
) {
4034 /* Layout transitions before the final only help to enable sampling
4035 * as an input attachment. If the input attachment supports sampling
4036 * using the auxiliary surface, we can skip such transitions by
4037 * making the target layout one that is CCS-aware.
4039 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
4041 target_layout
= subpass
->attachments
[i
].layout
;
4044 uint32_t base_layer
, layer_count
;
4045 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4047 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4048 iview
->planes
[0].isl
.base_level
);
4050 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4051 layer_count
= fb
->layers
;
4054 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4055 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4056 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4057 iview
->planes
[0].isl
.base_level
, 1,
4058 base_layer
, layer_count
,
4059 att_state
->current_layout
, target_layout
);
4062 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4063 transition_depth_buffer(cmd_buffer
, image
,
4064 att_state
->current_layout
, target_layout
);
4065 att_state
->aux_usage
=
4066 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
4067 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
4070 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4071 transition_stencil_buffer(cmd_buffer
, image
,
4072 iview
->planes
[0].isl
.base_level
, 1,
4073 base_layer
, layer_count
,
4074 att_state
->current_layout
, target_layout
);
4076 att_state
->current_layout
= target_layout
;
4078 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
4079 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4081 /* Multi-planar images are not supported as attachments */
4082 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4083 assert(image
->n_planes
== 1);
4085 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
4086 uint32_t clear_layer_count
= fb
->layers
;
4088 if (att_state
->fast_clear
&&
4089 do_first_layer_clear(cmd_state
, att_state
)) {
4090 /* We only support fast-clears on the first layer */
4091 assert(iview
->planes
[0].isl
.base_level
== 0);
4092 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4094 union isl_color_value clear_color
= {};
4095 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
4096 if (iview
->image
->samples
== 1) {
4097 anv_image_ccs_op(cmd_buffer
, image
,
4098 iview
->planes
[0].isl
.format
,
4099 VK_IMAGE_ASPECT_COLOR_BIT
,
4100 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4104 anv_image_mcs_op(cmd_buffer
, image
,
4105 iview
->planes
[0].isl
.format
,
4106 VK_IMAGE_ASPECT_COLOR_BIT
,
4107 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4112 clear_layer_count
--;
4114 att_state
->pending_clear_views
&= ~1;
4116 if (att_state
->clear_color_is_zero
) {
4117 /* This image has the auxiliary buffer enabled. We can mark the
4118 * subresource as not needing a resolve because the clear color
4119 * will match what's in every RENDER_SURFACE_STATE object when
4120 * it's being used for sampling.
4122 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4123 VK_IMAGE_ASPECT_COLOR_BIT
,
4124 ANV_FAST_CLEAR_DEFAULT_VALUE
);
4126 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4127 VK_IMAGE_ASPECT_COLOR_BIT
,
4128 ANV_FAST_CLEAR_ANY
);
4132 /* From the VkFramebufferCreateInfo spec:
4134 * "If the render pass uses multiview, then layers must be one and each
4135 * attachment requires a number of layers that is greater than the
4136 * maximum bit index set in the view mask in the subpasses in which it
4139 * So if multiview is active we ignore the number of layers in the
4140 * framebuffer and instead we honor the view mask from the subpass.
4143 assert(image
->n_planes
== 1);
4144 uint32_t pending_clear_mask
=
4145 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4148 for_each_bit(layer_idx
, pending_clear_mask
) {
4150 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4152 anv_image_clear_color(cmd_buffer
, image
,
4153 VK_IMAGE_ASPECT_COLOR_BIT
,
4154 att_state
->aux_usage
,
4155 iview
->planes
[0].isl
.format
,
4156 iview
->planes
[0].isl
.swizzle
,
4157 iview
->planes
[0].isl
.base_level
,
4160 vk_to_isl_color(att_state
->clear_value
.color
));
4163 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4164 } else if (clear_layer_count
> 0) {
4165 assert(image
->n_planes
== 1);
4166 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4167 att_state
->aux_usage
,
4168 iview
->planes
[0].isl
.format
,
4169 iview
->planes
[0].isl
.swizzle
,
4170 iview
->planes
[0].isl
.base_level
,
4171 base_clear_layer
, clear_layer_count
,
4173 vk_to_isl_color(att_state
->clear_value
.color
));
4175 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
4176 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4177 if (att_state
->fast_clear
&& !is_multiview
) {
4178 /* We currently only support HiZ for single-layer images */
4179 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4180 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
4181 assert(iview
->planes
[0].isl
.base_level
== 0);
4182 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4183 assert(fb
->layers
== 1);
4186 anv_image_hiz_clear(cmd_buffer
, image
,
4187 att_state
->pending_clear_aspects
,
4188 iview
->planes
[0].isl
.base_level
,
4189 iview
->planes
[0].isl
.base_array_layer
,
4190 fb
->layers
, render_area
,
4191 att_state
->clear_value
.depthStencil
.stencil
);
4192 } else if (is_multiview
) {
4193 uint32_t pending_clear_mask
=
4194 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4197 for_each_bit(layer_idx
, pending_clear_mask
) {
4199 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4201 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4202 att_state
->pending_clear_aspects
,
4203 att_state
->aux_usage
,
4204 iview
->planes
[0].isl
.base_level
,
4207 att_state
->clear_value
.depthStencil
.depth
,
4208 att_state
->clear_value
.depthStencil
.stencil
);
4211 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4213 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4214 att_state
->pending_clear_aspects
,
4215 att_state
->aux_usage
,
4216 iview
->planes
[0].isl
.base_level
,
4217 iview
->planes
[0].isl
.base_array_layer
,
4218 fb
->layers
, render_area
,
4219 att_state
->clear_value
.depthStencil
.depth
,
4220 att_state
->clear_value
.depthStencil
.stencil
);
4223 assert(att_state
->pending_clear_aspects
== 0);
4227 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4228 image
->planes
[0].aux_surface
.isl
.size_B
> 0 &&
4229 iview
->planes
[0].isl
.base_level
== 0 &&
4230 iview
->planes
[0].isl
.base_array_layer
== 0) {
4231 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
4232 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
4233 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4234 false /* copy to ss */);
4237 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
4238 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
4239 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
4240 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4241 false /* copy to ss */);
4245 if (subpass
->attachments
[i
].usage
==
4246 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
4247 /* We assume that if we're starting a subpass, we're going to do some
4248 * rendering so we may end up with compressed data.
4250 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
4251 VK_IMAGE_ASPECT_COLOR_BIT
,
4252 att_state
->aux_usage
,
4253 iview
->planes
[0].isl
.base_level
,
4254 iview
->planes
[0].isl
.base_array_layer
,
4256 } else if (subpass
->attachments
[i
].usage
==
4257 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
4258 /* We may be writing depth or stencil so we need to mark the surface.
4259 * Unfortunately, there's no way to know at this point whether the
4260 * depth or stencil tests used will actually write to the surface.
4262 * Even though stencil may be plane 1, it always shares a base_level
4265 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
4266 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4267 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4268 VK_IMAGE_ASPECT_DEPTH_BIT
,
4269 att_state
->aux_usage
,
4270 ds_view
->base_level
,
4271 ds_view
->base_array_layer
,
4274 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4275 /* Even though stencil may be plane 1, it always shares a
4276 * base_level with depth.
4278 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4279 VK_IMAGE_ASPECT_STENCIL_BIT
,
4281 ds_view
->base_level
,
4282 ds_view
->base_array_layer
,
4287 /* If multiview is enabled, then we are only done clearing when we no
4288 * longer have pending layers to clear, or when we have processed the
4289 * last subpass that uses this attachment.
4291 if (!is_multiview
||
4292 att_state
->pending_clear_views
== 0 ||
4293 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
4294 att_state
->pending_clear_aspects
= 0;
4297 att_state
->pending_load_aspects
= 0;
4300 cmd_buffer_emit_depth_stencil(cmd_buffer
);
4303 static enum blorp_filter
4304 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
4307 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
4308 return BLORP_FILTER_SAMPLE_0
;
4309 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
4310 return BLORP_FILTER_AVERAGE
;
4311 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
4312 return BLORP_FILTER_MIN_SAMPLE
;
4313 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
4314 return BLORP_FILTER_MAX_SAMPLE
;
4316 return BLORP_FILTER_NONE
;
4321 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
4323 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4324 struct anv_subpass
*subpass
= cmd_state
->subpass
;
4325 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
4326 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4328 if (subpass
->has_color_resolve
) {
4329 /* We are about to do some MSAA resolves. We need to flush so that the
4330 * result of writes to the MSAA color attachments show up in the sampler
4331 * when we blit to the single-sampled resolve target.
4333 cmd_buffer
->state
.pending_pipe_bits
|=
4334 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4335 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
4337 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
4338 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
4339 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
4341 if (dst_att
== VK_ATTACHMENT_UNUSED
)
4344 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4345 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4347 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4348 /* From the Vulkan 1.0 spec:
4350 * If the first use of an attachment in a render pass is as a
4351 * resolve attachment, then the loadOp is effectively ignored
4352 * as the resolve is guaranteed to overwrite all pixels in the
4355 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4358 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
4359 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
4361 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4363 enum isl_aux_usage src_aux_usage
=
4364 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
4365 enum isl_aux_usage dst_aux_usage
=
4366 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
4368 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
4369 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
4371 anv_image_msaa_resolve(cmd_buffer
,
4372 src_iview
->image
, src_aux_usage
,
4373 src_iview
->planes
[0].isl
.base_level
,
4374 src_iview
->planes
[0].isl
.base_array_layer
,
4375 dst_iview
->image
, dst_aux_usage
,
4376 dst_iview
->planes
[0].isl
.base_level
,
4377 dst_iview
->planes
[0].isl
.base_array_layer
,
4378 VK_IMAGE_ASPECT_COLOR_BIT
,
4379 render_area
.offset
.x
, render_area
.offset
.y
,
4380 render_area
.offset
.x
, render_area
.offset
.y
,
4381 render_area
.extent
.width
,
4382 render_area
.extent
.height
,
4383 fb
->layers
, BLORP_FILTER_NONE
);
4387 if (subpass
->ds_resolve_attachment
) {
4388 /* We are about to do some MSAA resolves. We need to flush so that the
4389 * result of writes to the MSAA depth attachments show up in the sampler
4390 * when we blit to the single-sampled resolve target.
4392 cmd_buffer
->state
.pending_pipe_bits
|=
4393 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4394 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
4396 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
4397 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
4399 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4400 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4402 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4403 /* From the Vulkan 1.0 spec:
4405 * If the first use of an attachment in a render pass is as a
4406 * resolve attachment, then the loadOp is effectively ignored
4407 * as the resolve is guaranteed to overwrite all pixels in the
4410 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4413 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
4414 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
4416 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4418 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
4419 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4421 struct anv_attachment_state
*src_state
=
4422 &cmd_state
->attachments
[src_att
];
4423 struct anv_attachment_state
*dst_state
=
4424 &cmd_state
->attachments
[dst_att
];
4426 /* MSAA resolves sample from the source attachment. Transition the
4427 * depth attachment first to get rid of any HiZ that we may not be
4430 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
4431 src_state
->current_layout
,
4432 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4433 src_state
->aux_usage
=
4434 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
4435 VK_IMAGE_ASPECT_DEPTH_BIT
,
4436 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4437 src_state
->current_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
4439 /* MSAA resolves write to the resolve attachment as if it were any
4440 * other transfer op. Transition the resolve attachment accordingly.
4442 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
4444 /* If our render area is the entire size of the image, we're going to
4445 * blow it all away so we can claim the initial layout is UNDEFINED
4446 * and we'll get a HiZ ambiguate instead of a resolve.
4448 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
4449 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
4450 render_area
.extent
.width
== dst_iview
->extent
.width
&&
4451 render_area
.extent
.height
== dst_iview
->extent
.height
)
4452 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
4454 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
4456 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4457 dst_state
->aux_usage
=
4458 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
4459 VK_IMAGE_ASPECT_DEPTH_BIT
,
4460 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4461 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
4463 enum blorp_filter filter
=
4464 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
4466 anv_image_msaa_resolve(cmd_buffer
,
4467 src_iview
->image
, src_state
->aux_usage
,
4468 src_iview
->planes
[0].isl
.base_level
,
4469 src_iview
->planes
[0].isl
.base_array_layer
,
4470 dst_iview
->image
, dst_state
->aux_usage
,
4471 dst_iview
->planes
[0].isl
.base_level
,
4472 dst_iview
->planes
[0].isl
.base_array_layer
,
4473 VK_IMAGE_ASPECT_DEPTH_BIT
,
4474 render_area
.offset
.x
, render_area
.offset
.y
,
4475 render_area
.offset
.x
, render_area
.offset
.y
,
4476 render_area
.extent
.width
,
4477 render_area
.extent
.height
,
4478 fb
->layers
, filter
);
4481 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
4482 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4484 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
4485 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
4487 enum blorp_filter filter
=
4488 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
4490 anv_image_msaa_resolve(cmd_buffer
,
4491 src_iview
->image
, src_aux_usage
,
4492 src_iview
->planes
[0].isl
.base_level
,
4493 src_iview
->planes
[0].isl
.base_array_layer
,
4494 dst_iview
->image
, dst_aux_usage
,
4495 dst_iview
->planes
[0].isl
.base_level
,
4496 dst_iview
->planes
[0].isl
.base_array_layer
,
4497 VK_IMAGE_ASPECT_STENCIL_BIT
,
4498 render_area
.offset
.x
, render_area
.offset
.y
,
4499 render_area
.offset
.x
, render_area
.offset
.y
,
4500 render_area
.extent
.width
,
4501 render_area
.extent
.height
,
4502 fb
->layers
, filter
);
4506 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4507 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4508 if (a
== VK_ATTACHMENT_UNUSED
)
4511 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4514 assert(a
< cmd_state
->pass
->attachment_count
);
4515 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4516 struct anv_image_view
*iview
= fb
->attachments
[a
];
4517 const struct anv_image
*image
= iview
->image
;
4519 if ((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4520 image
->vk_format
!= iview
->vk_format
) {
4521 enum anv_fast_clear_type fast_clear_type
=
4522 anv_layout_to_fast_clear_type(&cmd_buffer
->device
->info
,
4523 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4524 att_state
->current_layout
);
4526 /* If any clear color was used, flush it down the aux surfaces. If we
4527 * don't do it now using the view's format we might use the clear
4528 * color incorrectly in the following resolves (for example with an
4529 * SRGB view & a UNORM image).
4531 if (fast_clear_type
!= ANV_FAST_CLEAR_NONE
) {
4532 anv_perf_warn(cmd_buffer
->device
->instance
, fb
,
4533 "Doing a partial resolve to get rid of clear color at the "
4534 "end of a renderpass due to an image/view format mismatch");
4536 uint32_t base_layer
, layer_count
;
4537 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4539 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4540 iview
->planes
[0].isl
.base_level
);
4542 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4543 layer_count
= fb
->layers
;
4546 for (uint32_t a
= 0; a
< layer_count
; a
++) {
4547 uint32_t array_layer
= base_layer
+ a
;
4548 if (image
->samples
== 1) {
4549 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
4550 iview
->planes
[0].isl
.format
,
4551 VK_IMAGE_ASPECT_COLOR_BIT
,
4552 iview
->planes
[0].isl
.base_level
,
4554 ISL_AUX_OP_PARTIAL_RESOLVE
,
4555 ANV_FAST_CLEAR_NONE
);
4557 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
4558 iview
->planes
[0].isl
.format
,
4559 VK_IMAGE_ASPECT_COLOR_BIT
,
4561 ISL_AUX_OP_PARTIAL_RESOLVE
,
4562 ANV_FAST_CLEAR_NONE
);
4568 /* Transition the image into the final layout for this render pass */
4569 VkImageLayout target_layout
=
4570 cmd_state
->pass
->attachments
[a
].final_layout
;
4572 uint32_t base_layer
, layer_count
;
4573 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4575 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4576 iview
->planes
[0].isl
.base_level
);
4578 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4579 layer_count
= fb
->layers
;
4582 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4583 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4584 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4585 iview
->planes
[0].isl
.base_level
, 1,
4586 base_layer
, layer_count
,
4587 att_state
->current_layout
, target_layout
);
4590 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4591 transition_depth_buffer(cmd_buffer
, image
,
4592 att_state
->current_layout
, target_layout
);
4595 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4596 transition_stencil_buffer(cmd_buffer
, image
,
4597 iview
->planes
[0].isl
.base_level
, 1,
4598 base_layer
, layer_count
,
4599 att_state
->current_layout
, target_layout
);
4603 /* Accumulate any subpass flushes that need to happen after the subpass.
4604 * Yes, they do get accumulated twice in the NextSubpass case but since
4605 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
4606 * ORing the bits in twice so it's harmless.
4608 cmd_buffer
->state
.pending_pipe_bits
|=
4609 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
4612 void genX(CmdBeginRenderPass
)(
4613 VkCommandBuffer commandBuffer
,
4614 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4615 VkSubpassContents contents
)
4617 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4618 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4619 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4621 cmd_buffer
->state
.framebuffer
= framebuffer
;
4622 cmd_buffer
->state
.pass
= pass
;
4623 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4625 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
4627 /* If we failed to setup the attachments we should not try to go further */
4628 if (result
!= VK_SUCCESS
) {
4629 assert(anv_batch_has_error(&cmd_buffer
->batch
));
4633 genX(flush_pipeline_select_3d
)(cmd_buffer
);
4635 cmd_buffer_begin_subpass(cmd_buffer
, 0);
4638 void genX(CmdBeginRenderPass2KHR
)(
4639 VkCommandBuffer commandBuffer
,
4640 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4641 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
4643 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
4644 pSubpassBeginInfo
->contents
);
4647 void genX(CmdNextSubpass
)(
4648 VkCommandBuffer commandBuffer
,
4649 VkSubpassContents contents
)
4651 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4653 if (anv_batch_has_error(&cmd_buffer
->batch
))
4656 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4658 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
4659 cmd_buffer_end_subpass(cmd_buffer
);
4660 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4663 void genX(CmdNextSubpass2KHR
)(
4664 VkCommandBuffer commandBuffer
,
4665 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
4666 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4668 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
4671 void genX(CmdEndRenderPass
)(
4672 VkCommandBuffer commandBuffer
)
4674 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4676 if (anv_batch_has_error(&cmd_buffer
->batch
))
4679 cmd_buffer_end_subpass(cmd_buffer
);
4681 cmd_buffer
->state
.hiz_enabled
= false;
4684 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
4687 /* Remove references to render pass specific state. This enables us to
4688 * detect whether or not we're in a renderpass.
4690 cmd_buffer
->state
.framebuffer
= NULL
;
4691 cmd_buffer
->state
.pass
= NULL
;
4692 cmd_buffer
->state
.subpass
= NULL
;
4695 void genX(CmdEndRenderPass2KHR
)(
4696 VkCommandBuffer commandBuffer
,
4697 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4699 genX(CmdEndRenderPass
)(commandBuffer
);
4703 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
4705 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4706 struct gen_mi_builder b
;
4707 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4709 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
4710 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
4711 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
4713 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
4714 mip
.LoadOperation
= LOAD_LOADINV
;
4715 mip
.CombineOperation
= COMBINE_SET
;
4716 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4721 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4722 void genX(CmdBeginConditionalRenderingEXT
)(
4723 VkCommandBuffer commandBuffer
,
4724 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
4726 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4727 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
4728 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4729 struct anv_address value_address
=
4730 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
4732 const bool isInverted
= pConditionalRenderingBegin
->flags
&
4733 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
4735 cmd_state
->conditional_render_enabled
= true;
4737 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4739 struct gen_mi_builder b
;
4740 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4742 /* Section 19.4 of the Vulkan 1.1.85 spec says:
4744 * If the value of the predicate in buffer memory changes
4745 * while conditional rendering is active, the rendering commands
4746 * may be discarded in an implementation-dependent way.
4747 * Some implementations may latch the value of the predicate
4748 * upon beginning conditional rendering while others
4749 * may read it before every rendering command.
4751 * So it's perfectly fine to read a value from the buffer once.
4753 struct gen_mi_value value
= gen_mi_mem32(value_address
);
4755 /* Precompute predicate result, it is necessary to support secondary
4756 * command buffers since it is unknown if conditional rendering is
4757 * inverted when populating them.
4759 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
4760 isInverted
? gen_mi_uge(&b
, gen_mi_imm(0), value
) :
4761 gen_mi_ult(&b
, gen_mi_imm(0), value
));
4764 void genX(CmdEndConditionalRenderingEXT
)(
4765 VkCommandBuffer commandBuffer
)
4767 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4768 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4770 cmd_state
->conditional_render_enabled
= false;
4774 /* Set of stage bits for which are pipelined, i.e. they get queued by the
4775 * command streamer for later execution.
4777 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
4778 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
4779 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
4780 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
4781 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
4782 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
4783 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
4784 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
4785 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
4786 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
4787 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
4788 VK_PIPELINE_STAGE_TRANSFER_BIT | \
4789 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
4790 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
4791 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
4793 void genX(CmdSetEvent
)(
4794 VkCommandBuffer commandBuffer
,
4796 VkPipelineStageFlags stageMask
)
4798 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4799 ANV_FROM_HANDLE(anv_event
, event
, _event
);
4801 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4802 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
4803 pc
.StallAtPixelScoreboard
= true;
4804 pc
.CommandStreamerStallEnable
= true;
4807 pc
.DestinationAddressType
= DAT_PPGTT
,
4808 pc
.PostSyncOperation
= WriteImmediateData
,
4809 pc
.Address
= (struct anv_address
) {
4810 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4813 pc
.ImmediateData
= VK_EVENT_SET
;
4817 void genX(CmdResetEvent
)(
4818 VkCommandBuffer commandBuffer
,
4820 VkPipelineStageFlags stageMask
)
4822 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4823 ANV_FROM_HANDLE(anv_event
, event
, _event
);
4825 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4826 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
4827 pc
.StallAtPixelScoreboard
= true;
4828 pc
.CommandStreamerStallEnable
= true;
4831 pc
.DestinationAddressType
= DAT_PPGTT
;
4832 pc
.PostSyncOperation
= WriteImmediateData
;
4833 pc
.Address
= (struct anv_address
) {
4834 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4837 pc
.ImmediateData
= VK_EVENT_RESET
;
4841 void genX(CmdWaitEvents
)(
4842 VkCommandBuffer commandBuffer
,
4843 uint32_t eventCount
,
4844 const VkEvent
* pEvents
,
4845 VkPipelineStageFlags srcStageMask
,
4846 VkPipelineStageFlags destStageMask
,
4847 uint32_t memoryBarrierCount
,
4848 const VkMemoryBarrier
* pMemoryBarriers
,
4849 uint32_t bufferMemoryBarrierCount
,
4850 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
4851 uint32_t imageMemoryBarrierCount
,
4852 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
4855 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4857 for (uint32_t i
= 0; i
< eventCount
; i
++) {
4858 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
4860 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
4861 sem
.WaitMode
= PollingMode
,
4862 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
4863 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
4864 sem
.SemaphoreAddress
= (struct anv_address
) {
4865 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4871 anv_finishme("Implement events on gen7");
4874 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
4875 false, /* byRegion */
4876 memoryBarrierCount
, pMemoryBarriers
,
4877 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
4878 imageMemoryBarrierCount
, pImageMemoryBarriers
);