2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
31 #include "common/gen_l3_config.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
36 emit_lrm(struct anv_batch
*batch
, uint32_t reg
, struct anv_address addr
)
38 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
39 lrm
.RegisterAddress
= reg
;
40 lrm
.MemoryAddress
= addr
;
45 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
47 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
48 lri
.RegisterOffset
= reg
;
53 #if GEN_IS_HASWELL || GEN_GEN >= 8
55 emit_lrr(struct anv_batch
*batch
, uint32_t dst
, uint32_t src
)
57 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
58 lrr
.SourceRegisterAddress
= src
;
59 lrr
.DestinationRegisterAddress
= dst
;
65 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
67 struct anv_device
*device
= cmd_buffer
->device
;
69 /* If we are emitting a new state base address we probably need to re-emit
72 cmd_buffer
->state
.descriptors_dirty
|= ~0;
74 /* Emit a render target cache flush.
76 * This isn't documented anywhere in the PRM. However, it seems to be
77 * necessary prior to changing the surface state base adress. Without
78 * this, we get GPU hangs when using multi-level command buffers which
79 * clear depth, reset state base address, and then go render stuff.
81 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
82 pc
.DCFlushEnable
= true;
83 pc
.RenderTargetCacheFlushEnable
= true;
84 pc
.CommandStreamerStallEnable
= true;
87 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
88 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
89 sba
.GeneralStateMOCS
= GENX(MOCS
);
90 sba
.GeneralStateBaseAddressModifyEnable
= true;
92 sba
.SurfaceStateBaseAddress
=
93 anv_cmd_buffer_surface_base_address(cmd_buffer
);
94 sba
.SurfaceStateMOCS
= GENX(MOCS
);
95 sba
.SurfaceStateBaseAddressModifyEnable
= true;
97 sba
.DynamicStateBaseAddress
=
98 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
99 sba
.DynamicStateMOCS
= GENX(MOCS
);
100 sba
.DynamicStateBaseAddressModifyEnable
= true;
102 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
103 sba
.IndirectObjectMOCS
= GENX(MOCS
);
104 sba
.IndirectObjectBaseAddressModifyEnable
= true;
106 sba
.InstructionBaseAddress
=
107 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
108 sba
.InstructionMOCS
= GENX(MOCS
);
109 sba
.InstructionBaseAddressModifyEnable
= true;
112 /* Broadwell requires that we specify a buffer size for a bunch of
113 * these fields. However, since we will be growing the BO's live, we
114 * just set them all to the maximum.
116 sba
.GeneralStateBufferSize
= 0xfffff;
117 sba
.GeneralStateBufferSizeModifyEnable
= true;
118 sba
.DynamicStateBufferSize
= 0xfffff;
119 sba
.DynamicStateBufferSizeModifyEnable
= true;
120 sba
.IndirectObjectBufferSize
= 0xfffff;
121 sba
.IndirectObjectBufferSizeModifyEnable
= true;
122 sba
.InstructionBufferSize
= 0xfffff;
123 sba
.InstructionBuffersizeModifyEnable
= true;
126 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
127 sba
.BindlessSurfaceStateMOCS
= GENX(MOCS
);
128 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
129 sba
.BindlessSurfaceStateSize
= 0;
132 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
133 sba
.BindlessSamplerStateMOCS
= GENX(MOCS
);
134 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
135 sba
.BindlessSamplerStateBufferSize
= 0;
139 /* After re-setting the surface state base address, we have to do some
140 * cache flusing so that the sampler engine will pick up the new
141 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
142 * Shared Function > 3D Sampler > State > State Caching (page 96):
144 * Coherency with system memory in the state cache, like the texture
145 * cache is handled partially by software. It is expected that the
146 * command stream or shader will issue Cache Flush operation or
147 * Cache_Flush sampler message to ensure that the L1 cache remains
148 * coherent with system memory.
152 * Whenever the value of the Dynamic_State_Base_Addr,
153 * Surface_State_Base_Addr are altered, the L1 state cache must be
154 * invalidated to ensure the new surface or sampler state is fetched
155 * from system memory.
157 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
158 * which, according the PIPE_CONTROL instruction documentation in the
161 * Setting this bit is independent of any other bit in this packet.
162 * This bit controls the invalidation of the L1 and L2 state caches
163 * at the top of the pipe i.e. at the parsing time.
165 * Unfortunately, experimentation seems to indicate that state cache
166 * invalidation through a PIPE_CONTROL does nothing whatsoever in
167 * regards to surface state and binding tables. In stead, it seems that
168 * invalidating the texture cache is what is actually needed.
170 * XXX: As far as we have been able to determine through
171 * experimentation, shows that flush the texture cache appears to be
172 * sufficient. The theory here is that all of the sampling/rendering
173 * units cache the binding table in the texture cache. However, we have
174 * yet to be able to actually confirm this.
176 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
177 pc
.TextureCacheInvalidationEnable
= true;
178 pc
.ConstantCacheInvalidationEnable
= true;
179 pc
.StateCacheInvalidationEnable
= true;
184 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
185 struct anv_state state
, struct anv_address addr
)
187 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
190 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
191 state
.offset
+ isl_dev
->ss
.addr_offset
,
192 addr
.bo
, addr
.offset
);
193 if (result
!= VK_SUCCESS
)
194 anv_batch_set_error(&cmd_buffer
->batch
, result
);
198 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
199 struct anv_surface_state state
)
201 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
203 assert(!anv_address_is_null(state
.address
));
204 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
206 if (!anv_address_is_null(state
.aux_address
)) {
208 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
209 &cmd_buffer
->pool
->alloc
,
210 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
211 state
.aux_address
.bo
, state
.aux_address
.offset
);
212 if (result
!= VK_SUCCESS
)
213 anv_batch_set_error(&cmd_buffer
->batch
, result
);
216 if (!anv_address_is_null(state
.clear_address
)) {
218 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
219 &cmd_buffer
->pool
->alloc
,
221 isl_dev
->ss
.clear_color_state_offset
,
222 state
.clear_address
.bo
, state
.clear_address
.offset
);
223 if (result
!= VK_SUCCESS
)
224 anv_batch_set_error(&cmd_buffer
->batch
, result
);
229 color_attachment_compute_aux_usage(struct anv_device
* device
,
230 struct anv_cmd_state
* cmd_state
,
231 uint32_t att
, VkRect2D render_area
,
232 union isl_color_value
*fast_clear_color
)
234 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
235 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
237 assert(iview
->n_planes
== 1);
239 if (iview
->planes
[0].isl
.base_array_layer
>=
240 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
241 iview
->planes
[0].isl
.base_level
)) {
242 /* There is no aux buffer which corresponds to the level and layer(s)
245 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
246 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
247 att_state
->fast_clear
= false;
251 att_state
->aux_usage
=
252 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
253 VK_IMAGE_ASPECT_COLOR_BIT
,
254 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
256 /* If we don't have aux, then we should have returned early in the layer
257 * check above. If we got here, we must have something.
259 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
261 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
262 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
263 att_state
->input_aux_usage
= att_state
->aux_usage
;
265 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
267 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
268 * setting is only allowed if Surface Format supported for Fast
269 * Clear. In addition, if the surface is bound to the sampling
270 * engine, Surface Format must be supported for Render Target
271 * Compression for surfaces bound to the sampling engine."
273 * In other words, we can only sample from a fast-cleared image if it
274 * also supports color compression.
276 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
277 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
279 /* While fast-clear resolves and partial resolves are fairly cheap in the
280 * case where you render to most of the pixels, full resolves are not
281 * because they potentially involve reading and writing the entire
282 * framebuffer. If we can't texture with CCS_E, we should leave it off and
283 * limit ourselves to fast clears.
285 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
286 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
287 anv_perf_warn(device
->instance
, iview
->image
,
288 "Not temporarily enabling CCS_E.");
291 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
295 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
296 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
298 union isl_color_value clear_color
= {};
299 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
301 att_state
->clear_color_is_zero_one
=
302 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
303 att_state
->clear_color_is_zero
=
304 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
306 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
307 /* Start by getting the fast clear type. We use the first subpass
308 * layout here because we don't want to fast-clear if the first subpass
309 * to use the attachment can't handle fast-clears.
311 enum anv_fast_clear_type fast_clear_type
=
312 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
313 VK_IMAGE_ASPECT_COLOR_BIT
,
314 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
315 switch (fast_clear_type
) {
316 case ANV_FAST_CLEAR_NONE
:
317 att_state
->fast_clear
= false;
319 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
320 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
322 case ANV_FAST_CLEAR_ANY
:
323 att_state
->fast_clear
= true;
327 /* Potentially, we could do partial fast-clears but doing so has crazy
328 * alignment restrictions. It's easier to just restrict to full size
329 * fast clears for now.
331 if (render_area
.offset
.x
!= 0 ||
332 render_area
.offset
.y
!= 0 ||
333 render_area
.extent
.width
!= iview
->extent
.width
||
334 render_area
.extent
.height
!= iview
->extent
.height
)
335 att_state
->fast_clear
= false;
337 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
338 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
339 att_state
->fast_clear
= false;
341 /* We only allow fast clears to the first slice of an image (level 0,
342 * layer 0) and only for the entire slice. This guarantees us that, at
343 * any given time, there is only one clear color on any given image at
344 * any given time. At the time of our testing (Jan 17, 2018), there
345 * were no known applications which would benefit from fast-clearing
346 * more than just the first slice.
348 if (att_state
->fast_clear
&&
349 (iview
->planes
[0].isl
.base_level
> 0 ||
350 iview
->planes
[0].isl
.base_array_layer
> 0)) {
351 anv_perf_warn(device
->instance
, iview
->image
,
352 "Rendering with multi-lod or multi-layer framebuffer "
353 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
354 "baseArrayLayer > 0. Not fast clearing.");
355 att_state
->fast_clear
= false;
356 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
357 anv_perf_warn(device
->instance
, iview
->image
,
358 "Rendering to a multi-layer framebuffer with "
359 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
362 if (att_state
->fast_clear
)
363 *fast_clear_color
= clear_color
;
365 att_state
->fast_clear
= false;
370 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
371 struct anv_cmd_state
*cmd_state
,
372 uint32_t att
, VkRect2D render_area
)
374 struct anv_render_pass_attachment
*pass_att
=
375 &cmd_state
->pass
->attachments
[att
];
376 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
377 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
379 /* These will be initialized after the first subpass transition. */
380 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
381 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
384 /* We don't do any HiZ or depth fast-clears on gen7 yet */
385 att_state
->fast_clear
= false;
389 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
390 /* If we're just clearing stencil, we can always HiZ clear */
391 att_state
->fast_clear
= true;
395 /* Default to false for now */
396 att_state
->fast_clear
= false;
398 /* We must have depth in order to have HiZ */
399 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
402 const enum isl_aux_usage first_subpass_aux_usage
=
403 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
404 VK_IMAGE_ASPECT_DEPTH_BIT
,
405 pass_att
->first_subpass_layout
);
406 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
409 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
410 iview
->planes
[0].isl
.format
,
411 iview
->image
->samples
,
412 render_area
.offset
.x
,
413 render_area
.offset
.y
,
414 render_area
.offset
.x
+
415 render_area
.extent
.width
,
416 render_area
.offset
.y
+
417 render_area
.extent
.height
))
420 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
423 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
424 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
425 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
426 * only supports returning 0.0f. Gens prior to gen8 do not support this
432 /* If we got here, then we can fast clear */
433 att_state
->fast_clear
= true;
437 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
439 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
442 /* We only allocate input attachment states for color surfaces. Compression
443 * is not yet enabled for depth textures and stencil doesn't allow
444 * compression so we can just use the texture surface state from the view.
446 return vk_format_is_color(att
->format
);
449 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
450 * the initial layout is undefined, the HiZ buffer and depth buffer will
451 * represent the same data at the end of this operation.
454 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
455 const struct anv_image
*image
,
456 VkImageLayout initial_layout
,
457 VkImageLayout final_layout
)
459 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
460 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
461 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
462 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
463 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
464 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
466 enum isl_aux_op hiz_op
;
467 if (hiz_enabled
&& !enable_hiz
) {
468 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
469 } else if (!hiz_enabled
&& enable_hiz
) {
470 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
472 assert(hiz_enabled
== enable_hiz
);
473 /* If the same buffer will be used, no resolves are necessary. */
474 hiz_op
= ISL_AUX_OP_NONE
;
477 if (hiz_op
!= ISL_AUX_OP_NONE
)
478 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
482 #define MI_PREDICATE_SRC0 0x2400
483 #define MI_PREDICATE_SRC1 0x2408
484 #define MI_PREDICATE_RESULT 0x2418
487 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
488 const struct anv_image
*image
,
489 VkImageAspectFlagBits aspect
,
491 uint32_t base_layer
, uint32_t layer_count
,
494 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
496 /* We only have compression tracking for CCS_E */
497 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
500 for (uint32_t a
= 0; a
< layer_count
; a
++) {
501 uint32_t layer
= base_layer
+ a
;
502 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
503 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
506 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
512 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
513 const struct anv_image
*image
,
514 VkImageAspectFlagBits aspect
,
515 enum anv_fast_clear_type fast_clear
)
517 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
518 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
520 sdi
.ImmediateData
= fast_clear
;
523 /* Whenever we have fast-clear, we consider that slice to be compressed.
524 * This makes building predicates much easier.
526 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
527 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
530 #if GEN_IS_HASWELL || GEN_GEN >= 8
531 static inline uint32_t
532 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
534 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
536 .Operand1
= operand1
,
537 .Operand2
= operand2
,
541 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
547 #define CS_GPR(n) (0x2600 + (n) * 8)
549 /* This is only really practical on haswell and above because it requires
550 * MI math in order to get it correct.
552 #if GEN_GEN >= 8 || GEN_IS_HASWELL
554 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
555 const struct anv_image
*image
,
556 VkImageAspectFlagBits aspect
,
557 uint32_t level
, uint32_t array_layer
,
558 enum isl_aux_op resolve_op
,
559 enum anv_fast_clear_type fast_clear_supported
)
561 struct anv_address fast_clear_type_addr
=
562 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
564 /* Name some registers */
565 const int image_fc_reg
= MI_ALU_REG0
;
566 const int fc_imm_reg
= MI_ALU_REG1
;
567 const int pred_reg
= MI_ALU_REG2
;
571 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
572 /* In this case, we're doing a full resolve which means we want the
573 * resolve to happen if any compression (including fast-clears) is
576 * In order to simplify the logic a bit, we make the assumption that,
577 * if the first slice has been fast-cleared, it is also marked as
578 * compressed. See also set_image_fast_clear_state.
580 struct anv_address compression_state_addr
=
581 anv_image_get_compression_state_addr(cmd_buffer
->device
, image
,
582 aspect
, level
, array_layer
);
583 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
584 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
585 lrm
.MemoryAddress
= compression_state_addr
;
587 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
588 sdi
.Address
= compression_state_addr
;
589 sdi
.ImmediateData
= 0;
592 if (level
== 0 && array_layer
== 0) {
593 /* If the predicate is true, we want to write 0 to the fast clear type
594 * and, if it's false, leave it alone. We can do this by writing
596 * clear_type = clear_type & ~predicate;
598 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
599 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
600 lrm
.MemoryAddress
= fast_clear_type_addr
;
602 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
603 lrr
.DestinationRegisterAddress
= CS_GPR(pred_reg
);
604 lrr
.SourceRegisterAddress
= MI_PREDICATE_SRC0
;
607 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
608 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
609 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
610 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
611 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
613 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
614 srm
.MemoryAddress
= fast_clear_type_addr
;
615 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
618 } else if (level
== 0 && array_layer
== 0) {
619 /* In this case, we are doing a partial resolve to get rid of fast-clear
620 * colors. We don't care about the compression state but we do care
621 * about how much fast clear is allowed by the final layout.
623 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
624 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
626 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
627 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
628 lrm
.MemoryAddress
= fast_clear_type_addr
;
630 emit_lri(&cmd_buffer
->batch
, CS_GPR(image_fc_reg
) + 4, 0);
632 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
), fast_clear_supported
);
633 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
) + 4, 0);
635 /* We need to compute (fast_clear_supported < image->fast_clear).
636 * We do this by subtracting and storing the carry bit.
638 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
639 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, fc_imm_reg
);
640 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, image_fc_reg
);
641 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
642 dw
[4] = mi_alu(MI_ALU_STORE
, pred_reg
, MI_ALU_CF
);
644 /* Store the predicate */
645 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(pred_reg
));
647 /* If the predicate is true, we want to write 0 to the fast clear type
648 * and, if it's false, leave it alone. We can do this by writing
650 * clear_type = clear_type & ~predicate;
652 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
653 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
654 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
655 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
656 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
658 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
659 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
660 srm
.MemoryAddress
= fast_clear_type_addr
;
663 /* In this case, we're trying to do a partial resolve on a slice that
664 * doesn't have clear color. There's nothing to do.
666 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
670 /* We use the first half of src0 for the actual predicate. Set the second
671 * half of src0 and all of src1 to 0 as the predicate operation will be
672 * doing an implicit src0 != src1.
674 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
675 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
676 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
678 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
679 mip
.LoadOperation
= LOAD_LOADINV
;
680 mip
.CombineOperation
= COMBINE_SET
;
681 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
684 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
688 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
689 const struct anv_image
*image
,
690 VkImageAspectFlagBits aspect
,
691 uint32_t level
, uint32_t array_layer
,
692 enum isl_aux_op resolve_op
,
693 enum anv_fast_clear_type fast_clear_supported
)
695 struct anv_address fast_clear_type_addr
=
696 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
698 /* This only works for partial resolves and only when the clear color is
699 * all or nothing. On the upside, this emits less command streamer code
700 * and works on Ivybridge and Bay Trail.
702 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
703 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
705 /* We don't support fast clears on anything other than the first slice. */
706 if (level
> 0 || array_layer
> 0)
709 /* On gen8, we don't have a concept of default clear colors because we
710 * can't sample from CCS surfaces. It's enough to just load the fast clear
711 * state into the predicate register.
713 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
714 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
715 lrm
.MemoryAddress
= fast_clear_type_addr
;
717 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
718 sdi
.Address
= fast_clear_type_addr
;
719 sdi
.ImmediateData
= 0;
722 /* We use the first half of src0 for the actual predicate. Set the second
723 * half of src0 and all of src1 to 0 as the predicate operation will be
724 * doing an implicit src0 != src1.
726 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
727 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
728 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
730 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
731 mip
.LoadOperation
= LOAD_LOADINV
;
732 mip
.CombineOperation
= COMBINE_SET
;
733 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
736 #endif /* GEN_GEN <= 8 */
739 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
740 const struct anv_image
*image
,
741 enum isl_format format
,
742 VkImageAspectFlagBits aspect
,
743 uint32_t level
, uint32_t array_layer
,
744 enum isl_aux_op resolve_op
,
745 enum anv_fast_clear_type fast_clear_supported
)
747 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
750 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
751 aspect
, level
, array_layer
,
752 resolve_op
, fast_clear_supported
);
753 #else /* GEN_GEN <= 8 */
754 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
755 aspect
, level
, array_layer
,
756 resolve_op
, fast_clear_supported
);
759 /* CCS_D only supports full resolves and BLORP will assert on us if we try
760 * to do a partial resolve on a CCS_D surface.
762 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
763 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
764 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
766 anv_image_ccs_op(cmd_buffer
, image
, format
, aspect
, level
,
767 array_layer
, 1, resolve_op
, NULL
, true);
771 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
772 const struct anv_image
*image
,
773 enum isl_format format
,
774 VkImageAspectFlagBits aspect
,
775 uint32_t array_layer
,
776 enum isl_aux_op resolve_op
,
777 enum anv_fast_clear_type fast_clear_supported
)
779 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
780 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
782 #if GEN_GEN >= 8 || GEN_IS_HASWELL
783 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
784 aspect
, 0, array_layer
,
785 resolve_op
, fast_clear_supported
);
787 anv_image_mcs_op(cmd_buffer
, image
, format
, aspect
,
788 array_layer
, 1, resolve_op
, NULL
, true);
790 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
795 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
796 const struct anv_image
*image
,
797 VkImageAspectFlagBits aspect
,
798 enum isl_aux_usage aux_usage
,
801 uint32_t layer_count
)
803 /* The aspect must be exactly one of the image aspects. */
804 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
806 /* The only compression types with more than just fast-clears are MCS,
807 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
808 * track the current fast-clear and compression state. This leaves us
809 * with just MCS and CCS_E.
811 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
812 aux_usage
!= ISL_AUX_USAGE_MCS
)
815 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
816 level
, base_layer
, layer_count
, true);
820 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
821 const struct anv_image
*image
,
822 VkImageAspectFlagBits aspect
)
824 assert(cmd_buffer
&& image
);
825 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
827 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
828 ANV_FAST_CLEAR_NONE
);
830 /* The fast clear value dword(s) will be copied into a surface state object.
831 * Ensure that the restrictions of the fields in the dword(s) are followed.
833 * CCS buffers on SKL+ can have any value set for the clear colors.
835 if (image
->samples
== 1 && GEN_GEN
>= 9)
838 /* Other combinations of auxiliary buffers and platforms require specific
839 * values in the clear value dword(s).
841 struct anv_address addr
=
842 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
845 for (unsigned i
= 0; i
< 4; i
++) {
846 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
848 sdi
.Address
.offset
+= i
* 4;
849 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
850 assert(image
->samples
> 1);
851 sdi
.ImmediateData
= 0;
855 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
857 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
858 /* Pre-SKL, the dword containing the clear values also contains
859 * other fields, so we need to initialize those fields to match the
860 * values that would be in a color attachment.
862 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
863 ISL_CHANNEL_SELECT_GREEN
<< 22 |
864 ISL_CHANNEL_SELECT_BLUE
<< 19 |
865 ISL_CHANNEL_SELECT_ALPHA
<< 16;
866 } else if (GEN_GEN
== 7) {
867 /* On IVB, the dword containing the clear values also contains
868 * other fields that must be zero or can be zero.
870 sdi
.ImmediateData
= 0;
876 /* Copy the fast-clear value dword(s) between a surface state object and an
877 * image's fast clear state buffer.
880 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
881 struct anv_state surface_state
,
882 const struct anv_image
*image
,
883 VkImageAspectFlagBits aspect
,
884 bool copy_from_surface_state
)
886 assert(cmd_buffer
&& image
);
887 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
889 struct anv_address ss_clear_addr
= {
890 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
891 .offset
= surface_state
.offset
+
892 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
894 const struct anv_address entry_addr
=
895 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
896 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
898 if (copy_from_surface_state
) {
899 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, entry_addr
,
900 ss_clear_addr
, copy_size
);
902 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, ss_clear_addr
,
903 entry_addr
, copy_size
);
905 /* Updating a surface state object may require that the state cache be
906 * invalidated. From the SKL PRM, Shared Functions -> State -> State
909 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
910 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
911 * modified [...], the L1 state cache must be invalidated to ensure
912 * the new surface or sampler state is fetched from system memory.
914 * In testing, SKL doesn't actually seem to need this, but HSW does.
916 cmd_buffer
->state
.pending_pipe_bits
|=
917 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
922 * @brief Transitions a color buffer from one layout to another.
924 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
927 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
928 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
929 * this represents the maximum layers to transition at each
930 * specified miplevel.
933 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
934 const struct anv_image
*image
,
935 VkImageAspectFlagBits aspect
,
936 const uint32_t base_level
, uint32_t level_count
,
937 uint32_t base_layer
, uint32_t layer_count
,
938 VkImageLayout initial_layout
,
939 VkImageLayout final_layout
)
941 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
942 /* Validate the inputs. */
944 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
945 /* These values aren't supported for simplicity's sake. */
946 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
947 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
948 /* Ensure the subresource range is valid. */
949 uint64_t last_level_num
= base_level
+ level_count
;
950 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
951 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
952 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
953 assert(last_level_num
<= image
->levels
);
954 /* The spec disallows these final layouts. */
955 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
956 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
958 /* No work is necessary if the layout stays the same or if this subresource
959 * range lacks auxiliary data.
961 if (initial_layout
== final_layout
)
964 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
966 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
967 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
968 /* This surface is a linear compressed image with a tiled shadow surface
969 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
970 * we need to ensure the shadow copy is up-to-date.
972 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
973 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
974 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
975 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
977 anv_image_copy_to_shadow(cmd_buffer
, image
,
978 base_level
, level_count
,
979 base_layer
, layer_count
);
982 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
985 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
987 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
988 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
989 /* A subresource in the undefined layout may have been aliased and
990 * populated with any arrangement of bits. Therefore, we must initialize
991 * the related aux buffer and clear buffer entry with desirable values.
992 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
993 * images with VK_IMAGE_TILING_OPTIMAL.
995 * Initialize the relevant clear buffer entries.
997 if (base_level
== 0 && base_layer
== 0)
998 init_fast_clear_color(cmd_buffer
, image
, aspect
);
1000 /* Initialize the aux buffers to enable correct rendering. In order to
1001 * ensure that things such as storage images work correctly, aux buffers
1002 * need to be initialized to valid data.
1004 * Having an aux buffer with invalid data is a problem for two reasons:
1006 * 1) Having an invalid value in the buffer can confuse the hardware.
1007 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1008 * invalid and leads to the hardware doing strange things. It
1009 * doesn't hang as far as we can tell but rendering corruption can
1012 * 2) If this transition is into the GENERAL layout and we then use the
1013 * image as a storage image, then we must have the aux buffer in the
1014 * pass-through state so that, if we then go to texture from the
1015 * image, we get the results of our storage image writes and not the
1016 * fast clear color or other random data.
1018 * For CCS both of the problems above are real demonstrable issues. In
1019 * that case, the only thing we can do is to perform an ambiguate to
1020 * transition the aux surface into the pass-through state.
1022 * For MCS, (2) is never an issue because we don't support multisampled
1023 * storage images. In theory, issue (1) is a problem with MCS but we've
1024 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1025 * theory, be interpreted as something but we don't know that all bit
1026 * patterns are actually valid. For 2x and 8x, you could easily end up
1027 * with the MCS referring to an invalid plane because not all bits of
1028 * the MCS value are actually used. Even though we've never seen issues
1029 * in the wild, it's best to play it safe and initialize the MCS. We
1030 * can use a fast-clear for MCS because we only ever touch from render
1031 * and texture (no image load store).
1033 if (image
->samples
== 1) {
1034 for (uint32_t l
= 0; l
< level_count
; l
++) {
1035 const uint32_t level
= base_level
+ l
;
1037 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1038 if (base_layer
>= aux_layers
)
1039 break; /* We will only get fewer layers as level increases */
1040 uint32_t level_layer_count
=
1041 MIN2(layer_count
, aux_layers
- base_layer
);
1043 anv_image_ccs_op(cmd_buffer
, image
,
1044 image
->planes
[plane
].surface
.isl
.format
,
1045 aspect
, level
, base_layer
, level_layer_count
,
1046 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1048 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1049 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1050 level
, base_layer
, level_layer_count
,
1055 if (image
->samples
== 4 || image
->samples
== 16) {
1056 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1057 "Doing a potentially unnecessary fast-clear to "
1058 "define an MCS buffer.");
1061 assert(base_level
== 0 && level_count
== 1);
1062 anv_image_mcs_op(cmd_buffer
, image
,
1063 image
->planes
[plane
].surface
.isl
.format
,
1064 aspect
, base_layer
, layer_count
,
1065 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1070 const enum isl_aux_usage initial_aux_usage
=
1071 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1072 const enum isl_aux_usage final_aux_usage
=
1073 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1075 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1076 * We can handle transitions between CCS_D/E to and from NONE. What we
1077 * don't yet handle is switching between CCS_E and CCS_D within a given
1078 * image. Doing so in a performant way requires more detailed aux state
1079 * tracking such as what is done in i965. For now, just assume that we
1080 * only have one type of compression.
1082 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1083 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1084 initial_aux_usage
== final_aux_usage
);
1086 /* If initial aux usage is NONE, there is nothing to resolve */
1087 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1090 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1092 /* If the initial layout supports more fast clear than the final layout
1093 * then we need at least a partial resolve.
1095 const enum anv_fast_clear_type initial_fast_clear
=
1096 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1097 const enum anv_fast_clear_type final_fast_clear
=
1098 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1099 if (final_fast_clear
< initial_fast_clear
)
1100 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1102 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1103 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1104 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1106 if (resolve_op
== ISL_AUX_OP_NONE
)
1109 /* Perform a resolve to synchronize data between the main and aux buffer.
1110 * Before we begin, we must satisfy the cache flushing requirement specified
1111 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1113 * Any transition from any value in {Clear, Render, Resolve} to a
1114 * different value in {Clear, Render, Resolve} requires end of pipe
1117 * We perform a flush of the write cache before and after the clear and
1118 * resolve operations to meet this requirement.
1120 * Unlike other drawing, fast clear operations are not properly
1121 * synchronized. The first PIPE_CONTROL here likely ensures that the
1122 * contents of the previous render or clear hit the render target before we
1123 * resolve and the second likely ensures that the resolve is complete before
1124 * we do any more rendering or clearing.
1126 cmd_buffer
->state
.pending_pipe_bits
|=
1127 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1129 for (uint32_t l
= 0; l
< level_count
; l
++) {
1130 uint32_t level
= base_level
+ l
;
1132 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1133 if (base_layer
>= aux_layers
)
1134 break; /* We will only get fewer layers as level increases */
1135 uint32_t level_layer_count
=
1136 MIN2(layer_count
, aux_layers
- base_layer
);
1138 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1139 uint32_t array_layer
= base_layer
+ a
;
1140 if (image
->samples
== 1) {
1141 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1142 image
->planes
[plane
].surface
.isl
.format
,
1143 aspect
, level
, array_layer
, resolve_op
,
1146 /* We only support fast-clear on the first layer so partial
1147 * resolves should not be used on other layers as they will use
1148 * the clear color stored in memory that is only valid for layer0.
1150 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1154 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1155 image
->planes
[plane
].surface
.isl
.format
,
1156 aspect
, array_layer
, resolve_op
,
1162 cmd_buffer
->state
.pending_pipe_bits
|=
1163 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1167 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1170 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1171 struct anv_render_pass
*pass
,
1172 const VkRenderPassBeginInfo
*begin
)
1174 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1175 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1177 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1179 if (pass
->attachment_count
> 0) {
1180 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1181 pass
->attachment_count
*
1182 sizeof(state
->attachments
[0]),
1183 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1184 if (state
->attachments
== NULL
) {
1185 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1186 return anv_batch_set_error(&cmd_buffer
->batch
,
1187 VK_ERROR_OUT_OF_HOST_MEMORY
);
1190 state
->attachments
= NULL
;
1193 /* Reserve one for the NULL state. */
1194 unsigned num_states
= 1;
1195 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1196 if (vk_format_is_color(pass
->attachments
[i
].format
))
1199 if (need_input_attachment_state(&pass
->attachments
[i
]))
1203 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1204 state
->render_pass_states
=
1205 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1206 num_states
* ss_stride
, isl_dev
->ss
.align
);
1208 struct anv_state next_state
= state
->render_pass_states
;
1209 next_state
.alloc_size
= isl_dev
->ss
.size
;
1211 state
->null_surface_state
= next_state
;
1212 next_state
.offset
+= ss_stride
;
1213 next_state
.map
+= ss_stride
;
1215 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1216 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1217 state
->attachments
[i
].color
.state
= next_state
;
1218 next_state
.offset
+= ss_stride
;
1219 next_state
.map
+= ss_stride
;
1222 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1223 state
->attachments
[i
].input
.state
= next_state
;
1224 next_state
.offset
+= ss_stride
;
1225 next_state
.map
+= ss_stride
;
1228 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1229 state
->render_pass_states
.alloc_size
);
1232 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1233 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1235 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1236 isl_extent3d(framebuffer
->width
,
1237 framebuffer
->height
,
1238 framebuffer
->layers
));
1240 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1241 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1242 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1243 VkImageAspectFlags clear_aspects
= 0;
1244 VkImageAspectFlags load_aspects
= 0;
1246 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1247 /* color attachment */
1248 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1249 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1250 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1251 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1254 /* depthstencil attachment */
1255 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1256 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1257 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1258 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1259 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1262 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1263 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1264 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1265 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1266 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1271 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1272 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1273 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1275 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1277 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1278 anv_assert(iview
->vk_format
== att
->format
);
1280 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1281 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1283 union isl_color_value clear_color
= { .u32
= { 0, } };
1284 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1285 anv_assert(iview
->n_planes
== 1);
1286 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1287 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1288 state
, i
, begin
->renderArea
,
1291 anv_image_fill_surface_state(cmd_buffer
->device
,
1293 VK_IMAGE_ASPECT_COLOR_BIT
,
1294 &iview
->planes
[0].isl
,
1295 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1296 state
->attachments
[i
].aux_usage
,
1299 &state
->attachments
[i
].color
,
1302 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1304 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1309 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1310 anv_image_fill_surface_state(cmd_buffer
->device
,
1312 VK_IMAGE_ASPECT_COLOR_BIT
,
1313 &iview
->planes
[0].isl
,
1314 ISL_SURF_USAGE_TEXTURE_BIT
,
1315 state
->attachments
[i
].input_aux_usage
,
1318 &state
->attachments
[i
].input
,
1321 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1330 genX(BeginCommandBuffer
)(
1331 VkCommandBuffer commandBuffer
,
1332 const VkCommandBufferBeginInfo
* pBeginInfo
)
1334 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1336 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1337 * command buffer's state. Otherwise, we must *reset* its state. In both
1338 * cases we reset it.
1340 * From the Vulkan 1.0 spec:
1342 * If a command buffer is in the executable state and the command buffer
1343 * was allocated from a command pool with the
1344 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1345 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1346 * as if vkResetCommandBuffer had been called with
1347 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1348 * the command buffer in the recording state.
1350 anv_cmd_buffer_reset(cmd_buffer
);
1352 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1354 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1355 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1357 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1359 /* We sometimes store vertex data in the dynamic state buffer for blorp
1360 * operations and our dynamic state stream may re-use data from previous
1361 * command buffers. In order to prevent stale cache data, we flush the VF
1362 * cache. We could do this on every blorp call but that's not really
1363 * needed as all of the data will get written by the CPU prior to the GPU
1364 * executing anything. The chances are fairly high that they will use
1365 * blorp at least once per primary command buffer so it shouldn't be
1368 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1369 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1371 /* We send an "Indirect State Pointers Disable" packet at
1372 * EndCommandBuffer, so all push contant packets are ignored during a
1373 * context restore. Documentation says after that command, we need to
1374 * emit push constants again before any rendering operation. So we
1375 * flag them dirty here to make sure they get emitted.
1377 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1379 VkResult result
= VK_SUCCESS
;
1380 if (cmd_buffer
->usage_flags
&
1381 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1382 assert(pBeginInfo
->pInheritanceInfo
);
1383 cmd_buffer
->state
.pass
=
1384 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1385 cmd_buffer
->state
.subpass
=
1386 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1388 /* This is optional in the inheritance info. */
1389 cmd_buffer
->state
.framebuffer
=
1390 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1392 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1393 cmd_buffer
->state
.pass
, NULL
);
1395 /* Record that HiZ is enabled if we can. */
1396 if (cmd_buffer
->state
.framebuffer
) {
1397 const struct anv_image_view
* const iview
=
1398 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1401 VkImageLayout layout
=
1402 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1404 enum isl_aux_usage aux_usage
=
1405 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1406 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1408 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1412 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1415 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1416 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1417 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1418 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1420 /* If secondary buffer supports conditional rendering
1421 * we should emit commands as if conditional rendering is enabled.
1423 cmd_buffer
->state
.conditional_render_enabled
=
1424 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1431 /* From the PRM, Volume 2a:
1433 * "Indirect State Pointers Disable
1435 * At the completion of the post-sync operation associated with this pipe
1436 * control packet, the indirect state pointers in the hardware are
1437 * considered invalid; the indirect pointers are not saved in the context.
1438 * If any new indirect state commands are executed in the command stream
1439 * while the pipe control is pending, the new indirect state commands are
1442 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1443 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1444 * commands are only considered as Indirect State Pointers. Once ISP is
1445 * issued in a context, SW must initialize by programming push constant
1446 * commands for all the shaders (at least to zero length) before attempting
1447 * any rendering operation for the same context."
1449 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1450 * even though they point to a BO that has been already unreferenced at
1451 * the end of the previous batch buffer. This has been fine so far since
1452 * we are protected by these scratch page (every address not covered by
1453 * a BO should be pointing to the scratch page). But on CNL, it is
1454 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1457 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1458 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1459 * context restore, so the mentioned hang doesn't happen. However,
1460 * software must program push constant commands for all stages prior to
1461 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1463 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1464 * constants have been loaded into the EUs prior to disable the push constants
1465 * so that it doesn't hang a previous 3DPRIMITIVE.
1468 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1470 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1471 pc
.StallAtPixelScoreboard
= true;
1472 pc
.CommandStreamerStallEnable
= true;
1474 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1475 pc
.IndirectStatePointersDisable
= true;
1476 pc
.CommandStreamerStallEnable
= true;
1481 genX(EndCommandBuffer
)(
1482 VkCommandBuffer commandBuffer
)
1484 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1486 if (anv_batch_has_error(&cmd_buffer
->batch
))
1487 return cmd_buffer
->batch
.status
;
1489 /* We want every command buffer to start with the PMA fix in a known state,
1490 * so we disable it at the end of the command buffer.
1492 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1494 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1496 emit_isp_disable(cmd_buffer
);
1498 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1504 genX(CmdExecuteCommands
)(
1505 VkCommandBuffer commandBuffer
,
1506 uint32_t commandBufferCount
,
1507 const VkCommandBuffer
* pCmdBuffers
)
1509 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1511 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1513 if (anv_batch_has_error(&primary
->batch
))
1516 /* The secondary command buffers will assume that the PMA fix is disabled
1517 * when they begin executing. Make sure this is true.
1519 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1521 /* The secondary command buffer doesn't know which textures etc. have been
1522 * flushed prior to their execution. Apply those flushes now.
1524 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1526 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1527 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1529 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1530 assert(!anv_batch_has_error(&secondary
->batch
));
1532 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1533 if (secondary
->state
.conditional_render_enabled
) {
1534 if (!primary
->state
.conditional_render_enabled
) {
1535 /* Secondary buffer is constructed as if it will be executed
1536 * with conditional rendering, we should satisfy this dependency
1537 * regardless of conditional rendering being enabled in primary.
1539 emit_lri(&primary
->batch
, CS_GPR(ANV_PREDICATE_RESULT_REG
), UINT32_MAX
);
1540 emit_lri(&primary
->batch
, CS_GPR(ANV_PREDICATE_RESULT_REG
) + 4, UINT32_MAX
);
1545 if (secondary
->usage_flags
&
1546 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1547 /* If we're continuing a render pass from the primary, we need to
1548 * copy the surface states for the current subpass into the storage
1549 * we allocated for them in BeginCommandBuffer.
1551 struct anv_bo
*ss_bo
=
1552 primary
->device
->surface_state_pool
.block_pool
.bo
;
1553 struct anv_state src_state
= primary
->state
.render_pass_states
;
1554 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1555 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1557 genX(cmd_buffer_so_memcpy
)(primary
,
1558 (struct anv_address
) {
1560 .offset
= dst_state
.offset
,
1562 (struct anv_address
) {
1564 .offset
= src_state
.offset
,
1566 src_state
.alloc_size
);
1569 anv_cmd_buffer_add_secondary(primary
, secondary
);
1572 /* The secondary may have selected a different pipeline (3D or compute) and
1573 * may have changed the current L3$ configuration. Reset our tracking
1574 * variables to invalid values to ensure that we re-emit these in the case
1575 * where we do any draws or compute dispatches from the primary after the
1576 * secondary has returned.
1578 primary
->state
.current_pipeline
= UINT32_MAX
;
1579 primary
->state
.current_l3_config
= NULL
;
1581 /* Each of the secondary command buffers will use its own state base
1582 * address. We need to re-emit state base address for the primary after
1583 * all of the secondaries are done.
1585 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1588 genX(cmd_buffer_emit_state_base_address
)(primary
);
1591 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1592 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1593 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1596 * Program the hardware to use the specified L3 configuration.
1599 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1600 const struct gen_l3_config
*cfg
)
1603 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1606 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1607 intel_logd("L3 config transition: ");
1608 gen_dump_l3_config(cfg
, stderr
);
1611 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1613 /* According to the hardware docs, the L3 partitioning can only be changed
1614 * while the pipeline is completely drained and the caches are flushed,
1615 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1617 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1618 pc
.DCFlushEnable
= true;
1619 pc
.PostSyncOperation
= NoWrite
;
1620 pc
.CommandStreamerStallEnable
= true;
1623 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1624 * invalidation of the relevant caches. Note that because RO invalidation
1625 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1626 * command is processed by the CS) we cannot combine it with the previous
1627 * stalling flush as the hardware documentation suggests, because that
1628 * would cause the CS to stall on previous rendering *after* RO
1629 * invalidation and wouldn't prevent the RO caches from being polluted by
1630 * concurrent rendering before the stall completes. This intentionally
1631 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1632 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1633 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1634 * already guarantee that there is no concurrent GPGPU kernel execution
1635 * (see SKL HSD 2132585).
1637 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1638 pc
.TextureCacheInvalidationEnable
= true;
1639 pc
.ConstantCacheInvalidationEnable
= true;
1640 pc
.InstructionCacheInvalidateEnable
= true;
1641 pc
.StateCacheInvalidationEnable
= true;
1642 pc
.PostSyncOperation
= NoWrite
;
1645 /* Now send a third stalling flush to make sure that invalidation is
1646 * complete when the L3 configuration registers are modified.
1648 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1649 pc
.DCFlushEnable
= true;
1650 pc
.PostSyncOperation
= NoWrite
;
1651 pc
.CommandStreamerStallEnable
= true;
1656 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1659 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1660 .SLMEnable
= has_slm
,
1662 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1663 * in L3CNTLREG register. The default setting of the bit is not the
1664 * desirable behavior.
1666 .ErrorDetectionBehaviorControl
= true,
1667 .UseFullWays
= true,
1669 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1670 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1671 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1672 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1674 /* Set up the L3 partitioning. */
1675 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1679 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1680 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1681 cfg
->n
[GEN_L3P_ALL
];
1682 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1683 cfg
->n
[GEN_L3P_ALL
];
1684 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1685 cfg
->n
[GEN_L3P_ALL
];
1687 assert(!cfg
->n
[GEN_L3P_ALL
]);
1689 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1690 * the matching space on the remaining banks has to be allocated to a
1691 * client (URB for all validated configurations) set to the
1692 * lower-bandwidth 2-bank address hashing mode.
1694 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1695 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1696 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1698 /* Minimum number of ways that can be allocated to the URB. */
1699 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1700 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1702 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1703 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1704 .ConvertDC_UC
= !has_dc
,
1705 .ConvertIS_UC
= !has_is
,
1706 .ConvertC_UC
= !has_c
,
1707 .ConvertT_UC
= !has_t
);
1709 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1710 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1711 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1713 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1714 .SLMEnable
= has_slm
,
1715 .URBLowBandwidth
= urb_low_bw
,
1716 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1718 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1720 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1721 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1723 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1724 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1725 .ISLowBandwidth
= 0,
1726 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1728 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1729 .TLowBandwidth
= 0);
1731 /* Set up the L3 partitioning. */
1732 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1733 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1734 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1737 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1738 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1739 * them disabled to avoid crashing the system hard.
1741 uint32_t scratch1
, chicken3
;
1742 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1743 .L3AtomicDisable
= !has_dc
);
1744 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1745 .L3AtomicDisableMask
= true,
1746 .L3AtomicDisable
= !has_dc
);
1747 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1748 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1754 cmd_buffer
->state
.current_l3_config
= cfg
;
1758 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1760 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1762 /* Flushes are pipelined while invalidations are handled immediately.
1763 * Therefore, if we're flushing anything then we need to schedule a stall
1764 * before any invalidations can happen.
1766 if (bits
& ANV_PIPE_FLUSH_BITS
)
1767 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1769 /* If we're going to do an invalidate and we have a pending CS stall that
1770 * has yet to be resolved, we do the CS stall now.
1772 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1773 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1774 bits
|= ANV_PIPE_CS_STALL_BIT
;
1775 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1778 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1779 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1780 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1781 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1782 pipe
.RenderTargetCacheFlushEnable
=
1783 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1785 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1786 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1787 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1790 * According to the Broadwell documentation, any PIPE_CONTROL with the
1791 * "Command Streamer Stall" bit set must also have another bit set,
1792 * with five different options:
1794 * - Render Target Cache Flush
1795 * - Depth Cache Flush
1796 * - Stall at Pixel Scoreboard
1797 * - Post-Sync Operation
1801 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1802 * mesa and it seems to work fine. The choice is fairly arbitrary.
1804 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1805 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1806 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1807 pipe
.StallAtPixelScoreboard
= true;
1810 /* If a render target flush was emitted, then we can toggle off the bit
1811 * saying that render target writes are ongoing.
1813 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
1814 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
1816 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1819 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1820 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1822 * "If the VF Cache Invalidation Enable is set to a 1 in a
1823 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1824 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1825 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1828 * This appears to hang Broadwell, so we restrict it to just gen9.
1830 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1831 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1833 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1834 pipe
.StateCacheInvalidationEnable
=
1835 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1836 pipe
.ConstantCacheInvalidationEnable
=
1837 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1838 pipe
.VFCacheInvalidationEnable
=
1839 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1840 pipe
.TextureCacheInvalidationEnable
=
1841 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1842 pipe
.InstructionCacheInvalidateEnable
=
1843 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1845 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1847 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1848 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1849 * “Write Timestamp”.
1851 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1852 pipe
.PostSyncOperation
= WriteImmediateData
;
1854 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1858 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1861 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1864 void genX(CmdPipelineBarrier
)(
1865 VkCommandBuffer commandBuffer
,
1866 VkPipelineStageFlags srcStageMask
,
1867 VkPipelineStageFlags destStageMask
,
1869 uint32_t memoryBarrierCount
,
1870 const VkMemoryBarrier
* pMemoryBarriers
,
1871 uint32_t bufferMemoryBarrierCount
,
1872 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1873 uint32_t imageMemoryBarrierCount
,
1874 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1876 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1878 /* XXX: Right now, we're really dumb and just flush whatever categories
1879 * the app asks for. One of these days we may make this a bit better
1880 * but right now that's all the hardware allows for in most areas.
1882 VkAccessFlags src_flags
= 0;
1883 VkAccessFlags dst_flags
= 0;
1885 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1886 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1887 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1890 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1891 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1892 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1895 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1896 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1897 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1898 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1899 const VkImageSubresourceRange
*range
=
1900 &pImageMemoryBarriers
[i
].subresourceRange
;
1902 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1903 transition_depth_buffer(cmd_buffer
, image
,
1904 pImageMemoryBarriers
[i
].oldLayout
,
1905 pImageMemoryBarriers
[i
].newLayout
);
1906 } else if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1907 VkImageAspectFlags color_aspects
=
1908 anv_image_expand_aspects(image
, range
->aspectMask
);
1909 uint32_t aspect_bit
;
1911 uint32_t base_layer
, layer_count
;
1912 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1914 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1916 base_layer
= range
->baseArrayLayer
;
1917 layer_count
= anv_get_layerCount(image
, range
);
1920 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1921 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1922 range
->baseMipLevel
,
1923 anv_get_levelCount(image
, range
),
1924 base_layer
, layer_count
,
1925 pImageMemoryBarriers
[i
].oldLayout
,
1926 pImageMemoryBarriers
[i
].newLayout
);
1931 cmd_buffer
->state
.pending_pipe_bits
|=
1932 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1933 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1937 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1939 VkShaderStageFlags stages
=
1940 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1942 /* In order to avoid thrash, we assume that vertex and fragment stages
1943 * always exist. In the rare case where one is missing *and* the other
1944 * uses push concstants, this may be suboptimal. However, avoiding stalls
1945 * seems more important.
1947 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1949 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1953 const unsigned push_constant_kb
= 32;
1954 #elif GEN_IS_HASWELL
1955 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1957 const unsigned push_constant_kb
= 16;
1960 const unsigned num_stages
=
1961 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1962 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1964 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1965 * units of 2KB. Incidentally, these are the same platforms that have
1966 * 32KB worth of push constant space.
1968 if (push_constant_kb
== 32)
1969 size_per_stage
&= ~1u;
1971 uint32_t kb_used
= 0;
1972 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1973 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1974 anv_batch_emit(&cmd_buffer
->batch
,
1975 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1976 alloc
._3DCommandSubOpcode
= 18 + i
;
1977 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1978 alloc
.ConstantBufferSize
= push_size
;
1980 kb_used
+= push_size
;
1983 anv_batch_emit(&cmd_buffer
->batch
,
1984 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1985 alloc
.ConstantBufferOffset
= kb_used
;
1986 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1989 cmd_buffer
->state
.push_constant_stages
= stages
;
1991 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1993 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1994 * the next 3DPRIMITIVE command after programming the
1995 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1997 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1998 * pipeline setup, we need to dirty push constants.
2000 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
2003 static const struct anv_descriptor
*
2004 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
2005 const struct anv_pipeline_binding
*binding
)
2007 assert(binding
->set
< MAX_SETS
);
2008 const struct anv_descriptor_set
*set
=
2009 pipe_state
->descriptors
[binding
->set
];
2010 const uint32_t offset
=
2011 set
->layout
->binding
[binding
->binding
].descriptor_index
;
2012 return &set
->descriptors
[offset
+ binding
->index
];
2016 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
2017 const struct anv_pipeline_binding
*binding
)
2019 assert(binding
->set
< MAX_SETS
);
2020 const struct anv_descriptor_set
*set
=
2021 pipe_state
->descriptors
[binding
->set
];
2023 uint32_t dynamic_offset_idx
=
2024 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
2025 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
2028 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
2032 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2033 gl_shader_stage stage
,
2034 struct anv_state
*bt_state
)
2036 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
2037 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2038 struct anv_cmd_pipeline_state
*pipe_state
;
2039 struct anv_pipeline
*pipeline
;
2040 uint32_t bias
, state_offset
;
2043 case MESA_SHADER_COMPUTE
:
2044 pipe_state
= &cmd_buffer
->state
.compute
.base
;
2048 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
2052 pipeline
= pipe_state
->pipeline
;
2054 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2055 *bt_state
= (struct anv_state
) { 0, };
2059 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2060 if (bias
+ map
->surface_count
== 0) {
2061 *bt_state
= (struct anv_state
) { 0, };
2065 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2066 bias
+ map
->surface_count
,
2068 uint32_t *bt_map
= bt_state
->map
;
2070 if (bt_state
->map
== NULL
)
2071 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2073 if (stage
== MESA_SHADER_COMPUTE
&&
2074 get_cs_prog_data(pipeline
)->uses_num_work_groups
) {
2075 struct anv_state surface_state
;
2077 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2079 const enum isl_format format
=
2080 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2081 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2083 cmd_buffer
->state
.compute
.num_workgroups
,
2086 bt_map
[0] = surface_state
.offset
+ state_offset
;
2087 add_surface_reloc(cmd_buffer
, surface_state
,
2088 cmd_buffer
->state
.compute
.num_workgroups
);
2091 if (map
->surface_count
== 0)
2094 /* We only use push constant space for images before gen9 */
2095 if (map
->image_count
> 0 && devinfo
->gen
< 9) {
2097 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
2098 if (result
!= VK_SUCCESS
)
2101 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
2105 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2106 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2108 struct anv_state surface_state
;
2110 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2111 /* Color attachment binding */
2112 assert(stage
== MESA_SHADER_FRAGMENT
);
2113 assert(binding
->binding
== 0);
2114 if (binding
->index
< subpass
->color_count
) {
2115 const unsigned att
=
2116 subpass
->color_attachments
[binding
->index
].attachment
;
2118 /* From the Vulkan 1.0.46 spec:
2120 * "If any color or depth/stencil attachments are
2121 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2124 if (att
== VK_ATTACHMENT_UNUSED
) {
2125 surface_state
= cmd_buffer
->state
.null_surface_state
;
2127 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2130 surface_state
= cmd_buffer
->state
.null_surface_state
;
2133 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2135 } else if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2136 struct anv_state surface_state
=
2137 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2139 struct anv_address constant_data
= {
2140 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2141 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2143 unsigned constant_data_size
=
2144 pipeline
->shaders
[stage
]->constant_data_size
;
2146 const enum isl_format format
=
2147 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2148 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2149 surface_state
, format
,
2150 constant_data
, constant_data_size
, 1);
2152 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2153 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2157 const struct anv_descriptor
*desc
=
2158 anv_descriptor_for_binding(pipe_state
, binding
);
2160 switch (desc
->type
) {
2161 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2162 /* Nothing for us to do here */
2165 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2166 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2167 struct anv_surface_state sstate
=
2168 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2169 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2170 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2171 surface_state
= sstate
.state
;
2172 assert(surface_state
.alloc_size
);
2173 add_surface_state_relocs(cmd_buffer
, sstate
);
2176 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2177 assert(stage
== MESA_SHADER_FRAGMENT
);
2178 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2179 /* For depth and stencil input attachments, we treat it like any
2180 * old texture that a user may have bound.
2182 struct anv_surface_state sstate
=
2183 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2184 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2185 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2186 surface_state
= sstate
.state
;
2187 assert(surface_state
.alloc_size
);
2188 add_surface_state_relocs(cmd_buffer
, sstate
);
2190 /* For color input attachments, we create the surface state at
2191 * vkBeginRenderPass time so that we can include aux and clear
2192 * color information.
2194 assert(binding
->input_attachment_index
< subpass
->input_count
);
2195 const unsigned subpass_att
= binding
->input_attachment_index
;
2196 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2197 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2201 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2202 struct anv_surface_state sstate
= (binding
->write_only
)
2203 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2204 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2205 surface_state
= sstate
.state
;
2206 assert(surface_state
.alloc_size
);
2207 add_surface_state_relocs(cmd_buffer
, sstate
);
2208 if (devinfo
->gen
< 9) {
2209 assert(image
< MAX_GEN8_IMAGES
);
2210 struct brw_image_param
*image_param
=
2211 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
];
2214 desc
->image_view
->planes
[binding
->plane
].storage_image_param
;
2220 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2221 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2222 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2223 surface_state
= desc
->buffer_view
->surface_state
;
2224 assert(surface_state
.alloc_size
);
2225 add_surface_reloc(cmd_buffer
, surface_state
,
2226 desc
->buffer_view
->address
);
2229 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2230 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2231 /* Compute the offset within the buffer */
2232 uint32_t dynamic_offset
=
2233 dynamic_offset_for_binding(pipe_state
, binding
);
2234 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2235 /* Clamp to the buffer size */
2236 offset
= MIN2(offset
, desc
->buffer
->size
);
2237 /* Clamp the range to the buffer size */
2238 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2240 struct anv_address address
=
2241 anv_address_add(desc
->buffer
->address
, offset
);
2244 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2245 enum isl_format format
=
2246 anv_isl_format_for_descriptor_type(desc
->type
);
2248 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2249 format
, address
, range
, 1);
2250 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2254 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2255 surface_state
= (binding
->write_only
)
2256 ? desc
->buffer_view
->writeonly_storage_surface_state
2257 : desc
->buffer_view
->storage_surface_state
;
2258 assert(surface_state
.alloc_size
);
2259 add_surface_reloc(cmd_buffer
, surface_state
,
2260 desc
->buffer_view
->address
);
2261 if (devinfo
->gen
< 9) {
2262 assert(image
< MAX_GEN8_IMAGES
);
2263 struct brw_image_param
*image_param
=
2264 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
];
2266 *image_param
= desc
->buffer_view
->storage_image_param
;
2272 assert(!"Invalid descriptor type");
2276 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2278 assert(image
== map
->image_count
);
2282 /* The PIPE_CONTROL command description says:
2284 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2285 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2286 * Target Cache Flush by enabling this bit. When render target flush
2287 * is set due to new association of BTI, PS Scoreboard Stall bit must
2288 * be set in this packet."
2290 * FINISHME: Currently we shuffle around the surface states in the binding
2291 * table based on if they are getting used or not. So, we've to do below
2292 * pipe control flush for every binding table upload. Make changes so
2293 * that we do it only when we modify render target surface states.
2295 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2296 pc
.RenderTargetCacheFlushEnable
= true;
2297 pc
.StallAtPixelScoreboard
= true;
2305 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2306 gl_shader_stage stage
,
2307 struct anv_state
*state
)
2309 struct anv_cmd_pipeline_state
*pipe_state
=
2310 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2311 &cmd_buffer
->state
.gfx
.base
;
2312 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2314 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2315 *state
= (struct anv_state
) { 0, };
2319 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2320 if (map
->sampler_count
== 0) {
2321 *state
= (struct anv_state
) { 0, };
2325 uint32_t size
= map
->sampler_count
* 16;
2326 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2328 if (state
->map
== NULL
)
2329 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2331 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2332 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2333 const struct anv_descriptor
*desc
=
2334 anv_descriptor_for_binding(pipe_state
, binding
);
2336 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2337 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2340 struct anv_sampler
*sampler
= desc
->sampler
;
2342 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2343 * happens to be zero.
2345 if (sampler
== NULL
)
2348 memcpy(state
->map
+ (s
* 16),
2349 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2356 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2358 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2360 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2361 pipeline
->active_stages
;
2363 VkResult result
= VK_SUCCESS
;
2364 anv_foreach_stage(s
, dirty
) {
2365 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2366 if (result
!= VK_SUCCESS
)
2368 result
= emit_binding_table(cmd_buffer
, s
,
2369 &cmd_buffer
->state
.binding_tables
[s
]);
2370 if (result
!= VK_SUCCESS
)
2374 if (result
!= VK_SUCCESS
) {
2375 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2377 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2378 if (result
!= VK_SUCCESS
)
2381 /* Re-emit state base addresses so we get the new surface state base
2382 * address before we start emitting binding tables etc.
2384 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2386 /* Re-emit all active binding tables */
2387 dirty
|= pipeline
->active_stages
;
2388 anv_foreach_stage(s
, dirty
) {
2389 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2390 if (result
!= VK_SUCCESS
) {
2391 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2394 result
= emit_binding_table(cmd_buffer
, s
,
2395 &cmd_buffer
->state
.binding_tables
[s
]);
2396 if (result
!= VK_SUCCESS
) {
2397 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2403 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2409 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2412 static const uint32_t sampler_state_opcodes
[] = {
2413 [MESA_SHADER_VERTEX
] = 43,
2414 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2415 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2416 [MESA_SHADER_GEOMETRY
] = 46,
2417 [MESA_SHADER_FRAGMENT
] = 47,
2418 [MESA_SHADER_COMPUTE
] = 0,
2421 static const uint32_t binding_table_opcodes
[] = {
2422 [MESA_SHADER_VERTEX
] = 38,
2423 [MESA_SHADER_TESS_CTRL
] = 39,
2424 [MESA_SHADER_TESS_EVAL
] = 40,
2425 [MESA_SHADER_GEOMETRY
] = 41,
2426 [MESA_SHADER_FRAGMENT
] = 42,
2427 [MESA_SHADER_COMPUTE
] = 0,
2430 anv_foreach_stage(s
, stages
) {
2431 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2432 assert(binding_table_opcodes
[s
] > 0);
2434 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2435 anv_batch_emit(&cmd_buffer
->batch
,
2436 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2437 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2438 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2442 /* Always emit binding table pointers if we're asked to, since on SKL
2443 * this is what flushes push constants. */
2444 anv_batch_emit(&cmd_buffer
->batch
,
2445 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2446 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2447 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2453 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2454 VkShaderStageFlags dirty_stages
)
2456 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2457 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2459 static const uint32_t push_constant_opcodes
[] = {
2460 [MESA_SHADER_VERTEX
] = 21,
2461 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2462 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2463 [MESA_SHADER_GEOMETRY
] = 22,
2464 [MESA_SHADER_FRAGMENT
] = 23,
2465 [MESA_SHADER_COMPUTE
] = 0,
2468 VkShaderStageFlags flushed
= 0;
2470 anv_foreach_stage(stage
, dirty_stages
) {
2471 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2472 assert(push_constant_opcodes
[stage
] > 0);
2474 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2475 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2477 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2478 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2479 const struct brw_stage_prog_data
*prog_data
=
2480 pipeline
->shaders
[stage
]->prog_data
;
2481 const struct anv_pipeline_bind_map
*bind_map
=
2482 &pipeline
->shaders
[stage
]->bind_map
;
2484 /* The Skylake PRM contains the following restriction:
2486 * "The driver must ensure The following case does not occur
2487 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2488 * buffer 3 read length equal to zero committed followed by a
2489 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2492 * To avoid this, we program the buffers in the highest slots.
2493 * This way, slot 0 is only used if slot 3 is also used.
2497 for (int i
= 3; i
>= 0; i
--) {
2498 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2499 if (range
->length
== 0)
2502 const unsigned surface
=
2503 prog_data
->binding_table
.ubo_start
+ range
->block
;
2505 assert(surface
<= bind_map
->surface_count
);
2506 const struct anv_pipeline_binding
*binding
=
2507 &bind_map
->surface_to_descriptor
[surface
];
2509 struct anv_address read_addr
;
2511 if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2512 struct anv_address constant_data
= {
2513 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2514 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2516 unsigned constant_data_size
=
2517 pipeline
->shaders
[stage
]->constant_data_size
;
2519 read_len
= MIN2(range
->length
,
2520 DIV_ROUND_UP(constant_data_size
, 32) - range
->start
);
2521 read_addr
= anv_address_add(constant_data
,
2524 const struct anv_descriptor
*desc
=
2525 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2527 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2528 read_len
= MIN2(range
->length
,
2529 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2530 read_addr
= anv_address_add(desc
->buffer_view
->address
,
2533 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2535 uint32_t dynamic_offset
=
2536 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2537 uint32_t buf_offset
=
2538 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2539 uint32_t buf_range
=
2540 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2542 read_len
= MIN2(range
->length
,
2543 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2544 read_addr
= anv_address_add(desc
->buffer
->address
,
2545 buf_offset
+ range
->start
* 32);
2550 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2551 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2556 struct anv_state state
=
2557 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2559 if (state
.alloc_size
> 0) {
2560 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2561 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2562 .offset
= state
.offset
,
2564 c
.ConstantBody
.ReadLength
[n
] =
2565 DIV_ROUND_UP(state
.alloc_size
, 32);
2568 /* For Ivy Bridge, the push constants packets have a different
2569 * rule that would require us to iterate in the other direction
2570 * and possibly mess around with dynamic state base address.
2571 * Don't bother; just emit regular push constants at n = 0.
2573 struct anv_state state
=
2574 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2576 if (state
.alloc_size
> 0) {
2577 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2578 c
.ConstantBody
.ReadLength
[0] =
2579 DIV_ROUND_UP(state
.alloc_size
, 32);
2585 flushed
|= mesa_to_vk_shader_stage(stage
);
2588 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2592 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2594 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2597 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2598 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2599 vb_emit
|= pipeline
->vb_used
;
2601 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2603 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2605 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2608 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2609 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2611 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2612 GENX(3DSTATE_VERTEX_BUFFERS
));
2614 for_each_bit(vb
, vb_emit
) {
2615 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2616 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2618 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2619 .VertexBufferIndex
= vb
,
2621 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
2623 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2624 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2627 .AddressModifyEnable
= true,
2628 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2629 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2632 .BufferSize
= buffer
->size
- offset
2634 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2638 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2643 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2646 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
2647 /* We don't need any per-buffer dirty tracking because you're not
2648 * allowed to bind different XFB buffers while XFB is enabled.
2650 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
2651 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
2652 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
2653 sob
.SOBufferIndex
= idx
;
2655 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
) {
2656 sob
.SOBufferEnable
= true;
2657 sob
.MOCS
= cmd_buffer
->device
->default_mocs
,
2658 sob
.StreamOffsetWriteEnable
= false;
2659 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
2661 /* Size is in DWords - 1 */
2662 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
2667 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
2669 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2673 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2674 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2676 /* The exact descriptor layout is pulled from the pipeline, so we need
2677 * to re-emit binding tables on every pipeline change.
2679 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2681 /* If the pipeline changed, we may need to re-allocate push constant
2684 cmd_buffer_alloc_push_constants(cmd_buffer
);
2688 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2689 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2690 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2692 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2693 * stall needs to be sent just prior to any 3DSTATE_VS,
2694 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2695 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2696 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2697 * PIPE_CONTROL needs to be sent before any combination of VS
2698 * associated 3DSTATE."
2700 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2701 pc
.DepthStallEnable
= true;
2702 pc
.PostSyncOperation
= WriteImmediateData
;
2704 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2709 /* Render targets live in the same binding table as fragment descriptors */
2710 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2711 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2713 /* We emit the binding tables and sampler tables first, then emit push
2714 * constants and then finally emit binding table and sampler table
2715 * pointers. It has to happen in this order, since emitting the binding
2716 * tables may change the push constants (in case of storage images). After
2717 * emitting push constants, on SKL+ we have to emit the corresponding
2718 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2721 if (cmd_buffer
->state
.descriptors_dirty
)
2722 dirty
= flush_descriptor_sets(cmd_buffer
);
2724 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2725 /* Because we're pushing UBOs, we have to push whenever either
2726 * descriptors or push constants is dirty.
2728 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2729 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2730 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2734 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2736 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2737 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2739 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2740 ANV_CMD_DIRTY_PIPELINE
)) {
2741 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2742 pipeline
->depth_clamp_enable
);
2745 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2746 ANV_CMD_DIRTY_RENDER_TARGETS
))
2747 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2749 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2751 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2755 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2756 struct anv_address addr
,
2757 uint32_t size
, uint32_t index
)
2759 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2760 GENX(3DSTATE_VERTEX_BUFFERS
));
2762 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2763 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2764 .VertexBufferIndex
= index
,
2765 .AddressModifyEnable
= true,
2767 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
),
2769 .BufferStartingAddress
= addr
,
2772 .BufferStartingAddress
= addr
,
2773 .EndAddress
= anv_address_add(addr
, size
),
2779 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2780 struct anv_address addr
)
2782 emit_vertex_bo(cmd_buffer
, addr
, 8, ANV_SVGS_VB_INDEX
);
2786 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2787 uint32_t base_vertex
, uint32_t base_instance
)
2789 struct anv_state id_state
=
2790 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2792 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2793 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2795 struct anv_address addr
= {
2796 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2797 .offset
= id_state
.offset
,
2800 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2804 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2806 struct anv_state state
=
2807 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2809 ((uint32_t *)state
.map
)[0] = draw_index
;
2811 struct anv_address addr
= {
2812 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2813 .offset
= state
.offset
,
2816 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2820 VkCommandBuffer commandBuffer
,
2821 uint32_t vertexCount
,
2822 uint32_t instanceCount
,
2823 uint32_t firstVertex
,
2824 uint32_t firstInstance
)
2826 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2827 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2828 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2830 if (anv_batch_has_error(&cmd_buffer
->batch
))
2833 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2835 if (cmd_buffer
->state
.conditional_render_enabled
)
2836 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2838 if (vs_prog_data
->uses_firstvertex
||
2839 vs_prog_data
->uses_baseinstance
)
2840 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2841 if (vs_prog_data
->uses_drawid
)
2842 emit_draw_index(cmd_buffer
, 0);
2844 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2845 * different views. We need to multiply instanceCount by the view count.
2847 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2849 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2850 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2851 prim
.VertexAccessType
= SEQUENTIAL
;
2852 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2853 prim
.VertexCountPerInstance
= vertexCount
;
2854 prim
.StartVertexLocation
= firstVertex
;
2855 prim
.InstanceCount
= instanceCount
;
2856 prim
.StartInstanceLocation
= firstInstance
;
2857 prim
.BaseVertexLocation
= 0;
2861 void genX(CmdDrawIndexed
)(
2862 VkCommandBuffer commandBuffer
,
2863 uint32_t indexCount
,
2864 uint32_t instanceCount
,
2865 uint32_t firstIndex
,
2866 int32_t vertexOffset
,
2867 uint32_t firstInstance
)
2869 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2870 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2871 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2873 if (anv_batch_has_error(&cmd_buffer
->batch
))
2876 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2878 if (cmd_buffer
->state
.conditional_render_enabled
)
2879 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2881 if (vs_prog_data
->uses_firstvertex
||
2882 vs_prog_data
->uses_baseinstance
)
2883 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2884 if (vs_prog_data
->uses_drawid
)
2885 emit_draw_index(cmd_buffer
, 0);
2887 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2888 * different views. We need to multiply instanceCount by the view count.
2890 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2892 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2893 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2894 prim
.VertexAccessType
= RANDOM
;
2895 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2896 prim
.VertexCountPerInstance
= indexCount
;
2897 prim
.StartVertexLocation
= firstIndex
;
2898 prim
.InstanceCount
= instanceCount
;
2899 prim
.StartInstanceLocation
= firstInstance
;
2900 prim
.BaseVertexLocation
= vertexOffset
;
2904 /* Auto-Draw / Indirect Registers */
2905 #define GEN7_3DPRIM_END_OFFSET 0x2420
2906 #define GEN7_3DPRIM_START_VERTEX 0x2430
2907 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2908 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2909 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2910 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2912 /* MI_MATH only exists on Haswell+ */
2913 #if GEN_IS_HASWELL || GEN_GEN >= 8
2915 /* Emit dwords to multiply GPR0 by N */
2917 build_alu_multiply_gpr0(uint32_t *dw
, unsigned *dw_count
, uint32_t N
)
2919 VK_OUTARRAY_MAKE(out
, dw
, dw_count
);
2921 #define append_alu(opcode, operand1, operand2) \
2922 vk_outarray_append(&out, alu_dw) *alu_dw = mi_alu(opcode, operand1, operand2)
2925 unsigned top_bit
= 31 - __builtin_clz(N
);
2926 for (int i
= top_bit
- 1; i
>= 0; i
--) {
2927 /* We get our initial data in GPR0 and we write the final data out to
2928 * GPR0 but we use GPR1 as our scratch register.
2930 unsigned src_reg
= i
== top_bit
- 1 ? MI_ALU_REG0
: MI_ALU_REG1
;
2931 unsigned dst_reg
= i
== 0 ? MI_ALU_REG0
: MI_ALU_REG1
;
2933 /* Shift the current value left by 1 */
2934 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, src_reg
);
2935 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, src_reg
);
2936 append_alu(MI_ALU_ADD
, 0, 0);
2939 /* Store ACCU to R1 and add R0 to R1 */
2940 append_alu(MI_ALU_STORE
, MI_ALU_REG1
, MI_ALU_ACCU
);
2941 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
2942 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
2943 append_alu(MI_ALU_ADD
, 0, 0);
2946 append_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2953 emit_mul_gpr0(struct anv_batch
*batch
, uint32_t N
)
2955 uint32_t num_dwords
;
2956 build_alu_multiply_gpr0(NULL
, &num_dwords
, N
);
2958 uint32_t *dw
= anv_batch_emitn(batch
, 1 + num_dwords
, GENX(MI_MATH
));
2959 build_alu_multiply_gpr0(dw
+ 1, &num_dwords
, N
);
2962 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2965 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2966 struct anv_address addr
,
2969 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2971 emit_lrm(batch
, GEN7_3DPRIM_VERTEX_COUNT
, anv_address_add(addr
, 0));
2973 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2974 if (view_count
> 1) {
2975 #if GEN_IS_HASWELL || GEN_GEN >= 8
2976 emit_lrm(batch
, CS_GPR(0), anv_address_add(addr
, 4));
2977 emit_mul_gpr0(batch
, view_count
);
2978 emit_lrr(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, CS_GPR(0));
2980 anv_finishme("Multiview + indirect draw requires MI_MATH; "
2981 "MI_MATH is not supported on Ivy Bridge");
2982 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, anv_address_add(addr
, 4));
2985 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, anv_address_add(addr
, 4));
2988 emit_lrm(batch
, GEN7_3DPRIM_START_VERTEX
, anv_address_add(addr
, 8));
2991 emit_lrm(batch
, GEN7_3DPRIM_BASE_VERTEX
, anv_address_add(addr
, 12));
2992 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, anv_address_add(addr
, 16));
2994 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, anv_address_add(addr
, 12));
2995 emit_lri(batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
2999 void genX(CmdDrawIndirect
)(
3000 VkCommandBuffer commandBuffer
,
3002 VkDeviceSize offset
,
3006 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3007 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3008 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3009 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3011 if (anv_batch_has_error(&cmd_buffer
->batch
))
3014 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3016 if (cmd_buffer
->state
.conditional_render_enabled
)
3017 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3019 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3020 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3022 if (vs_prog_data
->uses_firstvertex
||
3023 vs_prog_data
->uses_baseinstance
)
3024 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3025 if (vs_prog_data
->uses_drawid
)
3026 emit_draw_index(cmd_buffer
, i
);
3028 load_indirect_parameters(cmd_buffer
, draw
, false);
3030 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3031 prim
.IndirectParameterEnable
= true;
3032 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3033 prim
.VertexAccessType
= SEQUENTIAL
;
3034 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3041 void genX(CmdDrawIndexedIndirect
)(
3042 VkCommandBuffer commandBuffer
,
3044 VkDeviceSize offset
,
3048 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3049 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3050 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3051 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3053 if (anv_batch_has_error(&cmd_buffer
->batch
))
3056 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3058 if (cmd_buffer
->state
.conditional_render_enabled
)
3059 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3061 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3062 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3064 /* TODO: We need to stomp base vertex to 0 somehow */
3065 if (vs_prog_data
->uses_firstvertex
||
3066 vs_prog_data
->uses_baseinstance
)
3067 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3068 if (vs_prog_data
->uses_drawid
)
3069 emit_draw_index(cmd_buffer
, i
);
3071 load_indirect_parameters(cmd_buffer
, draw
, true);
3073 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3074 prim
.IndirectParameterEnable
= true;
3075 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3076 prim
.VertexAccessType
= RANDOM
;
3077 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3084 #define TMP_DRAW_COUNT_REG MI_ALU_REG14
3087 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3088 struct anv_address count_address
,
3089 const bool conditional_render_enabled
)
3091 if (conditional_render_enabled
) {
3092 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3093 emit_lrm(&cmd_buffer
->batch
, CS_GPR(TMP_DRAW_COUNT_REG
), count_address
);
3094 emit_lri(&cmd_buffer
->batch
, CS_GPR(TMP_DRAW_COUNT_REG
) + 4, 0);
3097 /* Upload the current draw count from the draw parameters buffer to
3098 * MI_PREDICATE_SRC0.
3100 emit_lrm(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, count_address
);
3101 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
3103 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
3108 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3109 uint32_t draw_index
)
3111 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3112 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, draw_index
);
3114 if (draw_index
== 0) {
3115 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3116 mip
.LoadOperation
= LOAD_LOADINV
;
3117 mip
.CombineOperation
= COMBINE_SET
;
3118 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3121 /* While draw_index < draw_count the predicate's result will be
3122 * (draw_index == draw_count) ^ TRUE = TRUE
3123 * When draw_index == draw_count the result is
3124 * (TRUE) ^ TRUE = FALSE
3125 * After this all results will be:
3126 * (FALSE) ^ FALSE = FALSE
3128 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3129 mip
.LoadOperation
= LOAD_LOAD
;
3130 mip
.CombineOperation
= COMBINE_XOR
;
3131 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3136 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3138 emit_draw_count_predicate_with_conditional_render(
3139 struct anv_cmd_buffer
*cmd_buffer
,
3140 uint32_t draw_index
)
3142 const int draw_index_reg
= MI_ALU_REG0
;
3143 const int tmp_result_reg
= MI_ALU_REG1
;
3145 emit_lri(&cmd_buffer
->batch
, CS_GPR(draw_index_reg
), draw_index
);
3146 emit_lri(&cmd_buffer
->batch
, CS_GPR(draw_index_reg
) + 4, 0);
3149 /* Compute (draw_index < draw_count).
3150 * We do this by subtracting and storing the carry bit.
3152 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 9, GENX(MI_MATH
));
3153 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, draw_index_reg
);
3154 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, TMP_DRAW_COUNT_REG
);
3155 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
3156 dw
[4] = mi_alu(MI_ALU_STORE
, tmp_result_reg
, MI_ALU_CF
);
3158 dw
[5] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, tmp_result_reg
);
3159 dw
[6] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, ANV_PREDICATE_RESULT_REG
);
3160 dw
[7] = mi_alu(MI_ALU_AND
, 0, 0);
3161 dw
[8] = mi_alu(MI_ALU_STORE
, tmp_result_reg
, MI_ALU_ACCU
);
3164 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_RESULT
, CS_GPR(tmp_result_reg
));
3166 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3167 * so we emit MI_PREDICATE to set it.
3170 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(tmp_result_reg
));
3171 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
3172 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
3173 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
3175 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3176 mip
.LoadOperation
= LOAD_LOADINV
;
3177 mip
.CombineOperation
= COMBINE_SET
;
3178 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3184 void genX(CmdDrawIndirectCountKHR
)(
3185 VkCommandBuffer commandBuffer
,
3187 VkDeviceSize offset
,
3188 VkBuffer _countBuffer
,
3189 VkDeviceSize countBufferOffset
,
3190 uint32_t maxDrawCount
,
3193 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3194 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3195 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3196 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3197 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3198 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3200 if (anv_batch_has_error(&cmd_buffer
->batch
))
3203 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3205 struct anv_address count_address
=
3206 anv_address_add(count_buffer
->address
, countBufferOffset
);
3208 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3209 cmd_state
->conditional_render_enabled
);
3211 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3212 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3214 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3215 if (cmd_state
->conditional_render_enabled
) {
3216 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3218 emit_draw_count_predicate(cmd_buffer
, i
);
3221 emit_draw_count_predicate(cmd_buffer
, i
);
3224 if (vs_prog_data
->uses_firstvertex
||
3225 vs_prog_data
->uses_baseinstance
)
3226 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3227 if (vs_prog_data
->uses_drawid
)
3228 emit_draw_index(cmd_buffer
, i
);
3230 load_indirect_parameters(cmd_buffer
, draw
, false);
3232 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3233 prim
.IndirectParameterEnable
= true;
3234 prim
.PredicateEnable
= true;
3235 prim
.VertexAccessType
= SEQUENTIAL
;
3236 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3243 void genX(CmdDrawIndexedIndirectCountKHR
)(
3244 VkCommandBuffer commandBuffer
,
3246 VkDeviceSize offset
,
3247 VkBuffer _countBuffer
,
3248 VkDeviceSize countBufferOffset
,
3249 uint32_t maxDrawCount
,
3252 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3253 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3254 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3255 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3256 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3257 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3259 if (anv_batch_has_error(&cmd_buffer
->batch
))
3262 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3264 struct anv_address count_address
=
3265 anv_address_add(count_buffer
->address
, countBufferOffset
);
3267 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3268 cmd_state
->conditional_render_enabled
);
3270 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3271 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3273 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3274 if (cmd_state
->conditional_render_enabled
) {
3275 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3277 emit_draw_count_predicate(cmd_buffer
, i
);
3280 emit_draw_count_predicate(cmd_buffer
, i
);
3283 /* TODO: We need to stomp base vertex to 0 somehow */
3284 if (vs_prog_data
->uses_firstvertex
||
3285 vs_prog_data
->uses_baseinstance
)
3286 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3287 if (vs_prog_data
->uses_drawid
)
3288 emit_draw_index(cmd_buffer
, i
);
3290 load_indirect_parameters(cmd_buffer
, draw
, true);
3292 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3293 prim
.IndirectParameterEnable
= true;
3294 prim
.PredicateEnable
= true;
3295 prim
.VertexAccessType
= RANDOM
;
3296 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3303 void genX(CmdBeginTransformFeedbackEXT
)(
3304 VkCommandBuffer commandBuffer
,
3305 uint32_t firstCounterBuffer
,
3306 uint32_t counterBufferCount
,
3307 const VkBuffer
* pCounterBuffers
,
3308 const VkDeviceSize
* pCounterBufferOffsets
)
3310 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3312 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3313 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3314 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3316 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3318 * "Ssoftware must ensure that no HW stream output operations can be in
3319 * process or otherwise pending at the point that the MI_LOAD/STORE
3320 * commands are processed. This will likely require a pipeline flush."
3322 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3323 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3325 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3326 /* If we have a counter buffer, this is a resume so we need to load the
3327 * value into the streamout offset register. Otherwise, this is a begin
3328 * and we need to reset it to zero.
3330 if (pCounterBuffers
&&
3331 idx
>= firstCounterBuffer
&&
3332 idx
- firstCounterBuffer
< counterBufferCount
&&
3333 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
3334 uint32_t cb_idx
= idx
- firstCounterBuffer
;
3335 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3336 uint64_t offset
= pCounterBufferOffsets
?
3337 pCounterBufferOffsets
[cb_idx
] : 0;
3339 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3340 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3341 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3345 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
3346 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3352 cmd_buffer
->state
.xfb_enabled
= true;
3353 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3356 void genX(CmdEndTransformFeedbackEXT
)(
3357 VkCommandBuffer commandBuffer
,
3358 uint32_t firstCounterBuffer
,
3359 uint32_t counterBufferCount
,
3360 const VkBuffer
* pCounterBuffers
,
3361 const VkDeviceSize
* pCounterBufferOffsets
)
3363 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3365 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3366 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3367 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3369 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3371 * "Ssoftware must ensure that no HW stream output operations can be in
3372 * process or otherwise pending at the point that the MI_LOAD/STORE
3373 * commands are processed. This will likely require a pipeline flush."
3375 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3376 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3378 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
3379 unsigned idx
= firstCounterBuffer
+ cb_idx
;
3381 /* If we have a counter buffer, this is a resume so we need to load the
3382 * value into the streamout offset register. Otherwise, this is a begin
3383 * and we need to reset it to zero.
3385 if (pCounterBuffers
&&
3386 cb_idx
< counterBufferCount
&&
3387 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
3388 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3389 uint64_t offset
= pCounterBufferOffsets
?
3390 pCounterBufferOffsets
[cb_idx
] : 0;
3392 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
3393 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3395 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3400 cmd_buffer
->state
.xfb_enabled
= false;
3401 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3405 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
3407 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3408 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
3411 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3412 if (result
!= VK_SUCCESS
) {
3413 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3415 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
3416 if (result
!= VK_SUCCESS
)
3419 /* Re-emit state base addresses so we get the new surface state base
3420 * address before we start emitting binding tables etc.
3422 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
3424 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3425 if (result
!= VK_SUCCESS
) {
3426 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3431 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3432 if (result
!= VK_SUCCESS
) {
3433 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3437 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3438 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3439 .BindingTablePointer
= surfaces
.offset
,
3440 .SamplerStatePointer
= samplers
.offset
,
3442 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3444 struct anv_state state
=
3445 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3446 pipeline
->interface_descriptor_data
,
3447 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3450 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3451 anv_batch_emit(&cmd_buffer
->batch
,
3452 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3453 mid
.InterfaceDescriptorTotalLength
= size
;
3454 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3461 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3463 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3464 MAYBE_UNUSED VkResult result
;
3466 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3468 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3470 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3472 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3473 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3475 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3476 * the only bits that are changed are scoreboard related: Scoreboard
3477 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3478 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3481 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3482 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3484 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3487 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3488 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3489 /* FIXME: figure out descriptors for gen7 */
3490 result
= flush_compute_descriptor_set(cmd_buffer
);
3491 if (result
!= VK_SUCCESS
)
3494 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3497 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3498 struct anv_state push_state
=
3499 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3501 if (push_state
.alloc_size
) {
3502 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3503 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3504 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3508 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3511 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3513 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3519 verify_cmd_parser(const struct anv_device
*device
,
3520 int required_version
,
3521 const char *function
)
3523 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3524 return vk_errorf(device
->instance
, device
->instance
,
3525 VK_ERROR_FEATURE_NOT_PRESENT
,
3526 "cmd parser version %d is required for %s",
3527 required_version
, function
);
3536 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3537 uint32_t baseGroupX
,
3538 uint32_t baseGroupY
,
3539 uint32_t baseGroupZ
)
3541 if (anv_batch_has_error(&cmd_buffer
->batch
))
3545 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, MESA_SHADER_COMPUTE
,
3546 base_work_group_id
);
3547 if (result
!= VK_SUCCESS
) {
3548 cmd_buffer
->batch
.status
= result
;
3552 struct anv_push_constants
*push
=
3553 cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3554 if (push
->base_work_group_id
[0] != baseGroupX
||
3555 push
->base_work_group_id
[1] != baseGroupY
||
3556 push
->base_work_group_id
[2] != baseGroupZ
) {
3557 push
->base_work_group_id
[0] = baseGroupX
;
3558 push
->base_work_group_id
[1] = baseGroupY
;
3559 push
->base_work_group_id
[2] = baseGroupZ
;
3561 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3565 void genX(CmdDispatch
)(
3566 VkCommandBuffer commandBuffer
,
3571 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3574 void genX(CmdDispatchBase
)(
3575 VkCommandBuffer commandBuffer
,
3576 uint32_t baseGroupX
,
3577 uint32_t baseGroupY
,
3578 uint32_t baseGroupZ
,
3579 uint32_t groupCountX
,
3580 uint32_t groupCountY
,
3581 uint32_t groupCountZ
)
3583 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3584 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3585 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3587 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3588 baseGroupY
, baseGroupZ
);
3590 if (anv_batch_has_error(&cmd_buffer
->batch
))
3593 if (prog_data
->uses_num_work_groups
) {
3594 struct anv_state state
=
3595 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3596 uint32_t *sizes
= state
.map
;
3597 sizes
[0] = groupCountX
;
3598 sizes
[1] = groupCountY
;
3599 sizes
[2] = groupCountZ
;
3600 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3601 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3602 .offset
= state
.offset
,
3606 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3608 if (cmd_buffer
->state
.conditional_render_enabled
)
3609 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3611 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3612 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3613 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3614 ggw
.ThreadDepthCounterMaximum
= 0;
3615 ggw
.ThreadHeightCounterMaximum
= 0;
3616 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3617 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3618 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3619 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3620 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3621 ggw
.BottomExecutionMask
= 0xffffffff;
3624 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3627 #define GPGPU_DISPATCHDIMX 0x2500
3628 #define GPGPU_DISPATCHDIMY 0x2504
3629 #define GPGPU_DISPATCHDIMZ 0x2508
3631 void genX(CmdDispatchIndirect
)(
3632 VkCommandBuffer commandBuffer
,
3634 VkDeviceSize offset
)
3636 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3637 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3638 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3639 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3640 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3641 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3643 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3646 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3647 * indirect dispatch registers to be written.
3649 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3650 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3654 if (prog_data
->uses_num_work_groups
)
3655 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3657 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3659 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, anv_address_add(addr
, 0));
3660 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, anv_address_add(addr
, 4));
3661 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, anv_address_add(addr
, 8));
3664 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
3665 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
3666 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
3667 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
3669 /* Load compute_dispatch_indirect_x_size into SRC0 */
3670 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 0));
3672 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3673 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3674 mip
.LoadOperation
= LOAD_LOAD
;
3675 mip
.CombineOperation
= COMBINE_SET
;
3676 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3679 /* Load compute_dispatch_indirect_y_size into SRC0 */
3680 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 4));
3682 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3683 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3684 mip
.LoadOperation
= LOAD_LOAD
;
3685 mip
.CombineOperation
= COMBINE_OR
;
3686 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3689 /* Load compute_dispatch_indirect_z_size into SRC0 */
3690 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 8));
3692 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3693 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3694 mip
.LoadOperation
= LOAD_LOAD
;
3695 mip
.CombineOperation
= COMBINE_OR
;
3696 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3699 /* predicate = !predicate; */
3700 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3701 mip
.LoadOperation
= LOAD_LOADINV
;
3702 mip
.CombineOperation
= COMBINE_OR
;
3703 mip
.CompareOperation
= COMPARE_FALSE
;
3707 if (cmd_buffer
->state
.conditional_render_enabled
) {
3708 emit_lrr(batch
, MI_PREDICATE_SRC0
, CS_GPR(ANV_PREDICATE_RESULT_REG
));
3709 /* predicate &= !(conditional_rendering_predicate == 0); */
3710 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3711 mip
.LoadOperation
= LOAD_LOADINV
;
3712 mip
.CombineOperation
= COMBINE_AND
;
3713 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3718 #else /* GEN_GEN > 7 */
3719 if (cmd_buffer
->state
.conditional_render_enabled
)
3720 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3723 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3724 ggw
.IndirectParameterEnable
= true;
3725 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
3726 cmd_buffer
->state
.conditional_render_enabled
;
3727 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3728 ggw
.ThreadDepthCounterMaximum
= 0;
3729 ggw
.ThreadHeightCounterMaximum
= 0;
3730 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3731 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3732 ggw
.BottomExecutionMask
= 0xffffffff;
3735 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3739 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3742 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3744 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3747 #if GEN_GEN >= 8 && GEN_GEN < 10
3748 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3750 * Software must clear the COLOR_CALC_STATE Valid field in
3751 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3752 * with Pipeline Select set to GPGPU.
3754 * The internal hardware docs recommend the same workaround for Gen9
3757 if (pipeline
== GPGPU
)
3758 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3761 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3762 * PIPELINE_SELECT [DevBWR+]":
3766 * Software must ensure all the write caches are flushed through a
3767 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3768 * command to invalidate read only caches prior to programming
3769 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3771 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3772 pc
.RenderTargetCacheFlushEnable
= true;
3773 pc
.DepthCacheFlushEnable
= true;
3774 pc
.DCFlushEnable
= true;
3775 pc
.PostSyncOperation
= NoWrite
;
3776 pc
.CommandStreamerStallEnable
= true;
3779 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3780 pc
.TextureCacheInvalidationEnable
= true;
3781 pc
.ConstantCacheInvalidationEnable
= true;
3782 pc
.StateCacheInvalidationEnable
= true;
3783 pc
.InstructionCacheInvalidateEnable
= true;
3784 pc
.PostSyncOperation
= NoWrite
;
3787 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3791 ps
.PipelineSelection
= pipeline
;
3795 if (devinfo
->is_geminilake
) {
3798 * "This chicken bit works around a hardware issue with barrier logic
3799 * encountered when switching between GPGPU and 3D pipelines. To
3800 * workaround the issue, this mode bit should be set after a pipeline
3804 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3806 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3807 : GLK_BARRIER_MODE_3D_HULL
,
3808 .GLKBarrierModeMask
= 1);
3809 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3813 cmd_buffer
->state
.current_pipeline
= pipeline
;
3817 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3819 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3823 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3825 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3829 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3834 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3836 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3837 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3838 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3839 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3840 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3841 * Depth Flush Bit set, followed by another pipelined depth stall
3842 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3843 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3844 * via a preceding MI_FLUSH)."
3846 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3847 pipe
.DepthStallEnable
= true;
3849 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3850 pipe
.DepthCacheFlushEnable
= true;
3852 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3853 pipe
.DepthStallEnable
= true;
3858 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3860 struct anv_device
*device
= cmd_buffer
->device
;
3861 const struct anv_image_view
*iview
=
3862 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3863 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3865 /* FIXME: Width and Height are wrong */
3867 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3869 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3870 device
->isl_dev
.ds
.size
/ 4);
3874 struct isl_depth_stencil_hiz_emit_info info
= { };
3877 info
.view
= &iview
->planes
[0].isl
;
3879 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3880 uint32_t depth_plane
=
3881 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3882 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
3884 info
.depth_surf
= &surface
->isl
;
3886 info
.depth_address
=
3887 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3888 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
3889 image
->planes
[depth_plane
].address
.bo
,
3890 image
->planes
[depth_plane
].address
.offset
+
3893 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
3896 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
3897 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
3898 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
3899 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
3902 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3903 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
3904 image
->planes
[depth_plane
].address
.bo
,
3905 image
->planes
[depth_plane
].address
.offset
+
3906 image
->planes
[depth_plane
].aux_surface
.offset
);
3908 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
3912 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3913 uint32_t stencil_plane
=
3914 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
3915 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
3917 info
.stencil_surf
= &surface
->isl
;
3919 info
.stencil_address
=
3920 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3921 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
3922 image
->planes
[stencil_plane
].address
.bo
,
3923 image
->planes
[stencil_plane
].address
.offset
+
3926 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
3929 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
3931 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
3935 * This ANDs the view mask of the current subpass with the pending clear
3936 * views in the attachment to get the mask of views active in the subpass
3937 * that still need to be cleared.
3939 static inline uint32_t
3940 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
3941 const struct anv_attachment_state
*att_state
)
3943 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
3947 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
3948 const struct anv_attachment_state
*att_state
)
3950 if (!cmd_state
->subpass
->view_mask
)
3953 uint32_t pending_clear_mask
=
3954 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3956 return pending_clear_mask
& 1;
3960 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
3963 const uint32_t last_subpass_idx
=
3964 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
3965 const struct anv_subpass
*last_subpass
=
3966 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
3967 return last_subpass
== cmd_state
->subpass
;
3971 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
3972 uint32_t subpass_id
)
3974 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3975 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
3976 cmd_state
->subpass
= subpass
;
3978 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
3980 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3981 * different views. If the client asks for instancing, we need to use the
3982 * Instance Data Step Rate to ensure that we repeat the client's
3983 * per-instance data once for each view. Since this bit is in
3984 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
3988 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
3990 /* It is possible to start a render pass with an old pipeline. Because the
3991 * render pass and subpass index are both baked into the pipeline, this is
3992 * highly unlikely. In order to do so, it requires that you have a render
3993 * pass with a single subpass and that you use that render pass twice
3994 * back-to-back and use the same pipeline at the start of the second render
3995 * pass as at the end of the first. In order to avoid unpredictable issues
3996 * with this edge case, we just dirty the pipeline at the start of every
3999 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
4001 /* Accumulate any subpass flushes that need to happen before the subpass */
4002 cmd_buffer
->state
.pending_pipe_bits
|=
4003 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
4005 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4006 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4008 bool is_multiview
= subpass
->view_mask
!= 0;
4010 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4011 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4012 if (a
== VK_ATTACHMENT_UNUSED
)
4015 assert(a
< cmd_state
->pass
->attachment_count
);
4016 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4018 struct anv_image_view
*iview
= fb
->attachments
[a
];
4019 const struct anv_image
*image
= iview
->image
;
4021 /* A resolve is necessary before use as an input attachment if the clear
4022 * color or auxiliary buffer usage isn't supported by the sampler.
4024 const bool input_needs_resolve
=
4025 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
4026 att_state
->input_aux_usage
!= att_state
->aux_usage
;
4028 VkImageLayout target_layout
;
4029 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
4030 !input_needs_resolve
) {
4031 /* Layout transitions before the final only help to enable sampling
4032 * as an input attachment. If the input attachment supports sampling
4033 * using the auxiliary surface, we can skip such transitions by
4034 * making the target layout one that is CCS-aware.
4036 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
4038 target_layout
= subpass
->attachments
[i
].layout
;
4041 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4042 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4044 uint32_t base_layer
, layer_count
;
4045 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4047 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4048 iview
->planes
[0].isl
.base_level
);
4050 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4051 layer_count
= fb
->layers
;
4054 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4055 iview
->planes
[0].isl
.base_level
, 1,
4056 base_layer
, layer_count
,
4057 att_state
->current_layout
, target_layout
);
4058 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4059 transition_depth_buffer(cmd_buffer
, image
,
4060 att_state
->current_layout
, target_layout
);
4061 att_state
->aux_usage
=
4062 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
4063 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
4065 att_state
->current_layout
= target_layout
;
4067 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
4068 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4070 /* Multi-planar images are not supported as attachments */
4071 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4072 assert(image
->n_planes
== 1);
4074 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
4075 uint32_t clear_layer_count
= fb
->layers
;
4077 if (att_state
->fast_clear
&&
4078 do_first_layer_clear(cmd_state
, att_state
)) {
4079 /* We only support fast-clears on the first layer */
4080 assert(iview
->planes
[0].isl
.base_level
== 0);
4081 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4083 union isl_color_value clear_color
= {};
4084 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
4085 if (iview
->image
->samples
== 1) {
4086 anv_image_ccs_op(cmd_buffer
, image
,
4087 iview
->planes
[0].isl
.format
,
4088 VK_IMAGE_ASPECT_COLOR_BIT
,
4089 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4093 anv_image_mcs_op(cmd_buffer
, image
,
4094 iview
->planes
[0].isl
.format
,
4095 VK_IMAGE_ASPECT_COLOR_BIT
,
4096 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4101 clear_layer_count
--;
4103 att_state
->pending_clear_views
&= ~1;
4105 if (att_state
->clear_color_is_zero
) {
4106 /* This image has the auxiliary buffer enabled. We can mark the
4107 * subresource as not needing a resolve because the clear color
4108 * will match what's in every RENDER_SURFACE_STATE object when
4109 * it's being used for sampling.
4111 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4112 VK_IMAGE_ASPECT_COLOR_BIT
,
4113 ANV_FAST_CLEAR_DEFAULT_VALUE
);
4115 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4116 VK_IMAGE_ASPECT_COLOR_BIT
,
4117 ANV_FAST_CLEAR_ANY
);
4121 /* From the VkFramebufferCreateInfo spec:
4123 * "If the render pass uses multiview, then layers must be one and each
4124 * attachment requires a number of layers that is greater than the
4125 * maximum bit index set in the view mask in the subpasses in which it
4128 * So if multiview is active we ignore the number of layers in the
4129 * framebuffer and instead we honor the view mask from the subpass.
4132 assert(image
->n_planes
== 1);
4133 uint32_t pending_clear_mask
=
4134 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4137 for_each_bit(layer_idx
, pending_clear_mask
) {
4139 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4141 anv_image_clear_color(cmd_buffer
, image
,
4142 VK_IMAGE_ASPECT_COLOR_BIT
,
4143 att_state
->aux_usage
,
4144 iview
->planes
[0].isl
.format
,
4145 iview
->planes
[0].isl
.swizzle
,
4146 iview
->planes
[0].isl
.base_level
,
4149 vk_to_isl_color(att_state
->clear_value
.color
));
4152 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4153 } else if (clear_layer_count
> 0) {
4154 assert(image
->n_planes
== 1);
4155 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4156 att_state
->aux_usage
,
4157 iview
->planes
[0].isl
.format
,
4158 iview
->planes
[0].isl
.swizzle
,
4159 iview
->planes
[0].isl
.base_level
,
4160 base_clear_layer
, clear_layer_count
,
4162 vk_to_isl_color(att_state
->clear_value
.color
));
4164 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
4165 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4166 if (att_state
->fast_clear
&& !is_multiview
) {
4167 /* We currently only support HiZ for single-layer images */
4168 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4169 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
4170 assert(iview
->planes
[0].isl
.base_level
== 0);
4171 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4172 assert(fb
->layers
== 1);
4175 anv_image_hiz_clear(cmd_buffer
, image
,
4176 att_state
->pending_clear_aspects
,
4177 iview
->planes
[0].isl
.base_level
,
4178 iview
->planes
[0].isl
.base_array_layer
,
4179 fb
->layers
, render_area
,
4180 att_state
->clear_value
.depthStencil
.stencil
);
4181 } else if (is_multiview
) {
4182 uint32_t pending_clear_mask
=
4183 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4186 for_each_bit(layer_idx
, pending_clear_mask
) {
4188 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4190 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4191 att_state
->pending_clear_aspects
,
4192 att_state
->aux_usage
,
4193 iview
->planes
[0].isl
.base_level
,
4196 att_state
->clear_value
.depthStencil
.depth
,
4197 att_state
->clear_value
.depthStencil
.stencil
);
4200 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4202 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4203 att_state
->pending_clear_aspects
,
4204 att_state
->aux_usage
,
4205 iview
->planes
[0].isl
.base_level
,
4206 iview
->planes
[0].isl
.base_array_layer
,
4207 fb
->layers
, render_area
,
4208 att_state
->clear_value
.depthStencil
.depth
,
4209 att_state
->clear_value
.depthStencil
.stencil
);
4212 assert(att_state
->pending_clear_aspects
== 0);
4216 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4217 image
->planes
[0].aux_surface
.isl
.size_B
> 0 &&
4218 iview
->planes
[0].isl
.base_level
== 0 &&
4219 iview
->planes
[0].isl
.base_array_layer
== 0) {
4220 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
4221 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
4222 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4223 false /* copy to ss */);
4226 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
4227 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
4228 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
4229 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4230 false /* copy to ss */);
4234 if (subpass
->attachments
[i
].usage
==
4235 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
4236 /* We assume that if we're starting a subpass, we're going to do some
4237 * rendering so we may end up with compressed data.
4239 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
4240 VK_IMAGE_ASPECT_COLOR_BIT
,
4241 att_state
->aux_usage
,
4242 iview
->planes
[0].isl
.base_level
,
4243 iview
->planes
[0].isl
.base_array_layer
,
4245 } else if (subpass
->attachments
[i
].usage
==
4246 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
4247 /* We may be writing depth or stencil so we need to mark the surface.
4248 * Unfortunately, there's no way to know at this point whether the
4249 * depth or stencil tests used will actually write to the surface.
4251 * Even though stencil may be plane 1, it always shares a base_level
4254 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
4255 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4256 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4257 VK_IMAGE_ASPECT_DEPTH_BIT
,
4258 att_state
->aux_usage
,
4259 ds_view
->base_level
,
4260 ds_view
->base_array_layer
,
4263 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4264 /* Even though stencil may be plane 1, it always shares a
4265 * base_level with depth.
4267 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4268 VK_IMAGE_ASPECT_STENCIL_BIT
,
4270 ds_view
->base_level
,
4271 ds_view
->base_array_layer
,
4276 /* If multiview is enabled, then we are only done clearing when we no
4277 * longer have pending layers to clear, or when we have processed the
4278 * last subpass that uses this attachment.
4280 if (!is_multiview
||
4281 att_state
->pending_clear_views
== 0 ||
4282 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
4283 att_state
->pending_clear_aspects
= 0;
4286 att_state
->pending_load_aspects
= 0;
4289 cmd_buffer_emit_depth_stencil(cmd_buffer
);
4292 static enum blorp_filter
4293 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
4296 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
4297 return BLORP_FILTER_SAMPLE_0
;
4298 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
4299 return BLORP_FILTER_AVERAGE
;
4300 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
4301 return BLORP_FILTER_MIN_SAMPLE
;
4302 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
4303 return BLORP_FILTER_MAX_SAMPLE
;
4305 return BLORP_FILTER_NONE
;
4310 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
4312 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4313 struct anv_subpass
*subpass
= cmd_state
->subpass
;
4314 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
4315 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4317 if (subpass
->has_color_resolve
) {
4318 /* We are about to do some MSAA resolves. We need to flush so that the
4319 * result of writes to the MSAA color attachments show up in the sampler
4320 * when we blit to the single-sampled resolve target.
4322 cmd_buffer
->state
.pending_pipe_bits
|=
4323 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4324 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
4326 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
4327 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
4328 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
4330 if (dst_att
== VK_ATTACHMENT_UNUSED
)
4333 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4334 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4336 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4337 /* From the Vulkan 1.0 spec:
4339 * If the first use of an attachment in a render pass is as a
4340 * resolve attachment, then the loadOp is effectively ignored
4341 * as the resolve is guaranteed to overwrite all pixels in the
4344 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4347 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
4348 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
4350 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4352 enum isl_aux_usage src_aux_usage
=
4353 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
4354 enum isl_aux_usage dst_aux_usage
=
4355 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
4357 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
4358 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
4360 anv_image_msaa_resolve(cmd_buffer
,
4361 src_iview
->image
, src_aux_usage
,
4362 src_iview
->planes
[0].isl
.base_level
,
4363 src_iview
->planes
[0].isl
.base_array_layer
,
4364 dst_iview
->image
, dst_aux_usage
,
4365 dst_iview
->planes
[0].isl
.base_level
,
4366 dst_iview
->planes
[0].isl
.base_array_layer
,
4367 VK_IMAGE_ASPECT_COLOR_BIT
,
4368 render_area
.offset
.x
, render_area
.offset
.y
,
4369 render_area
.offset
.x
, render_area
.offset
.y
,
4370 render_area
.extent
.width
,
4371 render_area
.extent
.height
,
4372 fb
->layers
, BLORP_FILTER_NONE
);
4376 if (subpass
->ds_resolve_attachment
) {
4377 /* We are about to do some MSAA resolves. We need to flush so that the
4378 * result of writes to the MSAA depth attachments show up in the sampler
4379 * when we blit to the single-sampled resolve target.
4381 cmd_buffer
->state
.pending_pipe_bits
|=
4382 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4383 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
4385 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
4386 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
4388 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4389 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4391 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4392 /* From the Vulkan 1.0 spec:
4394 * If the first use of an attachment in a render pass is as a
4395 * resolve attachment, then the loadOp is effectively ignored
4396 * as the resolve is guaranteed to overwrite all pixels in the
4399 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4402 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
4403 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
4405 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4407 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
4408 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4410 struct anv_attachment_state
*src_state
=
4411 &cmd_state
->attachments
[src_att
];
4412 struct anv_attachment_state
*dst_state
=
4413 &cmd_state
->attachments
[dst_att
];
4415 /* MSAA resolves sample from the source attachment. Transition the
4416 * depth attachment first to get rid of any HiZ that we may not be
4419 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
4420 src_state
->current_layout
,
4421 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4422 src_state
->aux_usage
=
4423 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
4424 VK_IMAGE_ASPECT_DEPTH_BIT
,
4425 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4426 src_state
->current_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
4428 /* MSAA resolves write to the resolve attachment as if it were any
4429 * other transfer op. Transition the resolve attachment accordingly.
4431 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
4433 /* If our render area is the entire size of the image, we're going to
4434 * blow it all away so we can claim the initial layout is UNDEFINED
4435 * and we'll get a HiZ ambiguate instead of a resolve.
4437 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
4438 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
4439 render_area
.extent
.width
== dst_iview
->extent
.width
&&
4440 render_area
.extent
.height
== dst_iview
->extent
.height
)
4441 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
4443 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
4445 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4446 dst_state
->aux_usage
=
4447 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
4448 VK_IMAGE_ASPECT_DEPTH_BIT
,
4449 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4450 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
4452 enum blorp_filter filter
=
4453 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
4455 anv_image_msaa_resolve(cmd_buffer
,
4456 src_iview
->image
, src_state
->aux_usage
,
4457 src_iview
->planes
[0].isl
.base_level
,
4458 src_iview
->planes
[0].isl
.base_array_layer
,
4459 dst_iview
->image
, dst_state
->aux_usage
,
4460 dst_iview
->planes
[0].isl
.base_level
,
4461 dst_iview
->planes
[0].isl
.base_array_layer
,
4462 VK_IMAGE_ASPECT_DEPTH_BIT
,
4463 render_area
.offset
.x
, render_area
.offset
.y
,
4464 render_area
.offset
.x
, render_area
.offset
.y
,
4465 render_area
.extent
.width
,
4466 render_area
.extent
.height
,
4467 fb
->layers
, filter
);
4470 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
4471 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4473 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
4474 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
4476 enum blorp_filter filter
=
4477 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
4479 anv_image_msaa_resolve(cmd_buffer
,
4480 src_iview
->image
, src_aux_usage
,
4481 src_iview
->planes
[0].isl
.base_level
,
4482 src_iview
->planes
[0].isl
.base_array_layer
,
4483 dst_iview
->image
, dst_aux_usage
,
4484 dst_iview
->planes
[0].isl
.base_level
,
4485 dst_iview
->planes
[0].isl
.base_array_layer
,
4486 VK_IMAGE_ASPECT_STENCIL_BIT
,
4487 render_area
.offset
.x
, render_area
.offset
.y
,
4488 render_area
.offset
.x
, render_area
.offset
.y
,
4489 render_area
.extent
.width
,
4490 render_area
.extent
.height
,
4491 fb
->layers
, filter
);
4495 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4496 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4497 if (a
== VK_ATTACHMENT_UNUSED
)
4500 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4503 assert(a
< cmd_state
->pass
->attachment_count
);
4504 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4505 struct anv_image_view
*iview
= fb
->attachments
[a
];
4506 const struct anv_image
*image
= iview
->image
;
4508 if ((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4509 image
->vk_format
!= iview
->vk_format
) {
4510 enum anv_fast_clear_type fast_clear_type
=
4511 anv_layout_to_fast_clear_type(&cmd_buffer
->device
->info
,
4512 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4513 att_state
->current_layout
);
4515 /* If any clear color was used, flush it down the aux surfaces. If we
4516 * don't do it now using the view's format we might use the clear
4517 * color incorrectly in the following resolves (for example with an
4518 * SRGB view & a UNORM image).
4520 if (fast_clear_type
!= ANV_FAST_CLEAR_NONE
) {
4521 anv_perf_warn(cmd_buffer
->device
->instance
, fb
,
4522 "Doing a partial resolve to get rid of clear color at the "
4523 "end of a renderpass due to an image/view format mismatch");
4525 uint32_t base_layer
, layer_count
;
4526 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4528 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4529 iview
->planes
[0].isl
.base_level
);
4531 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4532 layer_count
= fb
->layers
;
4535 for (uint32_t a
= 0; a
< layer_count
; a
++) {
4536 uint32_t array_layer
= base_layer
+ a
;
4537 if (image
->samples
== 1) {
4538 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
4539 iview
->planes
[0].isl
.format
,
4540 VK_IMAGE_ASPECT_COLOR_BIT
,
4541 iview
->planes
[0].isl
.base_level
,
4543 ISL_AUX_OP_PARTIAL_RESOLVE
,
4544 ANV_FAST_CLEAR_NONE
);
4546 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
4547 iview
->planes
[0].isl
.format
,
4548 VK_IMAGE_ASPECT_COLOR_BIT
,
4550 ISL_AUX_OP_PARTIAL_RESOLVE
,
4551 ANV_FAST_CLEAR_NONE
);
4557 /* Transition the image into the final layout for this render pass */
4558 VkImageLayout target_layout
=
4559 cmd_state
->pass
->attachments
[a
].final_layout
;
4561 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4562 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4564 uint32_t base_layer
, layer_count
;
4565 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4567 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4568 iview
->planes
[0].isl
.base_level
);
4570 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4571 layer_count
= fb
->layers
;
4574 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4575 iview
->planes
[0].isl
.base_level
, 1,
4576 base_layer
, layer_count
,
4577 att_state
->current_layout
, target_layout
);
4578 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4579 transition_depth_buffer(cmd_buffer
, image
,
4580 att_state
->current_layout
, target_layout
);
4584 /* Accumulate any subpass flushes that need to happen after the subpass.
4585 * Yes, they do get accumulated twice in the NextSubpass case but since
4586 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
4587 * ORing the bits in twice so it's harmless.
4589 cmd_buffer
->state
.pending_pipe_bits
|=
4590 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
4593 void genX(CmdBeginRenderPass
)(
4594 VkCommandBuffer commandBuffer
,
4595 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4596 VkSubpassContents contents
)
4598 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4599 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4600 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4602 cmd_buffer
->state
.framebuffer
= framebuffer
;
4603 cmd_buffer
->state
.pass
= pass
;
4604 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4606 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
4608 /* If we failed to setup the attachments we should not try to go further */
4609 if (result
!= VK_SUCCESS
) {
4610 assert(anv_batch_has_error(&cmd_buffer
->batch
));
4614 genX(flush_pipeline_select_3d
)(cmd_buffer
);
4616 cmd_buffer_begin_subpass(cmd_buffer
, 0);
4619 void genX(CmdBeginRenderPass2KHR
)(
4620 VkCommandBuffer commandBuffer
,
4621 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4622 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
4624 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
4625 pSubpassBeginInfo
->contents
);
4628 void genX(CmdNextSubpass
)(
4629 VkCommandBuffer commandBuffer
,
4630 VkSubpassContents contents
)
4632 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4634 if (anv_batch_has_error(&cmd_buffer
->batch
))
4637 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4639 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
4640 cmd_buffer_end_subpass(cmd_buffer
);
4641 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4644 void genX(CmdNextSubpass2KHR
)(
4645 VkCommandBuffer commandBuffer
,
4646 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
4647 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4649 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
4652 void genX(CmdEndRenderPass
)(
4653 VkCommandBuffer commandBuffer
)
4655 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4657 if (anv_batch_has_error(&cmd_buffer
->batch
))
4660 cmd_buffer_end_subpass(cmd_buffer
);
4662 cmd_buffer
->state
.hiz_enabled
= false;
4665 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
4668 /* Remove references to render pass specific state. This enables us to
4669 * detect whether or not we're in a renderpass.
4671 cmd_buffer
->state
.framebuffer
= NULL
;
4672 cmd_buffer
->state
.pass
= NULL
;
4673 cmd_buffer
->state
.subpass
= NULL
;
4676 void genX(CmdEndRenderPass2KHR
)(
4677 VkCommandBuffer commandBuffer
,
4678 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4680 genX(CmdEndRenderPass
)(commandBuffer
);
4684 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
4686 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4687 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(ANV_PREDICATE_RESULT_REG
));
4688 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
4689 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
4690 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
4692 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
4693 mip
.LoadOperation
= LOAD_LOADINV
;
4694 mip
.CombineOperation
= COMBINE_SET
;
4695 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4700 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4701 void genX(CmdBeginConditionalRenderingEXT
)(
4702 VkCommandBuffer commandBuffer
,
4703 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
4705 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4706 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
4707 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4708 struct anv_address value_address
=
4709 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
4711 const bool isInverted
= pConditionalRenderingBegin
->flags
&
4712 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
4714 cmd_state
->conditional_render_enabled
= true;
4716 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4718 /* Section 19.4 of the Vulkan 1.1.85 spec says:
4720 * If the value of the predicate in buffer memory changes
4721 * while conditional rendering is active, the rendering commands
4722 * may be discarded in an implementation-dependent way.
4723 * Some implementations may latch the value of the predicate
4724 * upon beginning conditional rendering while others
4725 * may read it before every rendering command.
4727 * So it's perfectly fine to read a value from the buffer once.
4729 emit_lrm(&cmd_buffer
->batch
, CS_GPR(MI_ALU_REG0
), value_address
);
4730 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
4731 emit_lri(&cmd_buffer
->batch
, CS_GPR(MI_ALU_REG0
) + 4, 0);
4733 /* Precompute predicate result, it is necessary to support secondary
4734 * command buffers since it is unknown if conditional rendering is
4735 * inverted when populating them.
4737 uint32_t *dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
4738 dw
[1] = mi_alu(MI_ALU_LOAD0
, MI_ALU_SRCA
, 0);
4739 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG0
);
4740 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
4741 dw
[4] = mi_alu(isInverted
? MI_ALU_STOREINV
: MI_ALU_STORE
,
4742 ANV_PREDICATE_RESULT_REG
, MI_ALU_CF
);
4745 void genX(CmdEndConditionalRenderingEXT
)(
4746 VkCommandBuffer commandBuffer
)
4748 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4749 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4751 cmd_state
->conditional_render_enabled
= false;