2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "common/gen_l3_config.h"
31 #include "genxml/gen_macros.h"
32 #include "genxml/genX_pack.h"
35 emit_lrm(struct anv_batch
*batch
,
36 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
38 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
39 lrm
.RegisterAddress
= reg
;
40 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
45 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
47 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
48 lri
.RegisterOffset
= reg
;
54 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
56 struct anv_device
*device
= cmd_buffer
->device
;
58 /* XXX: Do we need this on more than just BDW? */
60 /* Emit a render target cache flush.
62 * This isn't documented anywhere in the PRM. However, it seems to be
63 * necessary prior to changing the surface state base adress. Without
64 * this, we get GPU hangs when using multi-level command buffers which
65 * clear depth, reset state base address, and then go render stuff.
67 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
68 pc
.RenderTargetCacheFlushEnable
= true;
72 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
73 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
74 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
75 sba
.GeneralStateBaseAddressModifyEnable
= true;
77 sba
.SurfaceStateBaseAddress
=
78 anv_cmd_buffer_surface_base_address(cmd_buffer
);
79 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
80 sba
.SurfaceStateBaseAddressModifyEnable
= true;
82 sba
.DynamicStateBaseAddress
=
83 (struct anv_address
) { &device
->dynamic_state_block_pool
.bo
, 0 };
84 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
85 sba
.DynamicStateBaseAddressModifyEnable
= true;
87 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
88 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
89 sba
.IndirectObjectBaseAddressModifyEnable
= true;
91 sba
.InstructionBaseAddress
=
92 (struct anv_address
) { &device
->instruction_block_pool
.bo
, 0 };
93 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
94 sba
.InstructionBaseAddressModifyEnable
= true;
97 /* Broadwell requires that we specify a buffer size for a bunch of
98 * these fields. However, since we will be growing the BO's live, we
99 * just set them all to the maximum.
101 sba
.GeneralStateBufferSize
= 0xfffff;
102 sba
.GeneralStateBufferSizeModifyEnable
= true;
103 sba
.DynamicStateBufferSize
= 0xfffff;
104 sba
.DynamicStateBufferSizeModifyEnable
= true;
105 sba
.IndirectObjectBufferSize
= 0xfffff;
106 sba
.IndirectObjectBufferSizeModifyEnable
= true;
107 sba
.InstructionBufferSize
= 0xfffff;
108 sba
.InstructionBuffersizeModifyEnable
= true;
112 /* After re-setting the surface state base address, we have to do some
113 * cache flusing so that the sampler engine will pick up the new
114 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
115 * Shared Function > 3D Sampler > State > State Caching (page 96):
117 * Coherency with system memory in the state cache, like the texture
118 * cache is handled partially by software. It is expected that the
119 * command stream or shader will issue Cache Flush operation or
120 * Cache_Flush sampler message to ensure that the L1 cache remains
121 * coherent with system memory.
125 * Whenever the value of the Dynamic_State_Base_Addr,
126 * Surface_State_Base_Addr are altered, the L1 state cache must be
127 * invalidated to ensure the new surface or sampler state is fetched
128 * from system memory.
130 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
131 * which, according the PIPE_CONTROL instruction documentation in the
134 * Setting this bit is independent of any other bit in this packet.
135 * This bit controls the invalidation of the L1 and L2 state caches
136 * at the top of the pipe i.e. at the parsing time.
138 * Unfortunately, experimentation seems to indicate that state cache
139 * invalidation through a PIPE_CONTROL does nothing whatsoever in
140 * regards to surface state and binding tables. In stead, it seems that
141 * invalidating the texture cache is what is actually needed.
143 * XXX: As far as we have been able to determine through
144 * experimentation, shows that flush the texture cache appears to be
145 * sufficient. The theory here is that all of the sampling/rendering
146 * units cache the binding table in the texture cache. However, we have
147 * yet to be able to actually confirm this.
149 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
150 pc
.TextureCacheInvalidationEnable
= true;
155 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
156 struct anv_state state
,
157 struct anv_bo
*bo
, uint32_t offset
)
159 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
161 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
162 state
.offset
+ isl_dev
->ss
.addr_offset
, bo
, offset
);
166 add_image_view_relocs(struct anv_cmd_buffer
*cmd_buffer
,
167 const struct anv_image_view
*iview
,
168 enum isl_aux_usage aux_usage
,
169 struct anv_state state
)
171 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
173 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
174 state
.offset
+ isl_dev
->ss
.addr_offset
,
175 iview
->bo
, iview
->offset
);
177 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
178 uint32_t aux_offset
= iview
->offset
+ iview
->image
->aux_surface
.offset
;
180 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
181 * used to store other information. This should be ok, however, because
182 * surface buffer addresses are always 4K page alinged.
184 assert((aux_offset
& 0xfff) == 0);
185 uint32_t *aux_addr_dw
= state
.map
+ isl_dev
->ss
.aux_addr_offset
;
186 aux_offset
+= *aux_addr_dw
& 0xfff;
188 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
189 state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
190 iview
->bo
, aux_offset
);
194 static enum isl_aux_usage
195 fb_attachment_get_aux_usage(struct anv_device
*device
,
196 struct anv_framebuffer
*fb
,
199 struct anv_image_view
*iview
= fb
->attachments
[attachment
];
201 if (iview
->image
->aux_surface
.isl
.size
== 0)
202 return ISL_AUX_USAGE_NONE
; /* No aux surface */
204 assert(iview
->image
->aux_surface
.isl
.usage
& ISL_SURF_USAGE_CCS_BIT
);
206 if (isl_format_supports_lossless_compression(&device
->info
,
208 return ISL_AUX_USAGE_CCS_E
;
210 return ISL_AUX_USAGE_NONE
;
214 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
217 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
218 struct anv_render_pass
*pass
,
219 struct anv_framebuffer
*framebuffer
,
220 const VkClearValue
*clear_values
)
222 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
223 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
225 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
227 if (pass
->attachment_count
== 0) {
228 state
->attachments
= NULL
;
232 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
233 pass
->attachment_count
*
234 sizeof(state
->attachments
[0]),
235 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
236 if (state
->attachments
== NULL
) {
237 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
241 bool need_null_state
= false;
242 unsigned num_states
= 0;
243 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
244 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
247 /* We need a null state for any depth-stencil-only subpasses.
248 * Importantly, this includes depth/stencil clears so we create one
249 * whenever we have depth or stencil
251 need_null_state
= true;
254 num_states
+= need_null_state
;
256 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
257 state
->render_pass_states
=
258 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
259 num_states
* ss_stride
, isl_dev
->ss
.align
);
261 struct anv_state next_state
= state
->render_pass_states
;
262 next_state
.alloc_size
= isl_dev
->ss
.size
;
264 if (need_null_state
) {
265 state
->null_surface_state
= next_state
;
266 next_state
.offset
+= ss_stride
;
267 next_state
.map
+= ss_stride
;
270 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
271 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
272 state
->attachments
[i
].color_rt_state
= next_state
;
273 next_state
.offset
+= ss_stride
;
274 next_state
.map
+= ss_stride
;
277 assert(next_state
.offset
== state
->render_pass_states
.offset
+
278 state
->render_pass_states
.alloc_size
);
281 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
283 if (need_null_state
) {
284 struct GENX(RENDER_SURFACE_STATE
) null_ss
= {
285 .SurfaceType
= SURFTYPE_NULL
,
286 .SurfaceArray
= framebuffer
->layers
> 0,
287 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
291 .TiledSurface
= true,
293 .Width
= framebuffer
->width
- 1,
294 .Height
= framebuffer
->height
- 1,
295 .Depth
= framebuffer
->layers
- 1,
296 .RenderTargetViewExtent
= framebuffer
->layers
- 1,
298 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
->null_surface_state
.map
,
302 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
303 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
304 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
305 VkImageAspectFlags clear_aspects
= 0;
307 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
308 /* color attachment */
309 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
310 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
313 /* depthstencil attachment */
314 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
315 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
316 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
318 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
319 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
320 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
324 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
326 state
->attachments
[i
].clear_value
= clear_values
[i
];
328 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
329 assert(iview
->vk_format
== att
->format
);
331 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
332 state
->attachments
[i
].aux_usage
=
333 fb_attachment_get_aux_usage(cmd_buffer
->device
, framebuffer
, i
);
335 struct isl_view view
= iview
->isl
;
336 view
.usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
337 isl_surf_fill_state(isl_dev
,
338 state
->attachments
[i
].color_rt_state
.map
,
339 .surf
= &iview
->image
->color_surface
.isl
,
341 .aux_surf
= &iview
->image
->aux_surface
.isl
,
342 .aux_usage
= state
->attachments
[i
].aux_usage
,
343 .mocs
= cmd_buffer
->device
->default_mocs
);
345 add_image_view_relocs(cmd_buffer
, iview
,
346 state
->attachments
[i
].aux_usage
,
347 state
->attachments
[i
].color_rt_state
);
349 state
->attachments
[i
].aux_usage
= ISL_AUX_USAGE_NONE
;
353 if (!cmd_buffer
->device
->info
.has_llc
)
354 anv_state_clflush(state
->render_pass_states
);
359 genX(BeginCommandBuffer
)(
360 VkCommandBuffer commandBuffer
,
361 const VkCommandBufferBeginInfo
* pBeginInfo
)
363 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
365 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
366 * command buffer's state. Otherwise, we must *reset* its state. In both
369 * From the Vulkan 1.0 spec:
371 * If a command buffer is in the executable state and the command buffer
372 * was allocated from a command pool with the
373 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
374 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
375 * as if vkResetCommandBuffer had been called with
376 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
377 * the command buffer in the recording state.
379 anv_cmd_buffer_reset(cmd_buffer
);
381 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
383 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
384 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
386 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
388 if (cmd_buffer
->usage_flags
&
389 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
390 cmd_buffer
->state
.pass
=
391 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
392 cmd_buffer
->state
.subpass
=
393 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
394 cmd_buffer
->state
.framebuffer
= NULL
;
396 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, cmd_buffer
->state
.pass
,
399 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
406 genX(EndCommandBuffer
)(
407 VkCommandBuffer commandBuffer
)
409 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
411 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
417 genX(CmdExecuteCommands
)(
418 VkCommandBuffer commandBuffer
,
419 uint32_t commandBufferCount
,
420 const VkCommandBuffer
* pCmdBuffers
)
422 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
424 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
426 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
427 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
429 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
431 if (secondary
->usage_flags
&
432 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
433 /* If we're continuing a render pass from the primary, we need to
434 * copy the surface states for the current subpass into the storage
435 * we allocated for them in BeginCommandBuffer.
437 struct anv_bo
*ss_bo
= &primary
->device
->surface_state_block_pool
.bo
;
438 struct anv_state src_state
= primary
->state
.render_pass_states
;
439 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
440 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
442 genX(cmd_buffer_gpu_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
443 ss_bo
, src_state
.offset
,
444 src_state
.alloc_size
);
447 anv_cmd_buffer_add_secondary(primary
, secondary
);
450 /* Each of the secondary command buffers will use its own state base
451 * address. We need to re-emit state base address for the primary after
452 * all of the secondaries are done.
454 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
457 genX(cmd_buffer_emit_state_base_address
)(primary
);
460 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
461 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
462 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
465 * Program the hardware to use the specified L3 configuration.
468 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
469 const struct gen_l3_config
*cfg
)
472 if (cfg
== cmd_buffer
->state
.current_l3_config
)
475 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
476 fprintf(stderr
, "L3 config transition: ");
477 gen_dump_l3_config(cfg
, stderr
);
480 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
482 /* According to the hardware docs, the L3 partitioning can only be changed
483 * while the pipeline is completely drained and the caches are flushed,
484 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
486 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
487 pc
.DCFlushEnable
= true;
488 pc
.PostSyncOperation
= NoWrite
;
489 pc
.CommandStreamerStallEnable
= true;
492 /* ...followed by a second pipelined PIPE_CONTROL that initiates
493 * invalidation of the relevant caches. Note that because RO invalidation
494 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
495 * command is processed by the CS) we cannot combine it with the previous
496 * stalling flush as the hardware documentation suggests, because that
497 * would cause the CS to stall on previous rendering *after* RO
498 * invalidation and wouldn't prevent the RO caches from being polluted by
499 * concurrent rendering before the stall completes. This intentionally
500 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
501 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
502 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
503 * already guarantee that there is no concurrent GPGPU kernel execution
504 * (see SKL HSD 2132585).
506 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
507 pc
.TextureCacheInvalidationEnable
= true;
508 pc
.ConstantCacheInvalidationEnable
= true;
509 pc
.InstructionCacheInvalidateEnable
= true;
510 pc
.StateCacheInvalidationEnable
= true;
511 pc
.PostSyncOperation
= NoWrite
;
514 /* Now send a third stalling flush to make sure that invalidation is
515 * complete when the L3 configuration registers are modified.
517 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
518 pc
.DCFlushEnable
= true;
519 pc
.PostSyncOperation
= NoWrite
;
520 pc
.CommandStreamerStallEnable
= true;
525 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
528 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
529 .SLMEnable
= has_slm
,
530 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
531 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
532 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
533 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
535 /* Set up the L3 partitioning. */
536 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
540 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
541 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
543 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
545 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
548 assert(!cfg
->n
[GEN_L3P_ALL
]);
550 /* When enabled SLM only uses a portion of the L3 on half of the banks,
551 * the matching space on the remaining banks has to be allocated to a
552 * client (URB for all validated configurations) set to the
553 * lower-bandwidth 2-bank address hashing mode.
555 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
556 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
557 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
559 /* Minimum number of ways that can be allocated to the URB. */
560 const unsigned n0_urb
= (devinfo
->is_baytrail
? 32 : 0);
561 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
563 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
564 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
565 .ConvertDC_UC
= !has_dc
,
566 .ConvertIS_UC
= !has_is
,
567 .ConvertC_UC
= !has_c
,
568 .ConvertT_UC
= !has_t
);
570 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
571 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
572 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
574 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
575 .SLMEnable
= has_slm
,
576 .URBLowBandwidth
= urb_low_bw
,
577 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
579 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
581 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
582 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
584 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
585 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
587 .CAllocation
= cfg
->n
[GEN_L3P_C
],
589 .TAllocation
= cfg
->n
[GEN_L3P_T
],
592 /* Set up the L3 partitioning. */
593 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
594 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
595 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
598 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
599 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
600 * them disabled to avoid crashing the system hard.
602 uint32_t scratch1
, chicken3
;
603 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
604 .L3AtomicDisable
= !has_dc
);
605 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
606 .L3AtomicDisableMask
= true,
607 .L3AtomicDisable
= !has_dc
);
608 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
609 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
615 cmd_buffer
->state
.current_l3_config
= cfg
;
619 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
621 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
623 /* Flushes are pipelined while invalidations are handled immediately.
624 * Therefore, if we're flushing anything then we need to schedule a stall
625 * before any invalidations can happen.
627 if (bits
& ANV_PIPE_FLUSH_BITS
)
628 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
630 /* If we're going to do an invalidate and we have a pending CS stall that
631 * has yet to be resolved, we do the CS stall now.
633 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
634 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
635 bits
|= ANV_PIPE_CS_STALL_BIT
;
636 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
639 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
640 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
641 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
642 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
643 pipe
.RenderTargetCacheFlushEnable
=
644 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
646 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
647 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
648 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
651 * According to the Broadwell documentation, any PIPE_CONTROL with the
652 * "Command Streamer Stall" bit set must also have another bit set,
653 * with five different options:
655 * - Render Target Cache Flush
656 * - Depth Cache Flush
657 * - Stall at Pixel Scoreboard
658 * - Post-Sync Operation
662 * I chose "Stall at Pixel Scoreboard" since that's what we use in
663 * mesa and it seems to work fine. The choice is fairly arbitrary.
665 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
666 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
667 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
668 pipe
.StallAtPixelScoreboard
= true;
671 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
674 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
675 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
676 pipe
.StateCacheInvalidationEnable
=
677 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
678 pipe
.ConstantCacheInvalidationEnable
=
679 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
680 pipe
.VFCacheInvalidationEnable
=
681 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
682 pipe
.TextureCacheInvalidationEnable
=
683 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
684 pipe
.InstructionCacheInvalidateEnable
=
685 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
688 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
691 cmd_buffer
->state
.pending_pipe_bits
= bits
;
694 void genX(CmdPipelineBarrier
)(
695 VkCommandBuffer commandBuffer
,
696 VkPipelineStageFlags srcStageMask
,
697 VkPipelineStageFlags destStageMask
,
699 uint32_t memoryBarrierCount
,
700 const VkMemoryBarrier
* pMemoryBarriers
,
701 uint32_t bufferMemoryBarrierCount
,
702 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
703 uint32_t imageMemoryBarrierCount
,
704 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
706 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
709 /* XXX: Right now, we're really dumb and just flush whatever categories
710 * the app asks for. One of these days we may make this a bit better
711 * but right now that's all the hardware allows for in most areas.
713 VkAccessFlags src_flags
= 0;
714 VkAccessFlags dst_flags
= 0;
716 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
717 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
718 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
721 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
722 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
723 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
726 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
727 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
728 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
731 enum anv_pipe_bits pipe_bits
= 0;
733 for_each_bit(b
, src_flags
) {
734 switch ((VkAccessFlagBits
)(1 << b
)) {
735 case VK_ACCESS_SHADER_WRITE_BIT
:
736 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
738 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
739 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
741 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
742 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
744 case VK_ACCESS_TRANSFER_WRITE_BIT
:
745 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
746 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
749 break; /* Nothing to do */
753 for_each_bit(b
, dst_flags
) {
754 switch ((VkAccessFlagBits
)(1 << b
)) {
755 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
756 case VK_ACCESS_INDEX_READ_BIT
:
757 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
758 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
760 case VK_ACCESS_UNIFORM_READ_BIT
:
761 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
762 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
764 case VK_ACCESS_SHADER_READ_BIT
:
765 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
766 case VK_ACCESS_TRANSFER_READ_BIT
:
767 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
770 break; /* Nothing to do */
774 cmd_buffer
->state
.pending_pipe_bits
|= pipe_bits
;
778 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
780 VkShaderStageFlags stages
= cmd_buffer
->state
.pipeline
->active_stages
;
782 /* In order to avoid thrash, we assume that vertex and fragment stages
783 * always exist. In the rare case where one is missing *and* the other
784 * uses push concstants, this may be suboptimal. However, avoiding stalls
785 * seems more important.
787 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
789 if (stages
== cmd_buffer
->state
.push_constant_stages
)
793 const unsigned push_constant_kb
= 32;
795 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
797 const unsigned push_constant_kb
= 16;
800 const unsigned num_stages
=
801 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
802 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
804 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
805 * units of 2KB. Incidentally, these are the same platforms that have
806 * 32KB worth of push constant space.
808 if (push_constant_kb
== 32)
809 size_per_stage
&= ~1u;
811 uint32_t kb_used
= 0;
812 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
813 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
814 anv_batch_emit(&cmd_buffer
->batch
,
815 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
816 alloc
._3DCommandSubOpcode
= 18 + i
;
817 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
818 alloc
.ConstantBufferSize
= push_size
;
820 kb_used
+= push_size
;
823 anv_batch_emit(&cmd_buffer
->batch
,
824 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
825 alloc
.ConstantBufferOffset
= kb_used
;
826 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
829 cmd_buffer
->state
.push_constant_stages
= stages
;
831 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
833 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
834 * the next 3DPRIMITIVE command after programming the
835 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
837 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
838 * pipeline setup, we need to dirty push constants.
840 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
844 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
845 gl_shader_stage stage
,
846 struct anv_state
*bt_state
)
848 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
849 struct anv_pipeline
*pipeline
;
850 uint32_t bias
, state_offset
;
853 case MESA_SHADER_COMPUTE
:
854 pipeline
= cmd_buffer
->state
.compute_pipeline
;
858 pipeline
= cmd_buffer
->state
.pipeline
;
863 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
864 *bt_state
= (struct anv_state
) { 0, };
868 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
869 if (bias
+ map
->surface_count
== 0) {
870 *bt_state
= (struct anv_state
) { 0, };
874 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
875 bias
+ map
->surface_count
,
877 uint32_t *bt_map
= bt_state
->map
;
879 if (bt_state
->map
== NULL
)
880 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
882 if (stage
== MESA_SHADER_COMPUTE
&&
883 get_cs_prog_data(cmd_buffer
->state
.compute_pipeline
)->uses_num_work_groups
) {
884 struct anv_bo
*bo
= cmd_buffer
->state
.num_workgroups_bo
;
885 uint32_t bo_offset
= cmd_buffer
->state
.num_workgroups_offset
;
887 struct anv_state surface_state
;
889 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
891 const enum isl_format format
=
892 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
893 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
894 format
, bo_offset
, 12, 1);
896 bt_map
[0] = surface_state
.offset
+ state_offset
;
897 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
900 if (map
->surface_count
== 0)
903 if (map
->image_count
> 0) {
905 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
906 if (result
!= VK_SUCCESS
)
909 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
913 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
914 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
916 struct anv_state surface_state
;
918 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
919 /* Color attachment binding */
920 assert(stage
== MESA_SHADER_FRAGMENT
);
921 assert(binding
->binding
== 0);
922 if (binding
->index
< subpass
->color_count
) {
923 const unsigned att
= subpass
->color_attachments
[binding
->index
];
924 surface_state
= cmd_buffer
->state
.attachments
[att
].color_rt_state
;
926 surface_state
= cmd_buffer
->state
.null_surface_state
;
929 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
933 struct anv_descriptor_set
*set
=
934 cmd_buffer
->state
.descriptors
[binding
->set
];
935 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
936 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
938 switch (desc
->type
) {
939 case VK_DESCRIPTOR_TYPE_SAMPLER
:
940 /* Nothing for us to do here */
943 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
944 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
945 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
946 surface_state
= desc
->image_view
->sampler_surface_state
;
947 assert(surface_state
.alloc_size
);
948 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
949 desc
->image_view
->image
->aux_usage
,
953 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
954 surface_state
= desc
->image_view
->storage_surface_state
;
955 assert(surface_state
.alloc_size
);
956 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
957 desc
->image_view
->image
->aux_usage
,
960 struct brw_image_param
*image_param
=
961 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
963 *image_param
= desc
->image_view
->storage_image_param
;
964 image_param
->surface_idx
= bias
+ s
;
968 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
969 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
970 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
971 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
972 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
973 surface_state
= desc
->buffer_view
->surface_state
;
974 assert(surface_state
.alloc_size
);
975 add_surface_state_reloc(cmd_buffer
, surface_state
,
976 desc
->buffer_view
->bo
,
977 desc
->buffer_view
->offset
);
980 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
981 surface_state
= desc
->buffer_view
->storage_surface_state
;
982 assert(surface_state
.alloc_size
);
983 add_surface_state_reloc(cmd_buffer
, surface_state
,
984 desc
->buffer_view
->bo
,
985 desc
->buffer_view
->offset
);
987 struct brw_image_param
*image_param
=
988 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
990 *image_param
= desc
->buffer_view
->storage_image_param
;
991 image_param
->surface_idx
= bias
+ s
;
995 assert(!"Invalid descriptor type");
999 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1001 assert(image
== map
->image_count
);
1004 if (!cmd_buffer
->device
->info
.has_llc
)
1005 anv_state_clflush(*bt_state
);
1011 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
1012 gl_shader_stage stage
,
1013 struct anv_state
*state
)
1015 struct anv_pipeline
*pipeline
;
1017 if (stage
== MESA_SHADER_COMPUTE
)
1018 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1020 pipeline
= cmd_buffer
->state
.pipeline
;
1022 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1023 *state
= (struct anv_state
) { 0, };
1027 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1028 if (map
->sampler_count
== 0) {
1029 *state
= (struct anv_state
) { 0, };
1033 uint32_t size
= map
->sampler_count
* 16;
1034 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
1036 if (state
->map
== NULL
)
1037 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1039 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
1040 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
1041 struct anv_descriptor_set
*set
=
1042 cmd_buffer
->state
.descriptors
[binding
->set
];
1043 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1044 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1046 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
1047 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
1050 struct anv_sampler
*sampler
= desc
->sampler
;
1052 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
1053 * happens to be zero.
1055 if (sampler
== NULL
)
1058 memcpy(state
->map
+ (s
* 16),
1059 sampler
->state
, sizeof(sampler
->state
));
1062 if (!cmd_buffer
->device
->info
.has_llc
)
1063 anv_state_clflush(*state
);
1069 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
1071 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
1072 cmd_buffer
->state
.pipeline
->active_stages
;
1074 VkResult result
= VK_SUCCESS
;
1075 anv_foreach_stage(s
, dirty
) {
1076 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1077 if (result
!= VK_SUCCESS
)
1079 result
= emit_binding_table(cmd_buffer
, s
,
1080 &cmd_buffer
->state
.binding_tables
[s
]);
1081 if (result
!= VK_SUCCESS
)
1085 if (result
!= VK_SUCCESS
) {
1086 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1088 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1089 assert(result
== VK_SUCCESS
);
1091 /* Re-emit state base addresses so we get the new surface state base
1092 * address before we start emitting binding tables etc.
1094 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1096 /* Re-emit all active binding tables */
1097 dirty
|= cmd_buffer
->state
.pipeline
->active_stages
;
1098 anv_foreach_stage(s
, dirty
) {
1099 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1100 if (result
!= VK_SUCCESS
)
1102 result
= emit_binding_table(cmd_buffer
, s
,
1103 &cmd_buffer
->state
.binding_tables
[s
]);
1104 if (result
!= VK_SUCCESS
)
1109 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
1115 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
1118 static const uint32_t sampler_state_opcodes
[] = {
1119 [MESA_SHADER_VERTEX
] = 43,
1120 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
1121 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
1122 [MESA_SHADER_GEOMETRY
] = 46,
1123 [MESA_SHADER_FRAGMENT
] = 47,
1124 [MESA_SHADER_COMPUTE
] = 0,
1127 static const uint32_t binding_table_opcodes
[] = {
1128 [MESA_SHADER_VERTEX
] = 38,
1129 [MESA_SHADER_TESS_CTRL
] = 39,
1130 [MESA_SHADER_TESS_EVAL
] = 40,
1131 [MESA_SHADER_GEOMETRY
] = 41,
1132 [MESA_SHADER_FRAGMENT
] = 42,
1133 [MESA_SHADER_COMPUTE
] = 0,
1136 anv_foreach_stage(s
, stages
) {
1137 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
1138 anv_batch_emit(&cmd_buffer
->batch
,
1139 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
1140 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
1141 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
1145 /* Always emit binding table pointers if we're asked to, since on SKL
1146 * this is what flushes push constants. */
1147 anv_batch_emit(&cmd_buffer
->batch
,
1148 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
1149 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
1150 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
1156 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1158 static const uint32_t push_constant_opcodes
[] = {
1159 [MESA_SHADER_VERTEX
] = 21,
1160 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
1161 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
1162 [MESA_SHADER_GEOMETRY
] = 22,
1163 [MESA_SHADER_FRAGMENT
] = 23,
1164 [MESA_SHADER_COMPUTE
] = 0,
1167 VkShaderStageFlags flushed
= 0;
1169 anv_foreach_stage(stage
, cmd_buffer
->state
.push_constants_dirty
) {
1170 if (stage
== MESA_SHADER_COMPUTE
)
1173 struct anv_state state
= anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
1175 if (state
.offset
== 0) {
1176 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
)
1177 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
1179 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
1180 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
],
1181 c
.ConstantBody
= (struct GENX(3DSTATE_CONSTANT_BODY
)) {
1183 .PointerToConstantBuffer2
= { &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, state
.offset
},
1184 .ConstantBuffer2ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1186 .PointerToConstantBuffer0
= { .offset
= state
.offset
},
1187 .ConstantBuffer0ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1193 flushed
|= mesa_to_vk_shader_stage(stage
);
1196 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_ALL_GRAPHICS
;
1202 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1204 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1207 uint32_t vb_emit
= cmd_buffer
->state
.vb_dirty
& pipeline
->vb_used
;
1209 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
1211 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1213 genX(flush_pipeline_select_3d
)(cmd_buffer
);
1216 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
1217 const uint32_t num_dwords
= 1 + num_buffers
* 4;
1219 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
1220 GENX(3DSTATE_VERTEX_BUFFERS
));
1222 for_each_bit(vb
, vb_emit
) {
1223 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1224 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
1226 struct GENX(VERTEX_BUFFER_STATE
) state
= {
1227 .VertexBufferIndex
= vb
,
1230 .MemoryObjectControlState
= GENX(MOCS
),
1232 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
1233 .InstanceDataStepRate
= 1,
1234 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1237 .AddressModifyEnable
= true,
1238 .BufferPitch
= pipeline
->binding_stride
[vb
],
1239 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
1242 .BufferSize
= buffer
->size
- offset
1244 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
1248 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
1253 cmd_buffer
->state
.vb_dirty
&= ~vb_emit
;
1255 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1256 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1258 /* The exact descriptor layout is pulled from the pipeline, so we need
1259 * to re-emit binding tables on every pipeline change.
1261 cmd_buffer
->state
.descriptors_dirty
|=
1262 cmd_buffer
->state
.pipeline
->active_stages
;
1264 /* If the pipeline changed, we may need to re-allocate push constant
1267 cmd_buffer_alloc_push_constants(cmd_buffer
);
1271 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
1272 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
1273 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
1275 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
1276 * stall needs to be sent just prior to any 3DSTATE_VS,
1277 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
1278 * 3DSTATE_BINDING_TABLE_POINTER_VS,
1279 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
1280 * PIPE_CONTROL needs to be sent before any combination of VS
1281 * associated 3DSTATE."
1283 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1284 pc
.DepthStallEnable
= true;
1285 pc
.PostSyncOperation
= WriteImmediateData
;
1287 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1292 /* Render targets live in the same binding table as fragment descriptors */
1293 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
1294 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
1296 /* We emit the binding tables and sampler tables first, then emit push
1297 * constants and then finally emit binding table and sampler table
1298 * pointers. It has to happen in this order, since emitting the binding
1299 * tables may change the push constants (in case of storage images). After
1300 * emitting push constants, on SKL+ we have to emit the corresponding
1301 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
1304 if (cmd_buffer
->state
.descriptors_dirty
)
1305 dirty
= flush_descriptor_sets(cmd_buffer
);
1307 if (cmd_buffer
->state
.push_constants_dirty
) {
1309 /* On Sky Lake and later, the binding table pointers commands are
1310 * what actually flush the changes to push constant state so we need
1311 * to dirty them so they get re-emitted below.
1313 dirty
|= cmd_buffer_flush_push_constants(cmd_buffer
);
1315 cmd_buffer_flush_push_constants(cmd_buffer
);
1320 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
1322 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
1323 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
1325 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
1326 ANV_CMD_DIRTY_PIPELINE
)) {
1327 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
1328 pipeline
->depth_clamp_enable
);
1331 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
1332 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
1334 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
1336 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1340 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
1341 struct anv_bo
*bo
, uint32_t offset
)
1343 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
1344 GENX(3DSTATE_VERTEX_BUFFERS
));
1346 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
1347 &(struct GENX(VERTEX_BUFFER_STATE
)) {
1348 .VertexBufferIndex
= 32, /* Reserved for this */
1349 .AddressModifyEnable
= true,
1352 .MemoryObjectControlState
= GENX(MOCS
),
1353 .BufferStartingAddress
= { bo
, offset
},
1356 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1357 .BufferStartingAddress
= { bo
, offset
},
1358 .EndAddress
= { bo
, offset
+ 8 },
1364 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
1365 uint32_t base_vertex
, uint32_t base_instance
)
1367 struct anv_state id_state
=
1368 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
1370 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
1371 ((uint32_t *)id_state
.map
)[1] = base_instance
;
1373 if (!cmd_buffer
->device
->info
.has_llc
)
1374 anv_state_clflush(id_state
);
1376 emit_base_vertex_instance_bo(cmd_buffer
,
1377 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, id_state
.offset
);
1381 VkCommandBuffer commandBuffer
,
1382 uint32_t vertexCount
,
1383 uint32_t instanceCount
,
1384 uint32_t firstVertex
,
1385 uint32_t firstInstance
)
1387 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1388 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1389 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1391 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1393 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1394 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
1396 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1397 prim
.VertexAccessType
= SEQUENTIAL
;
1398 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1399 prim
.VertexCountPerInstance
= vertexCount
;
1400 prim
.StartVertexLocation
= firstVertex
;
1401 prim
.InstanceCount
= instanceCount
;
1402 prim
.StartInstanceLocation
= firstInstance
;
1403 prim
.BaseVertexLocation
= 0;
1407 void genX(CmdDrawIndexed
)(
1408 VkCommandBuffer commandBuffer
,
1409 uint32_t indexCount
,
1410 uint32_t instanceCount
,
1411 uint32_t firstIndex
,
1412 int32_t vertexOffset
,
1413 uint32_t firstInstance
)
1415 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1416 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1417 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1419 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1421 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1422 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
1424 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1425 prim
.VertexAccessType
= RANDOM
;
1426 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1427 prim
.VertexCountPerInstance
= indexCount
;
1428 prim
.StartVertexLocation
= firstIndex
;
1429 prim
.InstanceCount
= instanceCount
;
1430 prim
.StartInstanceLocation
= firstInstance
;
1431 prim
.BaseVertexLocation
= vertexOffset
;
1435 /* Auto-Draw / Indirect Registers */
1436 #define GEN7_3DPRIM_END_OFFSET 0x2420
1437 #define GEN7_3DPRIM_START_VERTEX 0x2430
1438 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
1439 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
1440 #define GEN7_3DPRIM_START_INSTANCE 0x243C
1441 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
1443 void genX(CmdDrawIndirect
)(
1444 VkCommandBuffer commandBuffer
,
1446 VkDeviceSize offset
,
1450 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1451 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1452 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1453 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1454 struct anv_bo
*bo
= buffer
->bo
;
1455 uint32_t bo_offset
= buffer
->offset
+ offset
;
1457 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1459 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1460 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
1462 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1463 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1464 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1465 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
1466 emit_lri(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
1468 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1469 prim
.IndirectParameterEnable
= true;
1470 prim
.VertexAccessType
= SEQUENTIAL
;
1471 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1475 void genX(CmdDrawIndexedIndirect
)(
1476 VkCommandBuffer commandBuffer
,
1478 VkDeviceSize offset
,
1482 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1483 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1484 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1485 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1486 struct anv_bo
*bo
= buffer
->bo
;
1487 uint32_t bo_offset
= buffer
->offset
+ offset
;
1489 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1491 /* TODO: We need to stomp base vertex to 0 somehow */
1492 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1493 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
1495 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1496 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1497 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1498 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
1499 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
1501 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1502 prim
.IndirectParameterEnable
= true;
1503 prim
.VertexAccessType
= RANDOM
;
1504 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1509 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
1511 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1512 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
1515 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1516 if (result
!= VK_SUCCESS
) {
1517 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1518 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1519 assert(result
== VK_SUCCESS
);
1521 /* Re-emit state base addresses so we get the new surface state base
1522 * address before we start emitting binding tables etc.
1524 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1526 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1527 assert(result
== VK_SUCCESS
);
1530 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
1531 assert(result
== VK_SUCCESS
);
1533 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
1534 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
1535 .BindingTablePointer
= surfaces
.offset
,
1536 .SamplerStatePointer
= samplers
.offset
,
1538 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
1540 struct anv_state state
=
1541 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
1542 pipeline
->interface_descriptor_data
,
1543 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
1546 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
1547 anv_batch_emit(&cmd_buffer
->batch
,
1548 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
1549 mid
.InterfaceDescriptorTotalLength
= size
;
1550 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
1557 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1559 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1560 MAYBE_UNUSED VkResult result
;
1562 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
1564 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1566 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
1568 if (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1569 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
1571 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
1572 * the only bits that are changed are scoreboard related: Scoreboard
1573 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
1574 * these scoreboard related states, a MEDIA_STATE_FLUSH is
1577 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
1578 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1580 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1583 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
1584 struct anv_state push_state
=
1585 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
1587 if (push_state
.alloc_size
) {
1588 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
1589 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
1590 curbe
.CURBEDataStartAddress
= push_state
.offset
;
1595 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
1596 (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)) {
1597 /* FIXME: figure out descriptors for gen7 */
1598 result
= flush_compute_descriptor_set(cmd_buffer
);
1599 assert(result
== VK_SUCCESS
);
1600 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
1603 cmd_buffer
->state
.compute_dirty
= 0;
1605 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1611 verify_cmd_parser(const struct anv_device
*device
,
1612 int required_version
,
1613 const char *function
)
1615 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
1616 vk_errorf(VK_ERROR_FEATURE_NOT_PRESENT
,
1617 "cmd parser version %d is required for %s",
1618 required_version
, function
);
1627 void genX(CmdDispatch
)(
1628 VkCommandBuffer commandBuffer
,
1633 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1634 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1635 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1637 if (prog_data
->uses_num_work_groups
) {
1638 struct anv_state state
=
1639 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
1640 uint32_t *sizes
= state
.map
;
1644 if (!cmd_buffer
->device
->info
.has_llc
)
1645 anv_state_clflush(state
);
1646 cmd_buffer
->state
.num_workgroups_offset
= state
.offset
;
1647 cmd_buffer
->state
.num_workgroups_bo
=
1648 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
;
1651 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1653 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
1654 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
1655 ggw
.ThreadDepthCounterMaximum
= 0;
1656 ggw
.ThreadHeightCounterMaximum
= 0;
1657 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
1658 ggw
.ThreadGroupIDXDimension
= x
;
1659 ggw
.ThreadGroupIDYDimension
= y
;
1660 ggw
.ThreadGroupIDZDimension
= z
;
1661 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
1662 ggw
.BottomExecutionMask
= 0xffffffff;
1665 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
1668 #define GPGPU_DISPATCHDIMX 0x2500
1669 #define GPGPU_DISPATCHDIMY 0x2504
1670 #define GPGPU_DISPATCHDIMZ 0x2508
1672 #define MI_PREDICATE_SRC0 0x2400
1673 #define MI_PREDICATE_SRC1 0x2408
1675 void genX(CmdDispatchIndirect
)(
1676 VkCommandBuffer commandBuffer
,
1678 VkDeviceSize offset
)
1680 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1681 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1682 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1683 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1684 struct anv_bo
*bo
= buffer
->bo
;
1685 uint32_t bo_offset
= buffer
->offset
+ offset
;
1686 struct anv_batch
*batch
= &cmd_buffer
->batch
;
1689 /* Linux 4.4 added command parser version 5 which allows the GPGPU
1690 * indirect dispatch registers to be written.
1692 if (!verify_cmd_parser(cmd_buffer
->device
, 5, "vkCmdDispatchIndirect"))
1696 if (prog_data
->uses_num_work_groups
) {
1697 cmd_buffer
->state
.num_workgroups_offset
= bo_offset
;
1698 cmd_buffer
->state
.num_workgroups_bo
= bo
;
1701 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1703 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
1704 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
1705 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
1708 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
1709 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
1710 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
1711 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
1713 /* Load compute_dispatch_indirect_x_size into SRC0 */
1714 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
1716 /* predicate = (compute_dispatch_indirect_x_size == 0); */
1717 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1718 mip
.LoadOperation
= LOAD_LOAD
;
1719 mip
.CombineOperation
= COMBINE_SET
;
1720 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1723 /* Load compute_dispatch_indirect_y_size into SRC0 */
1724 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
1726 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
1727 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1728 mip
.LoadOperation
= LOAD_LOAD
;
1729 mip
.CombineOperation
= COMBINE_OR
;
1730 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1733 /* Load compute_dispatch_indirect_z_size into SRC0 */
1734 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
1736 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
1737 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1738 mip
.LoadOperation
= LOAD_LOAD
;
1739 mip
.CombineOperation
= COMBINE_OR
;
1740 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
1743 /* predicate = !predicate; */
1744 #define COMPARE_FALSE 1
1745 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
1746 mip
.LoadOperation
= LOAD_LOADINV
;
1747 mip
.CombineOperation
= COMBINE_OR
;
1748 mip
.CompareOperation
= COMPARE_FALSE
;
1752 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
1753 ggw
.IndirectParameterEnable
= true;
1754 ggw
.PredicateEnable
= GEN_GEN
<= 7;
1755 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
1756 ggw
.ThreadDepthCounterMaximum
= 0;
1757 ggw
.ThreadHeightCounterMaximum
= 0;
1758 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
1759 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
1760 ggw
.BottomExecutionMask
= 0xffffffff;
1763 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
1767 flush_pipeline_before_pipeline_select(struct anv_cmd_buffer
*cmd_buffer
,
1770 #if GEN_GEN >= 8 && GEN_GEN < 10
1771 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
1773 * Software must clear the COLOR_CALC_STATE Valid field in
1774 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
1775 * with Pipeline Select set to GPGPU.
1777 * The internal hardware docs recommend the same workaround for Gen9
1780 if (pipeline
== GPGPU
)
1781 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
1783 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
1784 * PIPELINE_SELECT [DevBWR+]":
1788 * Software must ensure all the write caches are flushed through a
1789 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
1790 * command to invalidate read only caches prior to programming
1791 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
1793 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1794 pc
.RenderTargetCacheFlushEnable
= true;
1795 pc
.DepthCacheFlushEnable
= true;
1796 pc
.DCFlushEnable
= true;
1797 pc
.PostSyncOperation
= NoWrite
;
1798 pc
.CommandStreamerStallEnable
= true;
1801 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1802 pc
.TextureCacheInvalidationEnable
= true;
1803 pc
.ConstantCacheInvalidationEnable
= true;
1804 pc
.StateCacheInvalidationEnable
= true;
1805 pc
.InstructionCacheInvalidateEnable
= true;
1806 pc
.PostSyncOperation
= NoWrite
;
1812 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
1814 if (cmd_buffer
->state
.current_pipeline
!= _3D
) {
1815 flush_pipeline_before_pipeline_select(cmd_buffer
, _3D
);
1817 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
1821 ps
.PipelineSelection
= _3D
;
1824 cmd_buffer
->state
.current_pipeline
= _3D
;
1829 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
1831 if (cmd_buffer
->state
.current_pipeline
!= GPGPU
) {
1832 flush_pipeline_before_pipeline_select(cmd_buffer
, GPGPU
);
1834 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
1838 ps
.PipelineSelection
= GPGPU
;
1841 cmd_buffer
->state
.current_pipeline
= GPGPU
;
1846 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
1851 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
1853 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
1854 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
1855 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
1856 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
1857 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
1858 * Depth Flush Bit set, followed by another pipelined depth stall
1859 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
1860 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
1861 * via a preceding MI_FLUSH)."
1863 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1864 pipe
.DepthStallEnable
= true;
1866 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1867 pipe
.DepthCacheFlushEnable
= true;
1869 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1870 pipe
.DepthStallEnable
= true;
1875 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
1877 struct anv_device
*device
= cmd_buffer
->device
;
1878 const struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1879 const struct anv_image_view
*iview
=
1880 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1881 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
1882 const bool has_depth
= image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
1883 const bool has_hiz
= image
!= NULL
&& anv_image_has_hiz(image
);
1884 const bool has_stencil
=
1885 image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
1887 /* FIXME: Implement the PMA stall W/A */
1888 /* FIXME: Width and Height are wrong */
1890 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
1892 /* Emit 3DSTATE_DEPTH_BUFFER */
1894 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
1895 db
.SurfaceType
= SURFTYPE_2D
;
1896 db
.DepthWriteEnable
= true;
1897 db
.StencilWriteEnable
= has_stencil
;
1899 if (cmd_buffer
->state
.pass
->subpass_count
== 1) {
1900 db
.HierarchicalDepthBufferEnable
= has_hiz
;
1902 anv_finishme("Multiple-subpass HiZ not implemented");
1905 db
.SurfaceFormat
= isl_surf_get_depth_format(&device
->isl_dev
,
1906 &image
->depth_surface
.isl
);
1908 db
.SurfaceBaseAddress
= (struct anv_address
) {
1910 .offset
= image
->offset
+ image
->depth_surface
.offset
,
1912 db
.DepthBufferObjectControlState
= GENX(MOCS
);
1914 db
.SurfacePitch
= image
->depth_surface
.isl
.row_pitch
- 1;
1915 db
.Height
= image
->extent
.height
- 1;
1916 db
.Width
= image
->extent
.width
- 1;
1917 db
.LOD
= iview
->isl
.base_level
;
1918 db
.Depth
= image
->array_size
- 1; /* FIXME: 3-D */
1919 db
.MinimumArrayElement
= iview
->isl
.base_array_layer
;
1923 isl_surf_get_array_pitch_el_rows(&image
->depth_surface
.isl
) >> 2;
1925 db
.RenderTargetViewExtent
= 1 - 1;
1928 /* Even when no depth buffer is present, the hardware requires that
1929 * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
1931 * If a null depth buffer is bound, the driver must instead bind depth as:
1932 * 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
1933 * 3DSTATE_DEPTH.Width = 1
1934 * 3DSTATE_DEPTH.Height = 1
1935 * 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
1936 * 3DSTATE_DEPTH.SurfaceBaseAddress = 0
1937 * 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
1938 * 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
1939 * 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
1941 * The PRM is wrong, though. The width and height must be programmed to
1942 * actual framebuffer's width and height, even when neither depth buffer
1943 * nor stencil buffer is present. Also, D16_UNORM is not allowed to
1944 * be combined with a stencil buffer so we use D32_FLOAT instead.
1946 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
1947 db
.SurfaceType
= SURFTYPE_2D
;
1948 db
.SurfaceFormat
= D32_FLOAT
;
1949 db
.Width
= fb
->width
- 1;
1950 db
.Height
= fb
->height
- 1;
1951 db
.StencilWriteEnable
= has_stencil
;
1956 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
) {
1957 hdb
.HierarchicalDepthBufferObjectControlState
= GENX(MOCS
);
1958 hdb
.SurfacePitch
= image
->aux_surface
.isl
.row_pitch
- 1;
1959 hdb
.SurfaceBaseAddress
= (struct anv_address
) {
1961 .offset
= image
->offset
+ image
->aux_surface
.offset
,
1964 /* From the SKL PRM Vol2a:
1966 * The interpretation of this field is dependent on Surface Type
1968 * - SURFTYPE_1D: distance in pixels between array slices
1969 * - SURFTYPE_2D/CUBE: distance in rows between array slices
1970 * - SURFTYPE_3D: distance in rows between R - slices
1973 image
->aux_surface
.isl
.dim
== ISL_SURF_DIM_1D
?
1974 isl_surf_get_array_pitch_el(&image
->aux_surface
.isl
) >> 2 :
1975 isl_surf_get_array_pitch_el_rows(&image
->aux_surface
.isl
) >> 2;
1979 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
);
1982 /* Emit 3DSTATE_STENCIL_BUFFER */
1984 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
) {
1985 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1986 sb
.StencilBufferEnable
= true;
1988 sb
.StencilBufferObjectControlState
= GENX(MOCS
);
1990 sb
.SurfacePitch
= image
->stencil_surface
.isl
.row_pitch
- 1;
1993 sb
.SurfaceQPitch
= isl_surf_get_array_pitch_el_rows(&image
->stencil_surface
.isl
) >> 2;
1995 sb
.SurfaceBaseAddress
= (struct anv_address
) {
1997 .offset
= image
->offset
+ image
->stencil_surface
.offset
,
2001 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
);
2004 /* From the IVB PRM Vol2P1, 11.5.5.4 3DSTATE_CLEAR_PARAMS:
2006 * 3DSTATE_CLEAR_PARAMS must always be programmed in the along with
2007 * the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER,
2008 * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER)
2010 * Testing also shows that some variant of this restriction may exist HSW+.
2011 * On BDW+, it is not possible to emit 2 of these packets consecutively when
2012 * both have DepthClearValueValid set. An analysis of such state programming
2013 * on SKL showed that the GPU doesn't register the latter packet's clear
2016 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CLEAR_PARAMS
), cp
) {
2018 cp
.DepthClearValueValid
= true;
2020 cmd_buffer
->state
.subpass
->depth_stencil_attachment
;
2021 cp
.DepthClearValue
=
2022 cmd_buffer
->state
.attachments
[ds
].clear_value
.depthStencil
.depth
;
2028 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
2029 struct anv_subpass
*subpass
)
2031 cmd_buffer
->state
.subpass
= subpass
;
2033 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
2035 cmd_buffer_emit_depth_stencil(cmd_buffer
);
2036 genX(cmd_buffer_emit_hz_op
)(cmd_buffer
, BLORP_HIZ_OP_HIZ_RESOLVE
);
2037 genX(cmd_buffer_emit_hz_op
)(cmd_buffer
, BLORP_HIZ_OP_DEPTH_CLEAR
);
2039 anv_cmd_buffer_clear_subpass(cmd_buffer
);
2042 void genX(CmdBeginRenderPass
)(
2043 VkCommandBuffer commandBuffer
,
2044 const VkRenderPassBeginInfo
* pRenderPassBegin
,
2045 VkSubpassContents contents
)
2047 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2048 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2049 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
2051 cmd_buffer
->state
.framebuffer
= framebuffer
;
2052 cmd_buffer
->state
.pass
= pass
;
2053 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
2054 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, framebuffer
,
2055 pRenderPassBegin
->pClearValues
);
2057 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2059 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
2062 void genX(CmdNextSubpass
)(
2063 VkCommandBuffer commandBuffer
,
2064 VkSubpassContents contents
)
2066 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2068 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
2070 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2071 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
2074 void genX(CmdEndRenderPass
)(
2075 VkCommandBuffer commandBuffer
)
2077 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2079 genX(cmd_buffer_emit_hz_op
)(cmd_buffer
, BLORP_HIZ_OP_DEPTH_RESOLVE
);
2080 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2083 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
2088 emit_ps_depth_count(struct anv_cmd_buffer
*cmd_buffer
,
2089 struct anv_bo
*bo
, uint32_t offset
)
2091 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2092 pc
.DestinationAddressType
= DAT_PPGTT
;
2093 pc
.PostSyncOperation
= WritePSDepthCount
;
2094 pc
.DepthStallEnable
= true;
2095 pc
.Address
= (struct anv_address
) { bo
, offset
};
2097 if (GEN_GEN
== 9 && cmd_buffer
->device
->info
.gt
== 4)
2098 pc
.CommandStreamerStallEnable
= true;
2103 emit_query_availability(struct anv_cmd_buffer
*cmd_buffer
,
2104 struct anv_bo
*bo
, uint32_t offset
)
2106 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2107 pc
.DestinationAddressType
= DAT_PPGTT
;
2108 pc
.PostSyncOperation
= WriteImmediateData
;
2109 pc
.Address
= (struct anv_address
) { bo
, offset
};
2110 pc
.ImmediateData
= 1;
2114 void genX(CmdBeginQuery
)(
2115 VkCommandBuffer commandBuffer
,
2116 VkQueryPool queryPool
,
2118 VkQueryControlFlags flags
)
2120 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2121 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2123 /* Workaround: When meta uses the pipeline with the VS disabled, it seems
2124 * that the pipelining of the depth write breaks. What we see is that
2125 * samples from the render pass clear leaks into the first query
2126 * immediately after the clear. Doing a pipecontrol with a post-sync
2127 * operation and DepthStallEnable seems to work around the issue.
2129 if (cmd_buffer
->state
.need_query_wa
) {
2130 cmd_buffer
->state
.need_query_wa
= false;
2131 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2132 pc
.DepthCacheFlushEnable
= true;
2133 pc
.DepthStallEnable
= true;
2137 switch (pool
->type
) {
2138 case VK_QUERY_TYPE_OCCLUSION
:
2139 emit_ps_depth_count(cmd_buffer
, &pool
->bo
,
2140 query
* sizeof(struct anv_query_pool_slot
));
2143 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
2149 void genX(CmdEndQuery
)(
2150 VkCommandBuffer commandBuffer
,
2151 VkQueryPool queryPool
,
2154 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2155 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2157 switch (pool
->type
) {
2158 case VK_QUERY_TYPE_OCCLUSION
:
2159 emit_ps_depth_count(cmd_buffer
, &pool
->bo
,
2160 query
* sizeof(struct anv_query_pool_slot
) + 8);
2162 emit_query_availability(cmd_buffer
, &pool
->bo
,
2163 query
* sizeof(struct anv_query_pool_slot
) + 16);
2166 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
2172 #define TIMESTAMP 0x2358
2174 void genX(CmdWriteTimestamp
)(
2175 VkCommandBuffer commandBuffer
,
2176 VkPipelineStageFlagBits pipelineStage
,
2177 VkQueryPool queryPool
,
2180 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2181 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2182 uint32_t offset
= query
* sizeof(struct anv_query_pool_slot
);
2184 assert(pool
->type
== VK_QUERY_TYPE_TIMESTAMP
);
2186 switch (pipelineStage
) {
2187 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
:
2188 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2189 srm
.RegisterAddress
= TIMESTAMP
;
2190 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
};
2192 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2193 srm
.RegisterAddress
= TIMESTAMP
+ 4;
2194 srm
.MemoryAddress
= (struct anv_address
) { &pool
->bo
, offset
+ 4 };
2199 /* Everything else is bottom-of-pipe */
2200 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2201 pc
.DestinationAddressType
= DAT_PPGTT
;
2202 pc
.PostSyncOperation
= WriteTimestamp
;
2203 pc
.Address
= (struct anv_address
) { &pool
->bo
, offset
};
2205 if (GEN_GEN
== 9 && cmd_buffer
->device
->info
.gt
== 4)
2206 pc
.CommandStreamerStallEnable
= true;
2211 emit_query_availability(cmd_buffer
, &pool
->bo
, query
+ 16);
2214 #if GEN_GEN > 7 || GEN_IS_HASWELL
2216 #define alu_opcode(v) __gen_uint((v), 20, 31)
2217 #define alu_operand1(v) __gen_uint((v), 10, 19)
2218 #define alu_operand2(v) __gen_uint((v), 0, 9)
2219 #define alu(opcode, operand1, operand2) \
2220 alu_opcode(opcode) | alu_operand1(operand1) | alu_operand2(operand2)
2222 #define OPCODE_NOOP 0x000
2223 #define OPCODE_LOAD 0x080
2224 #define OPCODE_LOADINV 0x480
2225 #define OPCODE_LOAD0 0x081
2226 #define OPCODE_LOAD1 0x481
2227 #define OPCODE_ADD 0x100
2228 #define OPCODE_SUB 0x101
2229 #define OPCODE_AND 0x102
2230 #define OPCODE_OR 0x103
2231 #define OPCODE_XOR 0x104
2232 #define OPCODE_STORE 0x180
2233 #define OPCODE_STOREINV 0x580
2235 #define OPERAND_R0 0x00
2236 #define OPERAND_R1 0x01
2237 #define OPERAND_R2 0x02
2238 #define OPERAND_R3 0x03
2239 #define OPERAND_R4 0x04
2240 #define OPERAND_SRCA 0x20
2241 #define OPERAND_SRCB 0x21
2242 #define OPERAND_ACCU 0x31
2243 #define OPERAND_ZF 0x32
2244 #define OPERAND_CF 0x33
2246 #define CS_GPR(n) (0x2600 + (n) * 8)
2249 emit_load_alu_reg_u64(struct anv_batch
*batch
, uint32_t reg
,
2250 struct anv_bo
*bo
, uint32_t offset
)
2252 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2253 lrm
.RegisterAddress
= reg
,
2254 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
2256 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2257 lrm
.RegisterAddress
= reg
+ 4;
2258 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
2263 store_query_result(struct anv_batch
*batch
, uint32_t reg
,
2264 struct anv_bo
*bo
, uint32_t offset
, VkQueryResultFlags flags
)
2266 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2267 srm
.RegisterAddress
= reg
;
2268 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
2271 if (flags
& VK_QUERY_RESULT_64_BIT
) {
2272 anv_batch_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
2273 srm
.RegisterAddress
= reg
+ 4;
2274 srm
.MemoryAddress
= (struct anv_address
) { bo
, offset
+ 4 };
2279 void genX(CmdCopyQueryPoolResults
)(
2280 VkCommandBuffer commandBuffer
,
2281 VkQueryPool queryPool
,
2282 uint32_t firstQuery
,
2283 uint32_t queryCount
,
2284 VkBuffer destBuffer
,
2285 VkDeviceSize destOffset
,
2286 VkDeviceSize destStride
,
2287 VkQueryResultFlags flags
)
2289 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2290 ANV_FROM_HANDLE(anv_query_pool
, pool
, queryPool
);
2291 ANV_FROM_HANDLE(anv_buffer
, buffer
, destBuffer
);
2292 uint32_t slot_offset
, dst_offset
;
2294 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
2295 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2296 pc
.CommandStreamerStallEnable
= true;
2297 pc
.StallAtPixelScoreboard
= true;
2301 dst_offset
= buffer
->offset
+ destOffset
;
2302 for (uint32_t i
= 0; i
< queryCount
; i
++) {
2304 slot_offset
= (firstQuery
+ i
) * sizeof(struct anv_query_pool_slot
);
2305 switch (pool
->type
) {
2306 case VK_QUERY_TYPE_OCCLUSION
:
2307 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2308 CS_GPR(0), &pool
->bo
, slot_offset
);
2309 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2310 CS_GPR(1), &pool
->bo
, slot_offset
+ 8);
2312 /* FIXME: We need to clamp the result for 32 bit. */
2314 uint32_t *dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
2315 dw
[1] = alu(OPCODE_LOAD
, OPERAND_SRCA
, OPERAND_R1
);
2316 dw
[2] = alu(OPCODE_LOAD
, OPERAND_SRCB
, OPERAND_R0
);
2317 dw
[3] = alu(OPCODE_SUB
, 0, 0);
2318 dw
[4] = alu(OPCODE_STORE
, OPERAND_R2
, OPERAND_ACCU
);
2321 case VK_QUERY_TYPE_TIMESTAMP
:
2322 emit_load_alu_reg_u64(&cmd_buffer
->batch
,
2323 CS_GPR(2), &pool
->bo
, slot_offset
);
2327 unreachable("unhandled query type");
2330 store_query_result(&cmd_buffer
->batch
,
2331 CS_GPR(2), buffer
->bo
, dst_offset
, flags
);
2333 if (flags
& VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
) {
2334 emit_load_alu_reg_u64(&cmd_buffer
->batch
, CS_GPR(0),
2335 &pool
->bo
, slot_offset
+ 16);
2336 if (flags
& VK_QUERY_RESULT_64_BIT
)
2337 store_query_result(&cmd_buffer
->batch
,
2338 CS_GPR(0), buffer
->bo
, dst_offset
+ 8, flags
);
2340 store_query_result(&cmd_buffer
->batch
,
2341 CS_GPR(0), buffer
->bo
, dst_offset
+ 4, flags
);
2344 dst_offset
+= destStride
;
2349 void genX(CmdCopyQueryPoolResults
)(
2350 VkCommandBuffer commandBuffer
,
2351 VkQueryPool queryPool
,
2352 uint32_t firstQuery
,
2353 uint32_t queryCount
,
2354 VkBuffer destBuffer
,
2355 VkDeviceSize destOffset
,
2356 VkDeviceSize destStride
,
2357 VkQueryResultFlags flags
)
2359 anv_finishme("Queries not yet supported on Ivy Bridge");