2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
31 #include "common/gen_l3_config.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
36 emit_lrm(struct anv_batch
*batch
, uint32_t reg
, struct anv_address addr
)
38 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
39 lrm
.RegisterAddress
= reg
;
40 lrm
.MemoryAddress
= addr
;
45 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
47 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
48 lri
.RegisterOffset
= reg
;
53 #if GEN_IS_HASWELL || GEN_GEN >= 8
55 emit_lrr(struct anv_batch
*batch
, uint32_t dst
, uint32_t src
)
57 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
58 lrr
.SourceRegisterAddress
= src
;
59 lrr
.DestinationRegisterAddress
= dst
;
65 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
67 struct anv_device
*device
= cmd_buffer
->device
;
69 /* If we are emitting a new state base address we probably need to re-emit
72 cmd_buffer
->state
.descriptors_dirty
|= ~0;
74 /* Emit a render target cache flush.
76 * This isn't documented anywhere in the PRM. However, it seems to be
77 * necessary prior to changing the surface state base adress. Without
78 * this, we get GPU hangs when using multi-level command buffers which
79 * clear depth, reset state base address, and then go render stuff.
81 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
82 pc
.DCFlushEnable
= true;
83 pc
.RenderTargetCacheFlushEnable
= true;
84 pc
.CommandStreamerStallEnable
= true;
87 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
88 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
89 sba
.GeneralStateMOCS
= GENX(MOCS
);
90 sba
.GeneralStateBaseAddressModifyEnable
= true;
92 sba
.SurfaceStateBaseAddress
=
93 anv_cmd_buffer_surface_base_address(cmd_buffer
);
94 sba
.SurfaceStateMOCS
= GENX(MOCS
);
95 sba
.SurfaceStateBaseAddressModifyEnable
= true;
97 sba
.DynamicStateBaseAddress
=
98 (struct anv_address
) { &device
->dynamic_state_pool
.block_pool
.bo
, 0 };
99 sba
.DynamicStateMOCS
= GENX(MOCS
);
100 sba
.DynamicStateBaseAddressModifyEnable
= true;
102 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
103 sba
.IndirectObjectMOCS
= GENX(MOCS
);
104 sba
.IndirectObjectBaseAddressModifyEnable
= true;
106 sba
.InstructionBaseAddress
=
107 (struct anv_address
) { &device
->instruction_state_pool
.block_pool
.bo
, 0 };
108 sba
.InstructionMOCS
= GENX(MOCS
);
109 sba
.InstructionBaseAddressModifyEnable
= true;
112 /* Broadwell requires that we specify a buffer size for a bunch of
113 * these fields. However, since we will be growing the BO's live, we
114 * just set them all to the maximum.
116 sba
.GeneralStateBufferSize
= 0xfffff;
117 sba
.GeneralStateBufferSizeModifyEnable
= true;
118 sba
.DynamicStateBufferSize
= 0xfffff;
119 sba
.DynamicStateBufferSizeModifyEnable
= true;
120 sba
.IndirectObjectBufferSize
= 0xfffff;
121 sba
.IndirectObjectBufferSizeModifyEnable
= true;
122 sba
.InstructionBufferSize
= 0xfffff;
123 sba
.InstructionBuffersizeModifyEnable
= true;
126 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
127 sba
.BindlessSurfaceStateMOCS
= GENX(MOCS
);
128 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
129 sba
.BindlessSurfaceStateSize
= 0;
132 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
133 sba
.BindlessSamplerStateMOCS
= GENX(MOCS
);
134 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
135 sba
.BindlessSamplerStateBufferSize
= 0;
139 /* After re-setting the surface state base address, we have to do some
140 * cache flusing so that the sampler engine will pick up the new
141 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
142 * Shared Function > 3D Sampler > State > State Caching (page 96):
144 * Coherency with system memory in the state cache, like the texture
145 * cache is handled partially by software. It is expected that the
146 * command stream or shader will issue Cache Flush operation or
147 * Cache_Flush sampler message to ensure that the L1 cache remains
148 * coherent with system memory.
152 * Whenever the value of the Dynamic_State_Base_Addr,
153 * Surface_State_Base_Addr are altered, the L1 state cache must be
154 * invalidated to ensure the new surface or sampler state is fetched
155 * from system memory.
157 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
158 * which, according the PIPE_CONTROL instruction documentation in the
161 * Setting this bit is independent of any other bit in this packet.
162 * This bit controls the invalidation of the L1 and L2 state caches
163 * at the top of the pipe i.e. at the parsing time.
165 * Unfortunately, experimentation seems to indicate that state cache
166 * invalidation through a PIPE_CONTROL does nothing whatsoever in
167 * regards to surface state and binding tables. In stead, it seems that
168 * invalidating the texture cache is what is actually needed.
170 * XXX: As far as we have been able to determine through
171 * experimentation, shows that flush the texture cache appears to be
172 * sufficient. The theory here is that all of the sampling/rendering
173 * units cache the binding table in the texture cache. However, we have
174 * yet to be able to actually confirm this.
176 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
177 pc
.TextureCacheInvalidationEnable
= true;
178 pc
.ConstantCacheInvalidationEnable
= true;
179 pc
.StateCacheInvalidationEnable
= true;
184 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
185 struct anv_state state
, struct anv_address addr
)
187 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
190 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
191 state
.offset
+ isl_dev
->ss
.addr_offset
,
192 addr
.bo
, addr
.offset
);
193 if (result
!= VK_SUCCESS
)
194 anv_batch_set_error(&cmd_buffer
->batch
, result
);
198 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
199 struct anv_surface_state state
)
201 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
203 assert(!anv_address_is_null(state
.address
));
204 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
206 if (!anv_address_is_null(state
.aux_address
)) {
208 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
209 &cmd_buffer
->pool
->alloc
,
210 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
211 state
.aux_address
.bo
, state
.aux_address
.offset
);
212 if (result
!= VK_SUCCESS
)
213 anv_batch_set_error(&cmd_buffer
->batch
, result
);
216 if (!anv_address_is_null(state
.clear_address
)) {
218 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
219 &cmd_buffer
->pool
->alloc
,
221 isl_dev
->ss
.clear_color_state_offset
,
222 state
.clear_address
.bo
, state
.clear_address
.offset
);
223 if (result
!= VK_SUCCESS
)
224 anv_batch_set_error(&cmd_buffer
->batch
, result
);
229 color_attachment_compute_aux_usage(struct anv_device
* device
,
230 struct anv_cmd_state
* cmd_state
,
231 uint32_t att
, VkRect2D render_area
,
232 union isl_color_value
*fast_clear_color
)
234 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
235 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
237 assert(iview
->n_planes
== 1);
239 if (iview
->planes
[0].isl
.base_array_layer
>=
240 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
241 iview
->planes
[0].isl
.base_level
)) {
242 /* There is no aux buffer which corresponds to the level and layer(s)
245 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
246 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
247 att_state
->fast_clear
= false;
251 att_state
->aux_usage
=
252 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
253 VK_IMAGE_ASPECT_COLOR_BIT
,
254 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
256 /* If we don't have aux, then we should have returned early in the layer
257 * check above. If we got here, we must have something.
259 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
261 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
262 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
263 att_state
->input_aux_usage
= att_state
->aux_usage
;
265 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
267 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
268 * setting is only allowed if Surface Format supported for Fast
269 * Clear. In addition, if the surface is bound to the sampling
270 * engine, Surface Format must be supported for Render Target
271 * Compression for surfaces bound to the sampling engine."
273 * In other words, we can only sample from a fast-cleared image if it
274 * also supports color compression.
276 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
277 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
279 /* While fast-clear resolves and partial resolves are fairly cheap in the
280 * case where you render to most of the pixels, full resolves are not
281 * because they potentially involve reading and writing the entire
282 * framebuffer. If we can't texture with CCS_E, we should leave it off and
283 * limit ourselves to fast clears.
285 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
286 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
287 anv_perf_warn(device
->instance
, iview
->image
,
288 "Not temporarily enabling CCS_E.");
291 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
295 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
296 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
298 union isl_color_value clear_color
= {};
299 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
301 att_state
->clear_color_is_zero_one
=
302 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
303 att_state
->clear_color_is_zero
=
304 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
306 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
307 /* Start by getting the fast clear type. We use the first subpass
308 * layout here because we don't want to fast-clear if the first subpass
309 * to use the attachment can't handle fast-clears.
311 enum anv_fast_clear_type fast_clear_type
=
312 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
313 VK_IMAGE_ASPECT_COLOR_BIT
,
314 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
315 switch (fast_clear_type
) {
316 case ANV_FAST_CLEAR_NONE
:
317 att_state
->fast_clear
= false;
319 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
320 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
322 case ANV_FAST_CLEAR_ANY
:
323 att_state
->fast_clear
= true;
327 /* Potentially, we could do partial fast-clears but doing so has crazy
328 * alignment restrictions. It's easier to just restrict to full size
329 * fast clears for now.
331 if (render_area
.offset
.x
!= 0 ||
332 render_area
.offset
.y
!= 0 ||
333 render_area
.extent
.width
!= iview
->extent
.width
||
334 render_area
.extent
.height
!= iview
->extent
.height
)
335 att_state
->fast_clear
= false;
337 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
338 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
339 att_state
->fast_clear
= false;
341 /* We only allow fast clears to the first slice of an image (level 0,
342 * layer 0) and only for the entire slice. This guarantees us that, at
343 * any given time, there is only one clear color on any given image at
344 * any given time. At the time of our testing (Jan 17, 2018), there
345 * were no known applications which would benefit from fast-clearing
346 * more than just the first slice.
348 if (att_state
->fast_clear
&&
349 (iview
->planes
[0].isl
.base_level
> 0 ||
350 iview
->planes
[0].isl
.base_array_layer
> 0)) {
351 anv_perf_warn(device
->instance
, iview
->image
,
352 "Rendering with multi-lod or multi-layer framebuffer "
353 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
354 "baseArrayLayer > 0. Not fast clearing.");
355 att_state
->fast_clear
= false;
356 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
357 anv_perf_warn(device
->instance
, iview
->image
,
358 "Rendering to a multi-layer framebuffer with "
359 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
362 if (att_state
->fast_clear
)
363 *fast_clear_color
= clear_color
;
365 att_state
->fast_clear
= false;
370 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
371 struct anv_cmd_state
*cmd_state
,
372 uint32_t att
, VkRect2D render_area
)
374 struct anv_render_pass_attachment
*pass_att
=
375 &cmd_state
->pass
->attachments
[att
];
376 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
377 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
379 /* These will be initialized after the first subpass transition. */
380 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
381 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
384 /* We don't do any HiZ or depth fast-clears on gen7 yet */
385 att_state
->fast_clear
= false;
389 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
390 /* If we're just clearing stencil, we can always HiZ clear */
391 att_state
->fast_clear
= true;
395 /* Default to false for now */
396 att_state
->fast_clear
= false;
398 /* We must have depth in order to have HiZ */
399 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
402 const enum isl_aux_usage first_subpass_aux_usage
=
403 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
404 VK_IMAGE_ASPECT_DEPTH_BIT
,
405 pass_att
->first_subpass_layout
);
406 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
409 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
410 iview
->planes
[0].isl
.format
,
411 iview
->image
->samples
,
412 render_area
.offset
.x
,
413 render_area
.offset
.y
,
414 render_area
.offset
.x
+
415 render_area
.extent
.width
,
416 render_area
.offset
.y
+
417 render_area
.extent
.height
))
420 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
423 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
424 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
425 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
426 * only supports returning 0.0f. Gens prior to gen8 do not support this
432 /* If we got here, then we can fast clear */
433 att_state
->fast_clear
= true;
437 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
439 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
442 /* We only allocate input attachment states for color surfaces. Compression
443 * is not yet enabled for depth textures and stencil doesn't allow
444 * compression so we can just use the texture surface state from the view.
446 return vk_format_is_color(att
->format
);
449 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
450 * the initial layout is undefined, the HiZ buffer and depth buffer will
451 * represent the same data at the end of this operation.
454 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
455 const struct anv_image
*image
,
456 VkImageLayout initial_layout
,
457 VkImageLayout final_layout
)
459 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
460 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
461 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
462 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
463 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
464 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
466 enum isl_aux_op hiz_op
;
467 if (hiz_enabled
&& !enable_hiz
) {
468 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
469 } else if (!hiz_enabled
&& enable_hiz
) {
470 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
472 assert(hiz_enabled
== enable_hiz
);
473 /* If the same buffer will be used, no resolves are necessary. */
474 hiz_op
= ISL_AUX_OP_NONE
;
477 if (hiz_op
!= ISL_AUX_OP_NONE
)
478 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
482 #define MI_PREDICATE_SRC0 0x2400
483 #define MI_PREDICATE_SRC1 0x2408
486 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
487 const struct anv_image
*image
,
488 VkImageAspectFlagBits aspect
,
490 uint32_t base_layer
, uint32_t layer_count
,
493 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
495 /* We only have compression tracking for CCS_E */
496 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
499 for (uint32_t a
= 0; a
< layer_count
; a
++) {
500 uint32_t layer
= base_layer
+ a
;
501 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
502 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
505 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
511 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
512 const struct anv_image
*image
,
513 VkImageAspectFlagBits aspect
,
514 enum anv_fast_clear_type fast_clear
)
516 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
517 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
519 sdi
.ImmediateData
= fast_clear
;
522 /* Whenever we have fast-clear, we consider that slice to be compressed.
523 * This makes building predicates much easier.
525 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
526 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
529 #if GEN_IS_HASWELL || GEN_GEN >= 8
530 static inline uint32_t
531 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
533 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
535 .Operand1
= operand1
,
536 .Operand2
= operand2
,
540 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
546 #define CS_GPR(n) (0x2600 + (n) * 8)
548 /* This is only really practical on haswell and above because it requires
549 * MI math in order to get it correct.
551 #if GEN_GEN >= 8 || GEN_IS_HASWELL
553 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
554 const struct anv_image
*image
,
555 VkImageAspectFlagBits aspect
,
556 uint32_t level
, uint32_t array_layer
,
557 enum isl_aux_op resolve_op
,
558 enum anv_fast_clear_type fast_clear_supported
)
560 struct anv_address fast_clear_type_addr
=
561 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
563 /* Name some registers */
564 const int image_fc_reg
= MI_ALU_REG0
;
565 const int fc_imm_reg
= MI_ALU_REG1
;
566 const int pred_reg
= MI_ALU_REG2
;
570 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
571 /* In this case, we're doing a full resolve which means we want the
572 * resolve to happen if any compression (including fast-clears) is
575 * In order to simplify the logic a bit, we make the assumption that,
576 * if the first slice has been fast-cleared, it is also marked as
577 * compressed. See also set_image_fast_clear_state.
579 struct anv_address compression_state_addr
=
580 anv_image_get_compression_state_addr(cmd_buffer
->device
, image
,
581 aspect
, level
, array_layer
);
582 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
583 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
584 lrm
.MemoryAddress
= compression_state_addr
;
586 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
587 sdi
.Address
= compression_state_addr
;
588 sdi
.ImmediateData
= 0;
591 if (level
== 0 && array_layer
== 0) {
592 /* If the predicate is true, we want to write 0 to the fast clear type
593 * and, if it's false, leave it alone. We can do this by writing
595 * clear_type = clear_type & ~predicate;
597 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
598 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
599 lrm
.MemoryAddress
= fast_clear_type_addr
;
601 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
602 lrr
.DestinationRegisterAddress
= CS_GPR(pred_reg
);
603 lrr
.SourceRegisterAddress
= MI_PREDICATE_SRC0
;
606 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
607 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
608 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
609 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
610 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
612 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
613 srm
.MemoryAddress
= fast_clear_type_addr
;
614 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
617 } else if (level
== 0 && array_layer
== 0) {
618 /* In this case, we are doing a partial resolve to get rid of fast-clear
619 * colors. We don't care about the compression state but we do care
620 * about how much fast clear is allowed by the final layout.
622 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
623 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
625 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
626 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
627 lrm
.MemoryAddress
= fast_clear_type_addr
;
629 emit_lri(&cmd_buffer
->batch
, CS_GPR(image_fc_reg
) + 4, 0);
631 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
), fast_clear_supported
);
632 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
) + 4, 0);
634 /* We need to compute (fast_clear_supported < image->fast_clear).
635 * We do this by subtracting and storing the carry bit.
637 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
638 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, fc_imm_reg
);
639 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, image_fc_reg
);
640 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
641 dw
[4] = mi_alu(MI_ALU_STORE
, pred_reg
, MI_ALU_CF
);
643 /* Store the predicate */
644 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(pred_reg
));
646 /* If the predicate is true, we want to write 0 to the fast clear type
647 * and, if it's false, leave it alone. We can do this by writing
649 * clear_type = clear_type & ~predicate;
651 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
652 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
653 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
654 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
655 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
657 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
658 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
659 srm
.MemoryAddress
= fast_clear_type_addr
;
662 /* In this case, we're trying to do a partial resolve on a slice that
663 * doesn't have clear color. There's nothing to do.
665 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
669 /* We use the first half of src0 for the actual predicate. Set the second
670 * half of src0 and all of src1 to 0 as the predicate operation will be
671 * doing an implicit src0 != src1.
673 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
674 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
675 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
677 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
678 mip
.LoadOperation
= LOAD_LOADINV
;
679 mip
.CombineOperation
= COMBINE_SET
;
680 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
683 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
687 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
688 const struct anv_image
*image
,
689 VkImageAspectFlagBits aspect
,
690 uint32_t level
, uint32_t array_layer
,
691 enum isl_aux_op resolve_op
,
692 enum anv_fast_clear_type fast_clear_supported
)
694 struct anv_address fast_clear_type_addr
=
695 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
697 /* This only works for partial resolves and only when the clear color is
698 * all or nothing. On the upside, this emits less command streamer code
699 * and works on Ivybridge and Bay Trail.
701 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
702 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
704 /* We don't support fast clears on anything other than the first slice. */
705 if (level
> 0 || array_layer
> 0)
708 /* On gen8, we don't have a concept of default clear colors because we
709 * can't sample from CCS surfaces. It's enough to just load the fast clear
710 * state into the predicate register.
712 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
713 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
714 lrm
.MemoryAddress
= fast_clear_type_addr
;
716 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
717 sdi
.Address
= fast_clear_type_addr
;
718 sdi
.ImmediateData
= 0;
721 /* We use the first half of src0 for the actual predicate. Set the second
722 * half of src0 and all of src1 to 0 as the predicate operation will be
723 * doing an implicit src0 != src1.
725 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
726 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
727 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
729 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
730 mip
.LoadOperation
= LOAD_LOADINV
;
731 mip
.CombineOperation
= COMBINE_SET
;
732 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
735 #endif /* GEN_GEN <= 8 */
738 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
739 const struct anv_image
*image
,
740 enum isl_format format
,
741 VkImageAspectFlagBits aspect
,
742 uint32_t level
, uint32_t array_layer
,
743 enum isl_aux_op resolve_op
,
744 enum anv_fast_clear_type fast_clear_supported
)
746 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
749 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
750 aspect
, level
, array_layer
,
751 resolve_op
, fast_clear_supported
);
752 #else /* GEN_GEN <= 8 */
753 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
754 aspect
, level
, array_layer
,
755 resolve_op
, fast_clear_supported
);
758 /* CCS_D only supports full resolves and BLORP will assert on us if we try
759 * to do a partial resolve on a CCS_D surface.
761 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
762 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
763 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
765 anv_image_ccs_op(cmd_buffer
, image
, format
, aspect
, level
,
766 array_layer
, 1, resolve_op
, NULL
, true);
770 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
771 const struct anv_image
*image
,
772 enum isl_format format
,
773 VkImageAspectFlagBits aspect
,
774 uint32_t array_layer
,
775 enum isl_aux_op resolve_op
,
776 enum anv_fast_clear_type fast_clear_supported
)
778 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
779 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
781 #if GEN_GEN >= 8 || GEN_IS_HASWELL
782 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
783 aspect
, 0, array_layer
,
784 resolve_op
, fast_clear_supported
);
786 anv_image_mcs_op(cmd_buffer
, image
, format
, aspect
,
787 array_layer
, 1, resolve_op
, NULL
, true);
789 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
794 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
795 const struct anv_image
*image
,
796 VkImageAspectFlagBits aspect
,
797 enum isl_aux_usage aux_usage
,
800 uint32_t layer_count
)
802 /* The aspect must be exactly one of the image aspects. */
803 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
805 /* The only compression types with more than just fast-clears are MCS,
806 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
807 * track the current fast-clear and compression state. This leaves us
808 * with just MCS and CCS_E.
810 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
811 aux_usage
!= ISL_AUX_USAGE_MCS
)
814 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
815 level
, base_layer
, layer_count
, true);
819 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
820 const struct anv_image
*image
,
821 VkImageAspectFlagBits aspect
)
823 assert(cmd_buffer
&& image
);
824 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
826 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
827 ANV_FAST_CLEAR_NONE
);
829 /* The fast clear value dword(s) will be copied into a surface state object.
830 * Ensure that the restrictions of the fields in the dword(s) are followed.
832 * CCS buffers on SKL+ can have any value set for the clear colors.
834 if (image
->samples
== 1 && GEN_GEN
>= 9)
837 /* Other combinations of auxiliary buffers and platforms require specific
838 * values in the clear value dword(s).
840 struct anv_address addr
=
841 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
844 for (unsigned i
= 0; i
< 4; i
++) {
845 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
847 sdi
.Address
.offset
+= i
* 4;
848 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
849 assert(image
->samples
> 1);
850 sdi
.ImmediateData
= 0;
854 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
856 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
857 /* Pre-SKL, the dword containing the clear values also contains
858 * other fields, so we need to initialize those fields to match the
859 * values that would be in a color attachment.
861 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
862 ISL_CHANNEL_SELECT_GREEN
<< 22 |
863 ISL_CHANNEL_SELECT_BLUE
<< 19 |
864 ISL_CHANNEL_SELECT_ALPHA
<< 16;
865 } else if (GEN_GEN
== 7) {
866 /* On IVB, the dword containing the clear values also contains
867 * other fields that must be zero or can be zero.
869 sdi
.ImmediateData
= 0;
875 /* Copy the fast-clear value dword(s) between a surface state object and an
876 * image's fast clear state buffer.
879 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
880 struct anv_state surface_state
,
881 const struct anv_image
*image
,
882 VkImageAspectFlagBits aspect
,
883 bool copy_from_surface_state
)
885 assert(cmd_buffer
&& image
);
886 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
888 struct anv_address ss_clear_addr
= {
889 .bo
= &cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
890 .offset
= surface_state
.offset
+
891 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
893 const struct anv_address entry_addr
=
894 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
895 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
897 if (copy_from_surface_state
) {
898 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, entry_addr
,
899 ss_clear_addr
, copy_size
);
901 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, ss_clear_addr
,
902 entry_addr
, copy_size
);
904 /* Updating a surface state object may require that the state cache be
905 * invalidated. From the SKL PRM, Shared Functions -> State -> State
908 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
909 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
910 * modified [...], the L1 state cache must be invalidated to ensure
911 * the new surface or sampler state is fetched from system memory.
913 * In testing, SKL doesn't actually seem to need this, but HSW does.
915 cmd_buffer
->state
.pending_pipe_bits
|=
916 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
921 * @brief Transitions a color buffer from one layout to another.
923 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
926 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
927 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
928 * this represents the maximum layers to transition at each
929 * specified miplevel.
932 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
933 const struct anv_image
*image
,
934 VkImageAspectFlagBits aspect
,
935 const uint32_t base_level
, uint32_t level_count
,
936 uint32_t base_layer
, uint32_t layer_count
,
937 VkImageLayout initial_layout
,
938 VkImageLayout final_layout
)
940 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
941 /* Validate the inputs. */
943 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
944 /* These values aren't supported for simplicity's sake. */
945 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
946 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
947 /* Ensure the subresource range is valid. */
948 uint64_t last_level_num
= base_level
+ level_count
;
949 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
950 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
951 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
952 assert(last_level_num
<= image
->levels
);
953 /* The spec disallows these final layouts. */
954 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
955 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
957 /* No work is necessary if the layout stays the same or if this subresource
958 * range lacks auxiliary data.
960 if (initial_layout
== final_layout
)
963 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
965 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
966 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
967 /* This surface is a linear compressed image with a tiled shadow surface
968 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
969 * we need to ensure the shadow copy is up-to-date.
971 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
972 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
973 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
974 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
976 anv_image_copy_to_shadow(cmd_buffer
, image
,
977 base_level
, level_count
,
978 base_layer
, layer_count
);
981 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
984 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
986 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
987 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
988 /* A subresource in the undefined layout may have been aliased and
989 * populated with any arrangement of bits. Therefore, we must initialize
990 * the related aux buffer and clear buffer entry with desirable values.
991 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
992 * images with VK_IMAGE_TILING_OPTIMAL.
994 * Initialize the relevant clear buffer entries.
996 if (base_level
== 0 && base_layer
== 0)
997 init_fast_clear_color(cmd_buffer
, image
, aspect
);
999 /* Initialize the aux buffers to enable correct rendering. In order to
1000 * ensure that things such as storage images work correctly, aux buffers
1001 * need to be initialized to valid data.
1003 * Having an aux buffer with invalid data is a problem for two reasons:
1005 * 1) Having an invalid value in the buffer can confuse the hardware.
1006 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1007 * invalid and leads to the hardware doing strange things. It
1008 * doesn't hang as far as we can tell but rendering corruption can
1011 * 2) If this transition is into the GENERAL layout and we then use the
1012 * image as a storage image, then we must have the aux buffer in the
1013 * pass-through state so that, if we then go to texture from the
1014 * image, we get the results of our storage image writes and not the
1015 * fast clear color or other random data.
1017 * For CCS both of the problems above are real demonstrable issues. In
1018 * that case, the only thing we can do is to perform an ambiguate to
1019 * transition the aux surface into the pass-through state.
1021 * For MCS, (2) is never an issue because we don't support multisampled
1022 * storage images. In theory, issue (1) is a problem with MCS but we've
1023 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1024 * theory, be interpreted as something but we don't know that all bit
1025 * patterns are actually valid. For 2x and 8x, you could easily end up
1026 * with the MCS referring to an invalid plane because not all bits of
1027 * the MCS value are actually used. Even though we've never seen issues
1028 * in the wild, it's best to play it safe and initialize the MCS. We
1029 * can use a fast-clear for MCS because we only ever touch from render
1030 * and texture (no image load store).
1032 if (image
->samples
== 1) {
1033 for (uint32_t l
= 0; l
< level_count
; l
++) {
1034 const uint32_t level
= base_level
+ l
;
1036 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1037 if (base_layer
>= aux_layers
)
1038 break; /* We will only get fewer layers as level increases */
1039 uint32_t level_layer_count
=
1040 MIN2(layer_count
, aux_layers
- base_layer
);
1042 anv_image_ccs_op(cmd_buffer
, image
,
1043 image
->planes
[plane
].surface
.isl
.format
,
1044 aspect
, level
, base_layer
, level_layer_count
,
1045 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1047 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1048 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1049 level
, base_layer
, level_layer_count
,
1054 if (image
->samples
== 4 || image
->samples
== 16) {
1055 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1056 "Doing a potentially unnecessary fast-clear to "
1057 "define an MCS buffer.");
1060 assert(base_level
== 0 && level_count
== 1);
1061 anv_image_mcs_op(cmd_buffer
, image
,
1062 image
->planes
[plane
].surface
.isl
.format
,
1063 aspect
, base_layer
, layer_count
,
1064 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1069 const enum isl_aux_usage initial_aux_usage
=
1070 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1071 const enum isl_aux_usage final_aux_usage
=
1072 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1074 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1075 * We can handle transitions between CCS_D/E to and from NONE. What we
1076 * don't yet handle is switching between CCS_E and CCS_D within a given
1077 * image. Doing so in a performant way requires more detailed aux state
1078 * tracking such as what is done in i965. For now, just assume that we
1079 * only have one type of compression.
1081 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1082 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1083 initial_aux_usage
== final_aux_usage
);
1085 /* If initial aux usage is NONE, there is nothing to resolve */
1086 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1089 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1091 /* If the initial layout supports more fast clear than the final layout
1092 * then we need at least a partial resolve.
1094 const enum anv_fast_clear_type initial_fast_clear
=
1095 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1096 const enum anv_fast_clear_type final_fast_clear
=
1097 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1098 if (final_fast_clear
< initial_fast_clear
)
1099 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1101 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1102 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1103 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1105 if (resolve_op
== ISL_AUX_OP_NONE
)
1108 /* Perform a resolve to synchronize data between the main and aux buffer.
1109 * Before we begin, we must satisfy the cache flushing requirement specified
1110 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1112 * Any transition from any value in {Clear, Render, Resolve} to a
1113 * different value in {Clear, Render, Resolve} requires end of pipe
1116 * We perform a flush of the write cache before and after the clear and
1117 * resolve operations to meet this requirement.
1119 * Unlike other drawing, fast clear operations are not properly
1120 * synchronized. The first PIPE_CONTROL here likely ensures that the
1121 * contents of the previous render or clear hit the render target before we
1122 * resolve and the second likely ensures that the resolve is complete before
1123 * we do any more rendering or clearing.
1125 cmd_buffer
->state
.pending_pipe_bits
|=
1126 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1128 for (uint32_t l
= 0; l
< level_count
; l
++) {
1129 uint32_t level
= base_level
+ l
;
1131 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1132 if (base_layer
>= aux_layers
)
1133 break; /* We will only get fewer layers as level increases */
1134 uint32_t level_layer_count
=
1135 MIN2(layer_count
, aux_layers
- base_layer
);
1137 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1138 uint32_t array_layer
= base_layer
+ a
;
1139 if (image
->samples
== 1) {
1140 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1141 image
->planes
[plane
].surface
.isl
.format
,
1142 aspect
, level
, array_layer
, resolve_op
,
1145 /* We only support fast-clear on the first layer so partial
1146 * resolves should not be used on other layers as they will use
1147 * the clear color stored in memory that is only valid for layer0.
1149 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1153 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1154 image
->planes
[plane
].surface
.isl
.format
,
1155 aspect
, array_layer
, resolve_op
,
1161 cmd_buffer
->state
.pending_pipe_bits
|=
1162 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1166 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1169 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1170 struct anv_render_pass
*pass
,
1171 const VkRenderPassBeginInfo
*begin
)
1173 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1174 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1176 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1178 if (pass
->attachment_count
> 0) {
1179 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1180 pass
->attachment_count
*
1181 sizeof(state
->attachments
[0]),
1182 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1183 if (state
->attachments
== NULL
) {
1184 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1185 return anv_batch_set_error(&cmd_buffer
->batch
,
1186 VK_ERROR_OUT_OF_HOST_MEMORY
);
1189 state
->attachments
= NULL
;
1192 /* Reserve one for the NULL state. */
1193 unsigned num_states
= 1;
1194 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1195 if (vk_format_is_color(pass
->attachments
[i
].format
))
1198 if (need_input_attachment_state(&pass
->attachments
[i
]))
1202 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1203 state
->render_pass_states
=
1204 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1205 num_states
* ss_stride
, isl_dev
->ss
.align
);
1207 struct anv_state next_state
= state
->render_pass_states
;
1208 next_state
.alloc_size
= isl_dev
->ss
.size
;
1210 state
->null_surface_state
= next_state
;
1211 next_state
.offset
+= ss_stride
;
1212 next_state
.map
+= ss_stride
;
1214 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1215 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1216 state
->attachments
[i
].color
.state
= next_state
;
1217 next_state
.offset
+= ss_stride
;
1218 next_state
.map
+= ss_stride
;
1221 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1222 state
->attachments
[i
].input
.state
= next_state
;
1223 next_state
.offset
+= ss_stride
;
1224 next_state
.map
+= ss_stride
;
1227 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1228 state
->render_pass_states
.alloc_size
);
1231 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1232 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1234 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1235 isl_extent3d(framebuffer
->width
,
1236 framebuffer
->height
,
1237 framebuffer
->layers
));
1239 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1240 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1241 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1242 VkImageAspectFlags clear_aspects
= 0;
1243 VkImageAspectFlags load_aspects
= 0;
1245 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1246 /* color attachment */
1247 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1248 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1249 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1250 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1253 /* depthstencil attachment */
1254 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1255 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1256 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1257 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1258 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1261 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1262 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1263 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1264 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1265 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1270 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1271 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1272 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1274 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1276 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1277 anv_assert(iview
->vk_format
== att
->format
);
1279 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1280 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1282 union isl_color_value clear_color
= { .u32
= { 0, } };
1283 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1284 anv_assert(iview
->n_planes
== 1);
1285 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1286 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1287 state
, i
, begin
->renderArea
,
1290 anv_image_fill_surface_state(cmd_buffer
->device
,
1292 VK_IMAGE_ASPECT_COLOR_BIT
,
1293 &iview
->planes
[0].isl
,
1294 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1295 state
->attachments
[i
].aux_usage
,
1298 &state
->attachments
[i
].color
,
1301 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1303 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1308 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1309 anv_image_fill_surface_state(cmd_buffer
->device
,
1311 VK_IMAGE_ASPECT_COLOR_BIT
,
1312 &iview
->planes
[0].isl
,
1313 ISL_SURF_USAGE_TEXTURE_BIT
,
1314 state
->attachments
[i
].input_aux_usage
,
1317 &state
->attachments
[i
].input
,
1320 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1329 genX(BeginCommandBuffer
)(
1330 VkCommandBuffer commandBuffer
,
1331 const VkCommandBufferBeginInfo
* pBeginInfo
)
1333 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1335 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1336 * command buffer's state. Otherwise, we must *reset* its state. In both
1337 * cases we reset it.
1339 * From the Vulkan 1.0 spec:
1341 * If a command buffer is in the executable state and the command buffer
1342 * was allocated from a command pool with the
1343 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1344 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1345 * as if vkResetCommandBuffer had been called with
1346 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1347 * the command buffer in the recording state.
1349 anv_cmd_buffer_reset(cmd_buffer
);
1351 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1353 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1354 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1356 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1358 /* We sometimes store vertex data in the dynamic state buffer for blorp
1359 * operations and our dynamic state stream may re-use data from previous
1360 * command buffers. In order to prevent stale cache data, we flush the VF
1361 * cache. We could do this on every blorp call but that's not really
1362 * needed as all of the data will get written by the CPU prior to the GPU
1363 * executing anything. The chances are fairly high that they will use
1364 * blorp at least once per primary command buffer so it shouldn't be
1367 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1368 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1370 /* We send an "Indirect State Pointers Disable" packet at
1371 * EndCommandBuffer, so all push contant packets are ignored during a
1372 * context restore. Documentation says after that command, we need to
1373 * emit push constants again before any rendering operation. So we
1374 * flag them dirty here to make sure they get emitted.
1376 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1378 VkResult result
= VK_SUCCESS
;
1379 if (cmd_buffer
->usage_flags
&
1380 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1381 assert(pBeginInfo
->pInheritanceInfo
);
1382 cmd_buffer
->state
.pass
=
1383 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1384 cmd_buffer
->state
.subpass
=
1385 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1387 /* This is optional in the inheritance info. */
1388 cmd_buffer
->state
.framebuffer
=
1389 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1391 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1392 cmd_buffer
->state
.pass
, NULL
);
1394 /* Record that HiZ is enabled if we can. */
1395 if (cmd_buffer
->state
.framebuffer
) {
1396 const struct anv_image_view
* const iview
=
1397 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1400 VkImageLayout layout
=
1401 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1403 enum isl_aux_usage aux_usage
=
1404 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1405 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1407 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1411 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1417 /* From the PRM, Volume 2a:
1419 * "Indirect State Pointers Disable
1421 * At the completion of the post-sync operation associated with this pipe
1422 * control packet, the indirect state pointers in the hardware are
1423 * considered invalid; the indirect pointers are not saved in the context.
1424 * If any new indirect state commands are executed in the command stream
1425 * while the pipe control is pending, the new indirect state commands are
1428 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1429 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1430 * commands are only considered as Indirect State Pointers. Once ISP is
1431 * issued in a context, SW must initialize by programming push constant
1432 * commands for all the shaders (at least to zero length) before attempting
1433 * any rendering operation for the same context."
1435 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1436 * even though they point to a BO that has been already unreferenced at
1437 * the end of the previous batch buffer. This has been fine so far since
1438 * we are protected by these scratch page (every address not covered by
1439 * a BO should be pointing to the scratch page). But on CNL, it is
1440 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1443 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1444 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1445 * context restore, so the mentioned hang doesn't happen. However,
1446 * software must program push constant commands for all stages prior to
1447 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1449 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1450 * constants have been loaded into the EUs prior to disable the push constants
1451 * so that it doesn't hang a previous 3DPRIMITIVE.
1454 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1456 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1457 pc
.StallAtPixelScoreboard
= true;
1458 pc
.CommandStreamerStallEnable
= true;
1460 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1461 pc
.IndirectStatePointersDisable
= true;
1462 pc
.CommandStreamerStallEnable
= true;
1467 genX(EndCommandBuffer
)(
1468 VkCommandBuffer commandBuffer
)
1470 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1472 if (anv_batch_has_error(&cmd_buffer
->batch
))
1473 return cmd_buffer
->batch
.status
;
1475 /* We want every command buffer to start with the PMA fix in a known state,
1476 * so we disable it at the end of the command buffer.
1478 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1480 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1482 emit_isp_disable(cmd_buffer
);
1484 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1490 genX(CmdExecuteCommands
)(
1491 VkCommandBuffer commandBuffer
,
1492 uint32_t commandBufferCount
,
1493 const VkCommandBuffer
* pCmdBuffers
)
1495 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1497 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1499 if (anv_batch_has_error(&primary
->batch
))
1502 /* The secondary command buffers will assume that the PMA fix is disabled
1503 * when they begin executing. Make sure this is true.
1505 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1507 /* The secondary command buffer doesn't know which textures etc. have been
1508 * flushed prior to their execution. Apply those flushes now.
1510 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1512 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1513 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1515 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1516 assert(!anv_batch_has_error(&secondary
->batch
));
1518 if (secondary
->usage_flags
&
1519 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1520 /* If we're continuing a render pass from the primary, we need to
1521 * copy the surface states for the current subpass into the storage
1522 * we allocated for them in BeginCommandBuffer.
1524 struct anv_bo
*ss_bo
=
1525 &primary
->device
->surface_state_pool
.block_pool
.bo
;
1526 struct anv_state src_state
= primary
->state
.render_pass_states
;
1527 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1528 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1530 genX(cmd_buffer_so_memcpy
)(primary
,
1531 (struct anv_address
) {
1533 .offset
= dst_state
.offset
,
1535 (struct anv_address
) {
1537 .offset
= src_state
.offset
,
1539 src_state
.alloc_size
);
1542 anv_cmd_buffer_add_secondary(primary
, secondary
);
1545 /* The secondary may have selected a different pipeline (3D or compute) and
1546 * may have changed the current L3$ configuration. Reset our tracking
1547 * variables to invalid values to ensure that we re-emit these in the case
1548 * where we do any draws or compute dispatches from the primary after the
1549 * secondary has returned.
1551 primary
->state
.current_pipeline
= UINT32_MAX
;
1552 primary
->state
.current_l3_config
= NULL
;
1554 /* Each of the secondary command buffers will use its own state base
1555 * address. We need to re-emit state base address for the primary after
1556 * all of the secondaries are done.
1558 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1561 genX(cmd_buffer_emit_state_base_address
)(primary
);
1564 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1565 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1566 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1569 * Program the hardware to use the specified L3 configuration.
1572 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1573 const struct gen_l3_config
*cfg
)
1576 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1579 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1580 intel_logd("L3 config transition: ");
1581 gen_dump_l3_config(cfg
, stderr
);
1584 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1586 /* According to the hardware docs, the L3 partitioning can only be changed
1587 * while the pipeline is completely drained and the caches are flushed,
1588 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1590 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1591 pc
.DCFlushEnable
= true;
1592 pc
.PostSyncOperation
= NoWrite
;
1593 pc
.CommandStreamerStallEnable
= true;
1596 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1597 * invalidation of the relevant caches. Note that because RO invalidation
1598 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1599 * command is processed by the CS) we cannot combine it with the previous
1600 * stalling flush as the hardware documentation suggests, because that
1601 * would cause the CS to stall on previous rendering *after* RO
1602 * invalidation and wouldn't prevent the RO caches from being polluted by
1603 * concurrent rendering before the stall completes. This intentionally
1604 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1605 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1606 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1607 * already guarantee that there is no concurrent GPGPU kernel execution
1608 * (see SKL HSD 2132585).
1610 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1611 pc
.TextureCacheInvalidationEnable
= true;
1612 pc
.ConstantCacheInvalidationEnable
= true;
1613 pc
.InstructionCacheInvalidateEnable
= true;
1614 pc
.StateCacheInvalidationEnable
= true;
1615 pc
.PostSyncOperation
= NoWrite
;
1618 /* Now send a third stalling flush to make sure that invalidation is
1619 * complete when the L3 configuration registers are modified.
1621 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1622 pc
.DCFlushEnable
= true;
1623 pc
.PostSyncOperation
= NoWrite
;
1624 pc
.CommandStreamerStallEnable
= true;
1629 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1632 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1633 .SLMEnable
= has_slm
,
1635 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1636 * in L3CNTLREG register. The default setting of the bit is not the
1637 * desirable behavior.
1639 .ErrorDetectionBehaviorControl
= true,
1640 .UseFullWays
= true,
1642 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1643 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1644 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1645 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1647 /* Set up the L3 partitioning. */
1648 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1652 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1653 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1654 cfg
->n
[GEN_L3P_ALL
];
1655 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1656 cfg
->n
[GEN_L3P_ALL
];
1657 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1658 cfg
->n
[GEN_L3P_ALL
];
1660 assert(!cfg
->n
[GEN_L3P_ALL
]);
1662 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1663 * the matching space on the remaining banks has to be allocated to a
1664 * client (URB for all validated configurations) set to the
1665 * lower-bandwidth 2-bank address hashing mode.
1667 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1668 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1669 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1671 /* Minimum number of ways that can be allocated to the URB. */
1672 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1673 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1675 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1676 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1677 .ConvertDC_UC
= !has_dc
,
1678 .ConvertIS_UC
= !has_is
,
1679 .ConvertC_UC
= !has_c
,
1680 .ConvertT_UC
= !has_t
);
1682 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1683 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1684 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1686 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1687 .SLMEnable
= has_slm
,
1688 .URBLowBandwidth
= urb_low_bw
,
1689 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1691 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1693 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1694 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1696 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1697 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1698 .ISLowBandwidth
= 0,
1699 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1701 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1702 .TLowBandwidth
= 0);
1704 /* Set up the L3 partitioning. */
1705 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1706 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1707 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1710 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1711 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1712 * them disabled to avoid crashing the system hard.
1714 uint32_t scratch1
, chicken3
;
1715 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1716 .L3AtomicDisable
= !has_dc
);
1717 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1718 .L3AtomicDisableMask
= true,
1719 .L3AtomicDisable
= !has_dc
);
1720 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1721 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1727 cmd_buffer
->state
.current_l3_config
= cfg
;
1731 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1733 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1735 /* Flushes are pipelined while invalidations are handled immediately.
1736 * Therefore, if we're flushing anything then we need to schedule a stall
1737 * before any invalidations can happen.
1739 if (bits
& ANV_PIPE_FLUSH_BITS
)
1740 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1742 /* If we're going to do an invalidate and we have a pending CS stall that
1743 * has yet to be resolved, we do the CS stall now.
1745 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1746 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1747 bits
|= ANV_PIPE_CS_STALL_BIT
;
1748 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1751 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1752 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1753 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1754 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1755 pipe
.RenderTargetCacheFlushEnable
=
1756 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1758 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1759 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1760 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1763 * According to the Broadwell documentation, any PIPE_CONTROL with the
1764 * "Command Streamer Stall" bit set must also have another bit set,
1765 * with five different options:
1767 * - Render Target Cache Flush
1768 * - Depth Cache Flush
1769 * - Stall at Pixel Scoreboard
1770 * - Post-Sync Operation
1774 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1775 * mesa and it seems to work fine. The choice is fairly arbitrary.
1777 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1778 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1779 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1780 pipe
.StallAtPixelScoreboard
= true;
1783 /* If a render target flush was emitted, then we can toggle off the bit
1784 * saying that render target writes are ongoing.
1786 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
1787 bits
&= ~(ANV_PIPE_RENDER_TARGET_WRITES
);
1789 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1792 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1793 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1795 * "If the VF Cache Invalidation Enable is set to a 1 in a
1796 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1797 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1798 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1801 * This appears to hang Broadwell, so we restrict it to just gen9.
1803 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1804 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1806 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1807 pipe
.StateCacheInvalidationEnable
=
1808 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1809 pipe
.ConstantCacheInvalidationEnable
=
1810 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1811 pipe
.VFCacheInvalidationEnable
=
1812 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1813 pipe
.TextureCacheInvalidationEnable
=
1814 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1815 pipe
.InstructionCacheInvalidateEnable
=
1816 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1818 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1820 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1821 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1822 * “Write Timestamp”.
1824 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1825 pipe
.PostSyncOperation
= WriteImmediateData
;
1827 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1831 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1834 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1837 void genX(CmdPipelineBarrier
)(
1838 VkCommandBuffer commandBuffer
,
1839 VkPipelineStageFlags srcStageMask
,
1840 VkPipelineStageFlags destStageMask
,
1842 uint32_t memoryBarrierCount
,
1843 const VkMemoryBarrier
* pMemoryBarriers
,
1844 uint32_t bufferMemoryBarrierCount
,
1845 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1846 uint32_t imageMemoryBarrierCount
,
1847 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1849 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1851 /* XXX: Right now, we're really dumb and just flush whatever categories
1852 * the app asks for. One of these days we may make this a bit better
1853 * but right now that's all the hardware allows for in most areas.
1855 VkAccessFlags src_flags
= 0;
1856 VkAccessFlags dst_flags
= 0;
1858 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1859 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1860 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1863 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1864 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1865 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1868 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1869 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1870 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1871 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1872 const VkImageSubresourceRange
*range
=
1873 &pImageMemoryBarriers
[i
].subresourceRange
;
1875 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1876 transition_depth_buffer(cmd_buffer
, image
,
1877 pImageMemoryBarriers
[i
].oldLayout
,
1878 pImageMemoryBarriers
[i
].newLayout
);
1879 } else if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1880 VkImageAspectFlags color_aspects
=
1881 anv_image_expand_aspects(image
, range
->aspectMask
);
1882 uint32_t aspect_bit
;
1884 uint32_t base_layer
, layer_count
;
1885 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1887 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1889 base_layer
= range
->baseArrayLayer
;
1890 layer_count
= anv_get_layerCount(image
, range
);
1893 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1894 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1895 range
->baseMipLevel
,
1896 anv_get_levelCount(image
, range
),
1897 base_layer
, layer_count
,
1898 pImageMemoryBarriers
[i
].oldLayout
,
1899 pImageMemoryBarriers
[i
].newLayout
);
1904 cmd_buffer
->state
.pending_pipe_bits
|=
1905 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1906 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1910 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1912 VkShaderStageFlags stages
=
1913 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1915 /* In order to avoid thrash, we assume that vertex and fragment stages
1916 * always exist. In the rare case where one is missing *and* the other
1917 * uses push concstants, this may be suboptimal. However, avoiding stalls
1918 * seems more important.
1920 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1922 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1926 const unsigned push_constant_kb
= 32;
1927 #elif GEN_IS_HASWELL
1928 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1930 const unsigned push_constant_kb
= 16;
1933 const unsigned num_stages
=
1934 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1935 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1937 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1938 * units of 2KB. Incidentally, these are the same platforms that have
1939 * 32KB worth of push constant space.
1941 if (push_constant_kb
== 32)
1942 size_per_stage
&= ~1u;
1944 uint32_t kb_used
= 0;
1945 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1946 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1947 anv_batch_emit(&cmd_buffer
->batch
,
1948 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1949 alloc
._3DCommandSubOpcode
= 18 + i
;
1950 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1951 alloc
.ConstantBufferSize
= push_size
;
1953 kb_used
+= push_size
;
1956 anv_batch_emit(&cmd_buffer
->batch
,
1957 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1958 alloc
.ConstantBufferOffset
= kb_used
;
1959 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1962 cmd_buffer
->state
.push_constant_stages
= stages
;
1964 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1966 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1967 * the next 3DPRIMITIVE command after programming the
1968 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1970 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1971 * pipeline setup, we need to dirty push constants.
1973 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1976 static const struct anv_descriptor
*
1977 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1978 const struct anv_pipeline_binding
*binding
)
1980 assert(binding
->set
< MAX_SETS
);
1981 const struct anv_descriptor_set
*set
=
1982 pipe_state
->descriptors
[binding
->set
];
1983 const uint32_t offset
=
1984 set
->layout
->binding
[binding
->binding
].descriptor_index
;
1985 return &set
->descriptors
[offset
+ binding
->index
];
1989 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1990 const struct anv_pipeline_binding
*binding
)
1992 assert(binding
->set
< MAX_SETS
);
1993 const struct anv_descriptor_set
*set
=
1994 pipe_state
->descriptors
[binding
->set
];
1996 uint32_t dynamic_offset_idx
=
1997 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
1998 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
2001 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
2005 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2006 gl_shader_stage stage
,
2007 struct anv_state
*bt_state
)
2009 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
2010 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2011 struct anv_cmd_pipeline_state
*pipe_state
;
2012 struct anv_pipeline
*pipeline
;
2013 uint32_t bias
, state_offset
;
2016 case MESA_SHADER_COMPUTE
:
2017 pipe_state
= &cmd_buffer
->state
.compute
.base
;
2021 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
2025 pipeline
= pipe_state
->pipeline
;
2027 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2028 *bt_state
= (struct anv_state
) { 0, };
2032 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2033 if (bias
+ map
->surface_count
== 0) {
2034 *bt_state
= (struct anv_state
) { 0, };
2038 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2039 bias
+ map
->surface_count
,
2041 uint32_t *bt_map
= bt_state
->map
;
2043 if (bt_state
->map
== NULL
)
2044 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2046 if (stage
== MESA_SHADER_COMPUTE
&&
2047 get_cs_prog_data(pipeline
)->uses_num_work_groups
) {
2048 struct anv_state surface_state
;
2050 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2052 const enum isl_format format
=
2053 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2054 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2056 cmd_buffer
->state
.compute
.num_workgroups
,
2059 bt_map
[0] = surface_state
.offset
+ state_offset
;
2060 add_surface_reloc(cmd_buffer
, surface_state
,
2061 cmd_buffer
->state
.compute
.num_workgroups
);
2064 if (map
->surface_count
== 0)
2067 /* We only use push constant space for images before gen9 */
2068 if (map
->image_count
> 0 && devinfo
->gen
< 9) {
2070 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
2071 if (result
!= VK_SUCCESS
)
2074 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
2078 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2079 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2081 struct anv_state surface_state
;
2083 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2084 /* Color attachment binding */
2085 assert(stage
== MESA_SHADER_FRAGMENT
);
2086 assert(binding
->binding
== 0);
2087 if (binding
->index
< subpass
->color_count
) {
2088 const unsigned att
=
2089 subpass
->color_attachments
[binding
->index
].attachment
;
2091 /* From the Vulkan 1.0.46 spec:
2093 * "If any color or depth/stencil attachments are
2094 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2097 if (att
== VK_ATTACHMENT_UNUSED
) {
2098 surface_state
= cmd_buffer
->state
.null_surface_state
;
2100 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2103 surface_state
= cmd_buffer
->state
.null_surface_state
;
2106 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2108 } else if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2109 struct anv_state surface_state
=
2110 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2112 struct anv_address constant_data
= {
2113 .bo
= &pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2114 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2116 unsigned constant_data_size
=
2117 pipeline
->shaders
[stage
]->constant_data_size
;
2119 const enum isl_format format
=
2120 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2121 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2122 surface_state
, format
,
2123 constant_data
, constant_data_size
, 1);
2125 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2126 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2130 const struct anv_descriptor
*desc
=
2131 anv_descriptor_for_binding(pipe_state
, binding
);
2133 switch (desc
->type
) {
2134 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2135 /* Nothing for us to do here */
2138 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2139 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2140 struct anv_surface_state sstate
=
2141 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2142 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2143 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2144 surface_state
= sstate
.state
;
2145 assert(surface_state
.alloc_size
);
2146 add_surface_state_relocs(cmd_buffer
, sstate
);
2149 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2150 assert(stage
== MESA_SHADER_FRAGMENT
);
2151 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2152 /* For depth and stencil input attachments, we treat it like any
2153 * old texture that a user may have bound.
2155 struct anv_surface_state sstate
=
2156 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2157 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2158 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2159 surface_state
= sstate
.state
;
2160 assert(surface_state
.alloc_size
);
2161 add_surface_state_relocs(cmd_buffer
, sstate
);
2163 /* For color input attachments, we create the surface state at
2164 * vkBeginRenderPass time so that we can include aux and clear
2165 * color information.
2167 assert(binding
->input_attachment_index
< subpass
->input_count
);
2168 const unsigned subpass_att
= binding
->input_attachment_index
;
2169 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2170 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2174 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2175 struct anv_surface_state sstate
= (binding
->write_only
)
2176 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2177 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2178 surface_state
= sstate
.state
;
2179 assert(surface_state
.alloc_size
);
2180 add_surface_state_relocs(cmd_buffer
, sstate
);
2181 if (devinfo
->gen
< 9) {
2182 assert(image
< MAX_GEN8_IMAGES
);
2183 struct brw_image_param
*image_param
=
2184 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
];
2187 desc
->image_view
->planes
[binding
->plane
].storage_image_param
;
2193 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2194 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2195 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2196 surface_state
= desc
->buffer_view
->surface_state
;
2197 assert(surface_state
.alloc_size
);
2198 add_surface_reloc(cmd_buffer
, surface_state
,
2199 desc
->buffer_view
->address
);
2202 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2203 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2204 /* Compute the offset within the buffer */
2205 uint32_t dynamic_offset
=
2206 dynamic_offset_for_binding(pipe_state
, binding
);
2207 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2208 /* Clamp to the buffer size */
2209 offset
= MIN2(offset
, desc
->buffer
->size
);
2210 /* Clamp the range to the buffer size */
2211 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2213 struct anv_address address
=
2214 anv_address_add(desc
->buffer
->address
, offset
);
2217 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2218 enum isl_format format
=
2219 anv_isl_format_for_descriptor_type(desc
->type
);
2221 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2222 format
, address
, range
, 1);
2223 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2227 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2228 surface_state
= (binding
->write_only
)
2229 ? desc
->buffer_view
->writeonly_storage_surface_state
2230 : desc
->buffer_view
->storage_surface_state
;
2231 assert(surface_state
.alloc_size
);
2232 add_surface_reloc(cmd_buffer
, surface_state
,
2233 desc
->buffer_view
->address
);
2234 if (devinfo
->gen
< 9) {
2235 assert(image
< MAX_GEN8_IMAGES
);
2236 struct brw_image_param
*image_param
=
2237 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
];
2239 *image_param
= desc
->buffer_view
->storage_image_param
;
2245 assert(!"Invalid descriptor type");
2249 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2251 assert(image
== map
->image_count
);
2254 anv_state_flush(cmd_buffer
->device
, *bt_state
);
2257 /* The PIPE_CONTROL command description says:
2259 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2260 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2261 * Target Cache Flush by enabling this bit. When render target flush
2262 * is set due to new association of BTI, PS Scoreboard Stall bit must
2263 * be set in this packet."
2265 * FINISHME: Currently we shuffle around the surface states in the binding
2266 * table based on if they are getting used or not. So, we've to do below
2267 * pipe control flush for every binding table upload. Make changes so
2268 * that we do it only when we modify render target surface states.
2270 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2271 pc
.RenderTargetCacheFlushEnable
= true;
2272 pc
.StallAtPixelScoreboard
= true;
2280 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2281 gl_shader_stage stage
,
2282 struct anv_state
*state
)
2284 struct anv_cmd_pipeline_state
*pipe_state
=
2285 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2286 &cmd_buffer
->state
.gfx
.base
;
2287 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2289 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2290 *state
= (struct anv_state
) { 0, };
2294 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2295 if (map
->sampler_count
== 0) {
2296 *state
= (struct anv_state
) { 0, };
2300 uint32_t size
= map
->sampler_count
* 16;
2301 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2303 if (state
->map
== NULL
)
2304 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2306 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2307 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2308 const struct anv_descriptor
*desc
=
2309 anv_descriptor_for_binding(pipe_state
, binding
);
2311 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2312 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2315 struct anv_sampler
*sampler
= desc
->sampler
;
2317 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2318 * happens to be zero.
2320 if (sampler
== NULL
)
2323 memcpy(state
->map
+ (s
* 16),
2324 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2327 anv_state_flush(cmd_buffer
->device
, *state
);
2333 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2335 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2337 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2338 pipeline
->active_stages
;
2340 VkResult result
= VK_SUCCESS
;
2341 anv_foreach_stage(s
, dirty
) {
2342 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2343 if (result
!= VK_SUCCESS
)
2345 result
= emit_binding_table(cmd_buffer
, s
,
2346 &cmd_buffer
->state
.binding_tables
[s
]);
2347 if (result
!= VK_SUCCESS
)
2351 if (result
!= VK_SUCCESS
) {
2352 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2354 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2355 if (result
!= VK_SUCCESS
)
2358 /* Re-emit state base addresses so we get the new surface state base
2359 * address before we start emitting binding tables etc.
2361 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2363 /* Re-emit all active binding tables */
2364 dirty
|= pipeline
->active_stages
;
2365 anv_foreach_stage(s
, dirty
) {
2366 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2367 if (result
!= VK_SUCCESS
) {
2368 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2371 result
= emit_binding_table(cmd_buffer
, s
,
2372 &cmd_buffer
->state
.binding_tables
[s
]);
2373 if (result
!= VK_SUCCESS
) {
2374 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2380 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2386 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2389 static const uint32_t sampler_state_opcodes
[] = {
2390 [MESA_SHADER_VERTEX
] = 43,
2391 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2392 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2393 [MESA_SHADER_GEOMETRY
] = 46,
2394 [MESA_SHADER_FRAGMENT
] = 47,
2395 [MESA_SHADER_COMPUTE
] = 0,
2398 static const uint32_t binding_table_opcodes
[] = {
2399 [MESA_SHADER_VERTEX
] = 38,
2400 [MESA_SHADER_TESS_CTRL
] = 39,
2401 [MESA_SHADER_TESS_EVAL
] = 40,
2402 [MESA_SHADER_GEOMETRY
] = 41,
2403 [MESA_SHADER_FRAGMENT
] = 42,
2404 [MESA_SHADER_COMPUTE
] = 0,
2407 anv_foreach_stage(s
, stages
) {
2408 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2409 assert(binding_table_opcodes
[s
] > 0);
2411 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2412 anv_batch_emit(&cmd_buffer
->batch
,
2413 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2414 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2415 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2419 /* Always emit binding table pointers if we're asked to, since on SKL
2420 * this is what flushes push constants. */
2421 anv_batch_emit(&cmd_buffer
->batch
,
2422 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2423 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2424 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2430 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2431 VkShaderStageFlags dirty_stages
)
2433 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2434 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2436 static const uint32_t push_constant_opcodes
[] = {
2437 [MESA_SHADER_VERTEX
] = 21,
2438 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2439 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2440 [MESA_SHADER_GEOMETRY
] = 22,
2441 [MESA_SHADER_FRAGMENT
] = 23,
2442 [MESA_SHADER_COMPUTE
] = 0,
2445 VkShaderStageFlags flushed
= 0;
2447 anv_foreach_stage(stage
, dirty_stages
) {
2448 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2449 assert(push_constant_opcodes
[stage
] > 0);
2451 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2452 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2454 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2455 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2456 const struct brw_stage_prog_data
*prog_data
=
2457 pipeline
->shaders
[stage
]->prog_data
;
2458 const struct anv_pipeline_bind_map
*bind_map
=
2459 &pipeline
->shaders
[stage
]->bind_map
;
2461 /* The Skylake PRM contains the following restriction:
2463 * "The driver must ensure The following case does not occur
2464 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2465 * buffer 3 read length equal to zero committed followed by a
2466 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2469 * To avoid this, we program the buffers in the highest slots.
2470 * This way, slot 0 is only used if slot 3 is also used.
2474 for (int i
= 3; i
>= 0; i
--) {
2475 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2476 if (range
->length
== 0)
2479 const unsigned surface
=
2480 prog_data
->binding_table
.ubo_start
+ range
->block
;
2482 assert(surface
<= bind_map
->surface_count
);
2483 const struct anv_pipeline_binding
*binding
=
2484 &bind_map
->surface_to_descriptor
[surface
];
2486 struct anv_address read_addr
;
2488 if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2489 struct anv_address constant_data
= {
2490 .bo
= &pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2491 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2493 unsigned constant_data_size
=
2494 pipeline
->shaders
[stage
]->constant_data_size
;
2496 read_len
= MIN2(range
->length
,
2497 DIV_ROUND_UP(constant_data_size
, 32) - range
->start
);
2498 read_addr
= anv_address_add(constant_data
,
2501 const struct anv_descriptor
*desc
=
2502 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2504 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2505 read_len
= MIN2(range
->length
,
2506 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2507 read_addr
= anv_address_add(desc
->buffer_view
->address
,
2510 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2512 uint32_t dynamic_offset
=
2513 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2514 uint32_t buf_offset
=
2515 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2516 uint32_t buf_range
=
2517 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2519 read_len
= MIN2(range
->length
,
2520 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2521 read_addr
= anv_address_add(desc
->buffer
->address
,
2522 buf_offset
+ range
->start
* 32);
2527 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2528 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2533 struct anv_state state
=
2534 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2536 if (state
.alloc_size
> 0) {
2537 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2538 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2539 .offset
= state
.offset
,
2541 c
.ConstantBody
.ReadLength
[n
] =
2542 DIV_ROUND_UP(state
.alloc_size
, 32);
2545 /* For Ivy Bridge, the push constants packets have a different
2546 * rule that would require us to iterate in the other direction
2547 * and possibly mess around with dynamic state base address.
2548 * Don't bother; just emit regular push constants at n = 0.
2550 struct anv_state state
=
2551 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2553 if (state
.alloc_size
> 0) {
2554 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2555 c
.ConstantBody
.ReadLength
[0] =
2556 DIV_ROUND_UP(state
.alloc_size
, 32);
2562 flushed
|= mesa_to_vk_shader_stage(stage
);
2565 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2569 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2571 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2574 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2575 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2576 vb_emit
|= pipeline
->vb_used
;
2578 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2580 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2582 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2585 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2586 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2588 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2589 GENX(3DSTATE_VERTEX_BUFFERS
));
2591 for_each_bit(vb
, vb_emit
) {
2592 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2593 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2595 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2596 .VertexBufferIndex
= vb
,
2598 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
2600 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2601 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2604 .AddressModifyEnable
= true,
2605 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2606 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2609 .BufferSize
= buffer
->size
- offset
2611 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2615 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2620 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2622 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2623 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2625 /* The exact descriptor layout is pulled from the pipeline, so we need
2626 * to re-emit binding tables on every pipeline change.
2628 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2630 /* If the pipeline changed, we may need to re-allocate push constant
2633 cmd_buffer_alloc_push_constants(cmd_buffer
);
2637 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2638 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2639 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2641 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2642 * stall needs to be sent just prior to any 3DSTATE_VS,
2643 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2644 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2645 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2646 * PIPE_CONTROL needs to be sent before any combination of VS
2647 * associated 3DSTATE."
2649 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2650 pc
.DepthStallEnable
= true;
2651 pc
.PostSyncOperation
= WriteImmediateData
;
2653 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2658 /* Render targets live in the same binding table as fragment descriptors */
2659 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2660 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2662 /* We emit the binding tables and sampler tables first, then emit push
2663 * constants and then finally emit binding table and sampler table
2664 * pointers. It has to happen in this order, since emitting the binding
2665 * tables may change the push constants (in case of storage images). After
2666 * emitting push constants, on SKL+ we have to emit the corresponding
2667 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2670 if (cmd_buffer
->state
.descriptors_dirty
)
2671 dirty
= flush_descriptor_sets(cmd_buffer
);
2673 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2674 /* Because we're pushing UBOs, we have to push whenever either
2675 * descriptors or push constants is dirty.
2677 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2678 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2679 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2683 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2685 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2686 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2688 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2689 ANV_CMD_DIRTY_PIPELINE
)) {
2690 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2691 pipeline
->depth_clamp_enable
);
2694 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2695 ANV_CMD_DIRTY_RENDER_TARGETS
))
2696 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2698 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2700 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2704 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2705 struct anv_address addr
,
2706 uint32_t size
, uint32_t index
)
2708 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2709 GENX(3DSTATE_VERTEX_BUFFERS
));
2711 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2712 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2713 .VertexBufferIndex
= index
,
2714 .AddressModifyEnable
= true,
2716 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
),
2718 .BufferStartingAddress
= addr
,
2721 .BufferStartingAddress
= addr
,
2722 .EndAddress
= anv_address_add(addr
, size
),
2728 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2729 struct anv_address addr
)
2731 emit_vertex_bo(cmd_buffer
, addr
, 8, ANV_SVGS_VB_INDEX
);
2735 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2736 uint32_t base_vertex
, uint32_t base_instance
)
2738 struct anv_state id_state
=
2739 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2741 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2742 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2744 anv_state_flush(cmd_buffer
->device
, id_state
);
2746 struct anv_address addr
= {
2747 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2748 .offset
= id_state
.offset
,
2751 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2755 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2757 struct anv_state state
=
2758 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2760 ((uint32_t *)state
.map
)[0] = draw_index
;
2762 anv_state_flush(cmd_buffer
->device
, state
);
2764 struct anv_address addr
= {
2765 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2766 .offset
= state
.offset
,
2769 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2773 VkCommandBuffer commandBuffer
,
2774 uint32_t vertexCount
,
2775 uint32_t instanceCount
,
2776 uint32_t firstVertex
,
2777 uint32_t firstInstance
)
2779 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2780 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2781 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2783 if (anv_batch_has_error(&cmd_buffer
->batch
))
2786 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2788 if (vs_prog_data
->uses_firstvertex
||
2789 vs_prog_data
->uses_baseinstance
)
2790 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2791 if (vs_prog_data
->uses_drawid
)
2792 emit_draw_index(cmd_buffer
, 0);
2794 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2795 * different views. We need to multiply instanceCount by the view count.
2797 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2799 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2800 prim
.VertexAccessType
= SEQUENTIAL
;
2801 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2802 prim
.VertexCountPerInstance
= vertexCount
;
2803 prim
.StartVertexLocation
= firstVertex
;
2804 prim
.InstanceCount
= instanceCount
;
2805 prim
.StartInstanceLocation
= firstInstance
;
2806 prim
.BaseVertexLocation
= 0;
2809 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_RENDER_TARGET_WRITES
;
2812 void genX(CmdDrawIndexed
)(
2813 VkCommandBuffer commandBuffer
,
2814 uint32_t indexCount
,
2815 uint32_t instanceCount
,
2816 uint32_t firstIndex
,
2817 int32_t vertexOffset
,
2818 uint32_t firstInstance
)
2820 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2821 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2822 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2824 if (anv_batch_has_error(&cmd_buffer
->batch
))
2827 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2829 if (vs_prog_data
->uses_firstvertex
||
2830 vs_prog_data
->uses_baseinstance
)
2831 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2832 if (vs_prog_data
->uses_drawid
)
2833 emit_draw_index(cmd_buffer
, 0);
2835 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2836 * different views. We need to multiply instanceCount by the view count.
2838 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2840 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2841 prim
.VertexAccessType
= RANDOM
;
2842 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2843 prim
.VertexCountPerInstance
= indexCount
;
2844 prim
.StartVertexLocation
= firstIndex
;
2845 prim
.InstanceCount
= instanceCount
;
2846 prim
.StartInstanceLocation
= firstInstance
;
2847 prim
.BaseVertexLocation
= vertexOffset
;
2850 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_RENDER_TARGET_WRITES
;
2853 /* Auto-Draw / Indirect Registers */
2854 #define GEN7_3DPRIM_END_OFFSET 0x2420
2855 #define GEN7_3DPRIM_START_VERTEX 0x2430
2856 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2857 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2858 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2859 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2861 /* MI_MATH only exists on Haswell+ */
2862 #if GEN_IS_HASWELL || GEN_GEN >= 8
2864 /* Emit dwords to multiply GPR0 by N */
2866 build_alu_multiply_gpr0(uint32_t *dw
, unsigned *dw_count
, uint32_t N
)
2868 VK_OUTARRAY_MAKE(out
, dw
, dw_count
);
2870 #define append_alu(opcode, operand1, operand2) \
2871 vk_outarray_append(&out, alu_dw) *alu_dw = mi_alu(opcode, operand1, operand2)
2874 unsigned top_bit
= 31 - __builtin_clz(N
);
2875 for (int i
= top_bit
- 1; i
>= 0; i
--) {
2876 /* We get our initial data in GPR0 and we write the final data out to
2877 * GPR0 but we use GPR1 as our scratch register.
2879 unsigned src_reg
= i
== top_bit
- 1 ? MI_ALU_REG0
: MI_ALU_REG1
;
2880 unsigned dst_reg
= i
== 0 ? MI_ALU_REG0
: MI_ALU_REG1
;
2882 /* Shift the current value left by 1 */
2883 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, src_reg
);
2884 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, src_reg
);
2885 append_alu(MI_ALU_ADD
, 0, 0);
2888 /* Store ACCU to R1 and add R0 to R1 */
2889 append_alu(MI_ALU_STORE
, MI_ALU_REG1
, MI_ALU_ACCU
);
2890 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
2891 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
2892 append_alu(MI_ALU_ADD
, 0, 0);
2895 append_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2902 emit_mul_gpr0(struct anv_batch
*batch
, uint32_t N
)
2904 uint32_t num_dwords
;
2905 build_alu_multiply_gpr0(NULL
, &num_dwords
, N
);
2907 uint32_t *dw
= anv_batch_emitn(batch
, 1 + num_dwords
, GENX(MI_MATH
));
2908 build_alu_multiply_gpr0(dw
+ 1, &num_dwords
, N
);
2911 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2914 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2915 struct anv_address addr
,
2918 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2920 emit_lrm(batch
, GEN7_3DPRIM_VERTEX_COUNT
, anv_address_add(addr
, 0));
2922 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2923 if (view_count
> 1) {
2924 #if GEN_IS_HASWELL || GEN_GEN >= 8
2925 emit_lrm(batch
, CS_GPR(0), anv_address_add(addr
, 4));
2926 emit_mul_gpr0(batch
, view_count
);
2927 emit_lrr(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, CS_GPR(0));
2929 anv_finishme("Multiview + indirect draw requires MI_MATH; "
2930 "MI_MATH is not supported on Ivy Bridge");
2931 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, anv_address_add(addr
, 4));
2934 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, anv_address_add(addr
, 4));
2937 emit_lrm(batch
, GEN7_3DPRIM_START_VERTEX
, anv_address_add(addr
, 8));
2940 emit_lrm(batch
, GEN7_3DPRIM_BASE_VERTEX
, anv_address_add(addr
, 12));
2941 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, anv_address_add(addr
, 16));
2943 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, anv_address_add(addr
, 12));
2944 emit_lri(batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
2948 void genX(CmdDrawIndirect
)(
2949 VkCommandBuffer commandBuffer
,
2951 VkDeviceSize offset
,
2955 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2956 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2957 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2958 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2960 if (anv_batch_has_error(&cmd_buffer
->batch
))
2963 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2965 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2966 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
2968 if (vs_prog_data
->uses_firstvertex
||
2969 vs_prog_data
->uses_baseinstance
)
2970 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
2971 if (vs_prog_data
->uses_drawid
)
2972 emit_draw_index(cmd_buffer
, i
);
2974 load_indirect_parameters(cmd_buffer
, draw
, false);
2976 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2977 prim
.IndirectParameterEnable
= true;
2978 prim
.VertexAccessType
= SEQUENTIAL
;
2979 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2985 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_RENDER_TARGET_WRITES
;
2988 void genX(CmdDrawIndexedIndirect
)(
2989 VkCommandBuffer commandBuffer
,
2991 VkDeviceSize offset
,
2995 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2996 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2997 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2998 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3000 if (anv_batch_has_error(&cmd_buffer
->batch
))
3003 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3005 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3006 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3008 /* TODO: We need to stomp base vertex to 0 somehow */
3009 if (vs_prog_data
->uses_firstvertex
||
3010 vs_prog_data
->uses_baseinstance
)
3011 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3012 if (vs_prog_data
->uses_drawid
)
3013 emit_draw_index(cmd_buffer
, i
);
3015 load_indirect_parameters(cmd_buffer
, draw
, true);
3017 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3018 prim
.IndirectParameterEnable
= true;
3019 prim
.VertexAccessType
= RANDOM
;
3020 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3026 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_RENDER_TARGET_WRITES
;
3030 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
3032 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3033 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
3036 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3037 if (result
!= VK_SUCCESS
) {
3038 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3040 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
3041 if (result
!= VK_SUCCESS
)
3044 /* Re-emit state base addresses so we get the new surface state base
3045 * address before we start emitting binding tables etc.
3047 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
3049 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3050 if (result
!= VK_SUCCESS
) {
3051 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3056 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3057 if (result
!= VK_SUCCESS
) {
3058 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3062 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3063 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3064 .BindingTablePointer
= surfaces
.offset
,
3065 .SamplerStatePointer
= samplers
.offset
,
3067 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3069 struct anv_state state
=
3070 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3071 pipeline
->interface_descriptor_data
,
3072 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3075 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3076 anv_batch_emit(&cmd_buffer
->batch
,
3077 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3078 mid
.InterfaceDescriptorTotalLength
= size
;
3079 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3086 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3088 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3089 MAYBE_UNUSED VkResult result
;
3091 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3093 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3095 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3097 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3098 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3100 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3101 * the only bits that are changed are scoreboard related: Scoreboard
3102 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3103 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3106 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3107 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3109 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3112 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3113 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3114 /* FIXME: figure out descriptors for gen7 */
3115 result
= flush_compute_descriptor_set(cmd_buffer
);
3116 if (result
!= VK_SUCCESS
)
3119 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3122 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3123 struct anv_state push_state
=
3124 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3126 if (push_state
.alloc_size
) {
3127 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3128 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3129 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3133 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3136 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3138 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3144 verify_cmd_parser(const struct anv_device
*device
,
3145 int required_version
,
3146 const char *function
)
3148 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3149 return vk_errorf(device
->instance
, device
->instance
,
3150 VK_ERROR_FEATURE_NOT_PRESENT
,
3151 "cmd parser version %d is required for %s",
3152 required_version
, function
);
3161 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3162 uint32_t baseGroupX
,
3163 uint32_t baseGroupY
,
3164 uint32_t baseGroupZ
)
3166 if (anv_batch_has_error(&cmd_buffer
->batch
))
3170 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, MESA_SHADER_COMPUTE
,
3171 base_work_group_id
);
3172 if (result
!= VK_SUCCESS
) {
3173 cmd_buffer
->batch
.status
= result
;
3177 struct anv_push_constants
*push
=
3178 cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3179 if (push
->base_work_group_id
[0] != baseGroupX
||
3180 push
->base_work_group_id
[1] != baseGroupY
||
3181 push
->base_work_group_id
[2] != baseGroupZ
) {
3182 push
->base_work_group_id
[0] = baseGroupX
;
3183 push
->base_work_group_id
[1] = baseGroupY
;
3184 push
->base_work_group_id
[2] = baseGroupZ
;
3186 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3190 void genX(CmdDispatch
)(
3191 VkCommandBuffer commandBuffer
,
3196 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3199 void genX(CmdDispatchBase
)(
3200 VkCommandBuffer commandBuffer
,
3201 uint32_t baseGroupX
,
3202 uint32_t baseGroupY
,
3203 uint32_t baseGroupZ
,
3204 uint32_t groupCountX
,
3205 uint32_t groupCountY
,
3206 uint32_t groupCountZ
)
3208 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3209 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3210 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3212 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3213 baseGroupY
, baseGroupZ
);
3215 if (anv_batch_has_error(&cmd_buffer
->batch
))
3218 if (prog_data
->uses_num_work_groups
) {
3219 struct anv_state state
=
3220 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3221 uint32_t *sizes
= state
.map
;
3222 sizes
[0] = groupCountX
;
3223 sizes
[1] = groupCountY
;
3224 sizes
[2] = groupCountZ
;
3225 anv_state_flush(cmd_buffer
->device
, state
);
3226 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3227 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3228 .offset
= state
.offset
,
3232 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3234 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3235 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3236 ggw
.ThreadDepthCounterMaximum
= 0;
3237 ggw
.ThreadHeightCounterMaximum
= 0;
3238 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3239 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3240 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3241 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3242 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3243 ggw
.BottomExecutionMask
= 0xffffffff;
3246 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3249 #define GPGPU_DISPATCHDIMX 0x2500
3250 #define GPGPU_DISPATCHDIMY 0x2504
3251 #define GPGPU_DISPATCHDIMZ 0x2508
3253 void genX(CmdDispatchIndirect
)(
3254 VkCommandBuffer commandBuffer
,
3256 VkDeviceSize offset
)
3258 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3259 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3260 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3261 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3262 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3263 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3265 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3268 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3269 * indirect dispatch registers to be written.
3271 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3272 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3276 if (prog_data
->uses_num_work_groups
)
3277 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3279 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3281 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, anv_address_add(addr
, 0));
3282 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, anv_address_add(addr
, 4));
3283 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, anv_address_add(addr
, 8));
3286 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
3287 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
3288 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
3289 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
3291 /* Load compute_dispatch_indirect_x_size into SRC0 */
3292 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 0));
3294 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3295 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3296 mip
.LoadOperation
= LOAD_LOAD
;
3297 mip
.CombineOperation
= COMBINE_SET
;
3298 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3301 /* Load compute_dispatch_indirect_y_size into SRC0 */
3302 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 4));
3304 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3305 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3306 mip
.LoadOperation
= LOAD_LOAD
;
3307 mip
.CombineOperation
= COMBINE_OR
;
3308 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3311 /* Load compute_dispatch_indirect_z_size into SRC0 */
3312 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 8));
3314 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3315 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3316 mip
.LoadOperation
= LOAD_LOAD
;
3317 mip
.CombineOperation
= COMBINE_OR
;
3318 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3321 /* predicate = !predicate; */
3322 #define COMPARE_FALSE 1
3323 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3324 mip
.LoadOperation
= LOAD_LOADINV
;
3325 mip
.CombineOperation
= COMBINE_OR
;
3326 mip
.CompareOperation
= COMPARE_FALSE
;
3330 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3331 ggw
.IndirectParameterEnable
= true;
3332 ggw
.PredicateEnable
= GEN_GEN
<= 7;
3333 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3334 ggw
.ThreadDepthCounterMaximum
= 0;
3335 ggw
.ThreadHeightCounterMaximum
= 0;
3336 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3337 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3338 ggw
.BottomExecutionMask
= 0xffffffff;
3341 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3345 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3348 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3350 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3353 #if GEN_GEN >= 8 && GEN_GEN < 10
3354 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3356 * Software must clear the COLOR_CALC_STATE Valid field in
3357 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3358 * with Pipeline Select set to GPGPU.
3360 * The internal hardware docs recommend the same workaround for Gen9
3363 if (pipeline
== GPGPU
)
3364 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3367 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3368 * PIPELINE_SELECT [DevBWR+]":
3372 * Software must ensure all the write caches are flushed through a
3373 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3374 * command to invalidate read only caches prior to programming
3375 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3377 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3378 pc
.RenderTargetCacheFlushEnable
= true;
3379 pc
.DepthCacheFlushEnable
= true;
3380 pc
.DCFlushEnable
= true;
3381 pc
.PostSyncOperation
= NoWrite
;
3382 pc
.CommandStreamerStallEnable
= true;
3385 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3386 pc
.TextureCacheInvalidationEnable
= true;
3387 pc
.ConstantCacheInvalidationEnable
= true;
3388 pc
.StateCacheInvalidationEnable
= true;
3389 pc
.InstructionCacheInvalidateEnable
= true;
3390 pc
.PostSyncOperation
= NoWrite
;
3393 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3397 ps
.PipelineSelection
= pipeline
;
3401 if (devinfo
->is_geminilake
) {
3404 * "This chicken bit works around a hardware issue with barrier logic
3405 * encountered when switching between GPGPU and 3D pipelines. To
3406 * workaround the issue, this mode bit should be set after a pipeline
3410 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3412 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3413 : GLK_BARRIER_MODE_3D_HULL
,
3414 .GLKBarrierModeMask
= 1);
3415 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3419 cmd_buffer
->state
.current_pipeline
= pipeline
;
3423 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3425 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3429 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3431 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3435 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3440 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3442 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3443 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3444 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3445 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3446 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3447 * Depth Flush Bit set, followed by another pipelined depth stall
3448 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3449 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3450 * via a preceding MI_FLUSH)."
3452 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3453 pipe
.DepthStallEnable
= true;
3455 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3456 pipe
.DepthCacheFlushEnable
= true;
3458 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3459 pipe
.DepthStallEnable
= true;
3464 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3466 struct anv_device
*device
= cmd_buffer
->device
;
3467 const struct anv_image_view
*iview
=
3468 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3469 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3471 /* FIXME: Width and Height are wrong */
3473 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3475 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3476 device
->isl_dev
.ds
.size
/ 4);
3480 struct isl_depth_stencil_hiz_emit_info info
= { };
3483 info
.view
= &iview
->planes
[0].isl
;
3485 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3486 uint32_t depth_plane
=
3487 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3488 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
3490 info
.depth_surf
= &surface
->isl
;
3492 info
.depth_address
=
3493 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3494 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
3495 image
->planes
[depth_plane
].address
.bo
,
3496 image
->planes
[depth_plane
].address
.offset
+
3499 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
3502 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
3503 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
3504 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
3505 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
3508 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3509 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
3510 image
->planes
[depth_plane
].address
.bo
,
3511 image
->planes
[depth_plane
].address
.offset
+
3512 image
->planes
[depth_plane
].aux_surface
.offset
);
3514 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
3518 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3519 uint32_t stencil_plane
=
3520 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
3521 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
3523 info
.stencil_surf
= &surface
->isl
;
3525 info
.stencil_address
=
3526 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3527 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
3528 image
->planes
[stencil_plane
].address
.bo
,
3529 image
->planes
[stencil_plane
].address
.offset
+
3532 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
3535 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
3537 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
3541 * This ANDs the view mask of the current subpass with the pending clear
3542 * views in the attachment to get the mask of views active in the subpass
3543 * that still need to be cleared.
3545 static inline uint32_t
3546 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
3547 const struct anv_attachment_state
*att_state
)
3549 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
3553 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
3554 const struct anv_attachment_state
*att_state
)
3556 if (!cmd_state
->subpass
->view_mask
)
3559 uint32_t pending_clear_mask
=
3560 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3562 return pending_clear_mask
& 1;
3566 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
3569 const uint32_t last_subpass_idx
=
3570 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
3571 const struct anv_subpass
*last_subpass
=
3572 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
3573 return last_subpass
== cmd_state
->subpass
;
3577 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
3578 uint32_t subpass_id
)
3580 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3581 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
3582 cmd_state
->subpass
= subpass
;
3584 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
3586 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3587 * different views. If the client asks for instancing, we need to use the
3588 * Instance Data Step Rate to ensure that we repeat the client's
3589 * per-instance data once for each view. Since this bit is in
3590 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
3594 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
3596 /* It is possible to start a render pass with an old pipeline. Because the
3597 * render pass and subpass index are both baked into the pipeline, this is
3598 * highly unlikely. In order to do so, it requires that you have a render
3599 * pass with a single subpass and that you use that render pass twice
3600 * back-to-back and use the same pipeline at the start of the second render
3601 * pass as at the end of the first. In order to avoid unpredictable issues
3602 * with this edge case, we just dirty the pipeline at the start of every
3605 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
3607 /* Accumulate any subpass flushes that need to happen before the subpass */
3608 cmd_buffer
->state
.pending_pipe_bits
|=
3609 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
3611 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
3612 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3614 bool is_multiview
= subpass
->view_mask
!= 0;
3616 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3617 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3618 if (a
== VK_ATTACHMENT_UNUSED
)
3621 assert(a
< cmd_state
->pass
->attachment_count
);
3622 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3624 struct anv_image_view
*iview
= fb
->attachments
[a
];
3625 const struct anv_image
*image
= iview
->image
;
3627 /* A resolve is necessary before use as an input attachment if the clear
3628 * color or auxiliary buffer usage isn't supported by the sampler.
3630 const bool input_needs_resolve
=
3631 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
3632 att_state
->input_aux_usage
!= att_state
->aux_usage
;
3634 VkImageLayout target_layout
;
3635 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
3636 !input_needs_resolve
) {
3637 /* Layout transitions before the final only help to enable sampling
3638 * as an input attachment. If the input attachment supports sampling
3639 * using the auxiliary surface, we can skip such transitions by
3640 * making the target layout one that is CCS-aware.
3642 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
3644 target_layout
= subpass
->attachments
[i
].layout
;
3647 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3648 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3650 uint32_t base_layer
, layer_count
;
3651 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3653 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3654 iview
->planes
[0].isl
.base_level
);
3656 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3657 layer_count
= fb
->layers
;
3660 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3661 iview
->planes
[0].isl
.base_level
, 1,
3662 base_layer
, layer_count
,
3663 att_state
->current_layout
, target_layout
);
3664 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3665 transition_depth_buffer(cmd_buffer
, image
,
3666 att_state
->current_layout
, target_layout
);
3667 att_state
->aux_usage
=
3668 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
3669 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
3671 att_state
->current_layout
= target_layout
;
3673 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
3674 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3676 /* Multi-planar images are not supported as attachments */
3677 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3678 assert(image
->n_planes
== 1);
3680 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
3681 uint32_t clear_layer_count
= fb
->layers
;
3683 if (att_state
->fast_clear
&&
3684 do_first_layer_clear(cmd_state
, att_state
)) {
3685 /* We only support fast-clears on the first layer */
3686 assert(iview
->planes
[0].isl
.base_level
== 0);
3687 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3689 union isl_color_value clear_color
= {};
3690 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
3691 if (iview
->image
->samples
== 1) {
3692 anv_image_ccs_op(cmd_buffer
, image
,
3693 iview
->planes
[0].isl
.format
,
3694 VK_IMAGE_ASPECT_COLOR_BIT
,
3695 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
3699 anv_image_mcs_op(cmd_buffer
, image
,
3700 iview
->planes
[0].isl
.format
,
3701 VK_IMAGE_ASPECT_COLOR_BIT
,
3702 0, 1, ISL_AUX_OP_FAST_CLEAR
,
3707 clear_layer_count
--;
3709 att_state
->pending_clear_views
&= ~1;
3711 if (att_state
->clear_color_is_zero
) {
3712 /* This image has the auxiliary buffer enabled. We can mark the
3713 * subresource as not needing a resolve because the clear color
3714 * will match what's in every RENDER_SURFACE_STATE object when
3715 * it's being used for sampling.
3717 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3718 VK_IMAGE_ASPECT_COLOR_BIT
,
3719 ANV_FAST_CLEAR_DEFAULT_VALUE
);
3721 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3722 VK_IMAGE_ASPECT_COLOR_BIT
,
3723 ANV_FAST_CLEAR_ANY
);
3727 /* From the VkFramebufferCreateInfo spec:
3729 * "If the render pass uses multiview, then layers must be one and each
3730 * attachment requires a number of layers that is greater than the
3731 * maximum bit index set in the view mask in the subpasses in which it
3734 * So if multiview is active we ignore the number of layers in the
3735 * framebuffer and instead we honor the view mask from the subpass.
3738 assert(image
->n_planes
== 1);
3739 uint32_t pending_clear_mask
=
3740 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3743 for_each_bit(layer_idx
, pending_clear_mask
) {
3745 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
3747 anv_image_clear_color(cmd_buffer
, image
,
3748 VK_IMAGE_ASPECT_COLOR_BIT
,
3749 att_state
->aux_usage
,
3750 iview
->planes
[0].isl
.format
,
3751 iview
->planes
[0].isl
.swizzle
,
3752 iview
->planes
[0].isl
.base_level
,
3755 vk_to_isl_color(att_state
->clear_value
.color
));
3758 att_state
->pending_clear_views
&= ~pending_clear_mask
;
3759 } else if (clear_layer_count
> 0) {
3760 assert(image
->n_planes
== 1);
3761 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3762 att_state
->aux_usage
,
3763 iview
->planes
[0].isl
.format
,
3764 iview
->planes
[0].isl
.swizzle
,
3765 iview
->planes
[0].isl
.base_level
,
3766 base_clear_layer
, clear_layer_count
,
3768 vk_to_isl_color(att_state
->clear_value
.color
));
3770 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
3771 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3772 if (att_state
->fast_clear
&& !is_multiview
) {
3773 /* We currently only support HiZ for single-layer images */
3774 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3775 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
3776 assert(iview
->planes
[0].isl
.base_level
== 0);
3777 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3778 assert(fb
->layers
== 1);
3781 anv_image_hiz_clear(cmd_buffer
, image
,
3782 att_state
->pending_clear_aspects
,
3783 iview
->planes
[0].isl
.base_level
,
3784 iview
->planes
[0].isl
.base_array_layer
,
3785 fb
->layers
, render_area
,
3786 att_state
->clear_value
.depthStencil
.stencil
);
3787 } else if (is_multiview
) {
3788 uint32_t pending_clear_mask
=
3789 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3792 for_each_bit(layer_idx
, pending_clear_mask
) {
3794 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
3796 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3797 att_state
->pending_clear_aspects
,
3798 att_state
->aux_usage
,
3799 iview
->planes
[0].isl
.base_level
,
3802 att_state
->clear_value
.depthStencil
.depth
,
3803 att_state
->clear_value
.depthStencil
.stencil
);
3806 att_state
->pending_clear_views
&= ~pending_clear_mask
;
3808 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3809 att_state
->pending_clear_aspects
,
3810 att_state
->aux_usage
,
3811 iview
->planes
[0].isl
.base_level
,
3812 iview
->planes
[0].isl
.base_array_layer
,
3813 fb
->layers
, render_area
,
3814 att_state
->clear_value
.depthStencil
.depth
,
3815 att_state
->clear_value
.depthStencil
.stencil
);
3818 assert(att_state
->pending_clear_aspects
== 0);
3822 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
3823 image
->planes
[0].aux_surface
.isl
.size_B
> 0 &&
3824 iview
->planes
[0].isl
.base_level
== 0 &&
3825 iview
->planes
[0].isl
.base_array_layer
== 0) {
3826 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
3827 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
3828 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3829 false /* copy to ss */);
3832 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
3833 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
3834 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
3835 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3836 false /* copy to ss */);
3840 if (subpass
->attachments
[i
].usage
==
3841 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
3842 /* We assume that if we're starting a subpass, we're going to do some
3843 * rendering so we may end up with compressed data.
3845 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
3846 VK_IMAGE_ASPECT_COLOR_BIT
,
3847 att_state
->aux_usage
,
3848 iview
->planes
[0].isl
.base_level
,
3849 iview
->planes
[0].isl
.base_array_layer
,
3851 } else if (subpass
->attachments
[i
].usage
==
3852 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
3853 /* We may be writing depth or stencil so we need to mark the surface.
3854 * Unfortunately, there's no way to know at this point whether the
3855 * depth or stencil tests used will actually write to the surface.
3857 * Even though stencil may be plane 1, it always shares a base_level
3860 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
3861 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3862 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3863 VK_IMAGE_ASPECT_DEPTH_BIT
,
3864 att_state
->aux_usage
,
3865 ds_view
->base_level
,
3866 ds_view
->base_array_layer
,
3869 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
3870 /* Even though stencil may be plane 1, it always shares a
3871 * base_level with depth.
3873 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3874 VK_IMAGE_ASPECT_STENCIL_BIT
,
3876 ds_view
->base_level
,
3877 ds_view
->base_array_layer
,
3882 /* If multiview is enabled, then we are only done clearing when we no
3883 * longer have pending layers to clear, or when we have processed the
3884 * last subpass that uses this attachment.
3886 if (!is_multiview
||
3887 att_state
->pending_clear_views
== 0 ||
3888 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
3889 att_state
->pending_clear_aspects
= 0;
3892 att_state
->pending_load_aspects
= 0;
3895 cmd_buffer_emit_depth_stencil(cmd_buffer
);
3898 static enum blorp_filter
3899 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
3902 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
3903 return BLORP_FILTER_SAMPLE_0
;
3904 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
3905 return BLORP_FILTER_AVERAGE
;
3906 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
3907 return BLORP_FILTER_MIN_SAMPLE
;
3908 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
3909 return BLORP_FILTER_MAX_SAMPLE
;
3911 return BLORP_FILTER_NONE
;
3916 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
3918 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3919 struct anv_subpass
*subpass
= cmd_state
->subpass
;
3920 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
3921 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3923 if (subpass
->has_color_resolve
) {
3924 /* We are about to do some MSAA resolves. We need to flush so that the
3925 * result of writes to the MSAA color attachments show up in the sampler
3926 * when we blit to the single-sampled resolve target.
3928 cmd_buffer
->state
.pending_pipe_bits
|=
3929 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
3930 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
3932 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
3933 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
3934 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
3936 if (dst_att
== VK_ATTACHMENT_UNUSED
)
3939 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
3940 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
3942 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
3943 /* From the Vulkan 1.0 spec:
3945 * If the first use of an attachment in a render pass is as a
3946 * resolve attachment, then the loadOp is effectively ignored
3947 * as the resolve is guaranteed to overwrite all pixels in the
3950 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
3953 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
3954 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
3956 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
3958 enum isl_aux_usage src_aux_usage
=
3959 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
3960 enum isl_aux_usage dst_aux_usage
=
3961 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
3963 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
3964 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
3966 anv_image_msaa_resolve(cmd_buffer
,
3967 src_iview
->image
, src_aux_usage
,
3968 src_iview
->planes
[0].isl
.base_level
,
3969 src_iview
->planes
[0].isl
.base_array_layer
,
3970 dst_iview
->image
, dst_aux_usage
,
3971 dst_iview
->planes
[0].isl
.base_level
,
3972 dst_iview
->planes
[0].isl
.base_array_layer
,
3973 VK_IMAGE_ASPECT_COLOR_BIT
,
3974 render_area
.offset
.x
, render_area
.offset
.y
,
3975 render_area
.offset
.x
, render_area
.offset
.y
,
3976 render_area
.extent
.width
,
3977 render_area
.extent
.height
,
3978 fb
->layers
, BLORP_FILTER_NONE
);
3982 if (subpass
->ds_resolve_attachment
) {
3983 /* We are about to do some MSAA resolves. We need to flush so that the
3984 * result of writes to the MSAA depth attachments show up in the sampler
3985 * when we blit to the single-sampled resolve target.
3987 cmd_buffer
->state
.pending_pipe_bits
|=
3988 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
3989 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
3991 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
3992 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
3994 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
3995 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
3997 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
3998 /* From the Vulkan 1.0 spec:
4000 * If the first use of an attachment in a render pass is as a
4001 * resolve attachment, then the loadOp is effectively ignored
4002 * as the resolve is guaranteed to overwrite all pixels in the
4005 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4008 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
4009 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
4011 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4013 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
4014 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4016 struct anv_attachment_state
*src_state
=
4017 &cmd_state
->attachments
[src_att
];
4018 struct anv_attachment_state
*dst_state
=
4019 &cmd_state
->attachments
[dst_att
];
4021 /* MSAA resolves sample from the source attachment. Transition the
4022 * depth attachment first to get rid of any HiZ that we may not be
4025 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
4026 src_state
->current_layout
,
4027 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4028 src_state
->aux_usage
=
4029 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
4030 VK_IMAGE_ASPECT_DEPTH_BIT
,
4031 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4032 src_state
->current_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
4034 /* MSAA resolves write to the resolve attachment as if it were any
4035 * other transfer op. Transition the resolve attachment accordingly.
4037 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
4039 /* If our render area is the entire size of the image, we're going to
4040 * blow it all away so we can claim the initial layout is UNDEFINED
4041 * and we'll get a HiZ ambiguate instead of a resolve.
4043 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
4044 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
4045 render_area
.extent
.width
== dst_iview
->extent
.width
&&
4046 render_area
.extent
.height
== dst_iview
->extent
.height
)
4047 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
4049 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
4051 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4052 dst_state
->aux_usage
=
4053 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
4054 VK_IMAGE_ASPECT_DEPTH_BIT
,
4055 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4056 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
4058 enum blorp_filter filter
=
4059 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
4061 anv_image_msaa_resolve(cmd_buffer
,
4062 src_iview
->image
, src_state
->aux_usage
,
4063 src_iview
->planes
[0].isl
.base_level
,
4064 src_iview
->planes
[0].isl
.base_array_layer
,
4065 dst_iview
->image
, dst_state
->aux_usage
,
4066 dst_iview
->planes
[0].isl
.base_level
,
4067 dst_iview
->planes
[0].isl
.base_array_layer
,
4068 VK_IMAGE_ASPECT_DEPTH_BIT
,
4069 render_area
.offset
.x
, render_area
.offset
.y
,
4070 render_area
.offset
.x
, render_area
.offset
.y
,
4071 render_area
.extent
.width
,
4072 render_area
.extent
.height
,
4073 fb
->layers
, filter
);
4076 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
4077 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4079 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
4080 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
4082 enum blorp_filter filter
=
4083 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
4085 anv_image_msaa_resolve(cmd_buffer
,
4086 src_iview
->image
, src_aux_usage
,
4087 src_iview
->planes
[0].isl
.base_level
,
4088 src_iview
->planes
[0].isl
.base_array_layer
,
4089 dst_iview
->image
, dst_aux_usage
,
4090 dst_iview
->planes
[0].isl
.base_level
,
4091 dst_iview
->planes
[0].isl
.base_array_layer
,
4092 VK_IMAGE_ASPECT_STENCIL_BIT
,
4093 render_area
.offset
.x
, render_area
.offset
.y
,
4094 render_area
.offset
.x
, render_area
.offset
.y
,
4095 render_area
.extent
.width
,
4096 render_area
.extent
.height
,
4097 fb
->layers
, filter
);
4101 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4102 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4103 if (a
== VK_ATTACHMENT_UNUSED
)
4106 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4109 assert(a
< cmd_state
->pass
->attachment_count
);
4110 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4111 struct anv_image_view
*iview
= fb
->attachments
[a
];
4112 const struct anv_image
*image
= iview
->image
;
4114 if ((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4115 image
->vk_format
!= iview
->vk_format
) {
4116 enum anv_fast_clear_type fast_clear_type
=
4117 anv_layout_to_fast_clear_type(&cmd_buffer
->device
->info
,
4118 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4119 att_state
->current_layout
);
4121 /* If any clear color was used, flush it down the aux surfaces. If we
4122 * don't do it now using the view's format we might use the clear
4123 * color incorrectly in the following resolves (for example with an
4124 * SRGB view & a UNORM image).
4126 if (fast_clear_type
!= ANV_FAST_CLEAR_NONE
) {
4127 anv_perf_warn(cmd_buffer
->device
->instance
, fb
,
4128 "Doing a partial resolve to get rid of clear color at the "
4129 "end of a renderpass due to an image/view format mismatch");
4131 uint32_t base_layer
, layer_count
;
4132 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4134 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4135 iview
->planes
[0].isl
.base_level
);
4137 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4138 layer_count
= fb
->layers
;
4141 for (uint32_t a
= 0; a
< layer_count
; a
++) {
4142 uint32_t array_layer
= base_layer
+ a
;
4143 if (image
->samples
== 1) {
4144 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
4145 iview
->planes
[0].isl
.format
,
4146 VK_IMAGE_ASPECT_COLOR_BIT
,
4147 iview
->planes
[0].isl
.base_level
,
4149 ISL_AUX_OP_PARTIAL_RESOLVE
,
4150 ANV_FAST_CLEAR_NONE
);
4152 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
4153 iview
->planes
[0].isl
.format
,
4154 VK_IMAGE_ASPECT_COLOR_BIT
,
4156 ISL_AUX_OP_PARTIAL_RESOLVE
,
4157 ANV_FAST_CLEAR_NONE
);
4163 /* Transition the image into the final layout for this render pass */
4164 VkImageLayout target_layout
=
4165 cmd_state
->pass
->attachments
[a
].final_layout
;
4167 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4168 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4170 uint32_t base_layer
, layer_count
;
4171 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4173 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4174 iview
->planes
[0].isl
.base_level
);
4176 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4177 layer_count
= fb
->layers
;
4180 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4181 iview
->planes
[0].isl
.base_level
, 1,
4182 base_layer
, layer_count
,
4183 att_state
->current_layout
, target_layout
);
4184 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4185 transition_depth_buffer(cmd_buffer
, image
,
4186 att_state
->current_layout
, target_layout
);
4190 /* Accumulate any subpass flushes that need to happen after the subpass.
4191 * Yes, they do get accumulated twice in the NextSubpass case but since
4192 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
4193 * ORing the bits in twice so it's harmless.
4195 cmd_buffer
->state
.pending_pipe_bits
|=
4196 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
4199 void genX(CmdBeginRenderPass
)(
4200 VkCommandBuffer commandBuffer
,
4201 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4202 VkSubpassContents contents
)
4204 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4205 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4206 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4208 cmd_buffer
->state
.framebuffer
= framebuffer
;
4209 cmd_buffer
->state
.pass
= pass
;
4210 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4212 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
4214 /* If we failed to setup the attachments we should not try to go further */
4215 if (result
!= VK_SUCCESS
) {
4216 assert(anv_batch_has_error(&cmd_buffer
->batch
));
4220 genX(flush_pipeline_select_3d
)(cmd_buffer
);
4222 cmd_buffer_begin_subpass(cmd_buffer
, 0);
4225 void genX(CmdBeginRenderPass2KHR
)(
4226 VkCommandBuffer commandBuffer
,
4227 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4228 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
4230 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
4231 pSubpassBeginInfo
->contents
);
4234 void genX(CmdNextSubpass
)(
4235 VkCommandBuffer commandBuffer
,
4236 VkSubpassContents contents
)
4238 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4240 if (anv_batch_has_error(&cmd_buffer
->batch
))
4243 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4245 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
4246 cmd_buffer_end_subpass(cmd_buffer
);
4247 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4250 void genX(CmdNextSubpass2KHR
)(
4251 VkCommandBuffer commandBuffer
,
4252 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
4253 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4255 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
4258 void genX(CmdEndRenderPass
)(
4259 VkCommandBuffer commandBuffer
)
4261 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4263 if (anv_batch_has_error(&cmd_buffer
->batch
))
4266 cmd_buffer_end_subpass(cmd_buffer
);
4268 cmd_buffer
->state
.hiz_enabled
= false;
4271 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
4274 /* Remove references to render pass specific state. This enables us to
4275 * detect whether or not we're in a renderpass.
4277 cmd_buffer
->state
.framebuffer
= NULL
;
4278 cmd_buffer
->state
.pass
= NULL
;
4279 cmd_buffer
->state
.subpass
= NULL
;
4282 void genX(CmdEndRenderPass2KHR
)(
4283 VkCommandBuffer commandBuffer
,
4284 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4286 genX(CmdEndRenderPass
)(commandBuffer
);