2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_aux_map.h"
33 #include "common/gen_l3_config.h"
34 #include "genxml/gen_macros.h"
35 #include "genxml/genX_pack.h"
37 /* We reserve GPR 14 and 15 for conditional rendering */
38 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
39 #define __gen_get_batch_dwords anv_batch_emit_dwords
40 #define __gen_address_offset anv_address_add
41 #include "common/gen_mi_builder.h"
44 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
46 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
47 lri
.RegisterOffset
= reg
;
53 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
55 struct anv_device
*device
= cmd_buffer
->device
;
56 uint32_t mocs
= device
->isl_dev
.mocs
.internal
;
58 /* If we are emitting a new state base address we probably need to re-emit
61 cmd_buffer
->state
.descriptors_dirty
|= ~0;
63 /* Emit a render target cache flush.
65 * This isn't documented anywhere in the PRM. However, it seems to be
66 * necessary prior to changing the surface state base adress. Without
67 * this, we get GPU hangs when using multi-level command buffers which
68 * clear depth, reset state base address, and then go render stuff.
70 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
71 pc
.DCFlushEnable
= true;
72 pc
.RenderTargetCacheFlushEnable
= true;
73 pc
.CommandStreamerStallEnable
= true;
75 pc
.TileCacheFlushEnable
= true;
79 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
80 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
81 sba
.GeneralStateMOCS
= mocs
;
82 sba
.GeneralStateBaseAddressModifyEnable
= true;
84 sba
.StatelessDataPortAccessMOCS
= mocs
;
86 sba
.SurfaceStateBaseAddress
=
87 anv_cmd_buffer_surface_base_address(cmd_buffer
);
88 sba
.SurfaceStateMOCS
= mocs
;
89 sba
.SurfaceStateBaseAddressModifyEnable
= true;
91 sba
.DynamicStateBaseAddress
=
92 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
93 sba
.DynamicStateMOCS
= mocs
;
94 sba
.DynamicStateBaseAddressModifyEnable
= true;
96 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
97 sba
.IndirectObjectMOCS
= mocs
;
98 sba
.IndirectObjectBaseAddressModifyEnable
= true;
100 sba
.InstructionBaseAddress
=
101 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
102 sba
.InstructionMOCS
= mocs
;
103 sba
.InstructionBaseAddressModifyEnable
= true;
106 /* Broadwell requires that we specify a buffer size for a bunch of
107 * these fields. However, since we will be growing the BO's live, we
108 * just set them all to the maximum.
110 sba
.GeneralStateBufferSize
= 0xfffff;
111 sba
.GeneralStateBufferSizeModifyEnable
= true;
112 sba
.DynamicStateBufferSize
= 0xfffff;
113 sba
.DynamicStateBufferSizeModifyEnable
= true;
114 sba
.IndirectObjectBufferSize
= 0xfffff;
115 sba
.IndirectObjectBufferSizeModifyEnable
= true;
116 sba
.InstructionBufferSize
= 0xfffff;
117 sba
.InstructionBuffersizeModifyEnable
= true;
119 /* On gen7, we have upper bounds instead. According to the docs,
120 * setting an upper bound of zero means that no bounds checking is
121 * performed so, in theory, we should be able to leave them zero.
122 * However, border color is broken and the GPU bounds-checks anyway.
123 * To avoid this and other potential problems, we may as well set it
126 sba
.GeneralStateAccessUpperBound
=
127 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
128 sba
.GeneralStateAccessUpperBoundModifyEnable
= true;
129 sba
.DynamicStateAccessUpperBound
=
130 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
131 sba
.DynamicStateAccessUpperBoundModifyEnable
= true;
132 sba
.InstructionAccessUpperBound
=
133 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
134 sba
.InstructionAccessUpperBoundModifyEnable
= true;
137 if (cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
) {
138 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) {
139 .bo
= device
->surface_state_pool
.block_pool
.bo
,
142 sba
.BindlessSurfaceStateSize
= (1 << 20) - 1;
144 sba
.BindlessSurfaceStateBaseAddress
= ANV_NULL_ADDRESS
;
145 sba
.BindlessSurfaceStateSize
= 0;
147 sba
.BindlessSurfaceStateMOCS
= mocs
;
148 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
151 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
152 sba
.BindlessSamplerStateMOCS
= mocs
;
153 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
154 sba
.BindlessSamplerStateBufferSize
= 0;
158 /* After re-setting the surface state base address, we have to do some
159 * cache flusing so that the sampler engine will pick up the new
160 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
161 * Shared Function > 3D Sampler > State > State Caching (page 96):
163 * Coherency with system memory in the state cache, like the texture
164 * cache is handled partially by software. It is expected that the
165 * command stream or shader will issue Cache Flush operation or
166 * Cache_Flush sampler message to ensure that the L1 cache remains
167 * coherent with system memory.
171 * Whenever the value of the Dynamic_State_Base_Addr,
172 * Surface_State_Base_Addr are altered, the L1 state cache must be
173 * invalidated to ensure the new surface or sampler state is fetched
174 * from system memory.
176 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
177 * which, according the PIPE_CONTROL instruction documentation in the
180 * Setting this bit is independent of any other bit in this packet.
181 * This bit controls the invalidation of the L1 and L2 state caches
182 * at the top of the pipe i.e. at the parsing time.
184 * Unfortunately, experimentation seems to indicate that state cache
185 * invalidation through a PIPE_CONTROL does nothing whatsoever in
186 * regards to surface state and binding tables. In stead, it seems that
187 * invalidating the texture cache is what is actually needed.
189 * XXX: As far as we have been able to determine through
190 * experimentation, shows that flush the texture cache appears to be
191 * sufficient. The theory here is that all of the sampling/rendering
192 * units cache the binding table in the texture cache. However, we have
193 * yet to be able to actually confirm this.
195 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
196 pc
.TextureCacheInvalidationEnable
= true;
197 pc
.ConstantCacheInvalidationEnable
= true;
198 pc
.StateCacheInvalidationEnable
= true;
203 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
204 struct anv_state state
, struct anv_address addr
)
206 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
209 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
210 state
.offset
+ isl_dev
->ss
.addr_offset
,
211 addr
.bo
, addr
.offset
, NULL
);
212 if (result
!= VK_SUCCESS
)
213 anv_batch_set_error(&cmd_buffer
->batch
, result
);
217 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
218 struct anv_surface_state state
)
220 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
222 assert(!anv_address_is_null(state
.address
));
223 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
225 if (!anv_address_is_null(state
.aux_address
)) {
227 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
228 &cmd_buffer
->pool
->alloc
,
229 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
230 state
.aux_address
.bo
,
231 state
.aux_address
.offset
,
233 if (result
!= VK_SUCCESS
)
234 anv_batch_set_error(&cmd_buffer
->batch
, result
);
237 if (!anv_address_is_null(state
.clear_address
)) {
239 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
240 &cmd_buffer
->pool
->alloc
,
242 isl_dev
->ss
.clear_color_state_offset
,
243 state
.clear_address
.bo
,
244 state
.clear_address
.offset
,
246 if (result
!= VK_SUCCESS
)
247 anv_batch_set_error(&cmd_buffer
->batch
, result
);
252 color_attachment_compute_aux_usage(struct anv_device
* device
,
253 struct anv_cmd_state
* cmd_state
,
254 uint32_t att
, VkRect2D render_area
,
255 union isl_color_value
*fast_clear_color
)
257 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
258 struct anv_image_view
*iview
= cmd_state
->attachments
[att
].image_view
;
260 assert(iview
->n_planes
== 1);
262 if (iview
->planes
[0].isl
.base_array_layer
>=
263 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
264 iview
->planes
[0].isl
.base_level
)) {
265 /* There is no aux buffer which corresponds to the level and layer(s)
268 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
269 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
270 att_state
->fast_clear
= false;
274 att_state
->aux_usage
=
275 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
276 VK_IMAGE_ASPECT_COLOR_BIT
,
277 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
279 /* If we don't have aux, then we should have returned early in the layer
280 * check above. If we got here, we must have something.
282 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
284 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
285 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
286 att_state
->input_aux_usage
= att_state
->aux_usage
;
288 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
290 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
291 * setting is only allowed if Surface Format supported for Fast
292 * Clear. In addition, if the surface is bound to the sampling
293 * engine, Surface Format must be supported for Render Target
294 * Compression for surfaces bound to the sampling engine."
296 * In other words, we can only sample from a fast-cleared image if it
297 * also supports color compression.
299 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
) &&
300 isl_format_supports_ccs_d(&device
->info
, iview
->planes
[0].isl
.format
)) {
301 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
303 /* While fast-clear resolves and partial resolves are fairly cheap in the
304 * case where you render to most of the pixels, full resolves are not
305 * because they potentially involve reading and writing the entire
306 * framebuffer. If we can't texture with CCS_E, we should leave it off and
307 * limit ourselves to fast clears.
309 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
310 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
311 anv_perf_warn(device
->instance
, iview
->image
,
312 "Not temporarily enabling CCS_E.");
315 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
319 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
320 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
322 union isl_color_value clear_color
= {};
323 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
325 att_state
->clear_color_is_zero_one
=
326 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
327 att_state
->clear_color_is_zero
=
328 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
330 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
331 /* Start by getting the fast clear type. We use the first subpass
332 * layout here because we don't want to fast-clear if the first subpass
333 * to use the attachment can't handle fast-clears.
335 enum anv_fast_clear_type fast_clear_type
=
336 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
337 VK_IMAGE_ASPECT_COLOR_BIT
,
338 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
339 switch (fast_clear_type
) {
340 case ANV_FAST_CLEAR_NONE
:
341 att_state
->fast_clear
= false;
343 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
344 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
346 case ANV_FAST_CLEAR_ANY
:
347 att_state
->fast_clear
= true;
351 /* Potentially, we could do partial fast-clears but doing so has crazy
352 * alignment restrictions. It's easier to just restrict to full size
353 * fast clears for now.
355 if (render_area
.offset
.x
!= 0 ||
356 render_area
.offset
.y
!= 0 ||
357 render_area
.extent
.width
!= iview
->extent
.width
||
358 render_area
.extent
.height
!= iview
->extent
.height
)
359 att_state
->fast_clear
= false;
361 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
362 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
363 att_state
->fast_clear
= false;
365 /* We only allow fast clears to the first slice of an image (level 0,
366 * layer 0) and only for the entire slice. This guarantees us that, at
367 * any given time, there is only one clear color on any given image at
368 * any given time. At the time of our testing (Jan 17, 2018), there
369 * were no known applications which would benefit from fast-clearing
370 * more than just the first slice.
372 if (att_state
->fast_clear
&&
373 (iview
->planes
[0].isl
.base_level
> 0 ||
374 iview
->planes
[0].isl
.base_array_layer
> 0)) {
375 anv_perf_warn(device
->instance
, iview
->image
,
376 "Rendering with multi-lod or multi-layer framebuffer "
377 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
378 "baseArrayLayer > 0. Not fast clearing.");
379 att_state
->fast_clear
= false;
380 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
381 anv_perf_warn(device
->instance
, iview
->image
,
382 "Rendering to a multi-layer framebuffer with "
383 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
386 if (att_state
->fast_clear
)
387 *fast_clear_color
= clear_color
;
389 att_state
->fast_clear
= false;
394 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
395 struct anv_cmd_state
*cmd_state
,
396 uint32_t att
, VkRect2D render_area
)
398 struct anv_render_pass_attachment
*pass_att
=
399 &cmd_state
->pass
->attachments
[att
];
400 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
401 struct anv_image_view
*iview
= cmd_state
->attachments
[att
].image_view
;
403 /* These will be initialized after the first subpass transition. */
404 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
405 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
408 /* We don't do any HiZ or depth fast-clears on gen7 yet */
409 att_state
->fast_clear
= false;
413 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
414 /* If we're just clearing stencil, we can always HiZ clear */
415 att_state
->fast_clear
= true;
419 /* Default to false for now */
420 att_state
->fast_clear
= false;
422 /* We must have depth in order to have HiZ */
423 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
426 const enum isl_aux_usage first_subpass_aux_usage
=
427 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
428 VK_IMAGE_ASPECT_DEPTH_BIT
,
429 pass_att
->first_subpass_layout
);
430 if (!blorp_can_hiz_clear_depth(&device
->info
,
431 &iview
->image
->planes
[0].surface
.isl
,
432 first_subpass_aux_usage
,
433 iview
->planes
[0].isl
.base_level
,
434 iview
->planes
[0].isl
.base_array_layer
,
435 render_area
.offset
.x
,
436 render_area
.offset
.y
,
437 render_area
.offset
.x
+
438 render_area
.extent
.width
,
439 render_area
.offset
.y
+
440 render_area
.extent
.height
))
443 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
446 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
447 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
448 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
449 * only supports returning 0.0f. Gens prior to gen8 do not support this
455 /* If we got here, then we can fast clear */
456 att_state
->fast_clear
= true;
460 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
462 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
465 /* We only allocate input attachment states for color surfaces. Compression
466 * is not yet enabled for depth textures and stencil doesn't allow
467 * compression so we can just use the texture surface state from the view.
469 return vk_format_is_color(att
->format
);
472 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
473 * the initial layout is undefined, the HiZ buffer and depth buffer will
474 * represent the same data at the end of this operation.
477 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
478 const struct anv_image
*image
,
479 VkImageLayout initial_layout
,
480 VkImageLayout final_layout
)
482 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
483 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
484 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
485 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
486 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
487 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
489 enum isl_aux_op hiz_op
;
490 if (hiz_enabled
&& !enable_hiz
) {
491 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
492 } else if (!hiz_enabled
&& enable_hiz
) {
493 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
495 assert(hiz_enabled
== enable_hiz
);
496 /* If the same buffer will be used, no resolves are necessary. */
497 hiz_op
= ISL_AUX_OP_NONE
;
500 if (hiz_op
!= ISL_AUX_OP_NONE
)
501 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
506 vk_image_layout_stencil_write_optimal(VkImageLayout layout
)
508 return layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
509 layout
== VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
||
510 layout
== VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
;
513 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
514 * the initial layout is undefined, the HiZ buffer and depth buffer will
515 * represent the same data at the end of this operation.
518 transition_stencil_buffer(struct anv_cmd_buffer
*cmd_buffer
,
519 const struct anv_image
*image
,
520 uint32_t base_level
, uint32_t level_count
,
521 uint32_t base_layer
, uint32_t layer_count
,
522 VkImageLayout initial_layout
,
523 VkImageLayout final_layout
)
526 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
527 VK_IMAGE_ASPECT_STENCIL_BIT
);
529 /* On gen7, we have to store a texturable version of the stencil buffer in
530 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
531 * forth at strategic points. Stencil writes are only allowed in following
534 * - VK_IMAGE_LAYOUT_GENERAL
535 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
536 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
537 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
538 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
540 * For general, we have no nice opportunity to transition so we do the copy
541 * to the shadow unconditionally at the end of the subpass. For transfer
542 * destinations, we can update it as part of the transfer op. For the other
543 * layouts, we delay the copy until a transition into some other layout.
545 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
546 vk_image_layout_stencil_write_optimal(initial_layout
) &&
547 !vk_image_layout_stencil_write_optimal(final_layout
)) {
548 anv_image_copy_to_shadow(cmd_buffer
, image
,
549 VK_IMAGE_ASPECT_STENCIL_BIT
,
550 base_level
, level_count
,
551 base_layer
, layer_count
);
553 #endif /* GEN_GEN == 7 */
556 #define MI_PREDICATE_SRC0 0x2400
557 #define MI_PREDICATE_SRC1 0x2408
558 #define MI_PREDICATE_RESULT 0x2418
561 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
562 const struct anv_image
*image
,
563 VkImageAspectFlagBits aspect
,
565 uint32_t base_layer
, uint32_t layer_count
,
568 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
570 /* We only have compression tracking for CCS_E */
571 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
574 for (uint32_t a
= 0; a
< layer_count
; a
++) {
575 uint32_t layer
= base_layer
+ a
;
576 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
577 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
580 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
586 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
587 const struct anv_image
*image
,
588 VkImageAspectFlagBits aspect
,
589 enum anv_fast_clear_type fast_clear
)
591 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
592 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
594 sdi
.ImmediateData
= fast_clear
;
597 /* Whenever we have fast-clear, we consider that slice to be compressed.
598 * This makes building predicates much easier.
600 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
601 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
604 /* This is only really practical on haswell and above because it requires
605 * MI math in order to get it correct.
607 #if GEN_GEN >= 8 || GEN_IS_HASWELL
609 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
610 const struct anv_image
*image
,
611 VkImageAspectFlagBits aspect
,
612 uint32_t level
, uint32_t array_layer
,
613 enum isl_aux_op resolve_op
,
614 enum anv_fast_clear_type fast_clear_supported
)
616 struct gen_mi_builder b
;
617 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
619 const struct gen_mi_value fast_clear_type
=
620 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
623 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
624 /* In this case, we're doing a full resolve which means we want the
625 * resolve to happen if any compression (including fast-clears) is
628 * In order to simplify the logic a bit, we make the assumption that,
629 * if the first slice has been fast-cleared, it is also marked as
630 * compressed. See also set_image_fast_clear_state.
632 const struct gen_mi_value compression_state
=
633 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer
->device
,
635 level
, array_layer
));
636 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
638 gen_mi_store(&b
, compression_state
, gen_mi_imm(0));
640 if (level
== 0 && array_layer
== 0) {
641 /* If the predicate is true, we want to write 0 to the fast clear type
642 * and, if it's false, leave it alone. We can do this by writing
644 * clear_type = clear_type & ~predicate;
646 struct gen_mi_value new_fast_clear_type
=
647 gen_mi_iand(&b
, fast_clear_type
,
648 gen_mi_inot(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
)));
649 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
651 } else if (level
== 0 && array_layer
== 0) {
652 /* In this case, we are doing a partial resolve to get rid of fast-clear
653 * colors. We don't care about the compression state but we do care
654 * about how much fast clear is allowed by the final layout.
656 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
657 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
659 /* We need to compute (fast_clear_supported < image->fast_clear) */
660 struct gen_mi_value pred
=
661 gen_mi_ult(&b
, gen_mi_imm(fast_clear_supported
), fast_clear_type
);
662 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
663 gen_mi_value_ref(&b
, pred
));
665 /* If the predicate is true, we want to write 0 to the fast clear type
666 * and, if it's false, leave it alone. We can do this by writing
668 * clear_type = clear_type & ~predicate;
670 struct gen_mi_value new_fast_clear_type
=
671 gen_mi_iand(&b
, fast_clear_type
, gen_mi_inot(&b
, pred
));
672 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
674 /* In this case, we're trying to do a partial resolve on a slice that
675 * doesn't have clear color. There's nothing to do.
677 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
681 /* Set src1 to 0 and use a != condition */
682 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
684 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
685 mip
.LoadOperation
= LOAD_LOADINV
;
686 mip
.CombineOperation
= COMBINE_SET
;
687 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
690 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
694 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
695 const struct anv_image
*image
,
696 VkImageAspectFlagBits aspect
,
697 uint32_t level
, uint32_t array_layer
,
698 enum isl_aux_op resolve_op
,
699 enum anv_fast_clear_type fast_clear_supported
)
701 struct gen_mi_builder b
;
702 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
704 struct gen_mi_value fast_clear_type_mem
=
705 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
708 /* This only works for partial resolves and only when the clear color is
709 * all or nothing. On the upside, this emits less command streamer code
710 * and works on Ivybridge and Bay Trail.
712 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
713 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
715 /* We don't support fast clears on anything other than the first slice. */
716 if (level
> 0 || array_layer
> 0)
719 /* On gen8, we don't have a concept of default clear colors because we
720 * can't sample from CCS surfaces. It's enough to just load the fast clear
721 * state into the predicate register.
723 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), fast_clear_type_mem
);
724 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
725 gen_mi_store(&b
, fast_clear_type_mem
, gen_mi_imm(0));
727 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
728 mip
.LoadOperation
= LOAD_LOADINV
;
729 mip
.CombineOperation
= COMBINE_SET
;
730 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
733 #endif /* GEN_GEN <= 8 */
736 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
737 const struct anv_image
*image
,
738 enum isl_format format
,
739 VkImageAspectFlagBits aspect
,
740 uint32_t level
, uint32_t array_layer
,
741 enum isl_aux_op resolve_op
,
742 enum anv_fast_clear_type fast_clear_supported
)
744 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
747 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
748 aspect
, level
, array_layer
,
749 resolve_op
, fast_clear_supported
);
750 #else /* GEN_GEN <= 8 */
751 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
752 aspect
, level
, array_layer
,
753 resolve_op
, fast_clear_supported
);
756 /* CCS_D only supports full resolves and BLORP will assert on us if we try
757 * to do a partial resolve on a CCS_D surface.
759 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
760 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
761 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
763 anv_image_ccs_op(cmd_buffer
, image
, format
, aspect
, level
,
764 array_layer
, 1, resolve_op
, NULL
, true);
768 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
769 const struct anv_image
*image
,
770 enum isl_format format
,
771 VkImageAspectFlagBits aspect
,
772 uint32_t array_layer
,
773 enum isl_aux_op resolve_op
,
774 enum anv_fast_clear_type fast_clear_supported
)
776 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
777 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
779 #if GEN_GEN >= 8 || GEN_IS_HASWELL
780 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
781 aspect
, 0, array_layer
,
782 resolve_op
, fast_clear_supported
);
784 anv_image_mcs_op(cmd_buffer
, image
, format
, aspect
,
785 array_layer
, 1, resolve_op
, NULL
, true);
787 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
792 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
793 const struct anv_image
*image
,
794 VkImageAspectFlagBits aspect
,
795 enum isl_aux_usage aux_usage
,
798 uint32_t layer_count
)
800 /* The aspect must be exactly one of the image aspects. */
801 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
803 /* The only compression types with more than just fast-clears are MCS,
804 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
805 * track the current fast-clear and compression state. This leaves us
806 * with just MCS and CCS_E.
808 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
809 aux_usage
!= ISL_AUX_USAGE_MCS
)
812 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
813 level
, base_layer
, layer_count
, true);
817 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
818 const struct anv_image
*image
,
819 VkImageAspectFlagBits aspect
)
821 assert(cmd_buffer
&& image
);
822 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
824 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
825 ANV_FAST_CLEAR_NONE
);
827 /* Initialize the struct fields that are accessed for fast-clears so that
828 * the HW restrictions on the field values are satisfied.
830 struct anv_address addr
=
831 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
834 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
835 const unsigned num_dwords
= GEN_GEN
>= 10 ?
836 isl_dev
->ss
.clear_color_state_size
/ 4 :
837 isl_dev
->ss
.clear_value_size
/ 4;
838 for (unsigned i
= 0; i
< num_dwords
; i
++) {
839 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
841 sdi
.Address
.offset
+= i
* 4;
842 sdi
.ImmediateData
= 0;
846 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
848 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
849 /* Pre-SKL, the dword containing the clear values also contains
850 * other fields, so we need to initialize those fields to match the
851 * values that would be in a color attachment.
853 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
854 ISL_CHANNEL_SELECT_GREEN
<< 22 |
855 ISL_CHANNEL_SELECT_BLUE
<< 19 |
856 ISL_CHANNEL_SELECT_ALPHA
<< 16;
857 } else if (GEN_GEN
== 7) {
858 /* On IVB, the dword containing the clear values also contains
859 * other fields that must be zero or can be zero.
861 sdi
.ImmediateData
= 0;
867 /* Copy the fast-clear value dword(s) between a surface state object and an
868 * image's fast clear state buffer.
871 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
872 struct anv_state surface_state
,
873 const struct anv_image
*image
,
874 VkImageAspectFlagBits aspect
,
875 bool copy_from_surface_state
)
877 assert(cmd_buffer
&& image
);
878 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
880 struct anv_address ss_clear_addr
= {
881 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
882 .offset
= surface_state
.offset
+
883 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
885 const struct anv_address entry_addr
=
886 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
887 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
890 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
891 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
892 * in-flight when they are issued even if the memory touched is not
893 * currently active for rendering. The weird bit is that it is not the
894 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
895 * rendering hangs such that the next stalling command after the
896 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
898 * It is unclear exactly why this hang occurs. Both MI commands come with
899 * warnings about the 3D pipeline but that doesn't seem to fully explain
900 * it. My (Jason's) best theory is that it has something to do with the
901 * fact that we're using a GPU state register as our temporary and that
902 * something with reading/writing it is causing problems.
904 * In order to work around this issue, we emit a PIPE_CONTROL with the
905 * command streamer stall bit set.
907 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
908 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
911 struct gen_mi_builder b
;
912 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
914 if (copy_from_surface_state
) {
915 gen_mi_memcpy(&b
, entry_addr
, ss_clear_addr
, copy_size
);
917 gen_mi_memcpy(&b
, ss_clear_addr
, entry_addr
, copy_size
);
919 /* Updating a surface state object may require that the state cache be
920 * invalidated. From the SKL PRM, Shared Functions -> State -> State
923 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
924 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
925 * modified [...], the L1 state cache must be invalidated to ensure
926 * the new surface or sampler state is fetched from system memory.
928 * In testing, SKL doesn't actually seem to need this, but HSW does.
930 cmd_buffer
->state
.pending_pipe_bits
|=
931 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
936 * @brief Transitions a color buffer from one layout to another.
938 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
941 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
942 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
943 * this represents the maximum layers to transition at each
944 * specified miplevel.
947 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
948 const struct anv_image
*image
,
949 VkImageAspectFlagBits aspect
,
950 const uint32_t base_level
, uint32_t level_count
,
951 uint32_t base_layer
, uint32_t layer_count
,
952 VkImageLayout initial_layout
,
953 VkImageLayout final_layout
)
955 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
956 /* Validate the inputs. */
958 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
959 /* These values aren't supported for simplicity's sake. */
960 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
961 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
962 /* Ensure the subresource range is valid. */
963 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
964 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
965 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
966 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
967 assert(last_level_num
<= image
->levels
);
968 /* The spec disallows these final layouts. */
969 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
970 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
972 /* No work is necessary if the layout stays the same or if this subresource
973 * range lacks auxiliary data.
975 if (initial_layout
== final_layout
)
978 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
980 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
981 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
982 /* This surface is a linear compressed image with a tiled shadow surface
983 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
984 * we need to ensure the shadow copy is up-to-date.
986 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
987 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
988 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
989 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
991 anv_image_copy_to_shadow(cmd_buffer
, image
,
992 VK_IMAGE_ASPECT_COLOR_BIT
,
993 base_level
, level_count
,
994 base_layer
, layer_count
);
997 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
1000 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
1002 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
1003 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
1004 /* A subresource in the undefined layout may have been aliased and
1005 * populated with any arrangement of bits. Therefore, we must initialize
1006 * the related aux buffer and clear buffer entry with desirable values.
1007 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
1008 * images with VK_IMAGE_TILING_OPTIMAL.
1010 * Initialize the relevant clear buffer entries.
1012 if (base_level
== 0 && base_layer
== 0)
1013 init_fast_clear_color(cmd_buffer
, image
, aspect
);
1015 /* Initialize the aux buffers to enable correct rendering. In order to
1016 * ensure that things such as storage images work correctly, aux buffers
1017 * need to be initialized to valid data.
1019 * Having an aux buffer with invalid data is a problem for two reasons:
1021 * 1) Having an invalid value in the buffer can confuse the hardware.
1022 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1023 * invalid and leads to the hardware doing strange things. It
1024 * doesn't hang as far as we can tell but rendering corruption can
1027 * 2) If this transition is into the GENERAL layout and we then use the
1028 * image as a storage image, then we must have the aux buffer in the
1029 * pass-through state so that, if we then go to texture from the
1030 * image, we get the results of our storage image writes and not the
1031 * fast clear color or other random data.
1033 * For CCS both of the problems above are real demonstrable issues. In
1034 * that case, the only thing we can do is to perform an ambiguate to
1035 * transition the aux surface into the pass-through state.
1037 * For MCS, (2) is never an issue because we don't support multisampled
1038 * storage images. In theory, issue (1) is a problem with MCS but we've
1039 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1040 * theory, be interpreted as something but we don't know that all bit
1041 * patterns are actually valid. For 2x and 8x, you could easily end up
1042 * with the MCS referring to an invalid plane because not all bits of
1043 * the MCS value are actually used. Even though we've never seen issues
1044 * in the wild, it's best to play it safe and initialize the MCS. We
1045 * can use a fast-clear for MCS because we only ever touch from render
1046 * and texture (no image load store).
1048 if (image
->samples
== 1) {
1049 for (uint32_t l
= 0; l
< level_count
; l
++) {
1050 const uint32_t level
= base_level
+ l
;
1052 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1053 if (base_layer
>= aux_layers
)
1054 break; /* We will only get fewer layers as level increases */
1055 uint32_t level_layer_count
=
1056 MIN2(layer_count
, aux_layers
- base_layer
);
1058 anv_image_ccs_op(cmd_buffer
, image
,
1059 image
->planes
[plane
].surface
.isl
.format
,
1060 aspect
, level
, base_layer
, level_layer_count
,
1061 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1063 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1064 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1065 level
, base_layer
, level_layer_count
,
1070 if (image
->samples
== 4 || image
->samples
== 16) {
1071 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1072 "Doing a potentially unnecessary fast-clear to "
1073 "define an MCS buffer.");
1076 assert(base_level
== 0 && level_count
== 1);
1077 anv_image_mcs_op(cmd_buffer
, image
,
1078 image
->planes
[plane
].surface
.isl
.format
,
1079 aspect
, base_layer
, layer_count
,
1080 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1085 const enum isl_aux_usage initial_aux_usage
=
1086 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1087 const enum isl_aux_usage final_aux_usage
=
1088 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1090 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1091 * We can handle transitions between CCS_D/E to and from NONE. What we
1092 * don't yet handle is switching between CCS_E and CCS_D within a given
1093 * image. Doing so in a performant way requires more detailed aux state
1094 * tracking such as what is done in i965. For now, just assume that we
1095 * only have one type of compression.
1097 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1098 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1099 initial_aux_usage
== final_aux_usage
);
1101 /* If initial aux usage is NONE, there is nothing to resolve */
1102 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1105 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1107 /* If the initial layout supports more fast clear than the final layout
1108 * then we need at least a partial resolve.
1110 const enum anv_fast_clear_type initial_fast_clear
=
1111 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1112 const enum anv_fast_clear_type final_fast_clear
=
1113 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1114 if (final_fast_clear
< initial_fast_clear
)
1115 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1117 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1118 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1119 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1121 if (resolve_op
== ISL_AUX_OP_NONE
)
1124 /* Perform a resolve to synchronize data between the main and aux buffer.
1125 * Before we begin, we must satisfy the cache flushing requirement specified
1126 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1128 * Any transition from any value in {Clear, Render, Resolve} to a
1129 * different value in {Clear, Render, Resolve} requires end of pipe
1132 * We perform a flush of the write cache before and after the clear and
1133 * resolve operations to meet this requirement.
1135 * Unlike other drawing, fast clear operations are not properly
1136 * synchronized. The first PIPE_CONTROL here likely ensures that the
1137 * contents of the previous render or clear hit the render target before we
1138 * resolve and the second likely ensures that the resolve is complete before
1139 * we do any more rendering or clearing.
1141 cmd_buffer
->state
.pending_pipe_bits
|=
1142 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1144 for (uint32_t l
= 0; l
< level_count
; l
++) {
1145 uint32_t level
= base_level
+ l
;
1147 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1148 if (base_layer
>= aux_layers
)
1149 break; /* We will only get fewer layers as level increases */
1150 uint32_t level_layer_count
=
1151 MIN2(layer_count
, aux_layers
- base_layer
);
1153 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1154 uint32_t array_layer
= base_layer
+ a
;
1155 if (image
->samples
== 1) {
1156 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1157 image
->planes
[plane
].surface
.isl
.format
,
1158 aspect
, level
, array_layer
, resolve_op
,
1161 /* We only support fast-clear on the first layer so partial
1162 * resolves should not be used on other layers as they will use
1163 * the clear color stored in memory that is only valid for layer0.
1165 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1169 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1170 image
->planes
[plane
].surface
.isl
.format
,
1171 aspect
, array_layer
, resolve_op
,
1177 cmd_buffer
->state
.pending_pipe_bits
|=
1178 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1182 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1185 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1186 struct anv_render_pass
*pass
,
1187 const VkRenderPassBeginInfo
*begin
)
1189 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1190 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1191 struct anv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1193 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1195 if (pass
->attachment_count
> 0) {
1196 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1197 pass
->attachment_count
*
1198 sizeof(state
->attachments
[0]),
1199 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1200 if (state
->attachments
== NULL
) {
1201 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1202 return anv_batch_set_error(&cmd_buffer
->batch
,
1203 VK_ERROR_OUT_OF_HOST_MEMORY
);
1206 state
->attachments
= NULL
;
1209 /* Reserve one for the NULL state. */
1210 unsigned num_states
= 1;
1211 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1212 if (vk_format_is_color(pass
->attachments
[i
].format
))
1215 if (need_input_attachment_state(&pass
->attachments
[i
]))
1219 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1220 state
->render_pass_states
=
1221 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1222 num_states
* ss_stride
, isl_dev
->ss
.align
);
1224 struct anv_state next_state
= state
->render_pass_states
;
1225 next_state
.alloc_size
= isl_dev
->ss
.size
;
1227 state
->null_surface_state
= next_state
;
1228 next_state
.offset
+= ss_stride
;
1229 next_state
.map
+= ss_stride
;
1231 const VkRenderPassAttachmentBeginInfoKHR
*begin_attachment
=
1232 vk_find_struct_const(begin
, RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR
);
1234 if (begin
&& !begin_attachment
)
1235 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1237 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1238 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1239 state
->attachments
[i
].color
.state
= next_state
;
1240 next_state
.offset
+= ss_stride
;
1241 next_state
.map
+= ss_stride
;
1244 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1245 state
->attachments
[i
].input
.state
= next_state
;
1246 next_state
.offset
+= ss_stride
;
1247 next_state
.map
+= ss_stride
;
1250 if (begin_attachment
&& begin_attachment
->attachmentCount
!= 0) {
1251 assert(begin_attachment
->attachmentCount
== pass
->attachment_count
);
1252 ANV_FROM_HANDLE(anv_image_view
, iview
, begin_attachment
->pAttachments
[i
]);
1253 cmd_buffer
->state
.attachments
[i
].image_view
= iview
;
1254 } else if (framebuffer
&& i
< framebuffer
->attachment_count
) {
1255 cmd_buffer
->state
.attachments
[i
].image_view
= framebuffer
->attachments
[i
];
1258 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1259 state
->render_pass_states
.alloc_size
);
1262 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1263 isl_extent3d(framebuffer
->width
,
1264 framebuffer
->height
,
1265 framebuffer
->layers
));
1267 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1268 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1269 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1270 VkImageAspectFlags clear_aspects
= 0;
1271 VkImageAspectFlags load_aspects
= 0;
1273 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1274 /* color attachment */
1275 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1276 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1277 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1278 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1281 /* depthstencil attachment */
1282 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1283 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1284 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1285 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1286 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1289 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1290 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1291 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1292 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1293 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1298 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1299 state
->attachments
[i
].current_stencil_layout
= att
->stencil_initial_layout
;
1300 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1301 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1303 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1305 struct anv_image_view
*iview
= cmd_buffer
->state
.attachments
[i
].image_view
;
1306 anv_assert(iview
->vk_format
== att
->format
);
1308 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1309 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1311 union isl_color_value clear_color
= { .u32
= { 0, } };
1312 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1313 anv_assert(iview
->n_planes
== 1);
1314 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1315 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1316 state
, i
, begin
->renderArea
,
1319 anv_image_fill_surface_state(cmd_buffer
->device
,
1321 VK_IMAGE_ASPECT_COLOR_BIT
,
1322 &iview
->planes
[0].isl
,
1323 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1324 state
->attachments
[i
].aux_usage
,
1327 &state
->attachments
[i
].color
,
1330 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1332 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1337 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1338 anv_image_fill_surface_state(cmd_buffer
->device
,
1340 VK_IMAGE_ASPECT_COLOR_BIT
,
1341 &iview
->planes
[0].isl
,
1342 ISL_SURF_USAGE_TEXTURE_BIT
,
1343 state
->attachments
[i
].input_aux_usage
,
1346 &state
->attachments
[i
].input
,
1349 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1358 genX(BeginCommandBuffer
)(
1359 VkCommandBuffer commandBuffer
,
1360 const VkCommandBufferBeginInfo
* pBeginInfo
)
1362 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1364 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1365 * command buffer's state. Otherwise, we must *reset* its state. In both
1366 * cases we reset it.
1368 * From the Vulkan 1.0 spec:
1370 * If a command buffer is in the executable state and the command buffer
1371 * was allocated from a command pool with the
1372 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1373 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1374 * as if vkResetCommandBuffer had been called with
1375 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1376 * the command buffer in the recording state.
1378 anv_cmd_buffer_reset(cmd_buffer
);
1380 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1382 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1383 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1385 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1387 /* We sometimes store vertex data in the dynamic state buffer for blorp
1388 * operations and our dynamic state stream may re-use data from previous
1389 * command buffers. In order to prevent stale cache data, we flush the VF
1390 * cache. We could do this on every blorp call but that's not really
1391 * needed as all of the data will get written by the CPU prior to the GPU
1392 * executing anything. The chances are fairly high that they will use
1393 * blorp at least once per primary command buffer so it shouldn't be
1396 * There is also a workaround on gen8 which requires us to invalidate the
1397 * VF cache occasionally. It's easier if we can assume we start with a
1398 * fresh cache (See also genX(cmd_buffer_set_binding_for_gen8_vb_flush).)
1400 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1402 /* We send an "Indirect State Pointers Disable" packet at
1403 * EndCommandBuffer, so all push contant packets are ignored during a
1404 * context restore. Documentation says after that command, we need to
1405 * emit push constants again before any rendering operation. So we
1406 * flag them dirty here to make sure they get emitted.
1408 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1410 VkResult result
= VK_SUCCESS
;
1411 if (cmd_buffer
->usage_flags
&
1412 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1413 assert(pBeginInfo
->pInheritanceInfo
);
1414 cmd_buffer
->state
.pass
=
1415 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1416 cmd_buffer
->state
.subpass
=
1417 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1419 /* This is optional in the inheritance info. */
1420 cmd_buffer
->state
.framebuffer
=
1421 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1423 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1424 cmd_buffer
->state
.pass
, NULL
);
1426 /* Record that HiZ is enabled if we can. */
1427 if (cmd_buffer
->state
.framebuffer
) {
1428 const struct anv_image_view
* const iview
=
1429 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1432 VkImageLayout layout
=
1433 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1435 enum isl_aux_usage aux_usage
=
1436 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1437 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1439 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1443 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1446 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1447 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1448 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1449 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1451 /* If secondary buffer supports conditional rendering
1452 * we should emit commands as if conditional rendering is enabled.
1454 cmd_buffer
->state
.conditional_render_enabled
=
1455 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1462 /* From the PRM, Volume 2a:
1464 * "Indirect State Pointers Disable
1466 * At the completion of the post-sync operation associated with this pipe
1467 * control packet, the indirect state pointers in the hardware are
1468 * considered invalid; the indirect pointers are not saved in the context.
1469 * If any new indirect state commands are executed in the command stream
1470 * while the pipe control is pending, the new indirect state commands are
1473 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1474 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1475 * commands are only considered as Indirect State Pointers. Once ISP is
1476 * issued in a context, SW must initialize by programming push constant
1477 * commands for all the shaders (at least to zero length) before attempting
1478 * any rendering operation for the same context."
1480 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1481 * even though they point to a BO that has been already unreferenced at
1482 * the end of the previous batch buffer. This has been fine so far since
1483 * we are protected by these scratch page (every address not covered by
1484 * a BO should be pointing to the scratch page). But on CNL, it is
1485 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1488 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1489 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1490 * context restore, so the mentioned hang doesn't happen. However,
1491 * software must program push constant commands for all stages prior to
1492 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1494 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1495 * constants have been loaded into the EUs prior to disable the push constants
1496 * so that it doesn't hang a previous 3DPRIMITIVE.
1499 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1501 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1502 pc
.StallAtPixelScoreboard
= true;
1503 pc
.CommandStreamerStallEnable
= true;
1505 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1506 pc
.IndirectStatePointersDisable
= true;
1507 pc
.CommandStreamerStallEnable
= true;
1512 genX(EndCommandBuffer
)(
1513 VkCommandBuffer commandBuffer
)
1515 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1517 if (anv_batch_has_error(&cmd_buffer
->batch
))
1518 return cmd_buffer
->batch
.status
;
1520 /* We want every command buffer to start with the PMA fix in a known state,
1521 * so we disable it at the end of the command buffer.
1523 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1525 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1527 emit_isp_disable(cmd_buffer
);
1529 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1535 genX(CmdExecuteCommands
)(
1536 VkCommandBuffer commandBuffer
,
1537 uint32_t commandBufferCount
,
1538 const VkCommandBuffer
* pCmdBuffers
)
1540 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1542 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1544 if (anv_batch_has_error(&primary
->batch
))
1547 /* The secondary command buffers will assume that the PMA fix is disabled
1548 * when they begin executing. Make sure this is true.
1550 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1552 /* The secondary command buffer doesn't know which textures etc. have been
1553 * flushed prior to their execution. Apply those flushes now.
1555 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1557 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1558 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1560 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1561 assert(!anv_batch_has_error(&secondary
->batch
));
1563 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1564 if (secondary
->state
.conditional_render_enabled
) {
1565 if (!primary
->state
.conditional_render_enabled
) {
1566 /* Secondary buffer is constructed as if it will be executed
1567 * with conditional rendering, we should satisfy this dependency
1568 * regardless of conditional rendering being enabled in primary.
1570 struct gen_mi_builder b
;
1571 gen_mi_builder_init(&b
, &primary
->batch
);
1572 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
1573 gen_mi_imm(UINT64_MAX
));
1578 if (secondary
->usage_flags
&
1579 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1580 /* If we're continuing a render pass from the primary, we need to
1581 * copy the surface states for the current subpass into the storage
1582 * we allocated for them in BeginCommandBuffer.
1584 struct anv_bo
*ss_bo
=
1585 primary
->device
->surface_state_pool
.block_pool
.bo
;
1586 struct anv_state src_state
= primary
->state
.render_pass_states
;
1587 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1588 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1590 genX(cmd_buffer_so_memcpy
)(primary
,
1591 (struct anv_address
) {
1593 .offset
= dst_state
.offset
,
1595 (struct anv_address
) {
1597 .offset
= src_state
.offset
,
1599 src_state
.alloc_size
);
1602 anv_cmd_buffer_add_secondary(primary
, secondary
);
1605 /* The secondary isn't counted in our VF cache tracking so we need to
1606 * invalidate the whole thing.
1608 if (GEN_GEN
>= 8 && GEN_GEN
<= 9) {
1609 primary
->state
.pending_pipe_bits
|=
1610 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1613 /* The secondary may have selected a different pipeline (3D or compute) and
1614 * may have changed the current L3$ configuration. Reset our tracking
1615 * variables to invalid values to ensure that we re-emit these in the case
1616 * where we do any draws or compute dispatches from the primary after the
1617 * secondary has returned.
1619 primary
->state
.current_pipeline
= UINT32_MAX
;
1620 primary
->state
.current_l3_config
= NULL
;
1621 primary
->state
.current_hash_scale
= 0;
1623 /* Each of the secondary command buffers will use its own state base
1624 * address. We need to re-emit state base address for the primary after
1625 * all of the secondaries are done.
1627 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1630 genX(cmd_buffer_emit_state_base_address
)(primary
);
1633 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1634 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1635 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1638 * Program the hardware to use the specified L3 configuration.
1641 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1642 const struct gen_l3_config
*cfg
)
1645 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1648 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1649 intel_logd("L3 config transition: ");
1650 gen_dump_l3_config(cfg
, stderr
);
1653 UNUSED
const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1655 /* According to the hardware docs, the L3 partitioning can only be changed
1656 * while the pipeline is completely drained and the caches are flushed,
1657 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1659 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1660 pc
.DCFlushEnable
= true;
1661 pc
.PostSyncOperation
= NoWrite
;
1662 pc
.CommandStreamerStallEnable
= true;
1665 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1666 * invalidation of the relevant caches. Note that because RO invalidation
1667 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1668 * command is processed by the CS) we cannot combine it with the previous
1669 * stalling flush as the hardware documentation suggests, because that
1670 * would cause the CS to stall on previous rendering *after* RO
1671 * invalidation and wouldn't prevent the RO caches from being polluted by
1672 * concurrent rendering before the stall completes. This intentionally
1673 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1674 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1675 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1676 * already guarantee that there is no concurrent GPGPU kernel execution
1677 * (see SKL HSD 2132585).
1679 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1680 pc
.TextureCacheInvalidationEnable
= true;
1681 pc
.ConstantCacheInvalidationEnable
= true;
1682 pc
.InstructionCacheInvalidateEnable
= true;
1683 pc
.StateCacheInvalidationEnable
= true;
1684 pc
.PostSyncOperation
= NoWrite
;
1687 /* Now send a third stalling flush to make sure that invalidation is
1688 * complete when the L3 configuration registers are modified.
1690 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1691 pc
.DCFlushEnable
= true;
1692 pc
.PostSyncOperation
= NoWrite
;
1693 pc
.CommandStreamerStallEnable
= true;
1698 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1701 #define L3_ALLOCATION_REG GENX(L3ALLOC)
1702 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
1704 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
1705 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
1709 anv_pack_struct(&l3cr
, L3_ALLOCATION_REG
,
1711 .SLMEnable
= has_slm
,
1714 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1715 * in L3CNTLREG register. The default setting of the bit is not the
1716 * desirable behavior.
1718 .ErrorDetectionBehaviorControl
= true,
1719 .UseFullWays
= true,
1721 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1722 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1723 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1724 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1726 /* Set up the L3 partitioning. */
1727 emit_lri(&cmd_buffer
->batch
, L3_ALLOCATION_REG_num
, l3cr
);
1731 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1732 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1733 cfg
->n
[GEN_L3P_ALL
];
1734 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1735 cfg
->n
[GEN_L3P_ALL
];
1736 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1737 cfg
->n
[GEN_L3P_ALL
];
1739 assert(!cfg
->n
[GEN_L3P_ALL
]);
1741 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1742 * the matching space on the remaining banks has to be allocated to a
1743 * client (URB for all validated configurations) set to the
1744 * lower-bandwidth 2-bank address hashing mode.
1746 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1747 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1748 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1750 /* Minimum number of ways that can be allocated to the URB. */
1751 const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1752 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1754 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1755 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1756 .ConvertDC_UC
= !has_dc
,
1757 .ConvertIS_UC
= !has_is
,
1758 .ConvertC_UC
= !has_c
,
1759 .ConvertT_UC
= !has_t
);
1761 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1762 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1763 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1765 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1766 .SLMEnable
= has_slm
,
1767 .URBLowBandwidth
= urb_low_bw
,
1768 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1770 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1772 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1773 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1775 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1776 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1777 .ISLowBandwidth
= 0,
1778 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1780 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1781 .TLowBandwidth
= 0);
1783 /* Set up the L3 partitioning. */
1784 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1785 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1786 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1789 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1790 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1791 * them disabled to avoid crashing the system hard.
1793 uint32_t scratch1
, chicken3
;
1794 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1795 .L3AtomicDisable
= !has_dc
);
1796 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1797 .L3AtomicDisableMask
= true,
1798 .L3AtomicDisable
= !has_dc
);
1799 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1800 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1806 cmd_buffer
->state
.current_l3_config
= cfg
;
1810 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1812 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1814 if (cmd_buffer
->device
->instance
->physicalDevice
.always_flush_cache
)
1815 bits
|= ANV_PIPE_FLUSH_BITS
| ANV_PIPE_INVALIDATE_BITS
;
1817 /* Flushes are pipelined while invalidations are handled immediately.
1818 * Therefore, if we're flushing anything then we need to schedule a stall
1819 * before any invalidations can happen.
1821 if (bits
& ANV_PIPE_FLUSH_BITS
)
1822 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1824 /* If we're going to do an invalidate and we have a pending CS stall that
1825 * has yet to be resolved, we do the CS stall now.
1827 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1828 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1829 bits
|= ANV_PIPE_CS_STALL_BIT
;
1830 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1833 if (GEN_GEN
>= 12 &&
1834 ((bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
) ||
1835 (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
))) {
1836 /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
1839 * Unified Cache (Tile Cache Disabled):
1841 * When the Color and Depth (Z) streams are enabled to be cached in
1842 * the DC space of L2, Software must use "Render Target Cache Flush
1843 * Enable" and "Depth Cache Flush Enable" along with "Tile Cache
1844 * Flush" for getting the color and depth (Z) write data to be
1845 * globally observable. In this mode of operation it is not required
1846 * to set "CS Stall" upon setting "Tile Cache Flush" bit.
1848 bits
|= ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
1851 if ((GEN_GEN
>= 8 && GEN_GEN
<= 9) &&
1852 (bits
& ANV_PIPE_CS_STALL_BIT
) &&
1853 (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
)) {
1854 /* If we are doing a VF cache invalidate AND a CS stall (it must be
1855 * both) then we can reset our vertex cache tracking.
1857 memset(cmd_buffer
->state
.gfx
.vb_dirty_ranges
, 0,
1858 sizeof(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
1859 memset(&cmd_buffer
->state
.gfx
.ib_dirty_range
, 0,
1860 sizeof(cmd_buffer
->state
.gfx
.ib_dirty_range
));
1863 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1864 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1866 pipe
.TileCacheFlushEnable
= bits
& ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
1868 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1869 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1870 pipe
.RenderTargetCacheFlushEnable
=
1871 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1873 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1874 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1875 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1878 * According to the Broadwell documentation, any PIPE_CONTROL with the
1879 * "Command Streamer Stall" bit set must also have another bit set,
1880 * with five different options:
1882 * - Render Target Cache Flush
1883 * - Depth Cache Flush
1884 * - Stall at Pixel Scoreboard
1885 * - Post-Sync Operation
1889 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1890 * mesa and it seems to work fine. The choice is fairly arbitrary.
1892 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1893 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1894 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1895 pipe
.StallAtPixelScoreboard
= true;
1898 /* If a render target flush was emitted, then we can toggle off the bit
1899 * saying that render target writes are ongoing.
1901 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
1902 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
1904 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1907 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1908 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1910 * "If the VF Cache Invalidation Enable is set to a 1 in a
1911 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1912 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1913 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1916 * This appears to hang Broadwell, so we restrict it to just gen9.
1918 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1919 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1921 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1922 pipe
.StateCacheInvalidationEnable
=
1923 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1924 pipe
.ConstantCacheInvalidationEnable
=
1925 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1926 pipe
.VFCacheInvalidationEnable
=
1927 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1928 pipe
.TextureCacheInvalidationEnable
=
1929 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1930 pipe
.InstructionCacheInvalidateEnable
=
1931 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1933 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1935 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1936 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1937 * “Write Timestamp”.
1939 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1940 pipe
.PostSyncOperation
= WriteImmediateData
;
1942 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
1946 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1949 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1952 void genX(CmdPipelineBarrier
)(
1953 VkCommandBuffer commandBuffer
,
1954 VkPipelineStageFlags srcStageMask
,
1955 VkPipelineStageFlags destStageMask
,
1957 uint32_t memoryBarrierCount
,
1958 const VkMemoryBarrier
* pMemoryBarriers
,
1959 uint32_t bufferMemoryBarrierCount
,
1960 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1961 uint32_t imageMemoryBarrierCount
,
1962 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1964 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1966 /* XXX: Right now, we're really dumb and just flush whatever categories
1967 * the app asks for. One of these days we may make this a bit better
1968 * but right now that's all the hardware allows for in most areas.
1970 VkAccessFlags src_flags
= 0;
1971 VkAccessFlags dst_flags
= 0;
1973 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1974 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1975 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1978 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1979 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1980 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1983 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1984 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1985 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1986 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1987 const VkImageSubresourceRange
*range
=
1988 &pImageMemoryBarriers
[i
].subresourceRange
;
1990 uint32_t base_layer
, layer_count
;
1991 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1993 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1995 base_layer
= range
->baseArrayLayer
;
1996 layer_count
= anv_get_layerCount(image
, range
);
1999 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
2000 transition_depth_buffer(cmd_buffer
, image
,
2001 pImageMemoryBarriers
[i
].oldLayout
,
2002 pImageMemoryBarriers
[i
].newLayout
);
2005 if (range
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
2006 transition_stencil_buffer(cmd_buffer
, image
,
2007 range
->baseMipLevel
,
2008 anv_get_levelCount(image
, range
),
2009 base_layer
, layer_count
,
2010 pImageMemoryBarriers
[i
].oldLayout
,
2011 pImageMemoryBarriers
[i
].newLayout
);
2014 if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
2015 VkImageAspectFlags color_aspects
=
2016 anv_image_expand_aspects(image
, range
->aspectMask
);
2017 uint32_t aspect_bit
;
2018 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
2019 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
2020 range
->baseMipLevel
,
2021 anv_get_levelCount(image
, range
),
2022 base_layer
, layer_count
,
2023 pImageMemoryBarriers
[i
].oldLayout
,
2024 pImageMemoryBarriers
[i
].newLayout
);
2029 cmd_buffer
->state
.pending_pipe_bits
|=
2030 anv_pipe_flush_bits_for_access_flags(src_flags
) |
2031 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
2035 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
2037 VkShaderStageFlags stages
=
2038 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
2040 /* In order to avoid thrash, we assume that vertex and fragment stages
2041 * always exist. In the rare case where one is missing *and* the other
2042 * uses push concstants, this may be suboptimal. However, avoiding stalls
2043 * seems more important.
2045 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
2047 if (stages
== cmd_buffer
->state
.push_constant_stages
)
2051 const unsigned push_constant_kb
= 32;
2052 #elif GEN_IS_HASWELL
2053 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
2055 const unsigned push_constant_kb
= 16;
2058 const unsigned num_stages
=
2059 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
2060 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
2062 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
2063 * units of 2KB. Incidentally, these are the same platforms that have
2064 * 32KB worth of push constant space.
2066 if (push_constant_kb
== 32)
2067 size_per_stage
&= ~1u;
2069 uint32_t kb_used
= 0;
2070 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
2071 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
2072 anv_batch_emit(&cmd_buffer
->batch
,
2073 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
2074 alloc
._3DCommandSubOpcode
= 18 + i
;
2075 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
2076 alloc
.ConstantBufferSize
= push_size
;
2078 kb_used
+= push_size
;
2081 anv_batch_emit(&cmd_buffer
->batch
,
2082 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
2083 alloc
.ConstantBufferOffset
= kb_used
;
2084 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
2087 cmd_buffer
->state
.push_constant_stages
= stages
;
2089 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
2091 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
2092 * the next 3DPRIMITIVE command after programming the
2093 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
2095 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
2096 * pipeline setup, we need to dirty push constants.
2098 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
2101 static struct anv_address
2102 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
2103 struct anv_descriptor_set
*set
)
2106 /* This is a normal descriptor set */
2107 return (struct anv_address
) {
2108 .bo
= set
->pool
->bo
,
2109 .offset
= set
->desc_mem
.offset
,
2112 /* This is a push descriptor set. We have to flag it as used on the GPU
2113 * so that the next time we push descriptors, we grab a new memory.
2115 struct anv_push_descriptor_set
*push_set
=
2116 (struct anv_push_descriptor_set
*)set
;
2117 push_set
->set_used_on_gpu
= true;
2119 return (struct anv_address
) {
2120 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2121 .offset
= set
->desc_mem
.offset
,
2127 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2128 gl_shader_stage stage
,
2129 struct anv_state
*bt_state
)
2131 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2132 struct anv_cmd_pipeline_state
*pipe_state
;
2133 struct anv_pipeline
*pipeline
;
2134 uint32_t state_offset
;
2137 case MESA_SHADER_COMPUTE
:
2138 pipe_state
= &cmd_buffer
->state
.compute
.base
;
2141 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
2144 pipeline
= pipe_state
->pipeline
;
2146 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2147 *bt_state
= (struct anv_state
) { 0, };
2151 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2152 if (map
->surface_count
== 0) {
2153 *bt_state
= (struct anv_state
) { 0, };
2157 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2160 uint32_t *bt_map
= bt_state
->map
;
2162 if (bt_state
->map
== NULL
)
2163 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2165 /* We only need to emit relocs if we're not using softpin. If we are using
2166 * softpin then we always keep all user-allocated memory objects resident.
2168 const bool need_client_mem_relocs
=
2169 !cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
;
2171 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2172 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2174 struct anv_state surface_state
;
2176 switch (binding
->set
) {
2177 case ANV_DESCRIPTOR_SET_NULL
:
2181 case ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
:
2182 /* Color attachment binding */
2183 assert(stage
== MESA_SHADER_FRAGMENT
);
2184 if (binding
->index
< subpass
->color_count
) {
2185 const unsigned att
=
2186 subpass
->color_attachments
[binding
->index
].attachment
;
2188 /* From the Vulkan 1.0.46 spec:
2190 * "If any color or depth/stencil attachments are
2191 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2194 if (att
== VK_ATTACHMENT_UNUSED
) {
2195 surface_state
= cmd_buffer
->state
.null_surface_state
;
2197 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2200 surface_state
= cmd_buffer
->state
.null_surface_state
;
2203 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2206 case ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
: {
2207 struct anv_state surface_state
=
2208 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2210 struct anv_address constant_data
= {
2211 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2212 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2214 unsigned constant_data_size
=
2215 pipeline
->shaders
[stage
]->constant_data_size
;
2217 const enum isl_format format
=
2218 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2219 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2220 surface_state
, format
,
2221 constant_data
, constant_data_size
, 1);
2223 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2224 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2228 case ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
: {
2229 /* This is always the first binding for compute shaders */
2230 assert(stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2232 struct anv_state surface_state
=
2233 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2235 const enum isl_format format
=
2236 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2237 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2239 cmd_buffer
->state
.compute
.num_workgroups
,
2241 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2242 if (need_client_mem_relocs
) {
2243 add_surface_reloc(cmd_buffer
, surface_state
,
2244 cmd_buffer
->state
.compute
.num_workgroups
);
2249 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2250 /* This is a descriptor set buffer so the set index is actually
2251 * given by binding->binding. (Yes, that's confusing.)
2253 struct anv_descriptor_set
*set
=
2254 pipe_state
->descriptors
[binding
->index
];
2255 assert(set
->desc_mem
.alloc_size
);
2256 assert(set
->desc_surface_state
.alloc_size
);
2257 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2258 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2259 anv_descriptor_set_address(cmd_buffer
, set
));
2264 assert(binding
->set
< MAX_SETS
);
2265 const struct anv_descriptor
*desc
=
2266 &pipe_state
->descriptors
[binding
->set
]->descriptors
[binding
->index
];
2268 switch (desc
->type
) {
2269 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2270 /* Nothing for us to do here */
2273 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2274 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2275 struct anv_surface_state sstate
=
2276 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2277 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2278 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2279 surface_state
= sstate
.state
;
2280 assert(surface_state
.alloc_size
);
2281 if (need_client_mem_relocs
)
2282 add_surface_state_relocs(cmd_buffer
, sstate
);
2285 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2286 assert(stage
== MESA_SHADER_FRAGMENT
);
2287 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2288 /* For depth and stencil input attachments, we treat it like any
2289 * old texture that a user may have bound.
2291 assert(desc
->image_view
->n_planes
== 1);
2292 struct anv_surface_state sstate
=
2293 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2294 desc
->image_view
->planes
[0].general_sampler_surface_state
:
2295 desc
->image_view
->planes
[0].optimal_sampler_surface_state
;
2296 surface_state
= sstate
.state
;
2297 assert(surface_state
.alloc_size
);
2298 if (need_client_mem_relocs
)
2299 add_surface_state_relocs(cmd_buffer
, sstate
);
2301 /* For color input attachments, we create the surface state at
2302 * vkBeginRenderPass time so that we can include aux and clear
2303 * color information.
2305 assert(binding
->input_attachment_index
< subpass
->input_count
);
2306 const unsigned subpass_att
= binding
->input_attachment_index
;
2307 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2308 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2312 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2313 struct anv_surface_state sstate
= (binding
->write_only
)
2314 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2315 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2316 surface_state
= sstate
.state
;
2317 assert(surface_state
.alloc_size
);
2318 if (need_client_mem_relocs
)
2319 add_surface_state_relocs(cmd_buffer
, sstate
);
2323 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2324 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2325 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2326 surface_state
= desc
->buffer_view
->surface_state
;
2327 assert(surface_state
.alloc_size
);
2328 if (need_client_mem_relocs
) {
2329 add_surface_reloc(cmd_buffer
, surface_state
,
2330 desc
->buffer_view
->address
);
2334 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2335 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2336 /* Compute the offset within the buffer */
2337 struct anv_push_constants
*push
=
2338 &cmd_buffer
->state
.push_constants
[stage
];
2340 uint32_t dynamic_offset
=
2341 push
->dynamic_offsets
[binding
->dynamic_offset_index
];
2342 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2343 /* Clamp to the buffer size */
2344 offset
= MIN2(offset
, desc
->buffer
->size
);
2345 /* Clamp the range to the buffer size */
2346 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2348 struct anv_address address
=
2349 anv_address_add(desc
->buffer
->address
, offset
);
2352 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2353 enum isl_format format
=
2354 anv_isl_format_for_descriptor_type(desc
->type
);
2356 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2357 format
, address
, range
, 1);
2358 if (need_client_mem_relocs
)
2359 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2363 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2364 surface_state
= (binding
->write_only
)
2365 ? desc
->buffer_view
->writeonly_storage_surface_state
2366 : desc
->buffer_view
->storage_surface_state
;
2367 assert(surface_state
.alloc_size
);
2368 if (need_client_mem_relocs
) {
2369 add_surface_reloc(cmd_buffer
, surface_state
,
2370 desc
->buffer_view
->address
);
2375 assert(!"Invalid descriptor type");
2378 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2388 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2389 gl_shader_stage stage
,
2390 struct anv_state
*state
)
2392 struct anv_cmd_pipeline_state
*pipe_state
=
2393 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2394 &cmd_buffer
->state
.gfx
.base
;
2395 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2397 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2398 *state
= (struct anv_state
) { 0, };
2402 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2403 if (map
->sampler_count
== 0) {
2404 *state
= (struct anv_state
) { 0, };
2408 uint32_t size
= map
->sampler_count
* 16;
2409 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2411 if (state
->map
== NULL
)
2412 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2414 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2415 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2416 const struct anv_descriptor
*desc
=
2417 &pipe_state
->descriptors
[binding
->set
]->descriptors
[binding
->index
];
2419 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2420 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2423 struct anv_sampler
*sampler
= desc
->sampler
;
2425 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2426 * happens to be zero.
2428 if (sampler
== NULL
)
2431 memcpy(state
->map
+ (s
* 16),
2432 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2439 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2441 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2443 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2444 pipeline
->active_stages
;
2446 VkResult result
= VK_SUCCESS
;
2447 anv_foreach_stage(s
, dirty
) {
2448 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2449 if (result
!= VK_SUCCESS
)
2451 result
= emit_binding_table(cmd_buffer
, s
,
2452 &cmd_buffer
->state
.binding_tables
[s
]);
2453 if (result
!= VK_SUCCESS
)
2457 if (result
!= VK_SUCCESS
) {
2458 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2460 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2461 if (result
!= VK_SUCCESS
)
2464 /* Re-emit state base addresses so we get the new surface state base
2465 * address before we start emitting binding tables etc.
2467 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2469 /* Re-emit all active binding tables */
2470 dirty
|= pipeline
->active_stages
;
2471 anv_foreach_stage(s
, dirty
) {
2472 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2473 if (result
!= VK_SUCCESS
) {
2474 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2477 result
= emit_binding_table(cmd_buffer
, s
,
2478 &cmd_buffer
->state
.binding_tables
[s
]);
2479 if (result
!= VK_SUCCESS
) {
2480 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2486 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2492 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2495 static const uint32_t sampler_state_opcodes
[] = {
2496 [MESA_SHADER_VERTEX
] = 43,
2497 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2498 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2499 [MESA_SHADER_GEOMETRY
] = 46,
2500 [MESA_SHADER_FRAGMENT
] = 47,
2501 [MESA_SHADER_COMPUTE
] = 0,
2504 static const uint32_t binding_table_opcodes
[] = {
2505 [MESA_SHADER_VERTEX
] = 38,
2506 [MESA_SHADER_TESS_CTRL
] = 39,
2507 [MESA_SHADER_TESS_EVAL
] = 40,
2508 [MESA_SHADER_GEOMETRY
] = 41,
2509 [MESA_SHADER_FRAGMENT
] = 42,
2510 [MESA_SHADER_COMPUTE
] = 0,
2513 anv_foreach_stage(s
, stages
) {
2514 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2515 assert(binding_table_opcodes
[s
] > 0);
2517 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2518 anv_batch_emit(&cmd_buffer
->batch
,
2519 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2520 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2521 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2525 /* Always emit binding table pointers if we're asked to, since on SKL
2526 * this is what flushes push constants. */
2527 anv_batch_emit(&cmd_buffer
->batch
,
2528 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2529 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2530 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2535 static struct anv_address
2536 get_push_range_address(struct anv_cmd_buffer
*cmd_buffer
,
2537 gl_shader_stage stage
,
2538 const struct anv_push_range
*range
)
2540 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2541 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2542 switch (range
->set
) {
2543 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2544 /* This is a descriptor set buffer so the set index is
2545 * actually given by binding->binding. (Yes, that's
2548 struct anv_descriptor_set
*set
=
2549 gfx_state
->base
.descriptors
[range
->index
];
2550 return anv_descriptor_set_address(cmd_buffer
, set
);
2554 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
: {
2555 struct anv_state state
=
2556 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2557 return (struct anv_address
) {
2558 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2559 .offset
= state
.offset
,
2565 assert(range
->set
< MAX_SETS
);
2566 struct anv_descriptor_set
*set
=
2567 gfx_state
->base
.descriptors
[range
->set
];
2568 const struct anv_descriptor
*desc
=
2569 &set
->descriptors
[range
->index
];
2571 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2572 return desc
->buffer_view
->address
;
2574 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2575 struct anv_push_constants
*push
=
2576 &cmd_buffer
->state
.push_constants
[stage
];
2577 uint32_t dynamic_offset
=
2578 push
->dynamic_offsets
[range
->dynamic_offset_index
];
2579 return anv_address_add(desc
->buffer
->address
,
2580 desc
->offset
+ dynamic_offset
);
2585 /* For Ivy Bridge, push constants are relative to dynamic state
2586 * base address and we only ever push actual push constants.
2588 assert(range
->length
> 0);
2589 assert(range
->set
== ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
);
2590 struct anv_state state
=
2591 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2592 return (struct anv_address
) {
2593 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2594 .offset
= state
.offset
,
2600 cmd_buffer_emit_push_constant(struct anv_cmd_buffer
*cmd_buffer
,
2601 gl_shader_stage stage
, unsigned buffer_count
)
2603 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2604 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2606 static const uint32_t push_constant_opcodes
[] = {
2607 [MESA_SHADER_VERTEX
] = 21,
2608 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2609 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2610 [MESA_SHADER_GEOMETRY
] = 22,
2611 [MESA_SHADER_FRAGMENT
] = 23,
2612 [MESA_SHADER_COMPUTE
] = 0,
2615 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2616 assert(push_constant_opcodes
[stage
] > 0);
2618 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2619 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2621 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2622 const struct anv_pipeline_bind_map
*bind_map
=
2623 &pipeline
->shaders
[stage
]->bind_map
;
2625 /* The Skylake PRM contains the following restriction:
2627 * "The driver must ensure The following case does not occur
2628 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2629 * buffer 3 read length equal to zero committed followed by a
2630 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2633 * To avoid this, we program the buffers in the highest slots.
2634 * This way, slot 0 is only used if slot 3 is also used.
2636 assert(buffer_count
<= 4);
2637 const unsigned shift
= 4 - buffer_count
;
2638 for (unsigned i
= 0; i
< buffer_count
; i
++) {
2639 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
2641 /* At this point we only have non-empty ranges */
2642 assert(range
->length
> 0);
2644 /* For Ivy Bridge, make sure we only set the first range (actual
2647 assert((GEN_GEN
>= 8 || GEN_IS_HASWELL
) || i
== 0);
2649 const struct anv_address addr
=
2650 get_push_range_address(cmd_buffer
, stage
, range
);
2651 c
.ConstantBody
.ReadLength
[i
+ shift
] = range
->length
;
2652 c
.ConstantBody
.Buffer
[i
+ shift
] =
2653 anv_address_add(addr
, range
->start
* 32);
2661 cmd_buffer_emit_push_constant_all(struct anv_cmd_buffer
*cmd_buffer
,
2662 uint32_t shader_mask
, uint32_t count
)
2665 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_ALL
), c
) {
2666 c
.ShaderUpdateEnable
= shader_mask
;
2671 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2672 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2674 static const uint32_t push_constant_opcodes
[] = {
2675 [MESA_SHADER_VERTEX
] = 21,
2676 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2677 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2678 [MESA_SHADER_GEOMETRY
] = 22,
2679 [MESA_SHADER_FRAGMENT
] = 23,
2680 [MESA_SHADER_COMPUTE
] = 0,
2683 gl_shader_stage stage
= vk_to_mesa_shader_stage(shader_mask
);
2684 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2685 assert(push_constant_opcodes
[stage
] > 0);
2687 const struct anv_pipeline_bind_map
*bind_map
=
2688 &pipeline
->shaders
[stage
]->bind_map
;
2691 const uint32_t buffers
= (1 << count
) - 1;
2692 const uint32_t num_dwords
= 2 + 2 * count
;
2694 dw
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2695 GENX(3DSTATE_CONSTANT_ALL
),
2696 .ShaderUpdateEnable
= shader_mask
,
2697 .PointerBufferMask
= buffers
);
2699 for (int i
= 0; i
< count
; i
++) {
2700 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
2701 const struct anv_address addr
=
2702 get_push_range_address(cmd_buffer
, stage
, range
);
2704 GENX(3DSTATE_CONSTANT_ALL_DATA_pack
)(
2705 &cmd_buffer
->batch
, dw
+ 2 + i
* 2,
2706 &(struct GENX(3DSTATE_CONSTANT_ALL_DATA
)) {
2707 .PointerToConstantBuffer
= anv_address_add(addr
, range
->start
* 32),
2708 .ConstantBufferReadLength
= range
->length
,
2715 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2716 VkShaderStageFlags dirty_stages
)
2718 VkShaderStageFlags flushed
= 0;
2719 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2720 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2723 uint32_t nobuffer_stages
= 0;
2726 anv_foreach_stage(stage
, dirty_stages
) {
2727 unsigned buffer_count
= 0;
2728 flushed
|= mesa_to_vk_shader_stage(stage
);
2729 uint32_t max_push_range
= 0;
2731 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2732 const struct anv_pipeline_bind_map
*bind_map
=
2733 &pipeline
->shaders
[stage
]->bind_map
;
2735 for (unsigned i
= 0; i
< 4; i
++) {
2736 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
2737 if (range
->length
> 0) {
2739 if (GEN_GEN
>= 12 && range
->length
> max_push_range
)
2740 max_push_range
= range
->length
;
2746 /* If this stage doesn't have any push constants, emit it later in a
2747 * single CONSTANT_ALL packet.
2749 if (buffer_count
== 0) {
2750 nobuffer_stages
|= 1 << stage
;
2754 /* The Constant Buffer Read Length field from 3DSTATE_CONSTANT_ALL
2755 * contains only 5 bits, so we can only use it for buffers smaller than
2758 if (max_push_range
< 32) {
2759 cmd_buffer_emit_push_constant_all(cmd_buffer
, 1 << stage
,
2765 cmd_buffer_emit_push_constant(cmd_buffer
, stage
, buffer_count
);
2769 if (nobuffer_stages
)
2770 cmd_buffer_emit_push_constant_all(cmd_buffer
, nobuffer_stages
, 0);
2773 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2778 genX(cmd_buffer_aux_map_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2780 void *aux_map_ctx
= cmd_buffer
->device
->aux_map_ctx
;
2783 uint32_t aux_map_state_num
= gen_aux_map_get_state_num(aux_map_ctx
);
2784 if (cmd_buffer
->state
.last_aux_map_state
!= aux_map_state_num
) {
2785 /* If the aux-map state number increased, then we need to rewrite the
2786 * register. Rewriting the register is used to both set the aux-map
2787 * translation table address, and also to invalidate any previously
2788 * cached translations.
2790 uint64_t base_addr
= gen_aux_map_get_base(aux_map_ctx
);
2791 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
2792 lri
.RegisterOffset
= GENX(GFX_AUX_TABLE_BASE_ADDR_num
);
2793 lri
.DataDWord
= base_addr
& 0xffffffff;
2795 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
2796 lri
.RegisterOffset
= GENX(GFX_AUX_TABLE_BASE_ADDR_num
) + 4;
2797 lri
.DataDWord
= base_addr
>> 32;
2799 cmd_buffer
->state
.last_aux_map_state
= aux_map_state_num
;
2805 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2807 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2810 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2811 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2812 vb_emit
|= pipeline
->vb_used
;
2814 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2816 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2818 genX(cmd_buffer_emit_hashing_mode
)(cmd_buffer
, UINT_MAX
, UINT_MAX
, 1);
2820 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2823 genX(cmd_buffer_aux_map_state
)(cmd_buffer
);
2827 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2828 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2830 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2831 GENX(3DSTATE_VERTEX_BUFFERS
));
2833 for_each_bit(vb
, vb_emit
) {
2834 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2835 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2837 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2838 .VertexBufferIndex
= vb
,
2840 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
2842 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2843 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2846 .AddressModifyEnable
= true,
2847 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2848 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2851 .BufferSize
= buffer
->size
- offset
2853 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2857 #if GEN_GEN >= 8 && GEN_GEN <= 9
2858 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(cmd_buffer
, vb
,
2859 state
.BufferStartingAddress
,
2863 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2868 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2871 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
2872 /* We don't need any per-buffer dirty tracking because you're not
2873 * allowed to bind different XFB buffers while XFB is enabled.
2875 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
2876 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
2877 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
2879 sob
.SOBufferIndex
= idx
;
2881 sob
._3DCommandOpcode
= 0;
2882 sob
._3DCommandSubOpcode
= SO_BUFFER_INDEX_0_CMD
+ idx
;
2885 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
2886 sob
.SOBufferEnable
= true;
2887 sob
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
,
2888 sob
.StreamOffsetWriteEnable
= false;
2889 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
2891 /* Size is in DWords - 1 */
2892 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
2897 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
2899 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2903 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2904 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2906 /* If the pipeline changed, we may need to re-allocate push constant
2909 cmd_buffer_alloc_push_constants(cmd_buffer
);
2913 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2914 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2915 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2917 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2918 * stall needs to be sent just prior to any 3DSTATE_VS,
2919 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2920 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2921 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2922 * PIPE_CONTROL needs to be sent before any combination of VS
2923 * associated 3DSTATE."
2925 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2926 pc
.DepthStallEnable
= true;
2927 pc
.PostSyncOperation
= WriteImmediateData
;
2929 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
2934 /* Render targets live in the same binding table as fragment descriptors */
2935 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2936 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2938 /* We emit the binding tables and sampler tables first, then emit push
2939 * constants and then finally emit binding table and sampler table
2940 * pointers. It has to happen in this order, since emitting the binding
2941 * tables may change the push constants (in case of storage images). After
2942 * emitting push constants, on SKL+ we have to emit the corresponding
2943 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2946 if (cmd_buffer
->state
.descriptors_dirty
)
2947 dirty
= flush_descriptor_sets(cmd_buffer
);
2949 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2950 /* Because we're pushing UBOs, we have to push whenever either
2951 * descriptors or push constants is dirty.
2953 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2954 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2955 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2959 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2961 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2962 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2964 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2965 ANV_CMD_DIRTY_PIPELINE
)) {
2966 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2967 pipeline
->depth_clamp_enable
);
2970 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2971 ANV_CMD_DIRTY_RENDER_TARGETS
))
2972 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2974 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2978 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2979 struct anv_address addr
,
2980 uint32_t size
, uint32_t index
)
2982 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2983 GENX(3DSTATE_VERTEX_BUFFERS
));
2985 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2986 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2987 .VertexBufferIndex
= index
,
2988 .AddressModifyEnable
= true,
2990 .MOCS
= addr
.bo
? anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
) : 0,
2991 .NullVertexBuffer
= size
== 0,
2993 .BufferStartingAddress
= addr
,
2996 .BufferStartingAddress
= addr
,
2997 .EndAddress
= anv_address_add(addr
, size
),
3001 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(cmd_buffer
,
3006 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
3007 struct anv_address addr
)
3009 emit_vertex_bo(cmd_buffer
, addr
, addr
.bo
? 8 : 0, ANV_SVGS_VB_INDEX
);
3013 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
3014 uint32_t base_vertex
, uint32_t base_instance
)
3016 if (base_vertex
== 0 && base_instance
== 0) {
3017 emit_base_vertex_instance_bo(cmd_buffer
, ANV_NULL_ADDRESS
);
3019 struct anv_state id_state
=
3020 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
3022 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
3023 ((uint32_t *)id_state
.map
)[1] = base_instance
;
3025 struct anv_address addr
= {
3026 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3027 .offset
= id_state
.offset
,
3030 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
3035 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
3037 struct anv_state state
=
3038 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
3040 ((uint32_t *)state
.map
)[0] = draw_index
;
3042 struct anv_address addr
= {
3043 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3044 .offset
= state
.offset
,
3047 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
3051 update_dirty_vbs_for_gen8_vb_flush(struct anv_cmd_buffer
*cmd_buffer
,
3052 uint32_t access_type
)
3054 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3055 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3057 uint64_t vb_used
= pipeline
->vb_used
;
3058 if (vs_prog_data
->uses_firstvertex
||
3059 vs_prog_data
->uses_baseinstance
)
3060 vb_used
|= 1ull << ANV_SVGS_VB_INDEX
;
3061 if (vs_prog_data
->uses_drawid
)
3062 vb_used
|= 1ull << ANV_DRAWID_VB_INDEX
;
3064 genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush
)(cmd_buffer
,
3065 access_type
== RANDOM
,
3070 VkCommandBuffer commandBuffer
,
3071 uint32_t vertexCount
,
3072 uint32_t instanceCount
,
3073 uint32_t firstVertex
,
3074 uint32_t firstInstance
)
3076 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3077 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3078 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3080 if (anv_batch_has_error(&cmd_buffer
->batch
))
3083 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3085 if (cmd_buffer
->state
.conditional_render_enabled
)
3086 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3088 if (vs_prog_data
->uses_firstvertex
||
3089 vs_prog_data
->uses_baseinstance
)
3090 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3091 if (vs_prog_data
->uses_drawid
)
3092 emit_draw_index(cmd_buffer
, 0);
3094 /* Emitting draw index or vertex index BOs may result in needing
3095 * additional VF cache flushes.
3097 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3099 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3100 * different views. We need to multiply instanceCount by the view count.
3102 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3104 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3105 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3106 prim
.VertexAccessType
= SEQUENTIAL
;
3107 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3108 prim
.VertexCountPerInstance
= vertexCount
;
3109 prim
.StartVertexLocation
= firstVertex
;
3110 prim
.InstanceCount
= instanceCount
;
3111 prim
.StartInstanceLocation
= firstInstance
;
3112 prim
.BaseVertexLocation
= 0;
3115 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3118 void genX(CmdDrawIndexed
)(
3119 VkCommandBuffer commandBuffer
,
3120 uint32_t indexCount
,
3121 uint32_t instanceCount
,
3122 uint32_t firstIndex
,
3123 int32_t vertexOffset
,
3124 uint32_t firstInstance
)
3126 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3127 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3128 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3130 if (anv_batch_has_error(&cmd_buffer
->batch
))
3133 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3135 if (cmd_buffer
->state
.conditional_render_enabled
)
3136 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3138 if (vs_prog_data
->uses_firstvertex
||
3139 vs_prog_data
->uses_baseinstance
)
3140 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
3141 if (vs_prog_data
->uses_drawid
)
3142 emit_draw_index(cmd_buffer
, 0);
3144 /* Emitting draw index or vertex index BOs may result in needing
3145 * additional VF cache flushes.
3147 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3149 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3150 * different views. We need to multiply instanceCount by the view count.
3152 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3154 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3155 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3156 prim
.VertexAccessType
= RANDOM
;
3157 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3158 prim
.VertexCountPerInstance
= indexCount
;
3159 prim
.StartVertexLocation
= firstIndex
;
3160 prim
.InstanceCount
= instanceCount
;
3161 prim
.StartInstanceLocation
= firstInstance
;
3162 prim
.BaseVertexLocation
= vertexOffset
;
3165 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
3168 /* Auto-Draw / Indirect Registers */
3169 #define GEN7_3DPRIM_END_OFFSET 0x2420
3170 #define GEN7_3DPRIM_START_VERTEX 0x2430
3171 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
3172 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
3173 #define GEN7_3DPRIM_START_INSTANCE 0x243C
3174 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
3176 void genX(CmdDrawIndirectByteCountEXT
)(
3177 VkCommandBuffer commandBuffer
,
3178 uint32_t instanceCount
,
3179 uint32_t firstInstance
,
3180 VkBuffer counterBuffer
,
3181 VkDeviceSize counterBufferOffset
,
3182 uint32_t counterOffset
,
3183 uint32_t vertexStride
)
3185 #if GEN_IS_HASWELL || GEN_GEN >= 8
3186 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3187 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
3188 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3189 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3191 /* firstVertex is always zero for this draw function */
3192 const uint32_t firstVertex
= 0;
3194 if (anv_batch_has_error(&cmd_buffer
->batch
))
3197 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3199 if (vs_prog_data
->uses_firstvertex
||
3200 vs_prog_data
->uses_baseinstance
)
3201 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3202 if (vs_prog_data
->uses_drawid
)
3203 emit_draw_index(cmd_buffer
, 0);
3205 /* Emitting draw index or vertex index BOs may result in needing
3206 * additional VF cache flushes.
3208 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3210 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3211 * different views. We need to multiply instanceCount by the view count.
3213 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3215 struct gen_mi_builder b
;
3216 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3217 struct gen_mi_value count
=
3218 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
3219 counterBufferOffset
));
3221 count
= gen_mi_isub(&b
, count
, gen_mi_imm(counterOffset
));
3222 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
3223 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
3225 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3226 gen_mi_imm(firstVertex
));
3227 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
3228 gen_mi_imm(instanceCount
));
3229 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3230 gen_mi_imm(firstInstance
));
3231 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3233 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3234 prim
.IndirectParameterEnable
= true;
3235 prim
.VertexAccessType
= SEQUENTIAL
;
3236 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3239 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3240 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3244 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
3245 struct anv_address addr
,
3248 struct gen_mi_builder b
;
3249 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3251 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
),
3252 gen_mi_mem32(anv_address_add(addr
, 0)));
3254 struct gen_mi_value instance_count
= gen_mi_mem32(anv_address_add(addr
, 4));
3255 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3256 if (view_count
> 1) {
3257 #if GEN_IS_HASWELL || GEN_GEN >= 8
3258 instance_count
= gen_mi_imul_imm(&b
, instance_count
, view_count
);
3260 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3261 "MI_MATH is not supported on Ivy Bridge");
3264 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
), instance_count
);
3266 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3267 gen_mi_mem32(anv_address_add(addr
, 8)));
3270 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
),
3271 gen_mi_mem32(anv_address_add(addr
, 12)));
3272 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3273 gen_mi_mem32(anv_address_add(addr
, 16)));
3275 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3276 gen_mi_mem32(anv_address_add(addr
, 12)));
3277 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3281 void genX(CmdDrawIndirect
)(
3282 VkCommandBuffer commandBuffer
,
3284 VkDeviceSize offset
,
3288 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3289 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3290 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3291 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3293 if (anv_batch_has_error(&cmd_buffer
->batch
))
3296 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3298 if (cmd_buffer
->state
.conditional_render_enabled
)
3299 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3301 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3302 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3304 if (vs_prog_data
->uses_firstvertex
||
3305 vs_prog_data
->uses_baseinstance
)
3306 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3307 if (vs_prog_data
->uses_drawid
)
3308 emit_draw_index(cmd_buffer
, i
);
3310 /* Emitting draw index or vertex index BOs may result in needing
3311 * additional VF cache flushes.
3313 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3315 load_indirect_parameters(cmd_buffer
, draw
, false);
3317 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3318 prim
.IndirectParameterEnable
= true;
3319 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3320 prim
.VertexAccessType
= SEQUENTIAL
;
3321 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3324 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3330 void genX(CmdDrawIndexedIndirect
)(
3331 VkCommandBuffer commandBuffer
,
3333 VkDeviceSize offset
,
3337 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3338 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3339 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3340 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3342 if (anv_batch_has_error(&cmd_buffer
->batch
))
3345 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3347 if (cmd_buffer
->state
.conditional_render_enabled
)
3348 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3350 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3351 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3353 /* TODO: We need to stomp base vertex to 0 somehow */
3354 if (vs_prog_data
->uses_firstvertex
||
3355 vs_prog_data
->uses_baseinstance
)
3356 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3357 if (vs_prog_data
->uses_drawid
)
3358 emit_draw_index(cmd_buffer
, i
);
3360 /* Emitting draw index or vertex index BOs may result in needing
3361 * additional VF cache flushes.
3363 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3365 load_indirect_parameters(cmd_buffer
, draw
, true);
3367 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3368 prim
.IndirectParameterEnable
= true;
3369 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3370 prim
.VertexAccessType
= RANDOM
;
3371 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3374 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
3380 #define TMP_DRAW_COUNT_REG 0x2670 /* MI_ALU_REG14 */
3383 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3384 struct anv_address count_address
,
3385 const bool conditional_render_enabled
)
3387 struct gen_mi_builder b
;
3388 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3390 if (conditional_render_enabled
) {
3391 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3392 gen_mi_store(&b
, gen_mi_reg64(TMP_DRAW_COUNT_REG
),
3393 gen_mi_mem32(count_address
));
3396 /* Upload the current draw count from the draw parameters buffer to
3397 * MI_PREDICATE_SRC0.
3399 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
3400 gen_mi_mem32(count_address
));
3402 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
+ 4), gen_mi_imm(0));
3407 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3408 uint32_t draw_index
)
3410 struct gen_mi_builder b
;
3411 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3413 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3414 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
), gen_mi_imm(draw_index
));
3416 if (draw_index
== 0) {
3417 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3418 mip
.LoadOperation
= LOAD_LOADINV
;
3419 mip
.CombineOperation
= COMBINE_SET
;
3420 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3423 /* While draw_index < draw_count the predicate's result will be
3424 * (draw_index == draw_count) ^ TRUE = TRUE
3425 * When draw_index == draw_count the result is
3426 * (TRUE) ^ TRUE = FALSE
3427 * After this all results will be:
3428 * (FALSE) ^ FALSE = FALSE
3430 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3431 mip
.LoadOperation
= LOAD_LOAD
;
3432 mip
.CombineOperation
= COMBINE_XOR
;
3433 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3438 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3440 emit_draw_count_predicate_with_conditional_render(
3441 struct anv_cmd_buffer
*cmd_buffer
,
3442 uint32_t draw_index
)
3444 struct gen_mi_builder b
;
3445 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3447 struct gen_mi_value pred
= gen_mi_ult(&b
, gen_mi_imm(draw_index
),
3448 gen_mi_reg64(TMP_DRAW_COUNT_REG
));
3449 pred
= gen_mi_iand(&b
, pred
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
));
3452 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_RESULT
), pred
);
3454 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3455 * so we emit MI_PREDICATE to set it.
3458 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), pred
);
3459 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3461 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3462 mip
.LoadOperation
= LOAD_LOADINV
;
3463 mip
.CombineOperation
= COMBINE_SET
;
3464 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3470 void genX(CmdDrawIndirectCountKHR
)(
3471 VkCommandBuffer commandBuffer
,
3473 VkDeviceSize offset
,
3474 VkBuffer _countBuffer
,
3475 VkDeviceSize countBufferOffset
,
3476 uint32_t maxDrawCount
,
3479 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3480 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3481 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3482 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3483 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3484 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3486 if (anv_batch_has_error(&cmd_buffer
->batch
))
3489 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3491 struct anv_address count_address
=
3492 anv_address_add(count_buffer
->address
, countBufferOffset
);
3494 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3495 cmd_state
->conditional_render_enabled
);
3497 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3498 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3500 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3501 if (cmd_state
->conditional_render_enabled
) {
3502 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3504 emit_draw_count_predicate(cmd_buffer
, i
);
3507 emit_draw_count_predicate(cmd_buffer
, i
);
3510 if (vs_prog_data
->uses_firstvertex
||
3511 vs_prog_data
->uses_baseinstance
)
3512 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3513 if (vs_prog_data
->uses_drawid
)
3514 emit_draw_index(cmd_buffer
, i
);
3516 /* Emitting draw index or vertex index BOs may result in needing
3517 * additional VF cache flushes.
3519 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3521 load_indirect_parameters(cmd_buffer
, draw
, false);
3523 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3524 prim
.IndirectParameterEnable
= true;
3525 prim
.PredicateEnable
= true;
3526 prim
.VertexAccessType
= SEQUENTIAL
;
3527 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3530 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3536 void genX(CmdDrawIndexedIndirectCountKHR
)(
3537 VkCommandBuffer commandBuffer
,
3539 VkDeviceSize offset
,
3540 VkBuffer _countBuffer
,
3541 VkDeviceSize countBufferOffset
,
3542 uint32_t maxDrawCount
,
3545 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3546 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3547 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3548 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3549 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3550 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3552 if (anv_batch_has_error(&cmd_buffer
->batch
))
3555 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3557 struct anv_address count_address
=
3558 anv_address_add(count_buffer
->address
, countBufferOffset
);
3560 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3561 cmd_state
->conditional_render_enabled
);
3563 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3564 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3566 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3567 if (cmd_state
->conditional_render_enabled
) {
3568 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3570 emit_draw_count_predicate(cmd_buffer
, i
);
3573 emit_draw_count_predicate(cmd_buffer
, i
);
3576 /* TODO: We need to stomp base vertex to 0 somehow */
3577 if (vs_prog_data
->uses_firstvertex
||
3578 vs_prog_data
->uses_baseinstance
)
3579 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3580 if (vs_prog_data
->uses_drawid
)
3581 emit_draw_index(cmd_buffer
, i
);
3583 /* Emitting draw index or vertex index BOs may result in needing
3584 * additional VF cache flushes.
3586 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3588 load_indirect_parameters(cmd_buffer
, draw
, true);
3590 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3591 prim
.IndirectParameterEnable
= true;
3592 prim
.PredicateEnable
= true;
3593 prim
.VertexAccessType
= RANDOM
;
3594 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3597 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
3603 void genX(CmdBeginTransformFeedbackEXT
)(
3604 VkCommandBuffer commandBuffer
,
3605 uint32_t firstCounterBuffer
,
3606 uint32_t counterBufferCount
,
3607 const VkBuffer
* pCounterBuffers
,
3608 const VkDeviceSize
* pCounterBufferOffsets
)
3610 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3612 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3613 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3614 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3616 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3618 * "Ssoftware must ensure that no HW stream output operations can be in
3619 * process or otherwise pending at the point that the MI_LOAD/STORE
3620 * commands are processed. This will likely require a pipeline flush."
3622 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3623 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3625 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3626 /* If we have a counter buffer, this is a resume so we need to load the
3627 * value into the streamout offset register. Otherwise, this is a begin
3628 * and we need to reset it to zero.
3630 if (pCounterBuffers
&&
3631 idx
>= firstCounterBuffer
&&
3632 idx
- firstCounterBuffer
< counterBufferCount
&&
3633 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
3634 uint32_t cb_idx
= idx
- firstCounterBuffer
;
3635 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3636 uint64_t offset
= pCounterBufferOffsets
?
3637 pCounterBufferOffsets
[cb_idx
] : 0;
3639 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3640 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3641 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3645 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
3646 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3652 cmd_buffer
->state
.xfb_enabled
= true;
3653 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3656 void genX(CmdEndTransformFeedbackEXT
)(
3657 VkCommandBuffer commandBuffer
,
3658 uint32_t firstCounterBuffer
,
3659 uint32_t counterBufferCount
,
3660 const VkBuffer
* pCounterBuffers
,
3661 const VkDeviceSize
* pCounterBufferOffsets
)
3663 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3665 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3666 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3667 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3669 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3671 * "Ssoftware must ensure that no HW stream output operations can be in
3672 * process or otherwise pending at the point that the MI_LOAD/STORE
3673 * commands are processed. This will likely require a pipeline flush."
3675 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3676 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3678 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
3679 unsigned idx
= firstCounterBuffer
+ cb_idx
;
3681 /* If we have a counter buffer, this is a resume so we need to load the
3682 * value into the streamout offset register. Otherwise, this is a begin
3683 * and we need to reset it to zero.
3685 if (pCounterBuffers
&&
3686 cb_idx
< counterBufferCount
&&
3687 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
3688 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3689 uint64_t offset
= pCounterBufferOffsets
?
3690 pCounterBufferOffsets
[cb_idx
] : 0;
3692 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
3693 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3695 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3700 cmd_buffer
->state
.xfb_enabled
= false;
3701 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3705 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
3707 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3708 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
3711 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3712 if (result
!= VK_SUCCESS
) {
3713 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3715 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
3716 if (result
!= VK_SUCCESS
)
3719 /* Re-emit state base addresses so we get the new surface state base
3720 * address before we start emitting binding tables etc.
3722 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
3724 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3725 if (result
!= VK_SUCCESS
) {
3726 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3731 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3732 if (result
!= VK_SUCCESS
) {
3733 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3737 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3738 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3739 .BindingTablePointer
= surfaces
.offset
,
3740 .SamplerStatePointer
= samplers
.offset
,
3742 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3744 struct anv_state state
=
3745 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3746 pipeline
->interface_descriptor_data
,
3747 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3750 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3751 anv_batch_emit(&cmd_buffer
->batch
,
3752 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3753 mid
.InterfaceDescriptorTotalLength
= size
;
3754 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3761 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3763 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3766 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3768 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3770 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3773 genX(cmd_buffer_aux_map_state
)(cmd_buffer
);
3776 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3777 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3779 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3780 * the only bits that are changed are scoreboard related: Scoreboard
3781 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3782 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3785 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3786 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3788 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3790 /* The workgroup size of the pipeline affects our push constant layout
3791 * so flag push constants as dirty if we change the pipeline.
3793 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3796 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3797 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3798 /* FIXME: figure out descriptors for gen7 */
3799 result
= flush_compute_descriptor_set(cmd_buffer
);
3800 if (result
!= VK_SUCCESS
)
3803 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3806 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3807 struct anv_state push_state
=
3808 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3810 if (push_state
.alloc_size
) {
3811 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3812 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3813 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3817 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3820 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3822 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3828 verify_cmd_parser(const struct anv_device
*device
,
3829 int required_version
,
3830 const char *function
)
3832 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3833 return vk_errorf(device
->instance
, device
->instance
,
3834 VK_ERROR_FEATURE_NOT_PRESENT
,
3835 "cmd parser version %d is required for %s",
3836 required_version
, function
);
3845 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3846 uint32_t baseGroupX
,
3847 uint32_t baseGroupY
,
3848 uint32_t baseGroupZ
)
3850 if (anv_batch_has_error(&cmd_buffer
->batch
))
3853 struct anv_push_constants
*push
=
3854 &cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3855 if (push
->cs
.base_work_group_id
[0] != baseGroupX
||
3856 push
->cs
.base_work_group_id
[1] != baseGroupY
||
3857 push
->cs
.base_work_group_id
[2] != baseGroupZ
) {
3858 push
->cs
.base_work_group_id
[0] = baseGroupX
;
3859 push
->cs
.base_work_group_id
[1] = baseGroupY
;
3860 push
->cs
.base_work_group_id
[2] = baseGroupZ
;
3862 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3866 void genX(CmdDispatch
)(
3867 VkCommandBuffer commandBuffer
,
3872 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3875 void genX(CmdDispatchBase
)(
3876 VkCommandBuffer commandBuffer
,
3877 uint32_t baseGroupX
,
3878 uint32_t baseGroupY
,
3879 uint32_t baseGroupZ
,
3880 uint32_t groupCountX
,
3881 uint32_t groupCountY
,
3882 uint32_t groupCountZ
)
3884 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3885 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3886 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3888 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3889 baseGroupY
, baseGroupZ
);
3891 if (anv_batch_has_error(&cmd_buffer
->batch
))
3894 if (prog_data
->uses_num_work_groups
) {
3895 struct anv_state state
=
3896 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3897 uint32_t *sizes
= state
.map
;
3898 sizes
[0] = groupCountX
;
3899 sizes
[1] = groupCountY
;
3900 sizes
[2] = groupCountZ
;
3901 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3902 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3903 .offset
= state
.offset
,
3907 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3909 if (cmd_buffer
->state
.conditional_render_enabled
)
3910 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3912 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3913 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3914 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3915 ggw
.ThreadDepthCounterMaximum
= 0;
3916 ggw
.ThreadHeightCounterMaximum
= 0;
3917 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3918 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3919 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3920 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3921 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3922 ggw
.BottomExecutionMask
= 0xffffffff;
3925 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3928 #define GPGPU_DISPATCHDIMX 0x2500
3929 #define GPGPU_DISPATCHDIMY 0x2504
3930 #define GPGPU_DISPATCHDIMZ 0x2508
3932 void genX(CmdDispatchIndirect
)(
3933 VkCommandBuffer commandBuffer
,
3935 VkDeviceSize offset
)
3937 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3938 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3939 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3940 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3941 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3942 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3944 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3947 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3948 * indirect dispatch registers to be written.
3950 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3951 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3955 if (prog_data
->uses_num_work_groups
)
3956 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3958 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3960 struct gen_mi_builder b
;
3961 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3963 struct gen_mi_value size_x
= gen_mi_mem32(anv_address_add(addr
, 0));
3964 struct gen_mi_value size_y
= gen_mi_mem32(anv_address_add(addr
, 4));
3965 struct gen_mi_value size_z
= gen_mi_mem32(anv_address_add(addr
, 8));
3967 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMX
), size_x
);
3968 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMY
), size_y
);
3969 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMZ
), size_z
);
3972 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3973 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), size_x
);
3974 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3975 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3976 mip
.LoadOperation
= LOAD_LOAD
;
3977 mip
.CombineOperation
= COMBINE_SET
;
3978 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3981 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3982 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_y
);
3983 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3984 mip
.LoadOperation
= LOAD_LOAD
;
3985 mip
.CombineOperation
= COMBINE_OR
;
3986 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3989 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3990 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_z
);
3991 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3992 mip
.LoadOperation
= LOAD_LOAD
;
3993 mip
.CombineOperation
= COMBINE_OR
;
3994 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3997 /* predicate = !predicate; */
3998 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3999 mip
.LoadOperation
= LOAD_LOADINV
;
4000 mip
.CombineOperation
= COMBINE_OR
;
4001 mip
.CompareOperation
= COMPARE_FALSE
;
4005 if (cmd_buffer
->state
.conditional_render_enabled
) {
4006 /* predicate &= !(conditional_rendering_predicate == 0); */
4007 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
),
4008 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
4009 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4010 mip
.LoadOperation
= LOAD_LOADINV
;
4011 mip
.CombineOperation
= COMBINE_AND
;
4012 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4017 #else /* GEN_GEN > 7 */
4018 if (cmd_buffer
->state
.conditional_render_enabled
)
4019 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
4022 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
4023 ggw
.IndirectParameterEnable
= true;
4024 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
4025 cmd_buffer
->state
.conditional_render_enabled
;
4026 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
4027 ggw
.ThreadDepthCounterMaximum
= 0;
4028 ggw
.ThreadHeightCounterMaximum
= 0;
4029 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
4030 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
4031 ggw
.BottomExecutionMask
= 0xffffffff;
4034 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
4038 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
4041 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4043 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
4046 #if GEN_GEN >= 8 && GEN_GEN < 10
4047 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
4049 * Software must clear the COLOR_CALC_STATE Valid field in
4050 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
4051 * with Pipeline Select set to GPGPU.
4053 * The internal hardware docs recommend the same workaround for Gen9
4056 if (pipeline
== GPGPU
)
4057 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
4061 if (pipeline
== _3D
) {
4062 /* There is a mid-object preemption workaround which requires you to
4063 * re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D. However,
4064 * even without preemption, we have issues with geometry flickering when
4065 * GPGPU and 3D are back-to-back and this seems to fix it. We don't
4068 const uint32_t subslices
=
4069 MAX2(cmd_buffer
->device
->instance
->physicalDevice
.subslice_total
, 1);
4070 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
4071 vfe
.MaximumNumberofThreads
=
4072 devinfo
->max_cs_threads
* subslices
- 1;
4073 vfe
.NumberofURBEntries
= 2;
4074 vfe
.URBEntryAllocationSize
= 2;
4079 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
4080 * PIPELINE_SELECT [DevBWR+]":
4084 * Software must ensure all the write caches are flushed through a
4085 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
4086 * command to invalidate read only caches prior to programming
4087 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
4089 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4090 pc
.RenderTargetCacheFlushEnable
= true;
4091 pc
.DepthCacheFlushEnable
= true;
4092 pc
.DCFlushEnable
= true;
4093 pc
.PostSyncOperation
= NoWrite
;
4094 pc
.CommandStreamerStallEnable
= true;
4096 pc
.TileCacheFlushEnable
= true;
4100 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4101 pc
.TextureCacheInvalidationEnable
= true;
4102 pc
.ConstantCacheInvalidationEnable
= true;
4103 pc
.StateCacheInvalidationEnable
= true;
4104 pc
.InstructionCacheInvalidateEnable
= true;
4105 pc
.PostSyncOperation
= NoWrite
;
4107 pc
.TileCacheFlushEnable
= true;
4111 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
4115 ps
.PipelineSelection
= pipeline
;
4119 if (devinfo
->is_geminilake
) {
4122 * "This chicken bit works around a hardware issue with barrier logic
4123 * encountered when switching between GPGPU and 3D pipelines. To
4124 * workaround the issue, this mode bit should be set after a pipeline
4128 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
4130 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
4131 : GLK_BARRIER_MODE_3D_HULL
,
4132 .GLKBarrierModeMask
= 1);
4133 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
4137 cmd_buffer
->state
.current_pipeline
= pipeline
;
4141 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
4143 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
4147 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
4149 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
4153 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
4158 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
4160 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
4161 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
4162 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
4163 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
4164 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
4165 * Depth Flush Bit set, followed by another pipelined depth stall
4166 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
4167 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
4168 * via a preceding MI_FLUSH)."
4170 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4171 pipe
.DepthStallEnable
= true;
4173 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4174 pipe
.DepthCacheFlushEnable
= true;
4176 pipe
.TileCacheFlushEnable
= true;
4179 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4180 pipe
.DepthStallEnable
= true;
4184 /* From the Skylake PRM, 3DSTATE_VERTEX_BUFFERS:
4186 * "The VF cache needs to be invalidated before binding and then using
4187 * Vertex Buffers that overlap with any previously bound Vertex Buffer
4188 * (at a 64B granularity) since the last invalidation. A VF cache
4189 * invalidate is performed by setting the "VF Cache Invalidation Enable"
4190 * bit in PIPE_CONTROL."
4192 * This is implemented by carefully tracking all vertex and index buffer
4193 * bindings and flushing if the cache ever ends up with a range in the cache
4194 * that would exceed 4 GiB. This is implemented in three parts:
4196 * 1. genX(cmd_buffer_set_binding_for_gen8_vb_flush)() which must be called
4197 * every time a 3DSTATE_VERTEX_BUFFER packet is emitted and informs the
4198 * tracking code of the new binding. If this new binding would cause
4199 * the cache to have a too-large range on the next draw call, a pipeline
4200 * stall and VF cache invalidate are added to pending_pipeline_bits.
4202 * 2. genX(cmd_buffer_apply_pipe_flushes)() resets the cache tracking to
4203 * empty whenever we emit a VF invalidate.
4205 * 3. genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush)() must be called
4206 * after every 3DPRIMITIVE and copies the bound range into the dirty
4207 * range for each used buffer. This has to be a separate step because
4208 * we don't always re-bind all buffers and so 1. can't know which
4209 * buffers are actually bound.
4212 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(struct anv_cmd_buffer
*cmd_buffer
,
4214 struct anv_address vb_address
,
4217 if (GEN_GEN
< 8 || GEN_GEN
> 9 ||
4218 !cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
)
4221 struct anv_vb_cache_range
*bound
, *dirty
;
4222 if (vb_index
== -1) {
4223 bound
= &cmd_buffer
->state
.gfx
.ib_bound_range
;
4224 dirty
= &cmd_buffer
->state
.gfx
.ib_dirty_range
;
4226 assert(vb_index
>= 0);
4227 assert(vb_index
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_bound_ranges
));
4228 assert(vb_index
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
4229 bound
= &cmd_buffer
->state
.gfx
.vb_bound_ranges
[vb_index
];
4230 dirty
= &cmd_buffer
->state
.gfx
.vb_dirty_ranges
[vb_index
];
4239 assert(vb_address
.bo
&& (vb_address
.bo
->flags
& EXEC_OBJECT_PINNED
));
4240 bound
->start
= gen_48b_address(anv_address_physical(vb_address
));
4241 bound
->end
= bound
->start
+ vb_size
;
4242 assert(bound
->end
> bound
->start
); /* No overflow */
4244 /* Align everything to a cache line */
4245 bound
->start
&= ~(64ull - 1ull);
4246 bound
->end
= align_u64(bound
->end
, 64);
4248 /* Compute the dirty range */
4249 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4250 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4252 /* If our range is larger than 32 bits, we have to flush */
4253 assert(bound
->end
- bound
->start
<= (1ull << 32));
4254 if (dirty
->end
- dirty
->start
> (1ull << 32)) {
4255 cmd_buffer
->state
.pending_pipe_bits
|=
4256 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
4261 genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush
)(struct anv_cmd_buffer
*cmd_buffer
,
4262 uint32_t access_type
,
4265 if (GEN_GEN
< 8 || GEN_GEN
> 9 ||
4266 !cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
)
4269 if (access_type
== RANDOM
) {
4270 /* We have an index buffer */
4271 struct anv_vb_cache_range
*bound
= &cmd_buffer
->state
.gfx
.ib_bound_range
;
4272 struct anv_vb_cache_range
*dirty
= &cmd_buffer
->state
.gfx
.ib_dirty_range
;
4274 if (bound
->end
> bound
->start
) {
4275 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4276 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4280 uint64_t mask
= vb_used
;
4282 int i
= u_bit_scan64(&mask
);
4284 assert(i
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_bound_ranges
));
4285 assert(i
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
4287 struct anv_vb_cache_range
*bound
, *dirty
;
4288 bound
= &cmd_buffer
->state
.gfx
.vb_bound_ranges
[i
];
4289 dirty
= &cmd_buffer
->state
.gfx
.vb_dirty_ranges
[i
];
4291 if (bound
->end
> bound
->start
) {
4292 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4293 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4299 * Update the pixel hashing modes that determine the balancing of PS threads
4300 * across subslices and slices.
4302 * \param width Width bound of the rendering area (already scaled down if \p
4303 * scale is greater than 1).
4304 * \param height Height bound of the rendering area (already scaled down if \p
4305 * scale is greater than 1).
4306 * \param scale The number of framebuffer samples that could potentially be
4307 * affected by an individual channel of the PS thread. This is
4308 * typically one for single-sampled rendering, but for operations
4309 * like CCS resolves and fast clears a single PS invocation may
4310 * update a huge number of pixels, in which case a finer
4311 * balancing is desirable in order to maximally utilize the
4312 * bandwidth available. UINT_MAX can be used as shorthand for
4313 * "finest hashing mode available".
4316 genX(cmd_buffer_emit_hashing_mode
)(struct anv_cmd_buffer
*cmd_buffer
,
4317 unsigned width
, unsigned height
,
4321 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4322 const unsigned slice_hashing
[] = {
4323 /* Because all Gen9 platforms with more than one slice require
4324 * three-way subslice hashing, a single "normal" 16x16 slice hashing
4325 * block is guaranteed to suffer from substantial imbalance, with one
4326 * subslice receiving twice as much work as the other two in the
4329 * The performance impact of that would be particularly severe when
4330 * three-way hashing is also in use for slice balancing (which is the
4331 * case for all Gen9 GT4 platforms), because one of the slices
4332 * receives one every three 16x16 blocks in either direction, which
4333 * is roughly the periodicity of the underlying subslice imbalance
4334 * pattern ("roughly" because in reality the hardware's
4335 * implementation of three-way hashing doesn't do exact modulo 3
4336 * arithmetic, which somewhat decreases the magnitude of this effect
4337 * in practice). This leads to a systematic subslice imbalance
4338 * within that slice regardless of the size of the primitive. The
4339 * 32x32 hashing mode guarantees that the subslice imbalance within a
4340 * single slice hashing block is minimal, largely eliminating this
4344 /* Finest slice hashing mode available. */
4347 const unsigned subslice_hashing
[] = {
4348 /* 16x16 would provide a slight cache locality benefit especially
4349 * visible in the sampler L1 cache efficiency of low-bandwidth
4350 * non-LLC platforms, but it comes at the cost of greater subslice
4351 * imbalance for primitives of dimensions approximately intermediate
4352 * between 16x4 and 16x16.
4355 /* Finest subslice hashing mode available. */
4358 /* Dimensions of the smallest hashing block of a given hashing mode. If
4359 * the rendering area is smaller than this there can't possibly be any
4360 * benefit from switching to this mode, so we optimize out the
4363 const unsigned min_size
[][2] = {
4367 const unsigned idx
= scale
> 1;
4369 if (cmd_buffer
->state
.current_hash_scale
!= scale
&&
4370 (width
> min_size
[idx
][0] || height
> min_size
[idx
][1])) {
4373 anv_pack_struct(>_mode
, GENX(GT_MODE
),
4374 .SliceHashing
= (devinfo
->num_slices
> 1 ? slice_hashing
[idx
] : 0),
4375 .SliceHashingMask
= (devinfo
->num_slices
> 1 ? -1 : 0),
4376 .SubsliceHashing
= subslice_hashing
[idx
],
4377 .SubsliceHashingMask
= -1);
4379 cmd_buffer
->state
.pending_pipe_bits
|=
4380 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
4381 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4383 emit_lri(&cmd_buffer
->batch
, GENX(GT_MODE_num
), gt_mode
);
4385 cmd_buffer
->state
.current_hash_scale
= scale
;
4391 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
4393 struct anv_device
*device
= cmd_buffer
->device
;
4394 const struct anv_image_view
*iview
=
4395 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
4396 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
4398 /* FIXME: Width and Height are wrong */
4400 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
4402 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
4403 device
->isl_dev
.ds
.size
/ 4);
4407 struct isl_depth_stencil_hiz_emit_info info
= { };
4410 info
.view
= &iview
->planes
[0].isl
;
4412 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
4413 uint32_t depth_plane
=
4414 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
4415 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
4417 info
.depth_surf
= &surface
->isl
;
4419 info
.depth_address
=
4420 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4421 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
4422 image
->planes
[depth_plane
].address
.bo
,
4423 image
->planes
[depth_plane
].address
.offset
+
4426 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
4429 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
4430 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
4431 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
4432 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
4435 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4436 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
4437 image
->planes
[depth_plane
].address
.bo
,
4438 image
->planes
[depth_plane
].address
.offset
+
4439 image
->planes
[depth_plane
].aux_surface
.offset
);
4441 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
4445 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4446 uint32_t stencil_plane
=
4447 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
4448 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
4450 info
.stencil_surf
= &surface
->isl
;
4452 info
.stencil_address
=
4453 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4454 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
4455 image
->planes
[stencil_plane
].address
.bo
,
4456 image
->planes
[stencil_plane
].address
.offset
+
4459 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
4462 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
4464 if (GEN_GEN
>= 12) {
4465 /* GEN:BUG:1408224581
4467 * Workaround: Gen12LP Astep only An additional pipe control with
4468 * post-sync = store dword operation would be required.( w/a is to
4469 * have an additional pipe control after the stencil state whenever
4470 * the surface state bits of this state is changing).
4472 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4473 pc
.PostSyncOperation
= WriteImmediateData
;
4475 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
4478 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
4482 * This ANDs the view mask of the current subpass with the pending clear
4483 * views in the attachment to get the mask of views active in the subpass
4484 * that still need to be cleared.
4486 static inline uint32_t
4487 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
4488 const struct anv_attachment_state
*att_state
)
4490 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
4494 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
4495 const struct anv_attachment_state
*att_state
)
4497 if (!cmd_state
->subpass
->view_mask
)
4500 uint32_t pending_clear_mask
=
4501 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4503 return pending_clear_mask
& 1;
4507 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
4510 const uint32_t last_subpass_idx
=
4511 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
4512 const struct anv_subpass
*last_subpass
=
4513 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
4514 return last_subpass
== cmd_state
->subpass
;
4518 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
4519 uint32_t subpass_id
)
4521 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4522 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
4523 cmd_state
->subpass
= subpass
;
4525 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
4527 /* Our implementation of VK_KHR_multiview uses instancing to draw the
4528 * different views. If the client asks for instancing, we need to use the
4529 * Instance Data Step Rate to ensure that we repeat the client's
4530 * per-instance data once for each view. Since this bit is in
4531 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
4535 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
4537 /* It is possible to start a render pass with an old pipeline. Because the
4538 * render pass and subpass index are both baked into the pipeline, this is
4539 * highly unlikely. In order to do so, it requires that you have a render
4540 * pass with a single subpass and that you use that render pass twice
4541 * back-to-back and use the same pipeline at the start of the second render
4542 * pass as at the end of the first. In order to avoid unpredictable issues
4543 * with this edge case, we just dirty the pipeline at the start of every
4546 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
4548 /* Accumulate any subpass flushes that need to happen before the subpass */
4549 cmd_buffer
->state
.pending_pipe_bits
|=
4550 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
4552 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4553 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4555 bool is_multiview
= subpass
->view_mask
!= 0;
4557 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4558 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4559 if (a
== VK_ATTACHMENT_UNUSED
)
4562 assert(a
< cmd_state
->pass
->attachment_count
);
4563 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4565 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
4566 const struct anv_image
*image
= iview
->image
;
4568 /* A resolve is necessary before use as an input attachment if the clear
4569 * color or auxiliary buffer usage isn't supported by the sampler.
4571 const bool input_needs_resolve
=
4572 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
4573 att_state
->input_aux_usage
!= att_state
->aux_usage
;
4575 VkImageLayout target_layout
, target_stencil_layout
;
4576 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
4577 !input_needs_resolve
) {
4578 /* Layout transitions before the final only help to enable sampling
4579 * as an input attachment. If the input attachment supports sampling
4580 * using the auxiliary surface, we can skip such transitions by
4581 * making the target layout one that is CCS-aware.
4583 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
4585 target_layout
= subpass
->attachments
[i
].layout
;
4586 target_stencil_layout
= subpass
->attachments
[i
].stencil_layout
;
4589 uint32_t base_layer
, layer_count
;
4590 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4592 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4593 iview
->planes
[0].isl
.base_level
);
4595 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4596 layer_count
= fb
->layers
;
4599 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4600 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4601 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4602 iview
->planes
[0].isl
.base_level
, 1,
4603 base_layer
, layer_count
,
4604 att_state
->current_layout
, target_layout
);
4607 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4608 transition_depth_buffer(cmd_buffer
, image
,
4609 att_state
->current_layout
, target_layout
);
4610 att_state
->aux_usage
=
4611 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
4612 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
4615 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4616 transition_stencil_buffer(cmd_buffer
, image
,
4617 iview
->planes
[0].isl
.base_level
, 1,
4618 base_layer
, layer_count
,
4619 att_state
->current_stencil_layout
,
4620 target_stencil_layout
);
4622 att_state
->current_layout
= target_layout
;
4623 att_state
->current_stencil_layout
= target_stencil_layout
;
4625 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
4626 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4628 /* Multi-planar images are not supported as attachments */
4629 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4630 assert(image
->n_planes
== 1);
4632 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
4633 uint32_t clear_layer_count
= fb
->layers
;
4635 if (att_state
->fast_clear
&&
4636 do_first_layer_clear(cmd_state
, att_state
)) {
4637 /* We only support fast-clears on the first layer */
4638 assert(iview
->planes
[0].isl
.base_level
== 0);
4639 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4641 union isl_color_value clear_color
= {};
4642 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
4643 if (iview
->image
->samples
== 1) {
4644 anv_image_ccs_op(cmd_buffer
, image
,
4645 iview
->planes
[0].isl
.format
,
4646 VK_IMAGE_ASPECT_COLOR_BIT
,
4647 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4651 anv_image_mcs_op(cmd_buffer
, image
,
4652 iview
->planes
[0].isl
.format
,
4653 VK_IMAGE_ASPECT_COLOR_BIT
,
4654 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4659 clear_layer_count
--;
4661 att_state
->pending_clear_views
&= ~1;
4663 if (att_state
->clear_color_is_zero
) {
4664 /* This image has the auxiliary buffer enabled. We can mark the
4665 * subresource as not needing a resolve because the clear color
4666 * will match what's in every RENDER_SURFACE_STATE object when
4667 * it's being used for sampling.
4669 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4670 VK_IMAGE_ASPECT_COLOR_BIT
,
4671 ANV_FAST_CLEAR_DEFAULT_VALUE
);
4673 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4674 VK_IMAGE_ASPECT_COLOR_BIT
,
4675 ANV_FAST_CLEAR_ANY
);
4679 /* From the VkFramebufferCreateInfo spec:
4681 * "If the render pass uses multiview, then layers must be one and each
4682 * attachment requires a number of layers that is greater than the
4683 * maximum bit index set in the view mask in the subpasses in which it
4686 * So if multiview is active we ignore the number of layers in the
4687 * framebuffer and instead we honor the view mask from the subpass.
4690 assert(image
->n_planes
== 1);
4691 uint32_t pending_clear_mask
=
4692 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4695 for_each_bit(layer_idx
, pending_clear_mask
) {
4697 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4699 anv_image_clear_color(cmd_buffer
, image
,
4700 VK_IMAGE_ASPECT_COLOR_BIT
,
4701 att_state
->aux_usage
,
4702 iview
->planes
[0].isl
.format
,
4703 iview
->planes
[0].isl
.swizzle
,
4704 iview
->planes
[0].isl
.base_level
,
4707 vk_to_isl_color(att_state
->clear_value
.color
));
4710 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4711 } else if (clear_layer_count
> 0) {
4712 assert(image
->n_planes
== 1);
4713 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4714 att_state
->aux_usage
,
4715 iview
->planes
[0].isl
.format
,
4716 iview
->planes
[0].isl
.swizzle
,
4717 iview
->planes
[0].isl
.base_level
,
4718 base_clear_layer
, clear_layer_count
,
4720 vk_to_isl_color(att_state
->clear_value
.color
));
4722 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
4723 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4724 if (att_state
->fast_clear
&& !is_multiview
) {
4725 /* We currently only support HiZ for single-layer images */
4726 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4727 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
4728 assert(iview
->planes
[0].isl
.base_level
== 0);
4729 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4730 assert(fb
->layers
== 1);
4733 anv_image_hiz_clear(cmd_buffer
, image
,
4734 att_state
->pending_clear_aspects
,
4735 iview
->planes
[0].isl
.base_level
,
4736 iview
->planes
[0].isl
.base_array_layer
,
4737 fb
->layers
, render_area
,
4738 att_state
->clear_value
.depthStencil
.stencil
);
4739 } else if (is_multiview
) {
4740 uint32_t pending_clear_mask
=
4741 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4744 for_each_bit(layer_idx
, pending_clear_mask
) {
4746 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4748 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4749 att_state
->pending_clear_aspects
,
4750 att_state
->aux_usage
,
4751 iview
->planes
[0].isl
.base_level
,
4754 att_state
->clear_value
.depthStencil
.depth
,
4755 att_state
->clear_value
.depthStencil
.stencil
);
4758 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4760 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4761 att_state
->pending_clear_aspects
,
4762 att_state
->aux_usage
,
4763 iview
->planes
[0].isl
.base_level
,
4764 iview
->planes
[0].isl
.base_array_layer
,
4765 fb
->layers
, render_area
,
4766 att_state
->clear_value
.depthStencil
.depth
,
4767 att_state
->clear_value
.depthStencil
.stencil
);
4770 assert(att_state
->pending_clear_aspects
== 0);
4774 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4775 image
->planes
[0].aux_surface
.isl
.size_B
> 0 &&
4776 iview
->planes
[0].isl
.base_level
== 0 &&
4777 iview
->planes
[0].isl
.base_array_layer
== 0) {
4778 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
4779 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
4780 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4781 false /* copy to ss */);
4784 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
4785 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
4786 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
4787 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4788 false /* copy to ss */);
4792 if (subpass
->attachments
[i
].usage
==
4793 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
4794 /* We assume that if we're starting a subpass, we're going to do some
4795 * rendering so we may end up with compressed data.
4797 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
4798 VK_IMAGE_ASPECT_COLOR_BIT
,
4799 att_state
->aux_usage
,
4800 iview
->planes
[0].isl
.base_level
,
4801 iview
->planes
[0].isl
.base_array_layer
,
4803 } else if (subpass
->attachments
[i
].usage
==
4804 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
4805 /* We may be writing depth or stencil so we need to mark the surface.
4806 * Unfortunately, there's no way to know at this point whether the
4807 * depth or stencil tests used will actually write to the surface.
4809 * Even though stencil may be plane 1, it always shares a base_level
4812 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
4813 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4814 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4815 VK_IMAGE_ASPECT_DEPTH_BIT
,
4816 att_state
->aux_usage
,
4817 ds_view
->base_level
,
4818 ds_view
->base_array_layer
,
4821 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4822 /* Even though stencil may be plane 1, it always shares a
4823 * base_level with depth.
4825 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4826 VK_IMAGE_ASPECT_STENCIL_BIT
,
4828 ds_view
->base_level
,
4829 ds_view
->base_array_layer
,
4834 /* If multiview is enabled, then we are only done clearing when we no
4835 * longer have pending layers to clear, or when we have processed the
4836 * last subpass that uses this attachment.
4838 if (!is_multiview
||
4839 att_state
->pending_clear_views
== 0 ||
4840 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
4841 att_state
->pending_clear_aspects
= 0;
4844 att_state
->pending_load_aspects
= 0;
4847 cmd_buffer_emit_depth_stencil(cmd_buffer
);
4850 /* The PIPE_CONTROL command description says:
4852 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
4853 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
4854 * Target Cache Flush by enabling this bit. When render target flush
4855 * is set due to new association of BTI, PS Scoreboard Stall bit must
4856 * be set in this packet."
4858 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4859 pc
.RenderTargetCacheFlushEnable
= true;
4860 pc
.StallAtPixelScoreboard
= true;
4862 pc
.TileCacheFlushEnable
= true;
4868 static enum blorp_filter
4869 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
4872 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
4873 return BLORP_FILTER_SAMPLE_0
;
4874 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
4875 return BLORP_FILTER_AVERAGE
;
4876 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
4877 return BLORP_FILTER_MIN_SAMPLE
;
4878 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
4879 return BLORP_FILTER_MAX_SAMPLE
;
4881 return BLORP_FILTER_NONE
;
4886 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
4888 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4889 struct anv_subpass
*subpass
= cmd_state
->subpass
;
4890 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
4891 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4893 if (subpass
->has_color_resolve
) {
4894 /* We are about to do some MSAA resolves. We need to flush so that the
4895 * result of writes to the MSAA color attachments show up in the sampler
4896 * when we blit to the single-sampled resolve target.
4898 cmd_buffer
->state
.pending_pipe_bits
|=
4899 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4900 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
4902 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
4903 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
4904 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
4906 if (dst_att
== VK_ATTACHMENT_UNUSED
)
4909 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4910 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4912 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4913 /* From the Vulkan 1.0 spec:
4915 * If the first use of an attachment in a render pass is as a
4916 * resolve attachment, then the loadOp is effectively ignored
4917 * as the resolve is guaranteed to overwrite all pixels in the
4920 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4923 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
4924 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
4926 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4928 enum isl_aux_usage src_aux_usage
=
4929 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
4930 enum isl_aux_usage dst_aux_usage
=
4931 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
4933 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
4934 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
4936 anv_image_msaa_resolve(cmd_buffer
,
4937 src_iview
->image
, src_aux_usage
,
4938 src_iview
->planes
[0].isl
.base_level
,
4939 src_iview
->planes
[0].isl
.base_array_layer
,
4940 dst_iview
->image
, dst_aux_usage
,
4941 dst_iview
->planes
[0].isl
.base_level
,
4942 dst_iview
->planes
[0].isl
.base_array_layer
,
4943 VK_IMAGE_ASPECT_COLOR_BIT
,
4944 render_area
.offset
.x
, render_area
.offset
.y
,
4945 render_area
.offset
.x
, render_area
.offset
.y
,
4946 render_area
.extent
.width
,
4947 render_area
.extent
.height
,
4948 fb
->layers
, BLORP_FILTER_NONE
);
4952 if (subpass
->ds_resolve_attachment
) {
4953 /* We are about to do some MSAA resolves. We need to flush so that the
4954 * result of writes to the MSAA depth attachments show up in the sampler
4955 * when we blit to the single-sampled resolve target.
4957 cmd_buffer
->state
.pending_pipe_bits
|=
4958 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4959 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
4961 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
4962 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
4964 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4965 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4967 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4968 /* From the Vulkan 1.0 spec:
4970 * If the first use of an attachment in a render pass is as a
4971 * resolve attachment, then the loadOp is effectively ignored
4972 * as the resolve is guaranteed to overwrite all pixels in the
4975 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4978 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
4979 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
4981 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4983 struct anv_attachment_state
*src_state
=
4984 &cmd_state
->attachments
[src_att
];
4985 struct anv_attachment_state
*dst_state
=
4986 &cmd_state
->attachments
[dst_att
];
4988 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
4989 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4991 /* MSAA resolves sample from the source attachment. Transition the
4992 * depth attachment first to get rid of any HiZ that we may not be
4995 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
4996 src_state
->current_layout
,
4997 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4998 src_state
->aux_usage
=
4999 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
5000 VK_IMAGE_ASPECT_DEPTH_BIT
,
5001 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
5002 src_state
->current_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
5004 /* MSAA resolves write to the resolve attachment as if it were any
5005 * other transfer op. Transition the resolve attachment accordingly.
5007 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
5009 /* If our render area is the entire size of the image, we're going to
5010 * blow it all away so we can claim the initial layout is UNDEFINED
5011 * and we'll get a HiZ ambiguate instead of a resolve.
5013 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
5014 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
5015 render_area
.extent
.width
== dst_iview
->extent
.width
&&
5016 render_area
.extent
.height
== dst_iview
->extent
.height
)
5017 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
5019 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
5021 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
5022 dst_state
->aux_usage
=
5023 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
5024 VK_IMAGE_ASPECT_DEPTH_BIT
,
5025 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
5026 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
5028 enum blorp_filter filter
=
5029 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
5031 anv_image_msaa_resolve(cmd_buffer
,
5032 src_iview
->image
, src_state
->aux_usage
,
5033 src_iview
->planes
[0].isl
.base_level
,
5034 src_iview
->planes
[0].isl
.base_array_layer
,
5035 dst_iview
->image
, dst_state
->aux_usage
,
5036 dst_iview
->planes
[0].isl
.base_level
,
5037 dst_iview
->planes
[0].isl
.base_array_layer
,
5038 VK_IMAGE_ASPECT_DEPTH_BIT
,
5039 render_area
.offset
.x
, render_area
.offset
.y
,
5040 render_area
.offset
.x
, render_area
.offset
.y
,
5041 render_area
.extent
.width
,
5042 render_area
.extent
.height
,
5043 fb
->layers
, filter
);
5046 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
5047 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
5049 src_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
5050 dst_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
5052 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
5053 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
5055 enum blorp_filter filter
=
5056 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
5058 anv_image_msaa_resolve(cmd_buffer
,
5059 src_iview
->image
, src_aux_usage
,
5060 src_iview
->planes
[0].isl
.base_level
,
5061 src_iview
->planes
[0].isl
.base_array_layer
,
5062 dst_iview
->image
, dst_aux_usage
,
5063 dst_iview
->planes
[0].isl
.base_level
,
5064 dst_iview
->planes
[0].isl
.base_array_layer
,
5065 VK_IMAGE_ASPECT_STENCIL_BIT
,
5066 render_area
.offset
.x
, render_area
.offset
.y
,
5067 render_area
.offset
.x
, render_area
.offset
.y
,
5068 render_area
.extent
.width
,
5069 render_area
.extent
.height
,
5070 fb
->layers
, filter
);
5075 /* On gen7, we have to store a texturable version of the stencil buffer in
5076 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
5077 * forth at strategic points. Stencil writes are only allowed in following
5080 * - VK_IMAGE_LAYOUT_GENERAL
5081 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
5082 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
5083 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
5084 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
5086 * For general, we have no nice opportunity to transition so we do the copy
5087 * to the shadow unconditionally at the end of the subpass. For transfer
5088 * destinations, we can update it as part of the transfer op. For the other
5089 * layouts, we delay the copy until a transition into some other layout.
5091 if (subpass
->depth_stencil_attachment
) {
5092 uint32_t a
= subpass
->depth_stencil_attachment
->attachment
;
5093 assert(a
!= VK_ATTACHMENT_UNUSED
);
5095 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5096 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;;
5097 const struct anv_image
*image
= iview
->image
;
5099 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5100 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
5101 VK_IMAGE_ASPECT_STENCIL_BIT
);
5103 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
5104 att_state
->current_stencil_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
5105 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
5106 anv_image_copy_to_shadow(cmd_buffer
, image
,
5107 VK_IMAGE_ASPECT_STENCIL_BIT
,
5108 iview
->planes
[plane
].isl
.base_level
, 1,
5109 iview
->planes
[plane
].isl
.base_array_layer
,
5114 #endif /* GEN_GEN == 7 */
5116 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5117 const uint32_t a
= subpass
->attachments
[i
].attachment
;
5118 if (a
== VK_ATTACHMENT_UNUSED
)
5121 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
5124 assert(a
< cmd_state
->pass
->attachment_count
);
5125 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5126 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
5127 const struct anv_image
*image
= iview
->image
;
5129 if ((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
5130 image
->vk_format
!= iview
->vk_format
) {
5131 enum anv_fast_clear_type fast_clear_type
=
5132 anv_layout_to_fast_clear_type(&cmd_buffer
->device
->info
,
5133 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5134 att_state
->current_layout
);
5136 /* If any clear color was used, flush it down the aux surfaces. If we
5137 * don't do it now using the view's format we might use the clear
5138 * color incorrectly in the following resolves (for example with an
5139 * SRGB view & a UNORM image).
5141 if (fast_clear_type
!= ANV_FAST_CLEAR_NONE
) {
5142 anv_perf_warn(cmd_buffer
->device
->instance
, iview
,
5143 "Doing a partial resolve to get rid of clear color at the "
5144 "end of a renderpass due to an image/view format mismatch");
5146 uint32_t base_layer
, layer_count
;
5147 if (image
->type
== VK_IMAGE_TYPE_3D
) {
5149 layer_count
= anv_minify(iview
->image
->extent
.depth
,
5150 iview
->planes
[0].isl
.base_level
);
5152 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
5153 layer_count
= fb
->layers
;
5156 for (uint32_t a
= 0; a
< layer_count
; a
++) {
5157 uint32_t array_layer
= base_layer
+ a
;
5158 if (image
->samples
== 1) {
5159 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
5160 iview
->planes
[0].isl
.format
,
5161 VK_IMAGE_ASPECT_COLOR_BIT
,
5162 iview
->planes
[0].isl
.base_level
,
5164 ISL_AUX_OP_PARTIAL_RESOLVE
,
5165 ANV_FAST_CLEAR_NONE
);
5167 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
5168 iview
->planes
[0].isl
.format
,
5169 VK_IMAGE_ASPECT_COLOR_BIT
,
5171 ISL_AUX_OP_PARTIAL_RESOLVE
,
5172 ANV_FAST_CLEAR_NONE
);
5178 /* Transition the image into the final layout for this render pass */
5179 VkImageLayout target_layout
=
5180 cmd_state
->pass
->attachments
[a
].final_layout
;
5181 VkImageLayout target_stencil_layout
=
5182 cmd_state
->pass
->attachments
[a
].stencil_final_layout
;
5184 uint32_t base_layer
, layer_count
;
5185 if (image
->type
== VK_IMAGE_TYPE_3D
) {
5187 layer_count
= anv_minify(iview
->image
->extent
.depth
,
5188 iview
->planes
[0].isl
.base_level
);
5190 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
5191 layer_count
= fb
->layers
;
5194 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
5195 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5196 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5197 iview
->planes
[0].isl
.base_level
, 1,
5198 base_layer
, layer_count
,
5199 att_state
->current_layout
, target_layout
);
5202 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5203 transition_depth_buffer(cmd_buffer
, image
,
5204 att_state
->current_layout
, target_layout
);
5207 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5208 transition_stencil_buffer(cmd_buffer
, image
,
5209 iview
->planes
[0].isl
.base_level
, 1,
5210 base_layer
, layer_count
,
5211 att_state
->current_stencil_layout
,
5212 target_stencil_layout
);
5216 /* Accumulate any subpass flushes that need to happen after the subpass.
5217 * Yes, they do get accumulated twice in the NextSubpass case but since
5218 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
5219 * ORing the bits in twice so it's harmless.
5221 cmd_buffer
->state
.pending_pipe_bits
|=
5222 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
5225 void genX(CmdBeginRenderPass
)(
5226 VkCommandBuffer commandBuffer
,
5227 const VkRenderPassBeginInfo
* pRenderPassBegin
,
5228 VkSubpassContents contents
)
5230 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5231 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
5232 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
5234 cmd_buffer
->state
.framebuffer
= framebuffer
;
5235 cmd_buffer
->state
.pass
= pass
;
5236 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
5238 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
5240 /* If we failed to setup the attachments we should not try to go further */
5241 if (result
!= VK_SUCCESS
) {
5242 assert(anv_batch_has_error(&cmd_buffer
->batch
));
5246 genX(flush_pipeline_select_3d
)(cmd_buffer
);
5248 cmd_buffer_begin_subpass(cmd_buffer
, 0);
5251 void genX(CmdBeginRenderPass2KHR
)(
5252 VkCommandBuffer commandBuffer
,
5253 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
5254 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
5256 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
5257 pSubpassBeginInfo
->contents
);
5260 void genX(CmdNextSubpass
)(
5261 VkCommandBuffer commandBuffer
,
5262 VkSubpassContents contents
)
5264 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5266 if (anv_batch_has_error(&cmd_buffer
->batch
))
5269 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
5271 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
5272 cmd_buffer_end_subpass(cmd_buffer
);
5273 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
5276 void genX(CmdNextSubpass2KHR
)(
5277 VkCommandBuffer commandBuffer
,
5278 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
5279 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5281 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
5284 void genX(CmdEndRenderPass
)(
5285 VkCommandBuffer commandBuffer
)
5287 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5289 if (anv_batch_has_error(&cmd_buffer
->batch
))
5292 cmd_buffer_end_subpass(cmd_buffer
);
5294 cmd_buffer
->state
.hiz_enabled
= false;
5297 anv_dump_add_attachments(cmd_buffer
);
5300 /* Remove references to render pass specific state. This enables us to
5301 * detect whether or not we're in a renderpass.
5303 cmd_buffer
->state
.framebuffer
= NULL
;
5304 cmd_buffer
->state
.pass
= NULL
;
5305 cmd_buffer
->state
.subpass
= NULL
;
5308 void genX(CmdEndRenderPass2KHR
)(
5309 VkCommandBuffer commandBuffer
,
5310 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5312 genX(CmdEndRenderPass
)(commandBuffer
);
5316 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
5318 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5319 struct gen_mi_builder b
;
5320 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5322 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
5323 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
5324 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
5326 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
5327 mip
.LoadOperation
= LOAD_LOADINV
;
5328 mip
.CombineOperation
= COMBINE_SET
;
5329 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
5334 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5335 void genX(CmdBeginConditionalRenderingEXT
)(
5336 VkCommandBuffer commandBuffer
,
5337 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5339 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5340 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5341 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5342 struct anv_address value_address
=
5343 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
5345 const bool isInverted
= pConditionalRenderingBegin
->flags
&
5346 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
5348 cmd_state
->conditional_render_enabled
= true;
5350 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5352 struct gen_mi_builder b
;
5353 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5355 /* Section 19.4 of the Vulkan 1.1.85 spec says:
5357 * If the value of the predicate in buffer memory changes
5358 * while conditional rendering is active, the rendering commands
5359 * may be discarded in an implementation-dependent way.
5360 * Some implementations may latch the value of the predicate
5361 * upon beginning conditional rendering while others
5362 * may read it before every rendering command.
5364 * So it's perfectly fine to read a value from the buffer once.
5366 struct gen_mi_value value
= gen_mi_mem32(value_address
);
5368 /* Precompute predicate result, it is necessary to support secondary
5369 * command buffers since it is unknown if conditional rendering is
5370 * inverted when populating them.
5372 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
5373 isInverted
? gen_mi_uge(&b
, gen_mi_imm(0), value
) :
5374 gen_mi_ult(&b
, gen_mi_imm(0), value
));
5377 void genX(CmdEndConditionalRenderingEXT
)(
5378 VkCommandBuffer commandBuffer
)
5380 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5381 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5383 cmd_state
->conditional_render_enabled
= false;
5387 /* Set of stage bits for which are pipelined, i.e. they get queued by the
5388 * command streamer for later execution.
5390 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
5391 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
5392 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
5393 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
5394 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
5395 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
5396 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
5397 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
5398 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
5399 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
5400 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
5401 VK_PIPELINE_STAGE_TRANSFER_BIT | \
5402 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
5403 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
5404 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
5406 void genX(CmdSetEvent
)(
5407 VkCommandBuffer commandBuffer
,
5409 VkPipelineStageFlags stageMask
)
5411 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5412 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5414 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5415 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5416 pc
.StallAtPixelScoreboard
= true;
5417 pc
.CommandStreamerStallEnable
= true;
5420 pc
.DestinationAddressType
= DAT_PPGTT
,
5421 pc
.PostSyncOperation
= WriteImmediateData
,
5422 pc
.Address
= (struct anv_address
) {
5423 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5426 pc
.ImmediateData
= VK_EVENT_SET
;
5430 void genX(CmdResetEvent
)(
5431 VkCommandBuffer commandBuffer
,
5433 VkPipelineStageFlags stageMask
)
5435 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5436 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5438 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5439 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5440 pc
.StallAtPixelScoreboard
= true;
5441 pc
.CommandStreamerStallEnable
= true;
5444 pc
.DestinationAddressType
= DAT_PPGTT
;
5445 pc
.PostSyncOperation
= WriteImmediateData
;
5446 pc
.Address
= (struct anv_address
) {
5447 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5450 pc
.ImmediateData
= VK_EVENT_RESET
;
5454 void genX(CmdWaitEvents
)(
5455 VkCommandBuffer commandBuffer
,
5456 uint32_t eventCount
,
5457 const VkEvent
* pEvents
,
5458 VkPipelineStageFlags srcStageMask
,
5459 VkPipelineStageFlags destStageMask
,
5460 uint32_t memoryBarrierCount
,
5461 const VkMemoryBarrier
* pMemoryBarriers
,
5462 uint32_t bufferMemoryBarrierCount
,
5463 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5464 uint32_t imageMemoryBarrierCount
,
5465 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5468 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5470 for (uint32_t i
= 0; i
< eventCount
; i
++) {
5471 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
5473 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
5474 sem
.WaitMode
= PollingMode
,
5475 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
5476 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
5477 sem
.SemaphoreAddress
= (struct anv_address
) {
5478 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5484 anv_finishme("Implement events on gen7");
5487 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
5488 false, /* byRegion */
5489 memoryBarrierCount
, pMemoryBarriers
,
5490 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5491 imageMemoryBarrierCount
, pImageMemoryBarriers
);
5494 VkResult
genX(CmdSetPerformanceOverrideINTEL
)(
5495 VkCommandBuffer commandBuffer
,
5496 const VkPerformanceOverrideInfoINTEL
* pOverrideInfo
)
5498 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5500 switch (pOverrideInfo
->type
) {
5501 case VK_PERFORMANCE_OVERRIDE_TYPE_NULL_HARDWARE_INTEL
: {
5505 anv_pack_struct(&dw
, GENX(CS_DEBUG_MODE2
),
5506 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
5507 .MediaInstructionDisable
= pOverrideInfo
->enable
,
5508 ._3DRenderingInstructionDisableMask
= true,
5509 .MediaInstructionDisableMask
= true);
5510 emit_lri(&cmd_buffer
->batch
, GENX(CS_DEBUG_MODE2_num
), dw
);
5512 anv_pack_struct(&dw
, GENX(INSTPM
),
5513 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
5514 .MediaInstructionDisable
= pOverrideInfo
->enable
,
5515 ._3DRenderingInstructionDisableMask
= true,
5516 .MediaInstructionDisableMask
= true);
5517 emit_lri(&cmd_buffer
->batch
, GENX(INSTPM_num
), dw
);
5522 case VK_PERFORMANCE_OVERRIDE_TYPE_FLUSH_GPU_CACHES_INTEL
:
5523 if (pOverrideInfo
->enable
) {
5524 /* FLUSH ALL THE THINGS! As requested by the MDAPI team. */
5525 cmd_buffer
->state
.pending_pipe_bits
|=
5526 ANV_PIPE_FLUSH_BITS
|
5527 ANV_PIPE_INVALIDATE_BITS
;
5528 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5533 unreachable("Invalid override");
5539 VkResult
genX(CmdSetPerformanceStreamMarkerINTEL
)(
5540 VkCommandBuffer commandBuffer
,
5541 const VkPerformanceStreamMarkerInfoINTEL
* pMarkerInfo
)
5543 /* TODO: Waiting on the register to write, might depend on generation. */