2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_l3_config.h"
33 #include "genxml/gen_macros.h"
34 #include "genxml/genX_pack.h"
36 /* We reserve GPR 14 and 15 for conditional rendering */
37 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
38 #define __gen_get_batch_dwords anv_batch_emit_dwords
39 #define __gen_address_offset anv_address_add
40 #include "common/gen_mi_builder.h"
43 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
45 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
46 lri
.RegisterOffset
= reg
;
52 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
54 struct anv_device
*device
= cmd_buffer
->device
;
56 /* If we are emitting a new state base address we probably need to re-emit
59 cmd_buffer
->state
.descriptors_dirty
|= ~0;
61 /* Emit a render target cache flush.
63 * This isn't documented anywhere in the PRM. However, it seems to be
64 * necessary prior to changing the surface state base adress. Without
65 * this, we get GPU hangs when using multi-level command buffers which
66 * clear depth, reset state base address, and then go render stuff.
68 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
69 pc
.DCFlushEnable
= true;
70 pc
.RenderTargetCacheFlushEnable
= true;
71 pc
.CommandStreamerStallEnable
= true;
74 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
75 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
76 sba
.GeneralStateMOCS
= GENX(MOCS
);
77 sba
.GeneralStateBaseAddressModifyEnable
= true;
79 sba
.SurfaceStateBaseAddress
=
80 anv_cmd_buffer_surface_base_address(cmd_buffer
);
81 sba
.SurfaceStateMOCS
= GENX(MOCS
);
82 sba
.SurfaceStateBaseAddressModifyEnable
= true;
84 sba
.DynamicStateBaseAddress
=
85 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
86 sba
.DynamicStateMOCS
= GENX(MOCS
);
87 sba
.DynamicStateBaseAddressModifyEnable
= true;
89 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
90 sba
.IndirectObjectMOCS
= GENX(MOCS
);
91 sba
.IndirectObjectBaseAddressModifyEnable
= true;
93 sba
.InstructionBaseAddress
=
94 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
95 sba
.InstructionMOCS
= GENX(MOCS
);
96 sba
.InstructionBaseAddressModifyEnable
= true;
99 /* Broadwell requires that we specify a buffer size for a bunch of
100 * these fields. However, since we will be growing the BO's live, we
101 * just set them all to the maximum.
103 sba
.GeneralStateBufferSize
= 0xfffff;
104 sba
.GeneralStateBufferSizeModifyEnable
= true;
105 sba
.DynamicStateBufferSize
= 0xfffff;
106 sba
.DynamicStateBufferSizeModifyEnable
= true;
107 sba
.IndirectObjectBufferSize
= 0xfffff;
108 sba
.IndirectObjectBufferSizeModifyEnable
= true;
109 sba
.InstructionBufferSize
= 0xfffff;
110 sba
.InstructionBuffersizeModifyEnable
= true;
113 if (cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
) {
114 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) {
115 .bo
= device
->surface_state_pool
.block_pool
.bo
,
118 sba
.BindlessSurfaceStateSize
= (1 << 20) - 1;
120 sba
.BindlessSurfaceStateBaseAddress
= ANV_NULL_ADDRESS
;
121 sba
.BindlessSurfaceStateSize
= 0;
123 sba
.BindlessSurfaceStateMOCS
= GENX(MOCS
);
124 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
127 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
128 sba
.BindlessSamplerStateMOCS
= GENX(MOCS
);
129 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
130 sba
.BindlessSamplerStateBufferSize
= 0;
134 /* After re-setting the surface state base address, we have to do some
135 * cache flusing so that the sampler engine will pick up the new
136 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
137 * Shared Function > 3D Sampler > State > State Caching (page 96):
139 * Coherency with system memory in the state cache, like the texture
140 * cache is handled partially by software. It is expected that the
141 * command stream or shader will issue Cache Flush operation or
142 * Cache_Flush sampler message to ensure that the L1 cache remains
143 * coherent with system memory.
147 * Whenever the value of the Dynamic_State_Base_Addr,
148 * Surface_State_Base_Addr are altered, the L1 state cache must be
149 * invalidated to ensure the new surface or sampler state is fetched
150 * from system memory.
152 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
153 * which, according the PIPE_CONTROL instruction documentation in the
156 * Setting this bit is independent of any other bit in this packet.
157 * This bit controls the invalidation of the L1 and L2 state caches
158 * at the top of the pipe i.e. at the parsing time.
160 * Unfortunately, experimentation seems to indicate that state cache
161 * invalidation through a PIPE_CONTROL does nothing whatsoever in
162 * regards to surface state and binding tables. In stead, it seems that
163 * invalidating the texture cache is what is actually needed.
165 * XXX: As far as we have been able to determine through
166 * experimentation, shows that flush the texture cache appears to be
167 * sufficient. The theory here is that all of the sampling/rendering
168 * units cache the binding table in the texture cache. However, we have
169 * yet to be able to actually confirm this.
171 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
172 pc
.TextureCacheInvalidationEnable
= true;
173 pc
.ConstantCacheInvalidationEnable
= true;
174 pc
.StateCacheInvalidationEnable
= true;
179 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
180 struct anv_state state
, struct anv_address addr
)
182 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
185 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
186 state
.offset
+ isl_dev
->ss
.addr_offset
,
187 addr
.bo
, addr
.offset
);
188 if (result
!= VK_SUCCESS
)
189 anv_batch_set_error(&cmd_buffer
->batch
, result
);
193 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
194 struct anv_surface_state state
)
196 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
198 assert(!anv_address_is_null(state
.address
));
199 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
201 if (!anv_address_is_null(state
.aux_address
)) {
203 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
204 &cmd_buffer
->pool
->alloc
,
205 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
206 state
.aux_address
.bo
, state
.aux_address
.offset
);
207 if (result
!= VK_SUCCESS
)
208 anv_batch_set_error(&cmd_buffer
->batch
, result
);
211 if (!anv_address_is_null(state
.clear_address
)) {
213 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
214 &cmd_buffer
->pool
->alloc
,
216 isl_dev
->ss
.clear_color_state_offset
,
217 state
.clear_address
.bo
, state
.clear_address
.offset
);
218 if (result
!= VK_SUCCESS
)
219 anv_batch_set_error(&cmd_buffer
->batch
, result
);
224 color_attachment_compute_aux_usage(struct anv_device
* device
,
225 struct anv_cmd_state
* cmd_state
,
226 uint32_t att
, VkRect2D render_area
,
227 union isl_color_value
*fast_clear_color
)
229 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
230 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
232 assert(iview
->n_planes
== 1);
234 if (iview
->planes
[0].isl
.base_array_layer
>=
235 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
236 iview
->planes
[0].isl
.base_level
)) {
237 /* There is no aux buffer which corresponds to the level and layer(s)
240 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
241 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
242 att_state
->fast_clear
= false;
246 att_state
->aux_usage
=
247 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
248 VK_IMAGE_ASPECT_COLOR_BIT
,
249 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
251 /* If we don't have aux, then we should have returned early in the layer
252 * check above. If we got here, we must have something.
254 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
256 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
257 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
258 att_state
->input_aux_usage
= att_state
->aux_usage
;
260 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
262 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
263 * setting is only allowed if Surface Format supported for Fast
264 * Clear. In addition, if the surface is bound to the sampling
265 * engine, Surface Format must be supported for Render Target
266 * Compression for surfaces bound to the sampling engine."
268 * In other words, we can only sample from a fast-cleared image if it
269 * also supports color compression.
271 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
272 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
274 /* While fast-clear resolves and partial resolves are fairly cheap in the
275 * case where you render to most of the pixels, full resolves are not
276 * because they potentially involve reading and writing the entire
277 * framebuffer. If we can't texture with CCS_E, we should leave it off and
278 * limit ourselves to fast clears.
280 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
281 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
282 anv_perf_warn(device
->instance
, iview
->image
,
283 "Not temporarily enabling CCS_E.");
286 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
290 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
291 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
293 union isl_color_value clear_color
= {};
294 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
296 att_state
->clear_color_is_zero_one
=
297 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
298 att_state
->clear_color_is_zero
=
299 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
301 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
302 /* Start by getting the fast clear type. We use the first subpass
303 * layout here because we don't want to fast-clear if the first subpass
304 * to use the attachment can't handle fast-clears.
306 enum anv_fast_clear_type fast_clear_type
=
307 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
308 VK_IMAGE_ASPECT_COLOR_BIT
,
309 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
310 switch (fast_clear_type
) {
311 case ANV_FAST_CLEAR_NONE
:
312 att_state
->fast_clear
= false;
314 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
315 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
317 case ANV_FAST_CLEAR_ANY
:
318 att_state
->fast_clear
= true;
322 /* Potentially, we could do partial fast-clears but doing so has crazy
323 * alignment restrictions. It's easier to just restrict to full size
324 * fast clears for now.
326 if (render_area
.offset
.x
!= 0 ||
327 render_area
.offset
.y
!= 0 ||
328 render_area
.extent
.width
!= iview
->extent
.width
||
329 render_area
.extent
.height
!= iview
->extent
.height
)
330 att_state
->fast_clear
= false;
332 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
333 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
334 att_state
->fast_clear
= false;
336 /* We only allow fast clears to the first slice of an image (level 0,
337 * layer 0) and only for the entire slice. This guarantees us that, at
338 * any given time, there is only one clear color on any given image at
339 * any given time. At the time of our testing (Jan 17, 2018), there
340 * were no known applications which would benefit from fast-clearing
341 * more than just the first slice.
343 if (att_state
->fast_clear
&&
344 (iview
->planes
[0].isl
.base_level
> 0 ||
345 iview
->planes
[0].isl
.base_array_layer
> 0)) {
346 anv_perf_warn(device
->instance
, iview
->image
,
347 "Rendering with multi-lod or multi-layer framebuffer "
348 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
349 "baseArrayLayer > 0. Not fast clearing.");
350 att_state
->fast_clear
= false;
351 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
352 anv_perf_warn(device
->instance
, iview
->image
,
353 "Rendering to a multi-layer framebuffer with "
354 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
357 if (att_state
->fast_clear
)
358 *fast_clear_color
= clear_color
;
360 att_state
->fast_clear
= false;
365 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
366 struct anv_cmd_state
*cmd_state
,
367 uint32_t att
, VkRect2D render_area
)
369 struct anv_render_pass_attachment
*pass_att
=
370 &cmd_state
->pass
->attachments
[att
];
371 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
372 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
374 /* These will be initialized after the first subpass transition. */
375 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
376 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
379 /* We don't do any HiZ or depth fast-clears on gen7 yet */
380 att_state
->fast_clear
= false;
384 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
385 /* If we're just clearing stencil, we can always HiZ clear */
386 att_state
->fast_clear
= true;
390 /* Default to false for now */
391 att_state
->fast_clear
= false;
393 /* We must have depth in order to have HiZ */
394 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
397 const enum isl_aux_usage first_subpass_aux_usage
=
398 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
399 VK_IMAGE_ASPECT_DEPTH_BIT
,
400 pass_att
->first_subpass_layout
);
401 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
404 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
405 iview
->planes
[0].isl
.format
,
406 iview
->image
->samples
,
407 render_area
.offset
.x
,
408 render_area
.offset
.y
,
409 render_area
.offset
.x
+
410 render_area
.extent
.width
,
411 render_area
.offset
.y
+
412 render_area
.extent
.height
))
415 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
418 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
419 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
420 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
421 * only supports returning 0.0f. Gens prior to gen8 do not support this
427 /* If we got here, then we can fast clear */
428 att_state
->fast_clear
= true;
432 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
434 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
437 /* We only allocate input attachment states for color surfaces. Compression
438 * is not yet enabled for depth textures and stencil doesn't allow
439 * compression so we can just use the texture surface state from the view.
441 return vk_format_is_color(att
->format
);
444 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
445 * the initial layout is undefined, the HiZ buffer and depth buffer will
446 * represent the same data at the end of this operation.
449 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
450 const struct anv_image
*image
,
451 VkImageLayout initial_layout
,
452 VkImageLayout final_layout
)
454 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
455 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
456 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
457 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
458 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
459 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
461 enum isl_aux_op hiz_op
;
462 if (hiz_enabled
&& !enable_hiz
) {
463 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
464 } else if (!hiz_enabled
&& enable_hiz
) {
465 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
467 assert(hiz_enabled
== enable_hiz
);
468 /* If the same buffer will be used, no resolves are necessary. */
469 hiz_op
= ISL_AUX_OP_NONE
;
472 if (hiz_op
!= ISL_AUX_OP_NONE
)
473 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
477 #define MI_PREDICATE_SRC0 0x2400
478 #define MI_PREDICATE_SRC1 0x2408
479 #define MI_PREDICATE_RESULT 0x2418
482 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
483 const struct anv_image
*image
,
484 VkImageAspectFlagBits aspect
,
486 uint32_t base_layer
, uint32_t layer_count
,
489 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
491 /* We only have compression tracking for CCS_E */
492 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
495 for (uint32_t a
= 0; a
< layer_count
; a
++) {
496 uint32_t layer
= base_layer
+ a
;
497 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
498 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
501 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
507 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
508 const struct anv_image
*image
,
509 VkImageAspectFlagBits aspect
,
510 enum anv_fast_clear_type fast_clear
)
512 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
513 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
515 sdi
.ImmediateData
= fast_clear
;
518 /* Whenever we have fast-clear, we consider that slice to be compressed.
519 * This makes building predicates much easier.
521 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
522 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
525 #if GEN_IS_HASWELL || GEN_GEN >= 8
526 static inline uint32_t
527 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
529 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
531 .Operand1
= operand1
,
532 .Operand2
= operand2
,
536 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
542 /* This is only really practical on haswell and above because it requires
543 * MI math in order to get it correct.
545 #if GEN_GEN >= 8 || GEN_IS_HASWELL
547 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
548 const struct anv_image
*image
,
549 VkImageAspectFlagBits aspect
,
550 uint32_t level
, uint32_t array_layer
,
551 enum isl_aux_op resolve_op
,
552 enum anv_fast_clear_type fast_clear_supported
)
554 struct gen_mi_builder b
;
555 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
557 const struct gen_mi_value fast_clear_type
=
558 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
561 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
562 /* In this case, we're doing a full resolve which means we want the
563 * resolve to happen if any compression (including fast-clears) is
566 * In order to simplify the logic a bit, we make the assumption that,
567 * if the first slice has been fast-cleared, it is also marked as
568 * compressed. See also set_image_fast_clear_state.
570 const struct gen_mi_value compression_state
=
571 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer
->device
,
573 level
, array_layer
));
574 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
576 gen_mi_store(&b
, compression_state
, gen_mi_imm(0));
578 if (level
== 0 && array_layer
== 0) {
579 /* If the predicate is true, we want to write 0 to the fast clear type
580 * and, if it's false, leave it alone. We can do this by writing
582 * clear_type = clear_type & ~predicate;
584 struct gen_mi_value new_fast_clear_type
=
585 gen_mi_iand(&b
, fast_clear_type
,
586 gen_mi_inot(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
)));
587 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
589 } else if (level
== 0 && array_layer
== 0) {
590 /* In this case, we are doing a partial resolve to get rid of fast-clear
591 * colors. We don't care about the compression state but we do care
592 * about how much fast clear is allowed by the final layout.
594 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
595 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
597 /* We need to compute (fast_clear_supported < image->fast_clear) */
598 struct gen_mi_value pred
=
599 gen_mi_ult(&b
, gen_mi_imm(fast_clear_supported
), fast_clear_type
);
600 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
601 gen_mi_value_ref(&b
, pred
));
603 /* If the predicate is true, we want to write 0 to the fast clear type
604 * and, if it's false, leave it alone. We can do this by writing
606 * clear_type = clear_type & ~predicate;
608 struct gen_mi_value new_fast_clear_type
=
609 gen_mi_iand(&b
, fast_clear_type
, gen_mi_inot(&b
, pred
));
610 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
612 /* In this case, we're trying to do a partial resolve on a slice that
613 * doesn't have clear color. There's nothing to do.
615 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
619 /* Set src1 to 0 and use a != condition */
620 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
622 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
623 mip
.LoadOperation
= LOAD_LOADINV
;
624 mip
.CombineOperation
= COMBINE_SET
;
625 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
628 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
632 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
633 const struct anv_image
*image
,
634 VkImageAspectFlagBits aspect
,
635 uint32_t level
, uint32_t array_layer
,
636 enum isl_aux_op resolve_op
,
637 enum anv_fast_clear_type fast_clear_supported
)
639 struct gen_mi_builder b
;
640 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
642 struct gen_mi_value fast_clear_type_mem
=
643 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
646 /* This only works for partial resolves and only when the clear color is
647 * all or nothing. On the upside, this emits less command streamer code
648 * and works on Ivybridge and Bay Trail.
650 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
651 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
653 /* We don't support fast clears on anything other than the first slice. */
654 if (level
> 0 || array_layer
> 0)
657 /* On gen8, we don't have a concept of default clear colors because we
658 * can't sample from CCS surfaces. It's enough to just load the fast clear
659 * state into the predicate register.
661 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), fast_clear_type_mem
);
662 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
663 gen_mi_store(&b
, fast_clear_type_mem
, gen_mi_imm(0));
665 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
666 mip
.LoadOperation
= LOAD_LOADINV
;
667 mip
.CombineOperation
= COMBINE_SET
;
668 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
671 #endif /* GEN_GEN <= 8 */
674 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
675 const struct anv_image
*image
,
676 enum isl_format format
,
677 VkImageAspectFlagBits aspect
,
678 uint32_t level
, uint32_t array_layer
,
679 enum isl_aux_op resolve_op
,
680 enum anv_fast_clear_type fast_clear_supported
)
682 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
685 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
686 aspect
, level
, array_layer
,
687 resolve_op
, fast_clear_supported
);
688 #else /* GEN_GEN <= 8 */
689 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
690 aspect
, level
, array_layer
,
691 resolve_op
, fast_clear_supported
);
694 /* CCS_D only supports full resolves and BLORP will assert on us if we try
695 * to do a partial resolve on a CCS_D surface.
697 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
698 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
699 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
701 anv_image_ccs_op(cmd_buffer
, image
, format
, aspect
, level
,
702 array_layer
, 1, resolve_op
, NULL
, true);
706 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
707 const struct anv_image
*image
,
708 enum isl_format format
,
709 VkImageAspectFlagBits aspect
,
710 uint32_t array_layer
,
711 enum isl_aux_op resolve_op
,
712 enum anv_fast_clear_type fast_clear_supported
)
714 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
715 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
717 #if GEN_GEN >= 8 || GEN_IS_HASWELL
718 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
719 aspect
, 0, array_layer
,
720 resolve_op
, fast_clear_supported
);
722 anv_image_mcs_op(cmd_buffer
, image
, format
, aspect
,
723 array_layer
, 1, resolve_op
, NULL
, true);
725 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
730 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
731 const struct anv_image
*image
,
732 VkImageAspectFlagBits aspect
,
733 enum isl_aux_usage aux_usage
,
736 uint32_t layer_count
)
738 /* The aspect must be exactly one of the image aspects. */
739 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
741 /* The only compression types with more than just fast-clears are MCS,
742 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
743 * track the current fast-clear and compression state. This leaves us
744 * with just MCS and CCS_E.
746 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
747 aux_usage
!= ISL_AUX_USAGE_MCS
)
750 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
751 level
, base_layer
, layer_count
, true);
755 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
756 const struct anv_image
*image
,
757 VkImageAspectFlagBits aspect
)
759 assert(cmd_buffer
&& image
);
760 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
762 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
763 ANV_FAST_CLEAR_NONE
);
765 /* Initialize the struct fields that are accessed for fast-clears so that
766 * the HW restrictions on the field values are satisfied.
768 struct anv_address addr
=
769 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
772 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
773 const unsigned num_dwords
= GEN_GEN
>= 10 ?
774 isl_dev
->ss
.clear_color_state_size
/ 4 :
775 isl_dev
->ss
.clear_value_size
/ 4;
776 for (unsigned i
= 0; i
< num_dwords
; i
++) {
777 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
779 sdi
.Address
.offset
+= i
* 4;
780 sdi
.ImmediateData
= 0;
784 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
786 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
787 /* Pre-SKL, the dword containing the clear values also contains
788 * other fields, so we need to initialize those fields to match the
789 * values that would be in a color attachment.
791 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
792 ISL_CHANNEL_SELECT_GREEN
<< 22 |
793 ISL_CHANNEL_SELECT_BLUE
<< 19 |
794 ISL_CHANNEL_SELECT_ALPHA
<< 16;
795 } else if (GEN_GEN
== 7) {
796 /* On IVB, the dword containing the clear values also contains
797 * other fields that must be zero or can be zero.
799 sdi
.ImmediateData
= 0;
805 /* Copy the fast-clear value dword(s) between a surface state object and an
806 * image's fast clear state buffer.
809 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
810 struct anv_state surface_state
,
811 const struct anv_image
*image
,
812 VkImageAspectFlagBits aspect
,
813 bool copy_from_surface_state
)
815 assert(cmd_buffer
&& image
);
816 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
818 struct anv_address ss_clear_addr
= {
819 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
820 .offset
= surface_state
.offset
+
821 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
823 const struct anv_address entry_addr
=
824 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
825 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
828 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
829 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
830 * in-flight when they are issued even if the memory touched is not
831 * currently active for rendering. The weird bit is that it is not the
832 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
833 * rendering hangs such that the next stalling command after the
834 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
836 * It is unclear exactly why this hang occurs. Both MI commands come with
837 * warnings about the 3D pipeline but that doesn't seem to fully explain
838 * it. My (Jason's) best theory is that it has something to do with the
839 * fact that we're using a GPU state register as our temporary and that
840 * something with reading/writing it is causing problems.
842 * In order to work around this issue, we emit a PIPE_CONTROL with the
843 * command streamer stall bit set.
845 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
846 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
849 struct gen_mi_builder b
;
850 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
852 if (copy_from_surface_state
) {
853 gen_mi_memcpy(&b
, entry_addr
, ss_clear_addr
, copy_size
);
855 gen_mi_memcpy(&b
, ss_clear_addr
, entry_addr
, copy_size
);
857 /* Updating a surface state object may require that the state cache be
858 * invalidated. From the SKL PRM, Shared Functions -> State -> State
861 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
862 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
863 * modified [...], the L1 state cache must be invalidated to ensure
864 * the new surface or sampler state is fetched from system memory.
866 * In testing, SKL doesn't actually seem to need this, but HSW does.
868 cmd_buffer
->state
.pending_pipe_bits
|=
869 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
874 * @brief Transitions a color buffer from one layout to another.
876 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
879 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
880 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
881 * this represents the maximum layers to transition at each
882 * specified miplevel.
885 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
886 const struct anv_image
*image
,
887 VkImageAspectFlagBits aspect
,
888 const uint32_t base_level
, uint32_t level_count
,
889 uint32_t base_layer
, uint32_t layer_count
,
890 VkImageLayout initial_layout
,
891 VkImageLayout final_layout
)
893 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
894 /* Validate the inputs. */
896 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
897 /* These values aren't supported for simplicity's sake. */
898 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
899 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
900 /* Ensure the subresource range is valid. */
901 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
902 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
903 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
904 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
905 assert(last_level_num
<= image
->levels
);
906 /* The spec disallows these final layouts. */
907 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
908 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
910 /* No work is necessary if the layout stays the same or if this subresource
911 * range lacks auxiliary data.
913 if (initial_layout
== final_layout
)
916 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
918 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
919 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
920 /* This surface is a linear compressed image with a tiled shadow surface
921 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
922 * we need to ensure the shadow copy is up-to-date.
924 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
925 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
926 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
927 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
929 anv_image_copy_to_shadow(cmd_buffer
, image
,
930 base_level
, level_count
,
931 base_layer
, layer_count
);
934 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
937 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
939 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
940 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
941 /* A subresource in the undefined layout may have been aliased and
942 * populated with any arrangement of bits. Therefore, we must initialize
943 * the related aux buffer and clear buffer entry with desirable values.
944 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
945 * images with VK_IMAGE_TILING_OPTIMAL.
947 * Initialize the relevant clear buffer entries.
949 if (base_level
== 0 && base_layer
== 0)
950 init_fast_clear_color(cmd_buffer
, image
, aspect
);
952 /* Initialize the aux buffers to enable correct rendering. In order to
953 * ensure that things such as storage images work correctly, aux buffers
954 * need to be initialized to valid data.
956 * Having an aux buffer with invalid data is a problem for two reasons:
958 * 1) Having an invalid value in the buffer can confuse the hardware.
959 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
960 * invalid and leads to the hardware doing strange things. It
961 * doesn't hang as far as we can tell but rendering corruption can
964 * 2) If this transition is into the GENERAL layout and we then use the
965 * image as a storage image, then we must have the aux buffer in the
966 * pass-through state so that, if we then go to texture from the
967 * image, we get the results of our storage image writes and not the
968 * fast clear color or other random data.
970 * For CCS both of the problems above are real demonstrable issues. In
971 * that case, the only thing we can do is to perform an ambiguate to
972 * transition the aux surface into the pass-through state.
974 * For MCS, (2) is never an issue because we don't support multisampled
975 * storage images. In theory, issue (1) is a problem with MCS but we've
976 * never seen it in the wild. For 4x and 16x, all bit patters could, in
977 * theory, be interpreted as something but we don't know that all bit
978 * patterns are actually valid. For 2x and 8x, you could easily end up
979 * with the MCS referring to an invalid plane because not all bits of
980 * the MCS value are actually used. Even though we've never seen issues
981 * in the wild, it's best to play it safe and initialize the MCS. We
982 * can use a fast-clear for MCS because we only ever touch from render
983 * and texture (no image load store).
985 if (image
->samples
== 1) {
986 for (uint32_t l
= 0; l
< level_count
; l
++) {
987 const uint32_t level
= base_level
+ l
;
989 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
990 if (base_layer
>= aux_layers
)
991 break; /* We will only get fewer layers as level increases */
992 uint32_t level_layer_count
=
993 MIN2(layer_count
, aux_layers
- base_layer
);
995 anv_image_ccs_op(cmd_buffer
, image
,
996 image
->planes
[plane
].surface
.isl
.format
,
997 aspect
, level
, base_layer
, level_layer_count
,
998 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1000 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1001 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1002 level
, base_layer
, level_layer_count
,
1007 if (image
->samples
== 4 || image
->samples
== 16) {
1008 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1009 "Doing a potentially unnecessary fast-clear to "
1010 "define an MCS buffer.");
1013 assert(base_level
== 0 && level_count
== 1);
1014 anv_image_mcs_op(cmd_buffer
, image
,
1015 image
->planes
[plane
].surface
.isl
.format
,
1016 aspect
, base_layer
, layer_count
,
1017 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1022 const enum isl_aux_usage initial_aux_usage
=
1023 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1024 const enum isl_aux_usage final_aux_usage
=
1025 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1027 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1028 * We can handle transitions between CCS_D/E to and from NONE. What we
1029 * don't yet handle is switching between CCS_E and CCS_D within a given
1030 * image. Doing so in a performant way requires more detailed aux state
1031 * tracking such as what is done in i965. For now, just assume that we
1032 * only have one type of compression.
1034 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1035 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1036 initial_aux_usage
== final_aux_usage
);
1038 /* If initial aux usage is NONE, there is nothing to resolve */
1039 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1042 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1044 /* If the initial layout supports more fast clear than the final layout
1045 * then we need at least a partial resolve.
1047 const enum anv_fast_clear_type initial_fast_clear
=
1048 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1049 const enum anv_fast_clear_type final_fast_clear
=
1050 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1051 if (final_fast_clear
< initial_fast_clear
)
1052 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1054 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1055 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1056 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1058 if (resolve_op
== ISL_AUX_OP_NONE
)
1061 /* Perform a resolve to synchronize data between the main and aux buffer.
1062 * Before we begin, we must satisfy the cache flushing requirement specified
1063 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1065 * Any transition from any value in {Clear, Render, Resolve} to a
1066 * different value in {Clear, Render, Resolve} requires end of pipe
1069 * We perform a flush of the write cache before and after the clear and
1070 * resolve operations to meet this requirement.
1072 * Unlike other drawing, fast clear operations are not properly
1073 * synchronized. The first PIPE_CONTROL here likely ensures that the
1074 * contents of the previous render or clear hit the render target before we
1075 * resolve and the second likely ensures that the resolve is complete before
1076 * we do any more rendering or clearing.
1078 cmd_buffer
->state
.pending_pipe_bits
|=
1079 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1081 for (uint32_t l
= 0; l
< level_count
; l
++) {
1082 uint32_t level
= base_level
+ l
;
1084 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1085 if (base_layer
>= aux_layers
)
1086 break; /* We will only get fewer layers as level increases */
1087 uint32_t level_layer_count
=
1088 MIN2(layer_count
, aux_layers
- base_layer
);
1090 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1091 uint32_t array_layer
= base_layer
+ a
;
1092 if (image
->samples
== 1) {
1093 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1094 image
->planes
[plane
].surface
.isl
.format
,
1095 aspect
, level
, array_layer
, resolve_op
,
1098 /* We only support fast-clear on the first layer so partial
1099 * resolves should not be used on other layers as they will use
1100 * the clear color stored in memory that is only valid for layer0.
1102 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1106 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1107 image
->planes
[plane
].surface
.isl
.format
,
1108 aspect
, array_layer
, resolve_op
,
1114 cmd_buffer
->state
.pending_pipe_bits
|=
1115 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1119 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1122 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1123 struct anv_render_pass
*pass
,
1124 const VkRenderPassBeginInfo
*begin
)
1126 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1127 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1129 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1131 if (pass
->attachment_count
> 0) {
1132 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1133 pass
->attachment_count
*
1134 sizeof(state
->attachments
[0]),
1135 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1136 if (state
->attachments
== NULL
) {
1137 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1138 return anv_batch_set_error(&cmd_buffer
->batch
,
1139 VK_ERROR_OUT_OF_HOST_MEMORY
);
1142 state
->attachments
= NULL
;
1145 /* Reserve one for the NULL state. */
1146 unsigned num_states
= 1;
1147 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1148 if (vk_format_is_color(pass
->attachments
[i
].format
))
1151 if (need_input_attachment_state(&pass
->attachments
[i
]))
1155 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1156 state
->render_pass_states
=
1157 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1158 num_states
* ss_stride
, isl_dev
->ss
.align
);
1160 struct anv_state next_state
= state
->render_pass_states
;
1161 next_state
.alloc_size
= isl_dev
->ss
.size
;
1163 state
->null_surface_state
= next_state
;
1164 next_state
.offset
+= ss_stride
;
1165 next_state
.map
+= ss_stride
;
1167 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1168 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1169 state
->attachments
[i
].color
.state
= next_state
;
1170 next_state
.offset
+= ss_stride
;
1171 next_state
.map
+= ss_stride
;
1174 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1175 state
->attachments
[i
].input
.state
= next_state
;
1176 next_state
.offset
+= ss_stride
;
1177 next_state
.map
+= ss_stride
;
1180 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1181 state
->render_pass_states
.alloc_size
);
1184 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1185 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1187 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1188 isl_extent3d(framebuffer
->width
,
1189 framebuffer
->height
,
1190 framebuffer
->layers
));
1192 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1193 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1194 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1195 VkImageAspectFlags clear_aspects
= 0;
1196 VkImageAspectFlags load_aspects
= 0;
1198 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1199 /* color attachment */
1200 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1201 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1202 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1203 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1206 /* depthstencil attachment */
1207 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1208 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1209 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1210 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1211 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1214 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1215 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1216 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1217 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1218 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1223 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1224 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1225 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1227 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1229 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1230 anv_assert(iview
->vk_format
== att
->format
);
1232 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1233 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1235 union isl_color_value clear_color
= { .u32
= { 0, } };
1236 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1237 anv_assert(iview
->n_planes
== 1);
1238 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1239 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1240 state
, i
, begin
->renderArea
,
1243 anv_image_fill_surface_state(cmd_buffer
->device
,
1245 VK_IMAGE_ASPECT_COLOR_BIT
,
1246 &iview
->planes
[0].isl
,
1247 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1248 state
->attachments
[i
].aux_usage
,
1251 &state
->attachments
[i
].color
,
1254 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1256 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1261 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1262 anv_image_fill_surface_state(cmd_buffer
->device
,
1264 VK_IMAGE_ASPECT_COLOR_BIT
,
1265 &iview
->planes
[0].isl
,
1266 ISL_SURF_USAGE_TEXTURE_BIT
,
1267 state
->attachments
[i
].input_aux_usage
,
1270 &state
->attachments
[i
].input
,
1273 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1282 genX(BeginCommandBuffer
)(
1283 VkCommandBuffer commandBuffer
,
1284 const VkCommandBufferBeginInfo
* pBeginInfo
)
1286 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1288 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1289 * command buffer's state. Otherwise, we must *reset* its state. In both
1290 * cases we reset it.
1292 * From the Vulkan 1.0 spec:
1294 * If a command buffer is in the executable state and the command buffer
1295 * was allocated from a command pool with the
1296 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1297 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1298 * as if vkResetCommandBuffer had been called with
1299 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1300 * the command buffer in the recording state.
1302 anv_cmd_buffer_reset(cmd_buffer
);
1304 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1306 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1307 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1309 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1311 /* We sometimes store vertex data in the dynamic state buffer for blorp
1312 * operations and our dynamic state stream may re-use data from previous
1313 * command buffers. In order to prevent stale cache data, we flush the VF
1314 * cache. We could do this on every blorp call but that's not really
1315 * needed as all of the data will get written by the CPU prior to the GPU
1316 * executing anything. The chances are fairly high that they will use
1317 * blorp at least once per primary command buffer so it shouldn't be
1320 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1321 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1323 /* We send an "Indirect State Pointers Disable" packet at
1324 * EndCommandBuffer, so all push contant packets are ignored during a
1325 * context restore. Documentation says after that command, we need to
1326 * emit push constants again before any rendering operation. So we
1327 * flag them dirty here to make sure they get emitted.
1329 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1331 VkResult result
= VK_SUCCESS
;
1332 if (cmd_buffer
->usage_flags
&
1333 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1334 assert(pBeginInfo
->pInheritanceInfo
);
1335 cmd_buffer
->state
.pass
=
1336 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1337 cmd_buffer
->state
.subpass
=
1338 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1340 /* This is optional in the inheritance info. */
1341 cmd_buffer
->state
.framebuffer
=
1342 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1344 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1345 cmd_buffer
->state
.pass
, NULL
);
1347 /* Record that HiZ is enabled if we can. */
1348 if (cmd_buffer
->state
.framebuffer
) {
1349 const struct anv_image_view
* const iview
=
1350 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1353 VkImageLayout layout
=
1354 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1356 enum isl_aux_usage aux_usage
=
1357 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1358 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1360 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1364 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1367 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1368 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1369 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1370 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1372 /* If secondary buffer supports conditional rendering
1373 * we should emit commands as if conditional rendering is enabled.
1375 cmd_buffer
->state
.conditional_render_enabled
=
1376 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1383 /* From the PRM, Volume 2a:
1385 * "Indirect State Pointers Disable
1387 * At the completion of the post-sync operation associated with this pipe
1388 * control packet, the indirect state pointers in the hardware are
1389 * considered invalid; the indirect pointers are not saved in the context.
1390 * If any new indirect state commands are executed in the command stream
1391 * while the pipe control is pending, the new indirect state commands are
1394 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1395 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1396 * commands are only considered as Indirect State Pointers. Once ISP is
1397 * issued in a context, SW must initialize by programming push constant
1398 * commands for all the shaders (at least to zero length) before attempting
1399 * any rendering operation for the same context."
1401 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1402 * even though they point to a BO that has been already unreferenced at
1403 * the end of the previous batch buffer. This has been fine so far since
1404 * we are protected by these scratch page (every address not covered by
1405 * a BO should be pointing to the scratch page). But on CNL, it is
1406 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1409 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1410 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1411 * context restore, so the mentioned hang doesn't happen. However,
1412 * software must program push constant commands for all stages prior to
1413 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1415 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1416 * constants have been loaded into the EUs prior to disable the push constants
1417 * so that it doesn't hang a previous 3DPRIMITIVE.
1420 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1422 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1423 pc
.StallAtPixelScoreboard
= true;
1424 pc
.CommandStreamerStallEnable
= true;
1426 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1427 pc
.IndirectStatePointersDisable
= true;
1428 pc
.CommandStreamerStallEnable
= true;
1433 genX(EndCommandBuffer
)(
1434 VkCommandBuffer commandBuffer
)
1436 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1438 if (anv_batch_has_error(&cmd_buffer
->batch
))
1439 return cmd_buffer
->batch
.status
;
1441 /* We want every command buffer to start with the PMA fix in a known state,
1442 * so we disable it at the end of the command buffer.
1444 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1446 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1448 emit_isp_disable(cmd_buffer
);
1450 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1456 genX(CmdExecuteCommands
)(
1457 VkCommandBuffer commandBuffer
,
1458 uint32_t commandBufferCount
,
1459 const VkCommandBuffer
* pCmdBuffers
)
1461 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1463 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1465 if (anv_batch_has_error(&primary
->batch
))
1468 /* The secondary command buffers will assume that the PMA fix is disabled
1469 * when they begin executing. Make sure this is true.
1471 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1473 /* The secondary command buffer doesn't know which textures etc. have been
1474 * flushed prior to their execution. Apply those flushes now.
1476 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1478 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1479 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1481 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1482 assert(!anv_batch_has_error(&secondary
->batch
));
1484 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1485 if (secondary
->state
.conditional_render_enabled
) {
1486 if (!primary
->state
.conditional_render_enabled
) {
1487 /* Secondary buffer is constructed as if it will be executed
1488 * with conditional rendering, we should satisfy this dependency
1489 * regardless of conditional rendering being enabled in primary.
1491 struct gen_mi_builder b
;
1492 gen_mi_builder_init(&b
, &primary
->batch
);
1493 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
1494 gen_mi_imm(UINT64_MAX
));
1499 if (secondary
->usage_flags
&
1500 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1501 /* If we're continuing a render pass from the primary, we need to
1502 * copy the surface states for the current subpass into the storage
1503 * we allocated for them in BeginCommandBuffer.
1505 struct anv_bo
*ss_bo
=
1506 primary
->device
->surface_state_pool
.block_pool
.bo
;
1507 struct anv_state src_state
= primary
->state
.render_pass_states
;
1508 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1509 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1511 genX(cmd_buffer_so_memcpy
)(primary
,
1512 (struct anv_address
) {
1514 .offset
= dst_state
.offset
,
1516 (struct anv_address
) {
1518 .offset
= src_state
.offset
,
1520 src_state
.alloc_size
);
1523 anv_cmd_buffer_add_secondary(primary
, secondary
);
1526 /* The secondary may have selected a different pipeline (3D or compute) and
1527 * may have changed the current L3$ configuration. Reset our tracking
1528 * variables to invalid values to ensure that we re-emit these in the case
1529 * where we do any draws or compute dispatches from the primary after the
1530 * secondary has returned.
1532 primary
->state
.current_pipeline
= UINT32_MAX
;
1533 primary
->state
.current_l3_config
= NULL
;
1535 /* Each of the secondary command buffers will use its own state base
1536 * address. We need to re-emit state base address for the primary after
1537 * all of the secondaries are done.
1539 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1542 genX(cmd_buffer_emit_state_base_address
)(primary
);
1545 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1546 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1547 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1550 * Program the hardware to use the specified L3 configuration.
1553 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1554 const struct gen_l3_config
*cfg
)
1557 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1560 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1561 intel_logd("L3 config transition: ");
1562 gen_dump_l3_config(cfg
, stderr
);
1565 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1567 /* According to the hardware docs, the L3 partitioning can only be changed
1568 * while the pipeline is completely drained and the caches are flushed,
1569 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1571 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1572 pc
.DCFlushEnable
= true;
1573 pc
.PostSyncOperation
= NoWrite
;
1574 pc
.CommandStreamerStallEnable
= true;
1577 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1578 * invalidation of the relevant caches. Note that because RO invalidation
1579 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1580 * command is processed by the CS) we cannot combine it with the previous
1581 * stalling flush as the hardware documentation suggests, because that
1582 * would cause the CS to stall on previous rendering *after* RO
1583 * invalidation and wouldn't prevent the RO caches from being polluted by
1584 * concurrent rendering before the stall completes. This intentionally
1585 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1586 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1587 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1588 * already guarantee that there is no concurrent GPGPU kernel execution
1589 * (see SKL HSD 2132585).
1591 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1592 pc
.TextureCacheInvalidationEnable
= true;
1593 pc
.ConstantCacheInvalidationEnable
= true;
1594 pc
.InstructionCacheInvalidateEnable
= true;
1595 pc
.StateCacheInvalidationEnable
= true;
1596 pc
.PostSyncOperation
= NoWrite
;
1599 /* Now send a third stalling flush to make sure that invalidation is
1600 * complete when the L3 configuration registers are modified.
1602 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1603 pc
.DCFlushEnable
= true;
1604 pc
.PostSyncOperation
= NoWrite
;
1605 pc
.CommandStreamerStallEnable
= true;
1610 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1613 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1614 .SLMEnable
= has_slm
,
1616 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1617 * in L3CNTLREG register. The default setting of the bit is not the
1618 * desirable behavior.
1620 .ErrorDetectionBehaviorControl
= true,
1621 .UseFullWays
= true,
1623 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1624 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1625 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1626 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1628 /* Set up the L3 partitioning. */
1629 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1633 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1634 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1635 cfg
->n
[GEN_L3P_ALL
];
1636 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1637 cfg
->n
[GEN_L3P_ALL
];
1638 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1639 cfg
->n
[GEN_L3P_ALL
];
1641 assert(!cfg
->n
[GEN_L3P_ALL
]);
1643 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1644 * the matching space on the remaining banks has to be allocated to a
1645 * client (URB for all validated configurations) set to the
1646 * lower-bandwidth 2-bank address hashing mode.
1648 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1649 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1650 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1652 /* Minimum number of ways that can be allocated to the URB. */
1653 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1654 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1656 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1657 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1658 .ConvertDC_UC
= !has_dc
,
1659 .ConvertIS_UC
= !has_is
,
1660 .ConvertC_UC
= !has_c
,
1661 .ConvertT_UC
= !has_t
);
1663 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1664 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1665 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1667 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1668 .SLMEnable
= has_slm
,
1669 .URBLowBandwidth
= urb_low_bw
,
1670 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1672 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1674 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1675 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1677 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1678 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1679 .ISLowBandwidth
= 0,
1680 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1682 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1683 .TLowBandwidth
= 0);
1685 /* Set up the L3 partitioning. */
1686 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1687 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1688 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1691 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1692 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1693 * them disabled to avoid crashing the system hard.
1695 uint32_t scratch1
, chicken3
;
1696 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1697 .L3AtomicDisable
= !has_dc
);
1698 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1699 .L3AtomicDisableMask
= true,
1700 .L3AtomicDisable
= !has_dc
);
1701 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1702 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1708 cmd_buffer
->state
.current_l3_config
= cfg
;
1712 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1714 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1716 /* Flushes are pipelined while invalidations are handled immediately.
1717 * Therefore, if we're flushing anything then we need to schedule a stall
1718 * before any invalidations can happen.
1720 if (bits
& ANV_PIPE_FLUSH_BITS
)
1721 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1723 /* If we're going to do an invalidate and we have a pending CS stall that
1724 * has yet to be resolved, we do the CS stall now.
1726 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1727 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1728 bits
|= ANV_PIPE_CS_STALL_BIT
;
1729 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1732 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1733 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1734 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1735 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1736 pipe
.RenderTargetCacheFlushEnable
=
1737 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1739 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1740 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1741 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1744 * According to the Broadwell documentation, any PIPE_CONTROL with the
1745 * "Command Streamer Stall" bit set must also have another bit set,
1746 * with five different options:
1748 * - Render Target Cache Flush
1749 * - Depth Cache Flush
1750 * - Stall at Pixel Scoreboard
1751 * - Post-Sync Operation
1755 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1756 * mesa and it seems to work fine. The choice is fairly arbitrary.
1758 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1759 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1760 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1761 pipe
.StallAtPixelScoreboard
= true;
1764 /* If a render target flush was emitted, then we can toggle off the bit
1765 * saying that render target writes are ongoing.
1767 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
1768 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
1770 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1773 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1774 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1776 * "If the VF Cache Invalidation Enable is set to a 1 in a
1777 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1778 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1779 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1782 * This appears to hang Broadwell, so we restrict it to just gen9.
1784 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1785 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1787 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1788 pipe
.StateCacheInvalidationEnable
=
1789 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1790 pipe
.ConstantCacheInvalidationEnable
=
1791 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1792 pipe
.VFCacheInvalidationEnable
=
1793 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1794 pipe
.TextureCacheInvalidationEnable
=
1795 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1796 pipe
.InstructionCacheInvalidateEnable
=
1797 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1799 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1801 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1802 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1803 * “Write Timestamp”.
1805 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1806 pipe
.PostSyncOperation
= WriteImmediateData
;
1808 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1812 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1815 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1818 void genX(CmdPipelineBarrier
)(
1819 VkCommandBuffer commandBuffer
,
1820 VkPipelineStageFlags srcStageMask
,
1821 VkPipelineStageFlags destStageMask
,
1823 uint32_t memoryBarrierCount
,
1824 const VkMemoryBarrier
* pMemoryBarriers
,
1825 uint32_t bufferMemoryBarrierCount
,
1826 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1827 uint32_t imageMemoryBarrierCount
,
1828 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1830 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1832 /* XXX: Right now, we're really dumb and just flush whatever categories
1833 * the app asks for. One of these days we may make this a bit better
1834 * but right now that's all the hardware allows for in most areas.
1836 VkAccessFlags src_flags
= 0;
1837 VkAccessFlags dst_flags
= 0;
1839 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1840 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1841 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1844 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1845 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1846 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1849 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1850 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1851 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1852 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1853 const VkImageSubresourceRange
*range
=
1854 &pImageMemoryBarriers
[i
].subresourceRange
;
1856 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1857 transition_depth_buffer(cmd_buffer
, image
,
1858 pImageMemoryBarriers
[i
].oldLayout
,
1859 pImageMemoryBarriers
[i
].newLayout
);
1860 } else if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1861 VkImageAspectFlags color_aspects
=
1862 anv_image_expand_aspects(image
, range
->aspectMask
);
1863 uint32_t aspect_bit
;
1865 uint32_t base_layer
, layer_count
;
1866 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1868 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1870 base_layer
= range
->baseArrayLayer
;
1871 layer_count
= anv_get_layerCount(image
, range
);
1874 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1875 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1876 range
->baseMipLevel
,
1877 anv_get_levelCount(image
, range
),
1878 base_layer
, layer_count
,
1879 pImageMemoryBarriers
[i
].oldLayout
,
1880 pImageMemoryBarriers
[i
].newLayout
);
1885 cmd_buffer
->state
.pending_pipe_bits
|=
1886 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1887 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1891 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1893 VkShaderStageFlags stages
=
1894 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1896 /* In order to avoid thrash, we assume that vertex and fragment stages
1897 * always exist. In the rare case where one is missing *and* the other
1898 * uses push concstants, this may be suboptimal. However, avoiding stalls
1899 * seems more important.
1901 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1903 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1907 const unsigned push_constant_kb
= 32;
1908 #elif GEN_IS_HASWELL
1909 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1911 const unsigned push_constant_kb
= 16;
1914 const unsigned num_stages
=
1915 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1916 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1918 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1919 * units of 2KB. Incidentally, these are the same platforms that have
1920 * 32KB worth of push constant space.
1922 if (push_constant_kb
== 32)
1923 size_per_stage
&= ~1u;
1925 uint32_t kb_used
= 0;
1926 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1927 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1928 anv_batch_emit(&cmd_buffer
->batch
,
1929 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1930 alloc
._3DCommandSubOpcode
= 18 + i
;
1931 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1932 alloc
.ConstantBufferSize
= push_size
;
1934 kb_used
+= push_size
;
1937 anv_batch_emit(&cmd_buffer
->batch
,
1938 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1939 alloc
.ConstantBufferOffset
= kb_used
;
1940 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1943 cmd_buffer
->state
.push_constant_stages
= stages
;
1945 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1947 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1948 * the next 3DPRIMITIVE command after programming the
1949 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1951 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1952 * pipeline setup, we need to dirty push constants.
1954 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1957 static const struct anv_descriptor
*
1958 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1959 const struct anv_pipeline_binding
*binding
)
1961 assert(binding
->set
< MAX_SETS
);
1962 const struct anv_descriptor_set
*set
=
1963 pipe_state
->descriptors
[binding
->set
];
1964 const uint32_t offset
=
1965 set
->layout
->binding
[binding
->binding
].descriptor_index
;
1966 return &set
->descriptors
[offset
+ binding
->index
];
1970 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1971 const struct anv_pipeline_binding
*binding
)
1973 assert(binding
->set
< MAX_SETS
);
1974 const struct anv_descriptor_set
*set
=
1975 pipe_state
->descriptors
[binding
->set
];
1977 uint32_t dynamic_offset_idx
=
1978 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
1979 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1982 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
1985 static struct anv_address
1986 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
1987 struct anv_descriptor_set
*set
)
1990 /* This is a normal descriptor set */
1991 return (struct anv_address
) {
1992 .bo
= &set
->pool
->bo
,
1993 .offset
= set
->desc_mem
.offset
,
1996 /* This is a push descriptor set. We have to flag it as used on the GPU
1997 * so that the next time we push descriptors, we grab a new memory.
1999 struct anv_push_descriptor_set
*push_set
=
2000 (struct anv_push_descriptor_set
*)set
;
2001 push_set
->set_used_on_gpu
= true;
2003 return (struct anv_address
) {
2004 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2005 .offset
= set
->desc_mem
.offset
,
2011 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2012 gl_shader_stage stage
,
2013 struct anv_state
*bt_state
)
2015 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2016 struct anv_cmd_pipeline_state
*pipe_state
;
2017 struct anv_pipeline
*pipeline
;
2018 uint32_t state_offset
;
2021 case MESA_SHADER_COMPUTE
:
2022 pipe_state
= &cmd_buffer
->state
.compute
.base
;
2025 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
2028 pipeline
= pipe_state
->pipeline
;
2030 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2031 *bt_state
= (struct anv_state
) { 0, };
2035 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2036 if (map
->surface_count
== 0) {
2037 *bt_state
= (struct anv_state
) { 0, };
2041 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2044 uint32_t *bt_map
= bt_state
->map
;
2046 if (bt_state
->map
== NULL
)
2047 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2049 /* We only need to emit relocs if we're not using softpin. If we are using
2050 * softpin then we always keep all user-allocated memory objects resident.
2052 const bool need_client_mem_relocs
=
2053 !cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
;
2055 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2056 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2058 struct anv_state surface_state
;
2060 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2061 /* Color attachment binding */
2062 assert(stage
== MESA_SHADER_FRAGMENT
);
2063 assert(binding
->binding
== 0);
2064 if (binding
->index
< subpass
->color_count
) {
2065 const unsigned att
=
2066 subpass
->color_attachments
[binding
->index
].attachment
;
2068 /* From the Vulkan 1.0.46 spec:
2070 * "If any color or depth/stencil attachments are
2071 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2074 if (att
== VK_ATTACHMENT_UNUSED
) {
2075 surface_state
= cmd_buffer
->state
.null_surface_state
;
2077 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2080 surface_state
= cmd_buffer
->state
.null_surface_state
;
2083 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2085 } else if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2086 struct anv_state surface_state
=
2087 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2089 struct anv_address constant_data
= {
2090 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2091 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2093 unsigned constant_data_size
=
2094 pipeline
->shaders
[stage
]->constant_data_size
;
2096 const enum isl_format format
=
2097 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2098 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2099 surface_state
, format
,
2100 constant_data
, constant_data_size
, 1);
2102 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2103 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2105 } else if (binding
->set
== ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
) {
2106 /* This is always the first binding for compute shaders */
2107 assert(stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2108 if (!get_cs_prog_data(pipeline
)->uses_num_work_groups
)
2111 struct anv_state surface_state
=
2112 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2114 const enum isl_format format
=
2115 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2116 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2118 cmd_buffer
->state
.compute
.num_workgroups
,
2120 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2121 if (need_client_mem_relocs
) {
2122 add_surface_reloc(cmd_buffer
, surface_state
,
2123 cmd_buffer
->state
.compute
.num_workgroups
);
2126 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2127 /* This is a descriptor set buffer so the set index is actually
2128 * given by binding->binding. (Yes, that's confusing.)
2130 struct anv_descriptor_set
*set
=
2131 pipe_state
->descriptors
[binding
->binding
];
2132 assert(set
->desc_mem
.alloc_size
);
2133 assert(set
->desc_surface_state
.alloc_size
);
2134 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2135 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2136 anv_descriptor_set_address(cmd_buffer
, set
));
2140 const struct anv_descriptor
*desc
=
2141 anv_descriptor_for_binding(pipe_state
, binding
);
2143 switch (desc
->type
) {
2144 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2145 /* Nothing for us to do here */
2148 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2149 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2150 struct anv_surface_state sstate
=
2151 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2152 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2153 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2154 surface_state
= sstate
.state
;
2155 assert(surface_state
.alloc_size
);
2156 if (need_client_mem_relocs
)
2157 add_surface_state_relocs(cmd_buffer
, sstate
);
2160 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2161 assert(stage
== MESA_SHADER_FRAGMENT
);
2162 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2163 /* For depth and stencil input attachments, we treat it like any
2164 * old texture that a user may have bound.
2166 struct anv_surface_state sstate
=
2167 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2168 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2169 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2170 surface_state
= sstate
.state
;
2171 assert(surface_state
.alloc_size
);
2172 if (need_client_mem_relocs
)
2173 add_surface_state_relocs(cmd_buffer
, sstate
);
2175 /* For color input attachments, we create the surface state at
2176 * vkBeginRenderPass time so that we can include aux and clear
2177 * color information.
2179 assert(binding
->input_attachment_index
< subpass
->input_count
);
2180 const unsigned subpass_att
= binding
->input_attachment_index
;
2181 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2182 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2186 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2187 struct anv_surface_state sstate
= (binding
->write_only
)
2188 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2189 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2190 surface_state
= sstate
.state
;
2191 assert(surface_state
.alloc_size
);
2192 if (need_client_mem_relocs
)
2193 add_surface_state_relocs(cmd_buffer
, sstate
);
2197 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2198 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2199 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2200 surface_state
= desc
->buffer_view
->surface_state
;
2201 assert(surface_state
.alloc_size
);
2202 if (need_client_mem_relocs
) {
2203 add_surface_reloc(cmd_buffer
, surface_state
,
2204 desc
->buffer_view
->address
);
2208 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2209 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2210 /* Compute the offset within the buffer */
2211 uint32_t dynamic_offset
=
2212 dynamic_offset_for_binding(pipe_state
, binding
);
2213 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2214 /* Clamp to the buffer size */
2215 offset
= MIN2(offset
, desc
->buffer
->size
);
2216 /* Clamp the range to the buffer size */
2217 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2219 struct anv_address address
=
2220 anv_address_add(desc
->buffer
->address
, offset
);
2223 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2224 enum isl_format format
=
2225 anv_isl_format_for_descriptor_type(desc
->type
);
2227 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2228 format
, address
, range
, 1);
2229 if (need_client_mem_relocs
)
2230 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2234 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2235 surface_state
= (binding
->write_only
)
2236 ? desc
->buffer_view
->writeonly_storage_surface_state
2237 : desc
->buffer_view
->storage_surface_state
;
2238 assert(surface_state
.alloc_size
);
2239 if (need_client_mem_relocs
) {
2240 add_surface_reloc(cmd_buffer
, surface_state
,
2241 desc
->buffer_view
->address
);
2246 assert(!"Invalid descriptor type");
2250 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2254 /* The PIPE_CONTROL command description says:
2256 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2257 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2258 * Target Cache Flush by enabling this bit. When render target flush
2259 * is set due to new association of BTI, PS Scoreboard Stall bit must
2260 * be set in this packet."
2262 * FINISHME: Currently we shuffle around the surface states in the binding
2263 * table based on if they are getting used or not. So, we've to do below
2264 * pipe control flush for every binding table upload. Make changes so
2265 * that we do it only when we modify render target surface states.
2267 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2268 pc
.RenderTargetCacheFlushEnable
= true;
2269 pc
.StallAtPixelScoreboard
= true;
2277 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2278 gl_shader_stage stage
,
2279 struct anv_state
*state
)
2281 struct anv_cmd_pipeline_state
*pipe_state
=
2282 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2283 &cmd_buffer
->state
.gfx
.base
;
2284 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2286 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2287 *state
= (struct anv_state
) { 0, };
2291 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2292 if (map
->sampler_count
== 0) {
2293 *state
= (struct anv_state
) { 0, };
2297 uint32_t size
= map
->sampler_count
* 16;
2298 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2300 if (state
->map
== NULL
)
2301 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2303 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2304 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2305 const struct anv_descriptor
*desc
=
2306 anv_descriptor_for_binding(pipe_state
, binding
);
2308 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2309 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2312 struct anv_sampler
*sampler
= desc
->sampler
;
2314 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2315 * happens to be zero.
2317 if (sampler
== NULL
)
2320 memcpy(state
->map
+ (s
* 16),
2321 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2328 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2330 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2332 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2333 pipeline
->active_stages
;
2335 VkResult result
= VK_SUCCESS
;
2336 anv_foreach_stage(s
, dirty
) {
2337 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2338 if (result
!= VK_SUCCESS
)
2340 result
= emit_binding_table(cmd_buffer
, s
,
2341 &cmd_buffer
->state
.binding_tables
[s
]);
2342 if (result
!= VK_SUCCESS
)
2346 if (result
!= VK_SUCCESS
) {
2347 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2349 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2350 if (result
!= VK_SUCCESS
)
2353 /* Re-emit state base addresses so we get the new surface state base
2354 * address before we start emitting binding tables etc.
2356 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2358 /* Re-emit all active binding tables */
2359 dirty
|= pipeline
->active_stages
;
2360 anv_foreach_stage(s
, dirty
) {
2361 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2362 if (result
!= VK_SUCCESS
) {
2363 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2366 result
= emit_binding_table(cmd_buffer
, s
,
2367 &cmd_buffer
->state
.binding_tables
[s
]);
2368 if (result
!= VK_SUCCESS
) {
2369 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2375 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2381 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2384 static const uint32_t sampler_state_opcodes
[] = {
2385 [MESA_SHADER_VERTEX
] = 43,
2386 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2387 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2388 [MESA_SHADER_GEOMETRY
] = 46,
2389 [MESA_SHADER_FRAGMENT
] = 47,
2390 [MESA_SHADER_COMPUTE
] = 0,
2393 static const uint32_t binding_table_opcodes
[] = {
2394 [MESA_SHADER_VERTEX
] = 38,
2395 [MESA_SHADER_TESS_CTRL
] = 39,
2396 [MESA_SHADER_TESS_EVAL
] = 40,
2397 [MESA_SHADER_GEOMETRY
] = 41,
2398 [MESA_SHADER_FRAGMENT
] = 42,
2399 [MESA_SHADER_COMPUTE
] = 0,
2402 anv_foreach_stage(s
, stages
) {
2403 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2404 assert(binding_table_opcodes
[s
] > 0);
2406 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2407 anv_batch_emit(&cmd_buffer
->batch
,
2408 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2409 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2410 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2414 /* Always emit binding table pointers if we're asked to, since on SKL
2415 * this is what flushes push constants. */
2416 anv_batch_emit(&cmd_buffer
->batch
,
2417 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2418 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2419 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2425 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2426 VkShaderStageFlags dirty_stages
)
2428 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2429 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2431 static const uint32_t push_constant_opcodes
[] = {
2432 [MESA_SHADER_VERTEX
] = 21,
2433 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2434 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2435 [MESA_SHADER_GEOMETRY
] = 22,
2436 [MESA_SHADER_FRAGMENT
] = 23,
2437 [MESA_SHADER_COMPUTE
] = 0,
2440 VkShaderStageFlags flushed
= 0;
2442 anv_foreach_stage(stage
, dirty_stages
) {
2443 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2444 assert(push_constant_opcodes
[stage
] > 0);
2446 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2447 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2449 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2450 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2451 const struct brw_stage_prog_data
*prog_data
=
2452 pipeline
->shaders
[stage
]->prog_data
;
2453 const struct anv_pipeline_bind_map
*bind_map
=
2454 &pipeline
->shaders
[stage
]->bind_map
;
2456 /* The Skylake PRM contains the following restriction:
2458 * "The driver must ensure The following case does not occur
2459 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2460 * buffer 3 read length equal to zero committed followed by a
2461 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2464 * To avoid this, we program the buffers in the highest slots.
2465 * This way, slot 0 is only used if slot 3 is also used.
2469 for (int i
= 3; i
>= 0; i
--) {
2470 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2471 if (range
->length
== 0)
2474 const unsigned surface
=
2475 prog_data
->binding_table
.ubo_start
+ range
->block
;
2477 assert(surface
<= bind_map
->surface_count
);
2478 const struct anv_pipeline_binding
*binding
=
2479 &bind_map
->surface_to_descriptor
[surface
];
2481 struct anv_address read_addr
;
2483 if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2484 struct anv_address constant_data
= {
2485 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2486 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2488 unsigned constant_data_size
=
2489 pipeline
->shaders
[stage
]->constant_data_size
;
2491 read_len
= MIN2(range
->length
,
2492 DIV_ROUND_UP(constant_data_size
, 32) - range
->start
);
2493 read_addr
= anv_address_add(constant_data
,
2495 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2496 /* This is a descriptor set buffer so the set index is
2497 * actually given by binding->binding. (Yes, that's
2500 struct anv_descriptor_set
*set
=
2501 gfx_state
->base
.descriptors
[binding
->binding
];
2502 struct anv_address desc_buffer_addr
=
2503 anv_descriptor_set_address(cmd_buffer
, set
);
2504 const unsigned desc_buffer_size
= set
->desc_mem
.alloc_size
;
2506 read_len
= MIN2(range
->length
,
2507 DIV_ROUND_UP(desc_buffer_size
, 32) - range
->start
);
2508 read_addr
= anv_address_add(desc_buffer_addr
,
2511 const struct anv_descriptor
*desc
=
2512 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2514 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2515 read_len
= MIN2(range
->length
,
2516 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2517 read_addr
= anv_address_add(desc
->buffer_view
->address
,
2520 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2522 uint32_t dynamic_offset
=
2523 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2524 uint32_t buf_offset
=
2525 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2526 uint32_t buf_range
=
2527 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2529 read_len
= MIN2(range
->length
,
2530 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2531 read_addr
= anv_address_add(desc
->buffer
->address
,
2532 buf_offset
+ range
->start
* 32);
2537 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2538 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2543 struct anv_state state
=
2544 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2546 if (state
.alloc_size
> 0) {
2547 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2548 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2549 .offset
= state
.offset
,
2551 c
.ConstantBody
.ReadLength
[n
] =
2552 DIV_ROUND_UP(state
.alloc_size
, 32);
2555 /* For Ivy Bridge, the push constants packets have a different
2556 * rule that would require us to iterate in the other direction
2557 * and possibly mess around with dynamic state base address.
2558 * Don't bother; just emit regular push constants at n = 0.
2560 struct anv_state state
=
2561 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2563 if (state
.alloc_size
> 0) {
2564 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2565 c
.ConstantBody
.ReadLength
[0] =
2566 DIV_ROUND_UP(state
.alloc_size
, 32);
2572 flushed
|= mesa_to_vk_shader_stage(stage
);
2575 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2579 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2581 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2584 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2585 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2586 vb_emit
|= pipeline
->vb_used
;
2588 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2590 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2592 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2595 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2596 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2598 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2599 GENX(3DSTATE_VERTEX_BUFFERS
));
2601 for_each_bit(vb
, vb_emit
) {
2602 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2603 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2605 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2606 .VertexBufferIndex
= vb
,
2608 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
2610 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2611 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2614 .AddressModifyEnable
= true,
2615 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2616 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2619 .BufferSize
= buffer
->size
- offset
2621 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2625 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2630 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2633 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
2634 /* We don't need any per-buffer dirty tracking because you're not
2635 * allowed to bind different XFB buffers while XFB is enabled.
2637 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
2638 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
2639 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
2640 sob
.SOBufferIndex
= idx
;
2642 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
2643 sob
.SOBufferEnable
= true;
2644 sob
.MOCS
= cmd_buffer
->device
->default_mocs
,
2645 sob
.StreamOffsetWriteEnable
= false;
2646 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
2648 /* Size is in DWords - 1 */
2649 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
2654 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
2656 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2660 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2661 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2663 /* The exact descriptor layout is pulled from the pipeline, so we need
2664 * to re-emit binding tables on every pipeline change.
2666 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2668 /* If the pipeline changed, we may need to re-allocate push constant
2671 cmd_buffer_alloc_push_constants(cmd_buffer
);
2675 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2676 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2677 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2679 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2680 * stall needs to be sent just prior to any 3DSTATE_VS,
2681 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2682 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2683 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2684 * PIPE_CONTROL needs to be sent before any combination of VS
2685 * associated 3DSTATE."
2687 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2688 pc
.DepthStallEnable
= true;
2689 pc
.PostSyncOperation
= WriteImmediateData
;
2691 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2696 /* Render targets live in the same binding table as fragment descriptors */
2697 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2698 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2700 /* We emit the binding tables and sampler tables first, then emit push
2701 * constants and then finally emit binding table and sampler table
2702 * pointers. It has to happen in this order, since emitting the binding
2703 * tables may change the push constants (in case of storage images). After
2704 * emitting push constants, on SKL+ we have to emit the corresponding
2705 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2708 if (cmd_buffer
->state
.descriptors_dirty
)
2709 dirty
= flush_descriptor_sets(cmd_buffer
);
2711 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2712 /* Because we're pushing UBOs, we have to push whenever either
2713 * descriptors or push constants is dirty.
2715 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2716 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2717 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2721 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2723 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2724 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2726 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2727 ANV_CMD_DIRTY_PIPELINE
)) {
2728 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2729 pipeline
->depth_clamp_enable
);
2732 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2733 ANV_CMD_DIRTY_RENDER_TARGETS
))
2734 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2736 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2738 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2742 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2743 struct anv_address addr
,
2744 uint32_t size
, uint32_t index
)
2746 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2747 GENX(3DSTATE_VERTEX_BUFFERS
));
2749 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2750 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2751 .VertexBufferIndex
= index
,
2752 .AddressModifyEnable
= true,
2754 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
),
2756 .BufferStartingAddress
= addr
,
2759 .BufferStartingAddress
= addr
,
2760 .EndAddress
= anv_address_add(addr
, size
),
2766 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2767 struct anv_address addr
)
2769 emit_vertex_bo(cmd_buffer
, addr
, 8, ANV_SVGS_VB_INDEX
);
2773 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2774 uint32_t base_vertex
, uint32_t base_instance
)
2776 struct anv_state id_state
=
2777 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2779 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2780 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2782 struct anv_address addr
= {
2783 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2784 .offset
= id_state
.offset
,
2787 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2791 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2793 struct anv_state state
=
2794 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2796 ((uint32_t *)state
.map
)[0] = draw_index
;
2798 struct anv_address addr
= {
2799 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2800 .offset
= state
.offset
,
2803 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2807 VkCommandBuffer commandBuffer
,
2808 uint32_t vertexCount
,
2809 uint32_t instanceCount
,
2810 uint32_t firstVertex
,
2811 uint32_t firstInstance
)
2813 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2814 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2815 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2817 if (anv_batch_has_error(&cmd_buffer
->batch
))
2820 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2822 if (cmd_buffer
->state
.conditional_render_enabled
)
2823 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2825 if (vs_prog_data
->uses_firstvertex
||
2826 vs_prog_data
->uses_baseinstance
)
2827 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2828 if (vs_prog_data
->uses_drawid
)
2829 emit_draw_index(cmd_buffer
, 0);
2831 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2832 * different views. We need to multiply instanceCount by the view count.
2834 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2836 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2837 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2838 prim
.VertexAccessType
= SEQUENTIAL
;
2839 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2840 prim
.VertexCountPerInstance
= vertexCount
;
2841 prim
.StartVertexLocation
= firstVertex
;
2842 prim
.InstanceCount
= instanceCount
;
2843 prim
.StartInstanceLocation
= firstInstance
;
2844 prim
.BaseVertexLocation
= 0;
2848 void genX(CmdDrawIndexed
)(
2849 VkCommandBuffer commandBuffer
,
2850 uint32_t indexCount
,
2851 uint32_t instanceCount
,
2852 uint32_t firstIndex
,
2853 int32_t vertexOffset
,
2854 uint32_t firstInstance
)
2856 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2857 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2858 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2860 if (anv_batch_has_error(&cmd_buffer
->batch
))
2863 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2865 if (cmd_buffer
->state
.conditional_render_enabled
)
2866 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2868 if (vs_prog_data
->uses_firstvertex
||
2869 vs_prog_data
->uses_baseinstance
)
2870 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2871 if (vs_prog_data
->uses_drawid
)
2872 emit_draw_index(cmd_buffer
, 0);
2874 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2875 * different views. We need to multiply instanceCount by the view count.
2877 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2879 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2880 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2881 prim
.VertexAccessType
= RANDOM
;
2882 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2883 prim
.VertexCountPerInstance
= indexCount
;
2884 prim
.StartVertexLocation
= firstIndex
;
2885 prim
.InstanceCount
= instanceCount
;
2886 prim
.StartInstanceLocation
= firstInstance
;
2887 prim
.BaseVertexLocation
= vertexOffset
;
2891 /* Auto-Draw / Indirect Registers */
2892 #define GEN7_3DPRIM_END_OFFSET 0x2420
2893 #define GEN7_3DPRIM_START_VERTEX 0x2430
2894 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2895 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2896 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2897 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2899 void genX(CmdDrawIndirectByteCountEXT
)(
2900 VkCommandBuffer commandBuffer
,
2901 uint32_t instanceCount
,
2902 uint32_t firstInstance
,
2903 VkBuffer counterBuffer
,
2904 VkDeviceSize counterBufferOffset
,
2905 uint32_t counterOffset
,
2906 uint32_t vertexStride
)
2908 #if GEN_IS_HASWELL || GEN_GEN >= 8
2909 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2910 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
2911 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2912 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2914 /* firstVertex is always zero for this draw function */
2915 const uint32_t firstVertex
= 0;
2917 if (anv_batch_has_error(&cmd_buffer
->batch
))
2920 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2922 if (vs_prog_data
->uses_firstvertex
||
2923 vs_prog_data
->uses_baseinstance
)
2924 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2925 if (vs_prog_data
->uses_drawid
)
2926 emit_draw_index(cmd_buffer
, 0);
2928 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2929 * different views. We need to multiply instanceCount by the view count.
2931 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2933 struct gen_mi_builder b
;
2934 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
2935 struct gen_mi_value count
=
2936 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
2937 counterBufferOffset
));
2939 count
= gen_mi_isub(&b
, count
, gen_mi_imm(counterOffset
));
2940 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
2941 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
2943 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
2944 gen_mi_imm(firstVertex
));
2945 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
2946 gen_mi_imm(instanceCount
));
2947 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
2948 gen_mi_imm(firstInstance
));
2949 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
2951 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2952 prim
.IndirectParameterEnable
= true;
2953 prim
.VertexAccessType
= SEQUENTIAL
;
2954 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2956 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2960 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2961 struct anv_address addr
,
2964 struct gen_mi_builder b
;
2965 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
2967 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
),
2968 gen_mi_mem32(anv_address_add(addr
, 0)));
2970 struct gen_mi_value instance_count
= gen_mi_mem32(anv_address_add(addr
, 4));
2971 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2972 if (view_count
> 1) {
2973 #if GEN_IS_HASWELL || GEN_GEN >= 8
2974 instance_count
= gen_mi_imul_imm(&b
, instance_count
, view_count
);
2976 anv_finishme("Multiview + indirect draw requires MI_MATH; "
2977 "MI_MATH is not supported on Ivy Bridge");
2980 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
), instance_count
);
2982 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
2983 gen_mi_mem32(anv_address_add(addr
, 8)));
2986 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
),
2987 gen_mi_mem32(anv_address_add(addr
, 12)));
2988 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
2989 gen_mi_mem32(anv_address_add(addr
, 16)));
2991 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
2992 gen_mi_mem32(anv_address_add(addr
, 12)));
2993 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
2997 void genX(CmdDrawIndirect
)(
2998 VkCommandBuffer commandBuffer
,
3000 VkDeviceSize offset
,
3004 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3005 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3006 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3007 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3009 if (anv_batch_has_error(&cmd_buffer
->batch
))
3012 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3014 if (cmd_buffer
->state
.conditional_render_enabled
)
3015 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3017 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3018 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3020 if (vs_prog_data
->uses_firstvertex
||
3021 vs_prog_data
->uses_baseinstance
)
3022 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3023 if (vs_prog_data
->uses_drawid
)
3024 emit_draw_index(cmd_buffer
, i
);
3026 load_indirect_parameters(cmd_buffer
, draw
, false);
3028 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3029 prim
.IndirectParameterEnable
= true;
3030 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3031 prim
.VertexAccessType
= SEQUENTIAL
;
3032 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3039 void genX(CmdDrawIndexedIndirect
)(
3040 VkCommandBuffer commandBuffer
,
3042 VkDeviceSize offset
,
3046 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3047 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3048 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3049 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3051 if (anv_batch_has_error(&cmd_buffer
->batch
))
3054 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3056 if (cmd_buffer
->state
.conditional_render_enabled
)
3057 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3059 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3060 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3062 /* TODO: We need to stomp base vertex to 0 somehow */
3063 if (vs_prog_data
->uses_firstvertex
||
3064 vs_prog_data
->uses_baseinstance
)
3065 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3066 if (vs_prog_data
->uses_drawid
)
3067 emit_draw_index(cmd_buffer
, i
);
3069 load_indirect_parameters(cmd_buffer
, draw
, true);
3071 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3072 prim
.IndirectParameterEnable
= true;
3073 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3074 prim
.VertexAccessType
= RANDOM
;
3075 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3082 #define TMP_DRAW_COUNT_REG 0x2670 /* MI_ALU_REG14 */
3085 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3086 struct anv_address count_address
,
3087 const bool conditional_render_enabled
)
3089 struct gen_mi_builder b
;
3090 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3092 if (conditional_render_enabled
) {
3093 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3094 gen_mi_store(&b
, gen_mi_reg64(TMP_DRAW_COUNT_REG
),
3095 gen_mi_mem32(count_address
));
3098 /* Upload the current draw count from the draw parameters buffer to
3099 * MI_PREDICATE_SRC0.
3101 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
3102 gen_mi_mem32(count_address
));
3104 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
+ 4), gen_mi_imm(0));
3109 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3110 uint32_t draw_index
)
3112 struct gen_mi_builder b
;
3113 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3115 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3116 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
), gen_mi_imm(draw_index
));
3118 if (draw_index
== 0) {
3119 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3120 mip
.LoadOperation
= LOAD_LOADINV
;
3121 mip
.CombineOperation
= COMBINE_SET
;
3122 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3125 /* While draw_index < draw_count the predicate's result will be
3126 * (draw_index == draw_count) ^ TRUE = TRUE
3127 * When draw_index == draw_count the result is
3128 * (TRUE) ^ TRUE = FALSE
3129 * After this all results will be:
3130 * (FALSE) ^ FALSE = FALSE
3132 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3133 mip
.LoadOperation
= LOAD_LOAD
;
3134 mip
.CombineOperation
= COMBINE_XOR
;
3135 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3140 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3142 emit_draw_count_predicate_with_conditional_render(
3143 struct anv_cmd_buffer
*cmd_buffer
,
3144 uint32_t draw_index
)
3146 struct gen_mi_builder b
;
3147 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3149 struct gen_mi_value pred
= gen_mi_ult(&b
, gen_mi_imm(draw_index
),
3150 gen_mi_reg64(TMP_DRAW_COUNT_REG
));
3151 pred
= gen_mi_iand(&b
, pred
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
));
3154 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_RESULT
), pred
);
3156 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3157 * so we emit MI_PREDICATE to set it.
3160 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), pred
);
3161 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3163 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3164 mip
.LoadOperation
= LOAD_LOADINV
;
3165 mip
.CombineOperation
= COMBINE_SET
;
3166 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3172 void genX(CmdDrawIndirectCountKHR
)(
3173 VkCommandBuffer commandBuffer
,
3175 VkDeviceSize offset
,
3176 VkBuffer _countBuffer
,
3177 VkDeviceSize countBufferOffset
,
3178 uint32_t maxDrawCount
,
3181 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3182 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3183 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3184 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3185 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3186 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3188 if (anv_batch_has_error(&cmd_buffer
->batch
))
3191 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3193 struct anv_address count_address
=
3194 anv_address_add(count_buffer
->address
, countBufferOffset
);
3196 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3197 cmd_state
->conditional_render_enabled
);
3199 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3200 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3202 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3203 if (cmd_state
->conditional_render_enabled
) {
3204 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3206 emit_draw_count_predicate(cmd_buffer
, i
);
3209 emit_draw_count_predicate(cmd_buffer
, i
);
3212 if (vs_prog_data
->uses_firstvertex
||
3213 vs_prog_data
->uses_baseinstance
)
3214 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3215 if (vs_prog_data
->uses_drawid
)
3216 emit_draw_index(cmd_buffer
, i
);
3218 load_indirect_parameters(cmd_buffer
, draw
, false);
3220 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3221 prim
.IndirectParameterEnable
= true;
3222 prim
.PredicateEnable
= true;
3223 prim
.VertexAccessType
= SEQUENTIAL
;
3224 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3231 void genX(CmdDrawIndexedIndirectCountKHR
)(
3232 VkCommandBuffer commandBuffer
,
3234 VkDeviceSize offset
,
3235 VkBuffer _countBuffer
,
3236 VkDeviceSize countBufferOffset
,
3237 uint32_t maxDrawCount
,
3240 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3241 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3242 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3243 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3244 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3245 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3247 if (anv_batch_has_error(&cmd_buffer
->batch
))
3250 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3252 struct anv_address count_address
=
3253 anv_address_add(count_buffer
->address
, countBufferOffset
);
3255 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3256 cmd_state
->conditional_render_enabled
);
3258 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3259 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3261 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3262 if (cmd_state
->conditional_render_enabled
) {
3263 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3265 emit_draw_count_predicate(cmd_buffer
, i
);
3268 emit_draw_count_predicate(cmd_buffer
, i
);
3271 /* TODO: We need to stomp base vertex to 0 somehow */
3272 if (vs_prog_data
->uses_firstvertex
||
3273 vs_prog_data
->uses_baseinstance
)
3274 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3275 if (vs_prog_data
->uses_drawid
)
3276 emit_draw_index(cmd_buffer
, i
);
3278 load_indirect_parameters(cmd_buffer
, draw
, true);
3280 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3281 prim
.IndirectParameterEnable
= true;
3282 prim
.PredicateEnable
= true;
3283 prim
.VertexAccessType
= RANDOM
;
3284 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3291 void genX(CmdBeginTransformFeedbackEXT
)(
3292 VkCommandBuffer commandBuffer
,
3293 uint32_t firstCounterBuffer
,
3294 uint32_t counterBufferCount
,
3295 const VkBuffer
* pCounterBuffers
,
3296 const VkDeviceSize
* pCounterBufferOffsets
)
3298 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3300 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3301 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3302 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3304 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3306 * "Ssoftware must ensure that no HW stream output operations can be in
3307 * process or otherwise pending at the point that the MI_LOAD/STORE
3308 * commands are processed. This will likely require a pipeline flush."
3310 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3311 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3313 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3314 /* If we have a counter buffer, this is a resume so we need to load the
3315 * value into the streamout offset register. Otherwise, this is a begin
3316 * and we need to reset it to zero.
3318 if (pCounterBuffers
&&
3319 idx
>= firstCounterBuffer
&&
3320 idx
- firstCounterBuffer
< counterBufferCount
&&
3321 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
3322 uint32_t cb_idx
= idx
- firstCounterBuffer
;
3323 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3324 uint64_t offset
= pCounterBufferOffsets
?
3325 pCounterBufferOffsets
[cb_idx
] : 0;
3327 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3328 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3329 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3333 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
3334 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3340 cmd_buffer
->state
.xfb_enabled
= true;
3341 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3344 void genX(CmdEndTransformFeedbackEXT
)(
3345 VkCommandBuffer commandBuffer
,
3346 uint32_t firstCounterBuffer
,
3347 uint32_t counterBufferCount
,
3348 const VkBuffer
* pCounterBuffers
,
3349 const VkDeviceSize
* pCounterBufferOffsets
)
3351 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3353 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3354 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3355 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3357 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3359 * "Ssoftware must ensure that no HW stream output operations can be in
3360 * process or otherwise pending at the point that the MI_LOAD/STORE
3361 * commands are processed. This will likely require a pipeline flush."
3363 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3364 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3366 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
3367 unsigned idx
= firstCounterBuffer
+ cb_idx
;
3369 /* If we have a counter buffer, this is a resume so we need to load the
3370 * value into the streamout offset register. Otherwise, this is a begin
3371 * and we need to reset it to zero.
3373 if (pCounterBuffers
&&
3374 cb_idx
< counterBufferCount
&&
3375 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
3376 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3377 uint64_t offset
= pCounterBufferOffsets
?
3378 pCounterBufferOffsets
[cb_idx
] : 0;
3380 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
3381 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3383 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3388 cmd_buffer
->state
.xfb_enabled
= false;
3389 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3393 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
3395 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3396 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
3399 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3400 if (result
!= VK_SUCCESS
) {
3401 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3403 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
3404 if (result
!= VK_SUCCESS
)
3407 /* Re-emit state base addresses so we get the new surface state base
3408 * address before we start emitting binding tables etc.
3410 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
3412 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3413 if (result
!= VK_SUCCESS
) {
3414 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3419 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3420 if (result
!= VK_SUCCESS
) {
3421 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3425 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3426 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3427 .BindingTablePointer
= surfaces
.offset
,
3428 .SamplerStatePointer
= samplers
.offset
,
3430 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3432 struct anv_state state
=
3433 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3434 pipeline
->interface_descriptor_data
,
3435 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3438 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3439 anv_batch_emit(&cmd_buffer
->batch
,
3440 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3441 mid
.InterfaceDescriptorTotalLength
= size
;
3442 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3449 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3451 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3452 MAYBE_UNUSED VkResult result
;
3454 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3456 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3458 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3460 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3461 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3463 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3464 * the only bits that are changed are scoreboard related: Scoreboard
3465 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3466 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3469 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3470 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3472 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3475 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3476 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3477 /* FIXME: figure out descriptors for gen7 */
3478 result
= flush_compute_descriptor_set(cmd_buffer
);
3479 if (result
!= VK_SUCCESS
)
3482 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3485 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3486 struct anv_state push_state
=
3487 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3489 if (push_state
.alloc_size
) {
3490 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3491 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3492 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3496 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3499 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3501 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3507 verify_cmd_parser(const struct anv_device
*device
,
3508 int required_version
,
3509 const char *function
)
3511 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3512 return vk_errorf(device
->instance
, device
->instance
,
3513 VK_ERROR_FEATURE_NOT_PRESENT
,
3514 "cmd parser version %d is required for %s",
3515 required_version
, function
);
3524 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3525 uint32_t baseGroupX
,
3526 uint32_t baseGroupY
,
3527 uint32_t baseGroupZ
)
3529 if (anv_batch_has_error(&cmd_buffer
->batch
))
3532 struct anv_push_constants
*push
=
3533 &cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3534 if (push
->base_work_group_id
[0] != baseGroupX
||
3535 push
->base_work_group_id
[1] != baseGroupY
||
3536 push
->base_work_group_id
[2] != baseGroupZ
) {
3537 push
->base_work_group_id
[0] = baseGroupX
;
3538 push
->base_work_group_id
[1] = baseGroupY
;
3539 push
->base_work_group_id
[2] = baseGroupZ
;
3541 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3545 void genX(CmdDispatch
)(
3546 VkCommandBuffer commandBuffer
,
3551 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3554 void genX(CmdDispatchBase
)(
3555 VkCommandBuffer commandBuffer
,
3556 uint32_t baseGroupX
,
3557 uint32_t baseGroupY
,
3558 uint32_t baseGroupZ
,
3559 uint32_t groupCountX
,
3560 uint32_t groupCountY
,
3561 uint32_t groupCountZ
)
3563 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3564 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3565 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3567 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3568 baseGroupY
, baseGroupZ
);
3570 if (anv_batch_has_error(&cmd_buffer
->batch
))
3573 if (prog_data
->uses_num_work_groups
) {
3574 struct anv_state state
=
3575 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3576 uint32_t *sizes
= state
.map
;
3577 sizes
[0] = groupCountX
;
3578 sizes
[1] = groupCountY
;
3579 sizes
[2] = groupCountZ
;
3580 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3581 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3582 .offset
= state
.offset
,
3586 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3588 if (cmd_buffer
->state
.conditional_render_enabled
)
3589 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3591 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3592 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3593 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3594 ggw
.ThreadDepthCounterMaximum
= 0;
3595 ggw
.ThreadHeightCounterMaximum
= 0;
3596 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3597 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3598 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3599 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3600 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3601 ggw
.BottomExecutionMask
= 0xffffffff;
3604 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3607 #define GPGPU_DISPATCHDIMX 0x2500
3608 #define GPGPU_DISPATCHDIMY 0x2504
3609 #define GPGPU_DISPATCHDIMZ 0x2508
3611 void genX(CmdDispatchIndirect
)(
3612 VkCommandBuffer commandBuffer
,
3614 VkDeviceSize offset
)
3616 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3617 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3618 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3619 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3620 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3621 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3623 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3626 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3627 * indirect dispatch registers to be written.
3629 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3630 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3634 if (prog_data
->uses_num_work_groups
)
3635 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3637 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3639 struct gen_mi_builder b
;
3640 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3642 struct gen_mi_value size_x
= gen_mi_mem32(anv_address_add(addr
, 0));
3643 struct gen_mi_value size_y
= gen_mi_mem32(anv_address_add(addr
, 4));
3644 struct gen_mi_value size_z
= gen_mi_mem32(anv_address_add(addr
, 8));
3646 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMX
), size_x
);
3647 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMY
), size_y
);
3648 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMZ
), size_z
);
3651 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3652 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), size_x
);
3653 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3654 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3655 mip
.LoadOperation
= LOAD_LOAD
;
3656 mip
.CombineOperation
= COMBINE_SET
;
3657 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3660 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3661 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_y
);
3662 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3663 mip
.LoadOperation
= LOAD_LOAD
;
3664 mip
.CombineOperation
= COMBINE_OR
;
3665 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3668 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3669 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_z
);
3670 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3671 mip
.LoadOperation
= LOAD_LOAD
;
3672 mip
.CombineOperation
= COMBINE_OR
;
3673 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3676 /* predicate = !predicate; */
3677 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3678 mip
.LoadOperation
= LOAD_LOADINV
;
3679 mip
.CombineOperation
= COMBINE_OR
;
3680 mip
.CompareOperation
= COMPARE_FALSE
;
3684 if (cmd_buffer
->state
.conditional_render_enabled
) {
3685 /* predicate &= !(conditional_rendering_predicate == 0); */
3686 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
),
3687 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
3688 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3689 mip
.LoadOperation
= LOAD_LOADINV
;
3690 mip
.CombineOperation
= COMBINE_AND
;
3691 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3696 #else /* GEN_GEN > 7 */
3697 if (cmd_buffer
->state
.conditional_render_enabled
)
3698 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3701 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3702 ggw
.IndirectParameterEnable
= true;
3703 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
3704 cmd_buffer
->state
.conditional_render_enabled
;
3705 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3706 ggw
.ThreadDepthCounterMaximum
= 0;
3707 ggw
.ThreadHeightCounterMaximum
= 0;
3708 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3709 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3710 ggw
.BottomExecutionMask
= 0xffffffff;
3713 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3717 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3720 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3722 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3725 #if GEN_GEN >= 8 && GEN_GEN < 10
3726 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3728 * Software must clear the COLOR_CALC_STATE Valid field in
3729 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3730 * with Pipeline Select set to GPGPU.
3732 * The internal hardware docs recommend the same workaround for Gen9
3735 if (pipeline
== GPGPU
)
3736 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3739 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3740 * PIPELINE_SELECT [DevBWR+]":
3744 * Software must ensure all the write caches are flushed through a
3745 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3746 * command to invalidate read only caches prior to programming
3747 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3749 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3750 pc
.RenderTargetCacheFlushEnable
= true;
3751 pc
.DepthCacheFlushEnable
= true;
3752 pc
.DCFlushEnable
= true;
3753 pc
.PostSyncOperation
= NoWrite
;
3754 pc
.CommandStreamerStallEnable
= true;
3757 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3758 pc
.TextureCacheInvalidationEnable
= true;
3759 pc
.ConstantCacheInvalidationEnable
= true;
3760 pc
.StateCacheInvalidationEnable
= true;
3761 pc
.InstructionCacheInvalidateEnable
= true;
3762 pc
.PostSyncOperation
= NoWrite
;
3765 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3769 ps
.PipelineSelection
= pipeline
;
3773 if (devinfo
->is_geminilake
) {
3776 * "This chicken bit works around a hardware issue with barrier logic
3777 * encountered when switching between GPGPU and 3D pipelines. To
3778 * workaround the issue, this mode bit should be set after a pipeline
3782 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3784 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3785 : GLK_BARRIER_MODE_3D_HULL
,
3786 .GLKBarrierModeMask
= 1);
3787 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3791 cmd_buffer
->state
.current_pipeline
= pipeline
;
3795 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3797 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3801 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3803 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3807 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3812 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3814 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3815 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3816 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3817 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3818 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3819 * Depth Flush Bit set, followed by another pipelined depth stall
3820 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3821 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3822 * via a preceding MI_FLUSH)."
3824 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3825 pipe
.DepthStallEnable
= true;
3827 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3828 pipe
.DepthCacheFlushEnable
= true;
3830 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3831 pipe
.DepthStallEnable
= true;
3836 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3838 struct anv_device
*device
= cmd_buffer
->device
;
3839 const struct anv_image_view
*iview
=
3840 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3841 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3843 /* FIXME: Width and Height are wrong */
3845 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3847 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3848 device
->isl_dev
.ds
.size
/ 4);
3852 struct isl_depth_stencil_hiz_emit_info info
= { };
3855 info
.view
= &iview
->planes
[0].isl
;
3857 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3858 uint32_t depth_plane
=
3859 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3860 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
3862 info
.depth_surf
= &surface
->isl
;
3864 info
.depth_address
=
3865 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3866 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
3867 image
->planes
[depth_plane
].address
.bo
,
3868 image
->planes
[depth_plane
].address
.offset
+
3871 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
3874 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
3875 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
3876 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
3877 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
3880 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3881 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
3882 image
->planes
[depth_plane
].address
.bo
,
3883 image
->planes
[depth_plane
].address
.offset
+
3884 image
->planes
[depth_plane
].aux_surface
.offset
);
3886 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
3890 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3891 uint32_t stencil_plane
=
3892 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
3893 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
3895 info
.stencil_surf
= &surface
->isl
;
3897 info
.stencil_address
=
3898 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3899 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
3900 image
->planes
[stencil_plane
].address
.bo
,
3901 image
->planes
[stencil_plane
].address
.offset
+
3904 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
3907 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
3909 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
3913 * This ANDs the view mask of the current subpass with the pending clear
3914 * views in the attachment to get the mask of views active in the subpass
3915 * that still need to be cleared.
3917 static inline uint32_t
3918 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
3919 const struct anv_attachment_state
*att_state
)
3921 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
3925 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
3926 const struct anv_attachment_state
*att_state
)
3928 if (!cmd_state
->subpass
->view_mask
)
3931 uint32_t pending_clear_mask
=
3932 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3934 return pending_clear_mask
& 1;
3938 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
3941 const uint32_t last_subpass_idx
=
3942 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
3943 const struct anv_subpass
*last_subpass
=
3944 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
3945 return last_subpass
== cmd_state
->subpass
;
3949 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
3950 uint32_t subpass_id
)
3952 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3953 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
3954 cmd_state
->subpass
= subpass
;
3956 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
3958 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3959 * different views. If the client asks for instancing, we need to use the
3960 * Instance Data Step Rate to ensure that we repeat the client's
3961 * per-instance data once for each view. Since this bit is in
3962 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
3966 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
3968 /* It is possible to start a render pass with an old pipeline. Because the
3969 * render pass and subpass index are both baked into the pipeline, this is
3970 * highly unlikely. In order to do so, it requires that you have a render
3971 * pass with a single subpass and that you use that render pass twice
3972 * back-to-back and use the same pipeline at the start of the second render
3973 * pass as at the end of the first. In order to avoid unpredictable issues
3974 * with this edge case, we just dirty the pipeline at the start of every
3977 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
3979 /* Accumulate any subpass flushes that need to happen before the subpass */
3980 cmd_buffer
->state
.pending_pipe_bits
|=
3981 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
3983 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
3984 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3986 bool is_multiview
= subpass
->view_mask
!= 0;
3988 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3989 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3990 if (a
== VK_ATTACHMENT_UNUSED
)
3993 assert(a
< cmd_state
->pass
->attachment_count
);
3994 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3996 struct anv_image_view
*iview
= fb
->attachments
[a
];
3997 const struct anv_image
*image
= iview
->image
;
3999 /* A resolve is necessary before use as an input attachment if the clear
4000 * color or auxiliary buffer usage isn't supported by the sampler.
4002 const bool input_needs_resolve
=
4003 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
4004 att_state
->input_aux_usage
!= att_state
->aux_usage
;
4006 VkImageLayout target_layout
;
4007 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
4008 !input_needs_resolve
) {
4009 /* Layout transitions before the final only help to enable sampling
4010 * as an input attachment. If the input attachment supports sampling
4011 * using the auxiliary surface, we can skip such transitions by
4012 * making the target layout one that is CCS-aware.
4014 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
4016 target_layout
= subpass
->attachments
[i
].layout
;
4019 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4020 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4022 uint32_t base_layer
, layer_count
;
4023 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4025 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4026 iview
->planes
[0].isl
.base_level
);
4028 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4029 layer_count
= fb
->layers
;
4032 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4033 iview
->planes
[0].isl
.base_level
, 1,
4034 base_layer
, layer_count
,
4035 att_state
->current_layout
, target_layout
);
4036 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4037 transition_depth_buffer(cmd_buffer
, image
,
4038 att_state
->current_layout
, target_layout
);
4039 att_state
->aux_usage
=
4040 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
4041 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
4043 att_state
->current_layout
= target_layout
;
4045 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
4046 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4048 /* Multi-planar images are not supported as attachments */
4049 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4050 assert(image
->n_planes
== 1);
4052 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
4053 uint32_t clear_layer_count
= fb
->layers
;
4055 if (att_state
->fast_clear
&&
4056 do_first_layer_clear(cmd_state
, att_state
)) {
4057 /* We only support fast-clears on the first layer */
4058 assert(iview
->planes
[0].isl
.base_level
== 0);
4059 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4061 union isl_color_value clear_color
= {};
4062 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
4063 if (iview
->image
->samples
== 1) {
4064 anv_image_ccs_op(cmd_buffer
, image
,
4065 iview
->planes
[0].isl
.format
,
4066 VK_IMAGE_ASPECT_COLOR_BIT
,
4067 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4071 anv_image_mcs_op(cmd_buffer
, image
,
4072 iview
->planes
[0].isl
.format
,
4073 VK_IMAGE_ASPECT_COLOR_BIT
,
4074 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4079 clear_layer_count
--;
4081 att_state
->pending_clear_views
&= ~1;
4083 if (att_state
->clear_color_is_zero
) {
4084 /* This image has the auxiliary buffer enabled. We can mark the
4085 * subresource as not needing a resolve because the clear color
4086 * will match what's in every RENDER_SURFACE_STATE object when
4087 * it's being used for sampling.
4089 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4090 VK_IMAGE_ASPECT_COLOR_BIT
,
4091 ANV_FAST_CLEAR_DEFAULT_VALUE
);
4093 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4094 VK_IMAGE_ASPECT_COLOR_BIT
,
4095 ANV_FAST_CLEAR_ANY
);
4099 /* From the VkFramebufferCreateInfo spec:
4101 * "If the render pass uses multiview, then layers must be one and each
4102 * attachment requires a number of layers that is greater than the
4103 * maximum bit index set in the view mask in the subpasses in which it
4106 * So if multiview is active we ignore the number of layers in the
4107 * framebuffer and instead we honor the view mask from the subpass.
4110 assert(image
->n_planes
== 1);
4111 uint32_t pending_clear_mask
=
4112 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4115 for_each_bit(layer_idx
, pending_clear_mask
) {
4117 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4119 anv_image_clear_color(cmd_buffer
, image
,
4120 VK_IMAGE_ASPECT_COLOR_BIT
,
4121 att_state
->aux_usage
,
4122 iview
->planes
[0].isl
.format
,
4123 iview
->planes
[0].isl
.swizzle
,
4124 iview
->planes
[0].isl
.base_level
,
4127 vk_to_isl_color(att_state
->clear_value
.color
));
4130 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4131 } else if (clear_layer_count
> 0) {
4132 assert(image
->n_planes
== 1);
4133 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4134 att_state
->aux_usage
,
4135 iview
->planes
[0].isl
.format
,
4136 iview
->planes
[0].isl
.swizzle
,
4137 iview
->planes
[0].isl
.base_level
,
4138 base_clear_layer
, clear_layer_count
,
4140 vk_to_isl_color(att_state
->clear_value
.color
));
4142 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
4143 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4144 if (att_state
->fast_clear
&& !is_multiview
) {
4145 /* We currently only support HiZ for single-layer images */
4146 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4147 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
4148 assert(iview
->planes
[0].isl
.base_level
== 0);
4149 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4150 assert(fb
->layers
== 1);
4153 anv_image_hiz_clear(cmd_buffer
, image
,
4154 att_state
->pending_clear_aspects
,
4155 iview
->planes
[0].isl
.base_level
,
4156 iview
->planes
[0].isl
.base_array_layer
,
4157 fb
->layers
, render_area
,
4158 att_state
->clear_value
.depthStencil
.stencil
);
4159 } else if (is_multiview
) {
4160 uint32_t pending_clear_mask
=
4161 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4164 for_each_bit(layer_idx
, pending_clear_mask
) {
4166 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4168 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4169 att_state
->pending_clear_aspects
,
4170 att_state
->aux_usage
,
4171 iview
->planes
[0].isl
.base_level
,
4174 att_state
->clear_value
.depthStencil
.depth
,
4175 att_state
->clear_value
.depthStencil
.stencil
);
4178 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4180 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4181 att_state
->pending_clear_aspects
,
4182 att_state
->aux_usage
,
4183 iview
->planes
[0].isl
.base_level
,
4184 iview
->planes
[0].isl
.base_array_layer
,
4185 fb
->layers
, render_area
,
4186 att_state
->clear_value
.depthStencil
.depth
,
4187 att_state
->clear_value
.depthStencil
.stencil
);
4190 assert(att_state
->pending_clear_aspects
== 0);
4194 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4195 image
->planes
[0].aux_surface
.isl
.size_B
> 0 &&
4196 iview
->planes
[0].isl
.base_level
== 0 &&
4197 iview
->planes
[0].isl
.base_array_layer
== 0) {
4198 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
4199 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
4200 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4201 false /* copy to ss */);
4204 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
4205 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
4206 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
4207 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4208 false /* copy to ss */);
4212 if (subpass
->attachments
[i
].usage
==
4213 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
4214 /* We assume that if we're starting a subpass, we're going to do some
4215 * rendering so we may end up with compressed data.
4217 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
4218 VK_IMAGE_ASPECT_COLOR_BIT
,
4219 att_state
->aux_usage
,
4220 iview
->planes
[0].isl
.base_level
,
4221 iview
->planes
[0].isl
.base_array_layer
,
4223 } else if (subpass
->attachments
[i
].usage
==
4224 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
4225 /* We may be writing depth or stencil so we need to mark the surface.
4226 * Unfortunately, there's no way to know at this point whether the
4227 * depth or stencil tests used will actually write to the surface.
4229 * Even though stencil may be plane 1, it always shares a base_level
4232 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
4233 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4234 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4235 VK_IMAGE_ASPECT_DEPTH_BIT
,
4236 att_state
->aux_usage
,
4237 ds_view
->base_level
,
4238 ds_view
->base_array_layer
,
4241 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4242 /* Even though stencil may be plane 1, it always shares a
4243 * base_level with depth.
4245 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4246 VK_IMAGE_ASPECT_STENCIL_BIT
,
4248 ds_view
->base_level
,
4249 ds_view
->base_array_layer
,
4254 /* If multiview is enabled, then we are only done clearing when we no
4255 * longer have pending layers to clear, or when we have processed the
4256 * last subpass that uses this attachment.
4258 if (!is_multiview
||
4259 att_state
->pending_clear_views
== 0 ||
4260 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
4261 att_state
->pending_clear_aspects
= 0;
4264 att_state
->pending_load_aspects
= 0;
4267 cmd_buffer_emit_depth_stencil(cmd_buffer
);
4270 static enum blorp_filter
4271 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
4274 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
4275 return BLORP_FILTER_SAMPLE_0
;
4276 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
4277 return BLORP_FILTER_AVERAGE
;
4278 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
4279 return BLORP_FILTER_MIN_SAMPLE
;
4280 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
4281 return BLORP_FILTER_MAX_SAMPLE
;
4283 return BLORP_FILTER_NONE
;
4288 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
4290 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4291 struct anv_subpass
*subpass
= cmd_state
->subpass
;
4292 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
4293 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4295 if (subpass
->has_color_resolve
) {
4296 /* We are about to do some MSAA resolves. We need to flush so that the
4297 * result of writes to the MSAA color attachments show up in the sampler
4298 * when we blit to the single-sampled resolve target.
4300 cmd_buffer
->state
.pending_pipe_bits
|=
4301 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4302 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
4304 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
4305 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
4306 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
4308 if (dst_att
== VK_ATTACHMENT_UNUSED
)
4311 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4312 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4314 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4315 /* From the Vulkan 1.0 spec:
4317 * If the first use of an attachment in a render pass is as a
4318 * resolve attachment, then the loadOp is effectively ignored
4319 * as the resolve is guaranteed to overwrite all pixels in the
4322 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4325 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
4326 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
4328 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4330 enum isl_aux_usage src_aux_usage
=
4331 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
4332 enum isl_aux_usage dst_aux_usage
=
4333 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
4335 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
4336 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
4338 anv_image_msaa_resolve(cmd_buffer
,
4339 src_iview
->image
, src_aux_usage
,
4340 src_iview
->planes
[0].isl
.base_level
,
4341 src_iview
->planes
[0].isl
.base_array_layer
,
4342 dst_iview
->image
, dst_aux_usage
,
4343 dst_iview
->planes
[0].isl
.base_level
,
4344 dst_iview
->planes
[0].isl
.base_array_layer
,
4345 VK_IMAGE_ASPECT_COLOR_BIT
,
4346 render_area
.offset
.x
, render_area
.offset
.y
,
4347 render_area
.offset
.x
, render_area
.offset
.y
,
4348 render_area
.extent
.width
,
4349 render_area
.extent
.height
,
4350 fb
->layers
, BLORP_FILTER_NONE
);
4354 if (subpass
->ds_resolve_attachment
) {
4355 /* We are about to do some MSAA resolves. We need to flush so that the
4356 * result of writes to the MSAA depth attachments show up in the sampler
4357 * when we blit to the single-sampled resolve target.
4359 cmd_buffer
->state
.pending_pipe_bits
|=
4360 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4361 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
4363 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
4364 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
4366 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4367 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4369 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4370 /* From the Vulkan 1.0 spec:
4372 * If the first use of an attachment in a render pass is as a
4373 * resolve attachment, then the loadOp is effectively ignored
4374 * as the resolve is guaranteed to overwrite all pixels in the
4377 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4380 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
4381 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
4383 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4385 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
4386 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4388 struct anv_attachment_state
*src_state
=
4389 &cmd_state
->attachments
[src_att
];
4390 struct anv_attachment_state
*dst_state
=
4391 &cmd_state
->attachments
[dst_att
];
4393 /* MSAA resolves sample from the source attachment. Transition the
4394 * depth attachment first to get rid of any HiZ that we may not be
4397 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
4398 src_state
->current_layout
,
4399 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4400 src_state
->aux_usage
=
4401 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
4402 VK_IMAGE_ASPECT_DEPTH_BIT
,
4403 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4404 src_state
->current_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
4406 /* MSAA resolves write to the resolve attachment as if it were any
4407 * other transfer op. Transition the resolve attachment accordingly.
4409 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
4411 /* If our render area is the entire size of the image, we're going to
4412 * blow it all away so we can claim the initial layout is UNDEFINED
4413 * and we'll get a HiZ ambiguate instead of a resolve.
4415 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
4416 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
4417 render_area
.extent
.width
== dst_iview
->extent
.width
&&
4418 render_area
.extent
.height
== dst_iview
->extent
.height
)
4419 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
4421 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
4423 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4424 dst_state
->aux_usage
=
4425 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
4426 VK_IMAGE_ASPECT_DEPTH_BIT
,
4427 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4428 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
4430 enum blorp_filter filter
=
4431 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
4433 anv_image_msaa_resolve(cmd_buffer
,
4434 src_iview
->image
, src_state
->aux_usage
,
4435 src_iview
->planes
[0].isl
.base_level
,
4436 src_iview
->planes
[0].isl
.base_array_layer
,
4437 dst_iview
->image
, dst_state
->aux_usage
,
4438 dst_iview
->planes
[0].isl
.base_level
,
4439 dst_iview
->planes
[0].isl
.base_array_layer
,
4440 VK_IMAGE_ASPECT_DEPTH_BIT
,
4441 render_area
.offset
.x
, render_area
.offset
.y
,
4442 render_area
.offset
.x
, render_area
.offset
.y
,
4443 render_area
.extent
.width
,
4444 render_area
.extent
.height
,
4445 fb
->layers
, filter
);
4448 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
4449 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4451 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
4452 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
4454 enum blorp_filter filter
=
4455 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
4457 anv_image_msaa_resolve(cmd_buffer
,
4458 src_iview
->image
, src_aux_usage
,
4459 src_iview
->planes
[0].isl
.base_level
,
4460 src_iview
->planes
[0].isl
.base_array_layer
,
4461 dst_iview
->image
, dst_aux_usage
,
4462 dst_iview
->planes
[0].isl
.base_level
,
4463 dst_iview
->planes
[0].isl
.base_array_layer
,
4464 VK_IMAGE_ASPECT_STENCIL_BIT
,
4465 render_area
.offset
.x
, render_area
.offset
.y
,
4466 render_area
.offset
.x
, render_area
.offset
.y
,
4467 render_area
.extent
.width
,
4468 render_area
.extent
.height
,
4469 fb
->layers
, filter
);
4473 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4474 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4475 if (a
== VK_ATTACHMENT_UNUSED
)
4478 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4481 assert(a
< cmd_state
->pass
->attachment_count
);
4482 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4483 struct anv_image_view
*iview
= fb
->attachments
[a
];
4484 const struct anv_image
*image
= iview
->image
;
4486 if ((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4487 image
->vk_format
!= iview
->vk_format
) {
4488 enum anv_fast_clear_type fast_clear_type
=
4489 anv_layout_to_fast_clear_type(&cmd_buffer
->device
->info
,
4490 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4491 att_state
->current_layout
);
4493 /* If any clear color was used, flush it down the aux surfaces. If we
4494 * don't do it now using the view's format we might use the clear
4495 * color incorrectly in the following resolves (for example with an
4496 * SRGB view & a UNORM image).
4498 if (fast_clear_type
!= ANV_FAST_CLEAR_NONE
) {
4499 anv_perf_warn(cmd_buffer
->device
->instance
, fb
,
4500 "Doing a partial resolve to get rid of clear color at the "
4501 "end of a renderpass due to an image/view format mismatch");
4503 uint32_t base_layer
, layer_count
;
4504 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4506 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4507 iview
->planes
[0].isl
.base_level
);
4509 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4510 layer_count
= fb
->layers
;
4513 for (uint32_t a
= 0; a
< layer_count
; a
++) {
4514 uint32_t array_layer
= base_layer
+ a
;
4515 if (image
->samples
== 1) {
4516 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
4517 iview
->planes
[0].isl
.format
,
4518 VK_IMAGE_ASPECT_COLOR_BIT
,
4519 iview
->planes
[0].isl
.base_level
,
4521 ISL_AUX_OP_PARTIAL_RESOLVE
,
4522 ANV_FAST_CLEAR_NONE
);
4524 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
4525 iview
->planes
[0].isl
.format
,
4526 VK_IMAGE_ASPECT_COLOR_BIT
,
4528 ISL_AUX_OP_PARTIAL_RESOLVE
,
4529 ANV_FAST_CLEAR_NONE
);
4535 /* Transition the image into the final layout for this render pass */
4536 VkImageLayout target_layout
=
4537 cmd_state
->pass
->attachments
[a
].final_layout
;
4539 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4540 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4542 uint32_t base_layer
, layer_count
;
4543 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4545 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4546 iview
->planes
[0].isl
.base_level
);
4548 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4549 layer_count
= fb
->layers
;
4552 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4553 iview
->planes
[0].isl
.base_level
, 1,
4554 base_layer
, layer_count
,
4555 att_state
->current_layout
, target_layout
);
4556 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4557 transition_depth_buffer(cmd_buffer
, image
,
4558 att_state
->current_layout
, target_layout
);
4562 /* Accumulate any subpass flushes that need to happen after the subpass.
4563 * Yes, they do get accumulated twice in the NextSubpass case but since
4564 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
4565 * ORing the bits in twice so it's harmless.
4567 cmd_buffer
->state
.pending_pipe_bits
|=
4568 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
4571 void genX(CmdBeginRenderPass
)(
4572 VkCommandBuffer commandBuffer
,
4573 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4574 VkSubpassContents contents
)
4576 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4577 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4578 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4580 cmd_buffer
->state
.framebuffer
= framebuffer
;
4581 cmd_buffer
->state
.pass
= pass
;
4582 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4584 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
4586 /* If we failed to setup the attachments we should not try to go further */
4587 if (result
!= VK_SUCCESS
) {
4588 assert(anv_batch_has_error(&cmd_buffer
->batch
));
4592 genX(flush_pipeline_select_3d
)(cmd_buffer
);
4594 cmd_buffer_begin_subpass(cmd_buffer
, 0);
4597 void genX(CmdBeginRenderPass2KHR
)(
4598 VkCommandBuffer commandBuffer
,
4599 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4600 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
4602 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
4603 pSubpassBeginInfo
->contents
);
4606 void genX(CmdNextSubpass
)(
4607 VkCommandBuffer commandBuffer
,
4608 VkSubpassContents contents
)
4610 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4612 if (anv_batch_has_error(&cmd_buffer
->batch
))
4615 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4617 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
4618 cmd_buffer_end_subpass(cmd_buffer
);
4619 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4622 void genX(CmdNextSubpass2KHR
)(
4623 VkCommandBuffer commandBuffer
,
4624 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
4625 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4627 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
4630 void genX(CmdEndRenderPass
)(
4631 VkCommandBuffer commandBuffer
)
4633 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4635 if (anv_batch_has_error(&cmd_buffer
->batch
))
4638 cmd_buffer_end_subpass(cmd_buffer
);
4640 cmd_buffer
->state
.hiz_enabled
= false;
4643 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
4646 /* Remove references to render pass specific state. This enables us to
4647 * detect whether or not we're in a renderpass.
4649 cmd_buffer
->state
.framebuffer
= NULL
;
4650 cmd_buffer
->state
.pass
= NULL
;
4651 cmd_buffer
->state
.subpass
= NULL
;
4654 void genX(CmdEndRenderPass2KHR
)(
4655 VkCommandBuffer commandBuffer
,
4656 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4658 genX(CmdEndRenderPass
)(commandBuffer
);
4662 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
4664 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4665 struct gen_mi_builder b
;
4666 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4668 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
4669 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
4670 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
4672 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
4673 mip
.LoadOperation
= LOAD_LOADINV
;
4674 mip
.CombineOperation
= COMBINE_SET
;
4675 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4680 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4681 void genX(CmdBeginConditionalRenderingEXT
)(
4682 VkCommandBuffer commandBuffer
,
4683 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
4685 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4686 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
4687 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4688 struct anv_address value_address
=
4689 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
4691 const bool isInverted
= pConditionalRenderingBegin
->flags
&
4692 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
4694 cmd_state
->conditional_render_enabled
= true;
4696 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4698 struct gen_mi_builder b
;
4699 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4701 /* Section 19.4 of the Vulkan 1.1.85 spec says:
4703 * If the value of the predicate in buffer memory changes
4704 * while conditional rendering is active, the rendering commands
4705 * may be discarded in an implementation-dependent way.
4706 * Some implementations may latch the value of the predicate
4707 * upon beginning conditional rendering while others
4708 * may read it before every rendering command.
4710 * So it's perfectly fine to read a value from the buffer once.
4712 struct gen_mi_value value
= gen_mi_mem32(value_address
);
4714 /* Precompute predicate result, it is necessary to support secondary
4715 * command buffers since it is unknown if conditional rendering is
4716 * inverted when populating them.
4718 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
4719 isInverted
? gen_mi_uge(&b
, gen_mi_imm(0), value
) :
4720 gen_mi_ult(&b
, gen_mi_imm(0), value
));
4723 void genX(CmdEndConditionalRenderingEXT
)(
4724 VkCommandBuffer commandBuffer
)
4726 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4727 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4729 cmd_state
->conditional_render_enabled
= false;
4733 /* Set of stage bits for which are pipelined, i.e. they get queued by the
4734 * command streamer for later execution.
4736 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
4737 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
4738 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
4739 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
4740 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
4741 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
4742 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
4743 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
4744 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
4745 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
4746 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
4747 VK_PIPELINE_STAGE_TRANSFER_BIT | \
4748 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
4749 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
4750 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
4752 void genX(CmdSetEvent
)(
4753 VkCommandBuffer commandBuffer
,
4755 VkPipelineStageFlags stageMask
)
4757 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4758 ANV_FROM_HANDLE(anv_event
, event
, _event
);
4760 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4761 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
4762 pc
.StallAtPixelScoreboard
= true;
4763 pc
.CommandStreamerStallEnable
= true;
4766 pc
.DestinationAddressType
= DAT_PPGTT
,
4767 pc
.PostSyncOperation
= WriteImmediateData
,
4768 pc
.Address
= (struct anv_address
) {
4769 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4772 pc
.ImmediateData
= VK_EVENT_SET
;
4776 void genX(CmdResetEvent
)(
4777 VkCommandBuffer commandBuffer
,
4779 VkPipelineStageFlags stageMask
)
4781 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4782 ANV_FROM_HANDLE(anv_event
, event
, _event
);
4784 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4785 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
4786 pc
.StallAtPixelScoreboard
= true;
4787 pc
.CommandStreamerStallEnable
= true;
4790 pc
.DestinationAddressType
= DAT_PPGTT
;
4791 pc
.PostSyncOperation
= WriteImmediateData
;
4792 pc
.Address
= (struct anv_address
) {
4793 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4796 pc
.ImmediateData
= VK_EVENT_RESET
;
4800 void genX(CmdWaitEvents
)(
4801 VkCommandBuffer commandBuffer
,
4802 uint32_t eventCount
,
4803 const VkEvent
* pEvents
,
4804 VkPipelineStageFlags srcStageMask
,
4805 VkPipelineStageFlags destStageMask
,
4806 uint32_t memoryBarrierCount
,
4807 const VkMemoryBarrier
* pMemoryBarriers
,
4808 uint32_t bufferMemoryBarrierCount
,
4809 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
4810 uint32_t imageMemoryBarrierCount
,
4811 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
4814 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4816 for (uint32_t i
= 0; i
< eventCount
; i
++) {
4817 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
4819 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
4820 sem
.WaitMode
= PollingMode
,
4821 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
4822 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
4823 sem
.SemaphoreAddress
= (struct anv_address
) {
4824 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4830 anv_finishme("Implement events on gen7");
4833 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
4834 false, /* byRegion */
4835 memoryBarrierCount
, pMemoryBarriers
,
4836 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
4837 imageMemoryBarrierCount
, pImageMemoryBarriers
);