2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_l3_config.h"
33 #include "genxml/gen_macros.h"
34 #include "genxml/genX_pack.h"
36 /* We reserve GPR 14 and 15 for conditional rendering */
37 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
38 #define __gen_get_batch_dwords anv_batch_emit_dwords
39 #define __gen_address_offset anv_address_add
40 #include "common/gen_mi_builder.h"
43 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
45 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
46 lri
.RegisterOffset
= reg
;
52 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
54 struct anv_device
*device
= cmd_buffer
->device
;
56 /* If we are emitting a new state base address we probably need to re-emit
59 cmd_buffer
->state
.descriptors_dirty
|= ~0;
61 /* Emit a render target cache flush.
63 * This isn't documented anywhere in the PRM. However, it seems to be
64 * necessary prior to changing the surface state base adress. Without
65 * this, we get GPU hangs when using multi-level command buffers which
66 * clear depth, reset state base address, and then go render stuff.
68 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
69 pc
.DCFlushEnable
= true;
70 pc
.RenderTargetCacheFlushEnable
= true;
71 pc
.CommandStreamerStallEnable
= true;
74 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
75 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
76 sba
.GeneralStateMOCS
= GENX(MOCS
);
77 sba
.GeneralStateBaseAddressModifyEnable
= true;
79 sba
.StatelessDataPortAccessMOCS
= GENX(MOCS
);
81 sba
.SurfaceStateBaseAddress
=
82 anv_cmd_buffer_surface_base_address(cmd_buffer
);
83 sba
.SurfaceStateMOCS
= GENX(MOCS
);
84 sba
.SurfaceStateBaseAddressModifyEnable
= true;
86 sba
.DynamicStateBaseAddress
=
87 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
88 sba
.DynamicStateMOCS
= GENX(MOCS
);
89 sba
.DynamicStateBaseAddressModifyEnable
= true;
91 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
92 sba
.IndirectObjectMOCS
= GENX(MOCS
);
93 sba
.IndirectObjectBaseAddressModifyEnable
= true;
95 sba
.InstructionBaseAddress
=
96 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
97 sba
.InstructionMOCS
= GENX(MOCS
);
98 sba
.InstructionBaseAddressModifyEnable
= true;
101 /* Broadwell requires that we specify a buffer size for a bunch of
102 * these fields. However, since we will be growing the BO's live, we
103 * just set them all to the maximum.
105 sba
.GeneralStateBufferSize
= 0xfffff;
106 sba
.GeneralStateBufferSizeModifyEnable
= true;
107 sba
.DynamicStateBufferSize
= 0xfffff;
108 sba
.DynamicStateBufferSizeModifyEnable
= true;
109 sba
.IndirectObjectBufferSize
= 0xfffff;
110 sba
.IndirectObjectBufferSizeModifyEnable
= true;
111 sba
.InstructionBufferSize
= 0xfffff;
112 sba
.InstructionBuffersizeModifyEnable
= true;
114 /* On gen7, we have upper bounds instead. According to the docs,
115 * setting an upper bound of zero means that no bounds checking is
116 * performed so, in theory, we should be able to leave them zero.
117 * However, border color is broken and the GPU bounds-checks anyway.
118 * To avoid this and other potential problems, we may as well set it
121 sba
.GeneralStateAccessUpperBound
=
122 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
123 sba
.GeneralStateAccessUpperBoundModifyEnable
= true;
124 sba
.DynamicStateAccessUpperBound
=
125 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
126 sba
.DynamicStateAccessUpperBoundModifyEnable
= true;
127 sba
.InstructionAccessUpperBound
=
128 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
129 sba
.InstructionAccessUpperBoundModifyEnable
= true;
132 if (cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
) {
133 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) {
134 .bo
= device
->surface_state_pool
.block_pool
.bo
,
137 sba
.BindlessSurfaceStateSize
= (1 << 20) - 1;
139 sba
.BindlessSurfaceStateBaseAddress
= ANV_NULL_ADDRESS
;
140 sba
.BindlessSurfaceStateSize
= 0;
142 sba
.BindlessSurfaceStateMOCS
= GENX(MOCS
);
143 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
146 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
147 sba
.BindlessSamplerStateMOCS
= GENX(MOCS
);
148 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
149 sba
.BindlessSamplerStateBufferSize
= 0;
153 /* After re-setting the surface state base address, we have to do some
154 * cache flusing so that the sampler engine will pick up the new
155 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
156 * Shared Function > 3D Sampler > State > State Caching (page 96):
158 * Coherency with system memory in the state cache, like the texture
159 * cache is handled partially by software. It is expected that the
160 * command stream or shader will issue Cache Flush operation or
161 * Cache_Flush sampler message to ensure that the L1 cache remains
162 * coherent with system memory.
166 * Whenever the value of the Dynamic_State_Base_Addr,
167 * Surface_State_Base_Addr are altered, the L1 state cache must be
168 * invalidated to ensure the new surface or sampler state is fetched
169 * from system memory.
171 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
172 * which, according the PIPE_CONTROL instruction documentation in the
175 * Setting this bit is independent of any other bit in this packet.
176 * This bit controls the invalidation of the L1 and L2 state caches
177 * at the top of the pipe i.e. at the parsing time.
179 * Unfortunately, experimentation seems to indicate that state cache
180 * invalidation through a PIPE_CONTROL does nothing whatsoever in
181 * regards to surface state and binding tables. In stead, it seems that
182 * invalidating the texture cache is what is actually needed.
184 * XXX: As far as we have been able to determine through
185 * experimentation, shows that flush the texture cache appears to be
186 * sufficient. The theory here is that all of the sampling/rendering
187 * units cache the binding table in the texture cache. However, we have
188 * yet to be able to actually confirm this.
190 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
191 pc
.TextureCacheInvalidationEnable
= true;
192 pc
.ConstantCacheInvalidationEnable
= true;
193 pc
.StateCacheInvalidationEnable
= true;
198 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
199 struct anv_state state
, struct anv_address addr
)
201 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
204 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
205 state
.offset
+ isl_dev
->ss
.addr_offset
,
206 addr
.bo
, addr
.offset
);
207 if (result
!= VK_SUCCESS
)
208 anv_batch_set_error(&cmd_buffer
->batch
, result
);
212 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
213 struct anv_surface_state state
)
215 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
217 assert(!anv_address_is_null(state
.address
));
218 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
220 if (!anv_address_is_null(state
.aux_address
)) {
222 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
223 &cmd_buffer
->pool
->alloc
,
224 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
225 state
.aux_address
.bo
, state
.aux_address
.offset
);
226 if (result
!= VK_SUCCESS
)
227 anv_batch_set_error(&cmd_buffer
->batch
, result
);
230 if (!anv_address_is_null(state
.clear_address
)) {
232 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
233 &cmd_buffer
->pool
->alloc
,
235 isl_dev
->ss
.clear_color_state_offset
,
236 state
.clear_address
.bo
, state
.clear_address
.offset
);
237 if (result
!= VK_SUCCESS
)
238 anv_batch_set_error(&cmd_buffer
->batch
, result
);
243 color_attachment_compute_aux_usage(struct anv_device
* device
,
244 struct anv_cmd_state
* cmd_state
,
245 uint32_t att
, VkRect2D render_area
,
246 union isl_color_value
*fast_clear_color
)
248 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
249 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
251 assert(iview
->n_planes
== 1);
253 if (iview
->planes
[0].isl
.base_array_layer
>=
254 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
255 iview
->planes
[0].isl
.base_level
)) {
256 /* There is no aux buffer which corresponds to the level and layer(s)
259 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
260 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
261 att_state
->fast_clear
= false;
265 att_state
->aux_usage
=
266 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
267 VK_IMAGE_ASPECT_COLOR_BIT
,
268 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
270 /* If we don't have aux, then we should have returned early in the layer
271 * check above. If we got here, we must have something.
273 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
275 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
276 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
277 att_state
->input_aux_usage
= att_state
->aux_usage
;
279 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
281 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
282 * setting is only allowed if Surface Format supported for Fast
283 * Clear. In addition, if the surface is bound to the sampling
284 * engine, Surface Format must be supported for Render Target
285 * Compression for surfaces bound to the sampling engine."
287 * In other words, we can only sample from a fast-cleared image if it
288 * also supports color compression.
290 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
291 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
293 /* While fast-clear resolves and partial resolves are fairly cheap in the
294 * case where you render to most of the pixels, full resolves are not
295 * because they potentially involve reading and writing the entire
296 * framebuffer. If we can't texture with CCS_E, we should leave it off and
297 * limit ourselves to fast clears.
299 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
300 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
301 anv_perf_warn(device
->instance
, iview
->image
,
302 "Not temporarily enabling CCS_E.");
305 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
309 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
310 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
312 union isl_color_value clear_color
= {};
313 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
315 att_state
->clear_color_is_zero_one
=
316 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
317 att_state
->clear_color_is_zero
=
318 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
320 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
321 /* Start by getting the fast clear type. We use the first subpass
322 * layout here because we don't want to fast-clear if the first subpass
323 * to use the attachment can't handle fast-clears.
325 enum anv_fast_clear_type fast_clear_type
=
326 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
327 VK_IMAGE_ASPECT_COLOR_BIT
,
328 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
329 switch (fast_clear_type
) {
330 case ANV_FAST_CLEAR_NONE
:
331 att_state
->fast_clear
= false;
333 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
334 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
336 case ANV_FAST_CLEAR_ANY
:
337 att_state
->fast_clear
= true;
341 /* Potentially, we could do partial fast-clears but doing so has crazy
342 * alignment restrictions. It's easier to just restrict to full size
343 * fast clears for now.
345 if (render_area
.offset
.x
!= 0 ||
346 render_area
.offset
.y
!= 0 ||
347 render_area
.extent
.width
!= iview
->extent
.width
||
348 render_area
.extent
.height
!= iview
->extent
.height
)
349 att_state
->fast_clear
= false;
351 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
352 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
353 att_state
->fast_clear
= false;
355 /* We only allow fast clears to the first slice of an image (level 0,
356 * layer 0) and only for the entire slice. This guarantees us that, at
357 * any given time, there is only one clear color on any given image at
358 * any given time. At the time of our testing (Jan 17, 2018), there
359 * were no known applications which would benefit from fast-clearing
360 * more than just the first slice.
362 if (att_state
->fast_clear
&&
363 (iview
->planes
[0].isl
.base_level
> 0 ||
364 iview
->planes
[0].isl
.base_array_layer
> 0)) {
365 anv_perf_warn(device
->instance
, iview
->image
,
366 "Rendering with multi-lod or multi-layer framebuffer "
367 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
368 "baseArrayLayer > 0. Not fast clearing.");
369 att_state
->fast_clear
= false;
370 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
371 anv_perf_warn(device
->instance
, iview
->image
,
372 "Rendering to a multi-layer framebuffer with "
373 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
376 if (att_state
->fast_clear
)
377 *fast_clear_color
= clear_color
;
379 att_state
->fast_clear
= false;
384 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
385 struct anv_cmd_state
*cmd_state
,
386 uint32_t att
, VkRect2D render_area
)
388 struct anv_render_pass_attachment
*pass_att
=
389 &cmd_state
->pass
->attachments
[att
];
390 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
391 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
393 /* These will be initialized after the first subpass transition. */
394 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
395 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
398 /* We don't do any HiZ or depth fast-clears on gen7 yet */
399 att_state
->fast_clear
= false;
403 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
404 /* If we're just clearing stencil, we can always HiZ clear */
405 att_state
->fast_clear
= true;
409 /* Default to false for now */
410 att_state
->fast_clear
= false;
412 /* We must have depth in order to have HiZ */
413 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
416 const enum isl_aux_usage first_subpass_aux_usage
=
417 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
418 VK_IMAGE_ASPECT_DEPTH_BIT
,
419 pass_att
->first_subpass_layout
);
420 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
423 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
424 iview
->planes
[0].isl
.format
,
425 iview
->image
->samples
,
426 render_area
.offset
.x
,
427 render_area
.offset
.y
,
428 render_area
.offset
.x
+
429 render_area
.extent
.width
,
430 render_area
.offset
.y
+
431 render_area
.extent
.height
))
434 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
437 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
438 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
439 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
440 * only supports returning 0.0f. Gens prior to gen8 do not support this
446 /* If we got here, then we can fast clear */
447 att_state
->fast_clear
= true;
451 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
453 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
456 /* We only allocate input attachment states for color surfaces. Compression
457 * is not yet enabled for depth textures and stencil doesn't allow
458 * compression so we can just use the texture surface state from the view.
460 return vk_format_is_color(att
->format
);
463 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
464 * the initial layout is undefined, the HiZ buffer and depth buffer will
465 * represent the same data at the end of this operation.
468 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
469 const struct anv_image
*image
,
470 VkImageLayout initial_layout
,
471 VkImageLayout final_layout
)
473 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
474 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
475 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
476 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
477 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
478 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
480 enum isl_aux_op hiz_op
;
481 if (hiz_enabled
&& !enable_hiz
) {
482 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
483 } else if (!hiz_enabled
&& enable_hiz
) {
484 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
486 assert(hiz_enabled
== enable_hiz
);
487 /* If the same buffer will be used, no resolves are necessary. */
488 hiz_op
= ISL_AUX_OP_NONE
;
491 if (hiz_op
!= ISL_AUX_OP_NONE
)
492 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
497 vk_image_layout_stencil_write_optimal(VkImageLayout layout
)
499 return layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
500 layout
== VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
;
503 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
504 * the initial layout is undefined, the HiZ buffer and depth buffer will
505 * represent the same data at the end of this operation.
508 transition_stencil_buffer(struct anv_cmd_buffer
*cmd_buffer
,
509 const struct anv_image
*image
,
510 uint32_t base_level
, uint32_t level_count
,
511 uint32_t base_layer
, uint32_t layer_count
,
512 VkImageLayout initial_layout
,
513 VkImageLayout final_layout
)
516 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
517 VK_IMAGE_ASPECT_STENCIL_BIT
);
519 /* On gen7, we have to store a texturable version of the stencil buffer in
520 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
521 * forth at strategic points. Stencil writes are only allowed in three
524 * - VK_IMAGE_LAYOUT_GENERAL
525 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
526 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
527 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
529 * For general, we have no nice opportunity to transition so we do the copy
530 * to the shadow unconditionally at the end of the subpass. For transfer
531 * destinations, we can update it as part of the transfer op. For the
532 * other two, we delay the copy until a transition into some other layout.
534 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
535 vk_image_layout_stencil_write_optimal(initial_layout
) &&
536 !vk_image_layout_stencil_write_optimal(final_layout
)) {
537 anv_image_copy_to_shadow(cmd_buffer
, image
,
538 VK_IMAGE_ASPECT_STENCIL_BIT
,
539 base_level
, level_count
,
540 base_layer
, layer_count
);
542 #endif /* GEN_GEN == 7 */
545 #define MI_PREDICATE_SRC0 0x2400
546 #define MI_PREDICATE_SRC1 0x2408
547 #define MI_PREDICATE_RESULT 0x2418
550 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
551 const struct anv_image
*image
,
552 VkImageAspectFlagBits aspect
,
554 uint32_t base_layer
, uint32_t layer_count
,
557 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
559 /* We only have compression tracking for CCS_E */
560 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
563 for (uint32_t a
= 0; a
< layer_count
; a
++) {
564 uint32_t layer
= base_layer
+ a
;
565 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
566 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
569 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
575 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
576 const struct anv_image
*image
,
577 VkImageAspectFlagBits aspect
,
578 enum anv_fast_clear_type fast_clear
)
580 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
581 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
583 sdi
.ImmediateData
= fast_clear
;
586 /* Whenever we have fast-clear, we consider that slice to be compressed.
587 * This makes building predicates much easier.
589 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
590 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
593 #if GEN_IS_HASWELL || GEN_GEN >= 8
594 static inline uint32_t
595 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
597 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
599 .Operand1
= operand1
,
600 .Operand2
= operand2
,
604 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
610 /* This is only really practical on haswell and above because it requires
611 * MI math in order to get it correct.
613 #if GEN_GEN >= 8 || GEN_IS_HASWELL
615 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
616 const struct anv_image
*image
,
617 VkImageAspectFlagBits aspect
,
618 uint32_t level
, uint32_t array_layer
,
619 enum isl_aux_op resolve_op
,
620 enum anv_fast_clear_type fast_clear_supported
)
622 struct gen_mi_builder b
;
623 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
625 const struct gen_mi_value fast_clear_type
=
626 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
629 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
630 /* In this case, we're doing a full resolve which means we want the
631 * resolve to happen if any compression (including fast-clears) is
634 * In order to simplify the logic a bit, we make the assumption that,
635 * if the first slice has been fast-cleared, it is also marked as
636 * compressed. See also set_image_fast_clear_state.
638 const struct gen_mi_value compression_state
=
639 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer
->device
,
641 level
, array_layer
));
642 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
644 gen_mi_store(&b
, compression_state
, gen_mi_imm(0));
646 if (level
== 0 && array_layer
== 0) {
647 /* If the predicate is true, we want to write 0 to the fast clear type
648 * and, if it's false, leave it alone. We can do this by writing
650 * clear_type = clear_type & ~predicate;
652 struct gen_mi_value new_fast_clear_type
=
653 gen_mi_iand(&b
, fast_clear_type
,
654 gen_mi_inot(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
)));
655 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
657 } else if (level
== 0 && array_layer
== 0) {
658 /* In this case, we are doing a partial resolve to get rid of fast-clear
659 * colors. We don't care about the compression state but we do care
660 * about how much fast clear is allowed by the final layout.
662 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
663 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
665 /* We need to compute (fast_clear_supported < image->fast_clear) */
666 struct gen_mi_value pred
=
667 gen_mi_ult(&b
, gen_mi_imm(fast_clear_supported
), fast_clear_type
);
668 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
669 gen_mi_value_ref(&b
, pred
));
671 /* If the predicate is true, we want to write 0 to the fast clear type
672 * and, if it's false, leave it alone. We can do this by writing
674 * clear_type = clear_type & ~predicate;
676 struct gen_mi_value new_fast_clear_type
=
677 gen_mi_iand(&b
, fast_clear_type
, gen_mi_inot(&b
, pred
));
678 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
680 /* In this case, we're trying to do a partial resolve on a slice that
681 * doesn't have clear color. There's nothing to do.
683 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
687 /* Set src1 to 0 and use a != condition */
688 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
690 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
691 mip
.LoadOperation
= LOAD_LOADINV
;
692 mip
.CombineOperation
= COMBINE_SET
;
693 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
696 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
700 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
701 const struct anv_image
*image
,
702 VkImageAspectFlagBits aspect
,
703 uint32_t level
, uint32_t array_layer
,
704 enum isl_aux_op resolve_op
,
705 enum anv_fast_clear_type fast_clear_supported
)
707 struct gen_mi_builder b
;
708 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
710 struct gen_mi_value fast_clear_type_mem
=
711 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
714 /* This only works for partial resolves and only when the clear color is
715 * all or nothing. On the upside, this emits less command streamer code
716 * and works on Ivybridge and Bay Trail.
718 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
719 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
721 /* We don't support fast clears on anything other than the first slice. */
722 if (level
> 0 || array_layer
> 0)
725 /* On gen8, we don't have a concept of default clear colors because we
726 * can't sample from CCS surfaces. It's enough to just load the fast clear
727 * state into the predicate register.
729 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), fast_clear_type_mem
);
730 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
731 gen_mi_store(&b
, fast_clear_type_mem
, gen_mi_imm(0));
733 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
734 mip
.LoadOperation
= LOAD_LOADINV
;
735 mip
.CombineOperation
= COMBINE_SET
;
736 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
739 #endif /* GEN_GEN <= 8 */
742 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
743 const struct anv_image
*image
,
744 enum isl_format format
,
745 VkImageAspectFlagBits aspect
,
746 uint32_t level
, uint32_t array_layer
,
747 enum isl_aux_op resolve_op
,
748 enum anv_fast_clear_type fast_clear_supported
)
750 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
753 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
754 aspect
, level
, array_layer
,
755 resolve_op
, fast_clear_supported
);
756 #else /* GEN_GEN <= 8 */
757 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
758 aspect
, level
, array_layer
,
759 resolve_op
, fast_clear_supported
);
762 /* CCS_D only supports full resolves and BLORP will assert on us if we try
763 * to do a partial resolve on a CCS_D surface.
765 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
766 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
767 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
769 anv_image_ccs_op(cmd_buffer
, image
, format
, aspect
, level
,
770 array_layer
, 1, resolve_op
, NULL
, true);
774 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
775 const struct anv_image
*image
,
776 enum isl_format format
,
777 VkImageAspectFlagBits aspect
,
778 uint32_t array_layer
,
779 enum isl_aux_op resolve_op
,
780 enum anv_fast_clear_type fast_clear_supported
)
782 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
783 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
785 #if GEN_GEN >= 8 || GEN_IS_HASWELL
786 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
787 aspect
, 0, array_layer
,
788 resolve_op
, fast_clear_supported
);
790 anv_image_mcs_op(cmd_buffer
, image
, format
, aspect
,
791 array_layer
, 1, resolve_op
, NULL
, true);
793 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
798 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
799 const struct anv_image
*image
,
800 VkImageAspectFlagBits aspect
,
801 enum isl_aux_usage aux_usage
,
804 uint32_t layer_count
)
806 /* The aspect must be exactly one of the image aspects. */
807 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
809 /* The only compression types with more than just fast-clears are MCS,
810 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
811 * track the current fast-clear and compression state. This leaves us
812 * with just MCS and CCS_E.
814 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
815 aux_usage
!= ISL_AUX_USAGE_MCS
)
818 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
819 level
, base_layer
, layer_count
, true);
823 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
824 const struct anv_image
*image
,
825 VkImageAspectFlagBits aspect
)
827 assert(cmd_buffer
&& image
);
828 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
830 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
831 ANV_FAST_CLEAR_NONE
);
833 /* Initialize the struct fields that are accessed for fast-clears so that
834 * the HW restrictions on the field values are satisfied.
836 struct anv_address addr
=
837 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
840 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
841 const unsigned num_dwords
= GEN_GEN
>= 10 ?
842 isl_dev
->ss
.clear_color_state_size
/ 4 :
843 isl_dev
->ss
.clear_value_size
/ 4;
844 for (unsigned i
= 0; i
< num_dwords
; i
++) {
845 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
847 sdi
.Address
.offset
+= i
* 4;
848 sdi
.ImmediateData
= 0;
852 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
854 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
855 /* Pre-SKL, the dword containing the clear values also contains
856 * other fields, so we need to initialize those fields to match the
857 * values that would be in a color attachment.
859 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
860 ISL_CHANNEL_SELECT_GREEN
<< 22 |
861 ISL_CHANNEL_SELECT_BLUE
<< 19 |
862 ISL_CHANNEL_SELECT_ALPHA
<< 16;
863 } else if (GEN_GEN
== 7) {
864 /* On IVB, the dword containing the clear values also contains
865 * other fields that must be zero or can be zero.
867 sdi
.ImmediateData
= 0;
873 /* Copy the fast-clear value dword(s) between a surface state object and an
874 * image's fast clear state buffer.
877 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
878 struct anv_state surface_state
,
879 const struct anv_image
*image
,
880 VkImageAspectFlagBits aspect
,
881 bool copy_from_surface_state
)
883 assert(cmd_buffer
&& image
);
884 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
886 struct anv_address ss_clear_addr
= {
887 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
888 .offset
= surface_state
.offset
+
889 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
891 const struct anv_address entry_addr
=
892 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
893 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
896 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
897 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
898 * in-flight when they are issued even if the memory touched is not
899 * currently active for rendering. The weird bit is that it is not the
900 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
901 * rendering hangs such that the next stalling command after the
902 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
904 * It is unclear exactly why this hang occurs. Both MI commands come with
905 * warnings about the 3D pipeline but that doesn't seem to fully explain
906 * it. My (Jason's) best theory is that it has something to do with the
907 * fact that we're using a GPU state register as our temporary and that
908 * something with reading/writing it is causing problems.
910 * In order to work around this issue, we emit a PIPE_CONTROL with the
911 * command streamer stall bit set.
913 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
914 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
917 struct gen_mi_builder b
;
918 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
920 if (copy_from_surface_state
) {
921 gen_mi_memcpy(&b
, entry_addr
, ss_clear_addr
, copy_size
);
923 gen_mi_memcpy(&b
, ss_clear_addr
, entry_addr
, copy_size
);
925 /* Updating a surface state object may require that the state cache be
926 * invalidated. From the SKL PRM, Shared Functions -> State -> State
929 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
930 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
931 * modified [...], the L1 state cache must be invalidated to ensure
932 * the new surface or sampler state is fetched from system memory.
934 * In testing, SKL doesn't actually seem to need this, but HSW does.
936 cmd_buffer
->state
.pending_pipe_bits
|=
937 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
942 * @brief Transitions a color buffer from one layout to another.
944 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
947 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
948 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
949 * this represents the maximum layers to transition at each
950 * specified miplevel.
953 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
954 const struct anv_image
*image
,
955 VkImageAspectFlagBits aspect
,
956 const uint32_t base_level
, uint32_t level_count
,
957 uint32_t base_layer
, uint32_t layer_count
,
958 VkImageLayout initial_layout
,
959 VkImageLayout final_layout
)
961 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
962 /* Validate the inputs. */
964 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
965 /* These values aren't supported for simplicity's sake. */
966 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
967 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
968 /* Ensure the subresource range is valid. */
969 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
970 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
971 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
972 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
973 assert(last_level_num
<= image
->levels
);
974 /* The spec disallows these final layouts. */
975 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
976 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
978 /* No work is necessary if the layout stays the same or if this subresource
979 * range lacks auxiliary data.
981 if (initial_layout
== final_layout
)
984 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
986 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
987 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
988 /* This surface is a linear compressed image with a tiled shadow surface
989 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
990 * we need to ensure the shadow copy is up-to-date.
992 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
993 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
994 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
995 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
997 anv_image_copy_to_shadow(cmd_buffer
, image
,
998 VK_IMAGE_ASPECT_COLOR_BIT
,
999 base_level
, level_count
,
1000 base_layer
, layer_count
);
1003 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
1006 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
1008 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
1009 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
1010 /* A subresource in the undefined layout may have been aliased and
1011 * populated with any arrangement of bits. Therefore, we must initialize
1012 * the related aux buffer and clear buffer entry with desirable values.
1013 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
1014 * images with VK_IMAGE_TILING_OPTIMAL.
1016 * Initialize the relevant clear buffer entries.
1018 if (base_level
== 0 && base_layer
== 0)
1019 init_fast_clear_color(cmd_buffer
, image
, aspect
);
1021 /* Initialize the aux buffers to enable correct rendering. In order to
1022 * ensure that things such as storage images work correctly, aux buffers
1023 * need to be initialized to valid data.
1025 * Having an aux buffer with invalid data is a problem for two reasons:
1027 * 1) Having an invalid value in the buffer can confuse the hardware.
1028 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1029 * invalid and leads to the hardware doing strange things. It
1030 * doesn't hang as far as we can tell but rendering corruption can
1033 * 2) If this transition is into the GENERAL layout and we then use the
1034 * image as a storage image, then we must have the aux buffer in the
1035 * pass-through state so that, if we then go to texture from the
1036 * image, we get the results of our storage image writes and not the
1037 * fast clear color or other random data.
1039 * For CCS both of the problems above are real demonstrable issues. In
1040 * that case, the only thing we can do is to perform an ambiguate to
1041 * transition the aux surface into the pass-through state.
1043 * For MCS, (2) is never an issue because we don't support multisampled
1044 * storage images. In theory, issue (1) is a problem with MCS but we've
1045 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1046 * theory, be interpreted as something but we don't know that all bit
1047 * patterns are actually valid. For 2x and 8x, you could easily end up
1048 * with the MCS referring to an invalid plane because not all bits of
1049 * the MCS value are actually used. Even though we've never seen issues
1050 * in the wild, it's best to play it safe and initialize the MCS. We
1051 * can use a fast-clear for MCS because we only ever touch from render
1052 * and texture (no image load store).
1054 if (image
->samples
== 1) {
1055 for (uint32_t l
= 0; l
< level_count
; l
++) {
1056 const uint32_t level
= base_level
+ l
;
1058 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1059 if (base_layer
>= aux_layers
)
1060 break; /* We will only get fewer layers as level increases */
1061 uint32_t level_layer_count
=
1062 MIN2(layer_count
, aux_layers
- base_layer
);
1064 anv_image_ccs_op(cmd_buffer
, image
,
1065 image
->planes
[plane
].surface
.isl
.format
,
1066 aspect
, level
, base_layer
, level_layer_count
,
1067 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1069 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1070 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1071 level
, base_layer
, level_layer_count
,
1076 if (image
->samples
== 4 || image
->samples
== 16) {
1077 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1078 "Doing a potentially unnecessary fast-clear to "
1079 "define an MCS buffer.");
1082 assert(base_level
== 0 && level_count
== 1);
1083 anv_image_mcs_op(cmd_buffer
, image
,
1084 image
->planes
[plane
].surface
.isl
.format
,
1085 aspect
, base_layer
, layer_count
,
1086 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1091 const enum isl_aux_usage initial_aux_usage
=
1092 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1093 const enum isl_aux_usage final_aux_usage
=
1094 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1096 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1097 * We can handle transitions between CCS_D/E to and from NONE. What we
1098 * don't yet handle is switching between CCS_E and CCS_D within a given
1099 * image. Doing so in a performant way requires more detailed aux state
1100 * tracking such as what is done in i965. For now, just assume that we
1101 * only have one type of compression.
1103 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1104 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1105 initial_aux_usage
== final_aux_usage
);
1107 /* If initial aux usage is NONE, there is nothing to resolve */
1108 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1111 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1113 /* If the initial layout supports more fast clear than the final layout
1114 * then we need at least a partial resolve.
1116 const enum anv_fast_clear_type initial_fast_clear
=
1117 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1118 const enum anv_fast_clear_type final_fast_clear
=
1119 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1120 if (final_fast_clear
< initial_fast_clear
)
1121 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1123 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1124 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1125 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1127 if (resolve_op
== ISL_AUX_OP_NONE
)
1130 /* Perform a resolve to synchronize data between the main and aux buffer.
1131 * Before we begin, we must satisfy the cache flushing requirement specified
1132 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1134 * Any transition from any value in {Clear, Render, Resolve} to a
1135 * different value in {Clear, Render, Resolve} requires end of pipe
1138 * We perform a flush of the write cache before and after the clear and
1139 * resolve operations to meet this requirement.
1141 * Unlike other drawing, fast clear operations are not properly
1142 * synchronized. The first PIPE_CONTROL here likely ensures that the
1143 * contents of the previous render or clear hit the render target before we
1144 * resolve and the second likely ensures that the resolve is complete before
1145 * we do any more rendering or clearing.
1147 cmd_buffer
->state
.pending_pipe_bits
|=
1148 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1150 for (uint32_t l
= 0; l
< level_count
; l
++) {
1151 uint32_t level
= base_level
+ l
;
1153 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1154 if (base_layer
>= aux_layers
)
1155 break; /* We will only get fewer layers as level increases */
1156 uint32_t level_layer_count
=
1157 MIN2(layer_count
, aux_layers
- base_layer
);
1159 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1160 uint32_t array_layer
= base_layer
+ a
;
1161 if (image
->samples
== 1) {
1162 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1163 image
->planes
[plane
].surface
.isl
.format
,
1164 aspect
, level
, array_layer
, resolve_op
,
1167 /* We only support fast-clear on the first layer so partial
1168 * resolves should not be used on other layers as they will use
1169 * the clear color stored in memory that is only valid for layer0.
1171 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1175 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1176 image
->planes
[plane
].surface
.isl
.format
,
1177 aspect
, array_layer
, resolve_op
,
1183 cmd_buffer
->state
.pending_pipe_bits
|=
1184 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1188 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1191 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1192 struct anv_render_pass
*pass
,
1193 const VkRenderPassBeginInfo
*begin
)
1195 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1196 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1198 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1200 if (pass
->attachment_count
> 0) {
1201 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1202 pass
->attachment_count
*
1203 sizeof(state
->attachments
[0]),
1204 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1205 if (state
->attachments
== NULL
) {
1206 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1207 return anv_batch_set_error(&cmd_buffer
->batch
,
1208 VK_ERROR_OUT_OF_HOST_MEMORY
);
1211 state
->attachments
= NULL
;
1214 /* Reserve one for the NULL state. */
1215 unsigned num_states
= 1;
1216 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1217 if (vk_format_is_color(pass
->attachments
[i
].format
))
1220 if (need_input_attachment_state(&pass
->attachments
[i
]))
1224 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1225 state
->render_pass_states
=
1226 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1227 num_states
* ss_stride
, isl_dev
->ss
.align
);
1229 struct anv_state next_state
= state
->render_pass_states
;
1230 next_state
.alloc_size
= isl_dev
->ss
.size
;
1232 state
->null_surface_state
= next_state
;
1233 next_state
.offset
+= ss_stride
;
1234 next_state
.map
+= ss_stride
;
1236 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1237 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1238 state
->attachments
[i
].color
.state
= next_state
;
1239 next_state
.offset
+= ss_stride
;
1240 next_state
.map
+= ss_stride
;
1243 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1244 state
->attachments
[i
].input
.state
= next_state
;
1245 next_state
.offset
+= ss_stride
;
1246 next_state
.map
+= ss_stride
;
1249 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1250 state
->render_pass_states
.alloc_size
);
1253 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1254 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1256 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1257 isl_extent3d(framebuffer
->width
,
1258 framebuffer
->height
,
1259 framebuffer
->layers
));
1261 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1262 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1263 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1264 VkImageAspectFlags clear_aspects
= 0;
1265 VkImageAspectFlags load_aspects
= 0;
1267 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1268 /* color attachment */
1269 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1270 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1271 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1272 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1275 /* depthstencil attachment */
1276 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1277 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1278 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1279 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1280 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1283 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1284 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1285 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1286 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1287 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1292 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1293 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1294 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1296 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1298 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1299 anv_assert(iview
->vk_format
== att
->format
);
1301 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1302 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1304 union isl_color_value clear_color
= { .u32
= { 0, } };
1305 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1306 anv_assert(iview
->n_planes
== 1);
1307 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1308 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1309 state
, i
, begin
->renderArea
,
1312 anv_image_fill_surface_state(cmd_buffer
->device
,
1314 VK_IMAGE_ASPECT_COLOR_BIT
,
1315 &iview
->planes
[0].isl
,
1316 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1317 state
->attachments
[i
].aux_usage
,
1320 &state
->attachments
[i
].color
,
1323 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1325 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1330 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1331 anv_image_fill_surface_state(cmd_buffer
->device
,
1333 VK_IMAGE_ASPECT_COLOR_BIT
,
1334 &iview
->planes
[0].isl
,
1335 ISL_SURF_USAGE_TEXTURE_BIT
,
1336 state
->attachments
[i
].input_aux_usage
,
1339 &state
->attachments
[i
].input
,
1342 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1351 genX(BeginCommandBuffer
)(
1352 VkCommandBuffer commandBuffer
,
1353 const VkCommandBufferBeginInfo
* pBeginInfo
)
1355 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1357 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1358 * command buffer's state. Otherwise, we must *reset* its state. In both
1359 * cases we reset it.
1361 * From the Vulkan 1.0 spec:
1363 * If a command buffer is in the executable state and the command buffer
1364 * was allocated from a command pool with the
1365 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1366 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1367 * as if vkResetCommandBuffer had been called with
1368 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1369 * the command buffer in the recording state.
1371 anv_cmd_buffer_reset(cmd_buffer
);
1373 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1375 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1376 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1378 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1380 /* We sometimes store vertex data in the dynamic state buffer for blorp
1381 * operations and our dynamic state stream may re-use data from previous
1382 * command buffers. In order to prevent stale cache data, we flush the VF
1383 * cache. We could do this on every blorp call but that's not really
1384 * needed as all of the data will get written by the CPU prior to the GPU
1385 * executing anything. The chances are fairly high that they will use
1386 * blorp at least once per primary command buffer so it shouldn't be
1389 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1390 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1392 /* We send an "Indirect State Pointers Disable" packet at
1393 * EndCommandBuffer, so all push contant packets are ignored during a
1394 * context restore. Documentation says after that command, we need to
1395 * emit push constants again before any rendering operation. So we
1396 * flag them dirty here to make sure they get emitted.
1398 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1400 VkResult result
= VK_SUCCESS
;
1401 if (cmd_buffer
->usage_flags
&
1402 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1403 assert(pBeginInfo
->pInheritanceInfo
);
1404 cmd_buffer
->state
.pass
=
1405 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1406 cmd_buffer
->state
.subpass
=
1407 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1409 /* This is optional in the inheritance info. */
1410 cmd_buffer
->state
.framebuffer
=
1411 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1413 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1414 cmd_buffer
->state
.pass
, NULL
);
1416 /* Record that HiZ is enabled if we can. */
1417 if (cmd_buffer
->state
.framebuffer
) {
1418 const struct anv_image_view
* const iview
=
1419 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1422 VkImageLayout layout
=
1423 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1425 enum isl_aux_usage aux_usage
=
1426 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1427 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1429 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1433 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1436 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1437 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1438 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1439 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1441 /* If secondary buffer supports conditional rendering
1442 * we should emit commands as if conditional rendering is enabled.
1444 cmd_buffer
->state
.conditional_render_enabled
=
1445 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1452 /* From the PRM, Volume 2a:
1454 * "Indirect State Pointers Disable
1456 * At the completion of the post-sync operation associated with this pipe
1457 * control packet, the indirect state pointers in the hardware are
1458 * considered invalid; the indirect pointers are not saved in the context.
1459 * If any new indirect state commands are executed in the command stream
1460 * while the pipe control is pending, the new indirect state commands are
1463 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1464 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1465 * commands are only considered as Indirect State Pointers. Once ISP is
1466 * issued in a context, SW must initialize by programming push constant
1467 * commands for all the shaders (at least to zero length) before attempting
1468 * any rendering operation for the same context."
1470 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1471 * even though they point to a BO that has been already unreferenced at
1472 * the end of the previous batch buffer. This has been fine so far since
1473 * we are protected by these scratch page (every address not covered by
1474 * a BO should be pointing to the scratch page). But on CNL, it is
1475 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1478 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1479 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1480 * context restore, so the mentioned hang doesn't happen. However,
1481 * software must program push constant commands for all stages prior to
1482 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1484 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1485 * constants have been loaded into the EUs prior to disable the push constants
1486 * so that it doesn't hang a previous 3DPRIMITIVE.
1489 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1491 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1492 pc
.StallAtPixelScoreboard
= true;
1493 pc
.CommandStreamerStallEnable
= true;
1495 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1496 pc
.IndirectStatePointersDisable
= true;
1497 pc
.CommandStreamerStallEnable
= true;
1502 genX(EndCommandBuffer
)(
1503 VkCommandBuffer commandBuffer
)
1505 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1507 if (anv_batch_has_error(&cmd_buffer
->batch
))
1508 return cmd_buffer
->batch
.status
;
1510 /* We want every command buffer to start with the PMA fix in a known state,
1511 * so we disable it at the end of the command buffer.
1513 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1515 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1517 emit_isp_disable(cmd_buffer
);
1519 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1525 genX(CmdExecuteCommands
)(
1526 VkCommandBuffer commandBuffer
,
1527 uint32_t commandBufferCount
,
1528 const VkCommandBuffer
* pCmdBuffers
)
1530 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1532 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1534 if (anv_batch_has_error(&primary
->batch
))
1537 /* The secondary command buffers will assume that the PMA fix is disabled
1538 * when they begin executing. Make sure this is true.
1540 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1542 /* The secondary command buffer doesn't know which textures etc. have been
1543 * flushed prior to their execution. Apply those flushes now.
1545 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1547 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1548 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1550 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1551 assert(!anv_batch_has_error(&secondary
->batch
));
1553 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1554 if (secondary
->state
.conditional_render_enabled
) {
1555 if (!primary
->state
.conditional_render_enabled
) {
1556 /* Secondary buffer is constructed as if it will be executed
1557 * with conditional rendering, we should satisfy this dependency
1558 * regardless of conditional rendering being enabled in primary.
1560 struct gen_mi_builder b
;
1561 gen_mi_builder_init(&b
, &primary
->batch
);
1562 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
1563 gen_mi_imm(UINT64_MAX
));
1568 if (secondary
->usage_flags
&
1569 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1570 /* If we're continuing a render pass from the primary, we need to
1571 * copy the surface states for the current subpass into the storage
1572 * we allocated for them in BeginCommandBuffer.
1574 struct anv_bo
*ss_bo
=
1575 primary
->device
->surface_state_pool
.block_pool
.bo
;
1576 struct anv_state src_state
= primary
->state
.render_pass_states
;
1577 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1578 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1580 genX(cmd_buffer_so_memcpy
)(primary
,
1581 (struct anv_address
) {
1583 .offset
= dst_state
.offset
,
1585 (struct anv_address
) {
1587 .offset
= src_state
.offset
,
1589 src_state
.alloc_size
);
1592 anv_cmd_buffer_add_secondary(primary
, secondary
);
1595 /* The secondary may have selected a different pipeline (3D or compute) and
1596 * may have changed the current L3$ configuration. Reset our tracking
1597 * variables to invalid values to ensure that we re-emit these in the case
1598 * where we do any draws or compute dispatches from the primary after the
1599 * secondary has returned.
1601 primary
->state
.current_pipeline
= UINT32_MAX
;
1602 primary
->state
.current_l3_config
= NULL
;
1604 /* Each of the secondary command buffers will use its own state base
1605 * address. We need to re-emit state base address for the primary after
1606 * all of the secondaries are done.
1608 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1611 genX(cmd_buffer_emit_state_base_address
)(primary
);
1614 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1615 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1616 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1619 * Program the hardware to use the specified L3 configuration.
1622 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1623 const struct gen_l3_config
*cfg
)
1626 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1629 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1630 intel_logd("L3 config transition: ");
1631 gen_dump_l3_config(cfg
, stderr
);
1634 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1636 /* According to the hardware docs, the L3 partitioning can only be changed
1637 * while the pipeline is completely drained and the caches are flushed,
1638 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1640 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1641 pc
.DCFlushEnable
= true;
1642 pc
.PostSyncOperation
= NoWrite
;
1643 pc
.CommandStreamerStallEnable
= true;
1646 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1647 * invalidation of the relevant caches. Note that because RO invalidation
1648 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1649 * command is processed by the CS) we cannot combine it with the previous
1650 * stalling flush as the hardware documentation suggests, because that
1651 * would cause the CS to stall on previous rendering *after* RO
1652 * invalidation and wouldn't prevent the RO caches from being polluted by
1653 * concurrent rendering before the stall completes. This intentionally
1654 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1655 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1656 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1657 * already guarantee that there is no concurrent GPGPU kernel execution
1658 * (see SKL HSD 2132585).
1660 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1661 pc
.TextureCacheInvalidationEnable
= true;
1662 pc
.ConstantCacheInvalidationEnable
= true;
1663 pc
.InstructionCacheInvalidateEnable
= true;
1664 pc
.StateCacheInvalidationEnable
= true;
1665 pc
.PostSyncOperation
= NoWrite
;
1668 /* Now send a third stalling flush to make sure that invalidation is
1669 * complete when the L3 configuration registers are modified.
1671 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1672 pc
.DCFlushEnable
= true;
1673 pc
.PostSyncOperation
= NoWrite
;
1674 pc
.CommandStreamerStallEnable
= true;
1679 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1682 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1683 .SLMEnable
= has_slm
,
1685 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1686 * in L3CNTLREG register. The default setting of the bit is not the
1687 * desirable behavior.
1689 .ErrorDetectionBehaviorControl
= true,
1690 .UseFullWays
= true,
1692 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1693 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1694 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1695 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1697 /* Set up the L3 partitioning. */
1698 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1702 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1703 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1704 cfg
->n
[GEN_L3P_ALL
];
1705 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1706 cfg
->n
[GEN_L3P_ALL
];
1707 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1708 cfg
->n
[GEN_L3P_ALL
];
1710 assert(!cfg
->n
[GEN_L3P_ALL
]);
1712 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1713 * the matching space on the remaining banks has to be allocated to a
1714 * client (URB for all validated configurations) set to the
1715 * lower-bandwidth 2-bank address hashing mode.
1717 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1718 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1719 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1721 /* Minimum number of ways that can be allocated to the URB. */
1722 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1723 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1725 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1726 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1727 .ConvertDC_UC
= !has_dc
,
1728 .ConvertIS_UC
= !has_is
,
1729 .ConvertC_UC
= !has_c
,
1730 .ConvertT_UC
= !has_t
);
1732 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1733 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1734 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1736 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1737 .SLMEnable
= has_slm
,
1738 .URBLowBandwidth
= urb_low_bw
,
1739 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1741 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1743 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1744 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1746 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1747 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1748 .ISLowBandwidth
= 0,
1749 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1751 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1752 .TLowBandwidth
= 0);
1754 /* Set up the L3 partitioning. */
1755 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1756 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1757 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1760 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1761 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1762 * them disabled to avoid crashing the system hard.
1764 uint32_t scratch1
, chicken3
;
1765 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1766 .L3AtomicDisable
= !has_dc
);
1767 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1768 .L3AtomicDisableMask
= true,
1769 .L3AtomicDisable
= !has_dc
);
1770 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1771 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1777 cmd_buffer
->state
.current_l3_config
= cfg
;
1781 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1783 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1785 /* Flushes are pipelined while invalidations are handled immediately.
1786 * Therefore, if we're flushing anything then we need to schedule a stall
1787 * before any invalidations can happen.
1789 if (bits
& ANV_PIPE_FLUSH_BITS
)
1790 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1792 /* If we're going to do an invalidate and we have a pending CS stall that
1793 * has yet to be resolved, we do the CS stall now.
1795 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1796 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1797 bits
|= ANV_PIPE_CS_STALL_BIT
;
1798 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1801 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1802 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1803 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1804 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1805 pipe
.RenderTargetCacheFlushEnable
=
1806 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1808 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1809 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1810 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1813 * According to the Broadwell documentation, any PIPE_CONTROL with the
1814 * "Command Streamer Stall" bit set must also have another bit set,
1815 * with five different options:
1817 * - Render Target Cache Flush
1818 * - Depth Cache Flush
1819 * - Stall at Pixel Scoreboard
1820 * - Post-Sync Operation
1824 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1825 * mesa and it seems to work fine. The choice is fairly arbitrary.
1827 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1828 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1829 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1830 pipe
.StallAtPixelScoreboard
= true;
1833 /* If a render target flush was emitted, then we can toggle off the bit
1834 * saying that render target writes are ongoing.
1836 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
1837 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
1839 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1842 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1843 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1845 * "If the VF Cache Invalidation Enable is set to a 1 in a
1846 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1847 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1848 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1851 * This appears to hang Broadwell, so we restrict it to just gen9.
1853 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1854 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1856 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1857 pipe
.StateCacheInvalidationEnable
=
1858 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1859 pipe
.ConstantCacheInvalidationEnable
=
1860 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1861 pipe
.VFCacheInvalidationEnable
=
1862 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1863 pipe
.TextureCacheInvalidationEnable
=
1864 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1865 pipe
.InstructionCacheInvalidateEnable
=
1866 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1868 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1870 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1871 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1872 * “Write Timestamp”.
1874 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1875 pipe
.PostSyncOperation
= WriteImmediateData
;
1877 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1881 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1884 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1887 void genX(CmdPipelineBarrier
)(
1888 VkCommandBuffer commandBuffer
,
1889 VkPipelineStageFlags srcStageMask
,
1890 VkPipelineStageFlags destStageMask
,
1892 uint32_t memoryBarrierCount
,
1893 const VkMemoryBarrier
* pMemoryBarriers
,
1894 uint32_t bufferMemoryBarrierCount
,
1895 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1896 uint32_t imageMemoryBarrierCount
,
1897 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1899 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1901 /* XXX: Right now, we're really dumb and just flush whatever categories
1902 * the app asks for. One of these days we may make this a bit better
1903 * but right now that's all the hardware allows for in most areas.
1905 VkAccessFlags src_flags
= 0;
1906 VkAccessFlags dst_flags
= 0;
1908 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1909 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1910 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1913 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1914 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1915 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1918 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1919 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1920 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1921 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1922 const VkImageSubresourceRange
*range
=
1923 &pImageMemoryBarriers
[i
].subresourceRange
;
1925 uint32_t base_layer
, layer_count
;
1926 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1928 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1930 base_layer
= range
->baseArrayLayer
;
1931 layer_count
= anv_get_layerCount(image
, range
);
1934 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1935 transition_depth_buffer(cmd_buffer
, image
,
1936 pImageMemoryBarriers
[i
].oldLayout
,
1937 pImageMemoryBarriers
[i
].newLayout
);
1940 if (range
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1941 transition_stencil_buffer(cmd_buffer
, image
,
1942 range
->baseMipLevel
,
1943 anv_get_levelCount(image
, range
),
1944 base_layer
, layer_count
,
1945 pImageMemoryBarriers
[i
].oldLayout
,
1946 pImageMemoryBarriers
[i
].newLayout
);
1949 if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1950 VkImageAspectFlags color_aspects
=
1951 anv_image_expand_aspects(image
, range
->aspectMask
);
1952 uint32_t aspect_bit
;
1953 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1954 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1955 range
->baseMipLevel
,
1956 anv_get_levelCount(image
, range
),
1957 base_layer
, layer_count
,
1958 pImageMemoryBarriers
[i
].oldLayout
,
1959 pImageMemoryBarriers
[i
].newLayout
);
1964 cmd_buffer
->state
.pending_pipe_bits
|=
1965 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1966 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1970 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1972 VkShaderStageFlags stages
=
1973 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1975 /* In order to avoid thrash, we assume that vertex and fragment stages
1976 * always exist. In the rare case where one is missing *and* the other
1977 * uses push concstants, this may be suboptimal. However, avoiding stalls
1978 * seems more important.
1980 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1982 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1986 const unsigned push_constant_kb
= 32;
1987 #elif GEN_IS_HASWELL
1988 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1990 const unsigned push_constant_kb
= 16;
1993 const unsigned num_stages
=
1994 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1995 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1997 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1998 * units of 2KB. Incidentally, these are the same platforms that have
1999 * 32KB worth of push constant space.
2001 if (push_constant_kb
== 32)
2002 size_per_stage
&= ~1u;
2004 uint32_t kb_used
= 0;
2005 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
2006 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
2007 anv_batch_emit(&cmd_buffer
->batch
,
2008 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
2009 alloc
._3DCommandSubOpcode
= 18 + i
;
2010 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
2011 alloc
.ConstantBufferSize
= push_size
;
2013 kb_used
+= push_size
;
2016 anv_batch_emit(&cmd_buffer
->batch
,
2017 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
2018 alloc
.ConstantBufferOffset
= kb_used
;
2019 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
2022 cmd_buffer
->state
.push_constant_stages
= stages
;
2024 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
2026 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
2027 * the next 3DPRIMITIVE command after programming the
2028 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
2030 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
2031 * pipeline setup, we need to dirty push constants.
2033 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
2036 static const struct anv_descriptor
*
2037 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
2038 const struct anv_pipeline_binding
*binding
)
2040 assert(binding
->set
< MAX_SETS
);
2041 const struct anv_descriptor_set
*set
=
2042 pipe_state
->descriptors
[binding
->set
];
2043 const uint32_t offset
=
2044 set
->layout
->binding
[binding
->binding
].descriptor_index
;
2045 return &set
->descriptors
[offset
+ binding
->index
];
2049 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
2050 const struct anv_pipeline_binding
*binding
)
2052 assert(binding
->set
< MAX_SETS
);
2053 const struct anv_descriptor_set
*set
=
2054 pipe_state
->descriptors
[binding
->set
];
2056 uint32_t dynamic_offset_idx
=
2057 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
2058 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
2061 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
2064 static struct anv_address
2065 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
2066 struct anv_descriptor_set
*set
)
2069 /* This is a normal descriptor set */
2070 return (struct anv_address
) {
2071 .bo
= &set
->pool
->bo
,
2072 .offset
= set
->desc_mem
.offset
,
2075 /* This is a push descriptor set. We have to flag it as used on the GPU
2076 * so that the next time we push descriptors, we grab a new memory.
2078 struct anv_push_descriptor_set
*push_set
=
2079 (struct anv_push_descriptor_set
*)set
;
2080 push_set
->set_used_on_gpu
= true;
2082 return (struct anv_address
) {
2083 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2084 .offset
= set
->desc_mem
.offset
,
2090 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2091 gl_shader_stage stage
,
2092 struct anv_state
*bt_state
)
2094 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2095 struct anv_cmd_pipeline_state
*pipe_state
;
2096 struct anv_pipeline
*pipeline
;
2097 uint32_t state_offset
;
2100 case MESA_SHADER_COMPUTE
:
2101 pipe_state
= &cmd_buffer
->state
.compute
.base
;
2104 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
2107 pipeline
= pipe_state
->pipeline
;
2109 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2110 *bt_state
= (struct anv_state
) { 0, };
2114 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2115 if (map
->surface_count
== 0) {
2116 *bt_state
= (struct anv_state
) { 0, };
2120 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2123 uint32_t *bt_map
= bt_state
->map
;
2125 if (bt_state
->map
== NULL
)
2126 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2128 /* We only need to emit relocs if we're not using softpin. If we are using
2129 * softpin then we always keep all user-allocated memory objects resident.
2131 const bool need_client_mem_relocs
=
2132 !cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
;
2134 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2135 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2137 struct anv_state surface_state
;
2139 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2140 /* Color attachment binding */
2141 assert(stage
== MESA_SHADER_FRAGMENT
);
2142 assert(binding
->binding
== 0);
2143 if (binding
->index
< subpass
->color_count
) {
2144 const unsigned att
=
2145 subpass
->color_attachments
[binding
->index
].attachment
;
2147 /* From the Vulkan 1.0.46 spec:
2149 * "If any color or depth/stencil attachments are
2150 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2153 if (att
== VK_ATTACHMENT_UNUSED
) {
2154 surface_state
= cmd_buffer
->state
.null_surface_state
;
2156 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2159 surface_state
= cmd_buffer
->state
.null_surface_state
;
2162 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2164 } else if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2165 struct anv_state surface_state
=
2166 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2168 struct anv_address constant_data
= {
2169 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2170 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2172 unsigned constant_data_size
=
2173 pipeline
->shaders
[stage
]->constant_data_size
;
2175 const enum isl_format format
=
2176 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2177 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2178 surface_state
, format
,
2179 constant_data
, constant_data_size
, 1);
2181 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2182 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2184 } else if (binding
->set
== ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
) {
2185 /* This is always the first binding for compute shaders */
2186 assert(stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2187 if (!get_cs_prog_data(pipeline
)->uses_num_work_groups
)
2190 struct anv_state surface_state
=
2191 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2193 const enum isl_format format
=
2194 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2195 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2197 cmd_buffer
->state
.compute
.num_workgroups
,
2199 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2200 if (need_client_mem_relocs
) {
2201 add_surface_reloc(cmd_buffer
, surface_state
,
2202 cmd_buffer
->state
.compute
.num_workgroups
);
2205 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2206 /* This is a descriptor set buffer so the set index is actually
2207 * given by binding->binding. (Yes, that's confusing.)
2209 struct anv_descriptor_set
*set
=
2210 pipe_state
->descriptors
[binding
->binding
];
2211 assert(set
->desc_mem
.alloc_size
);
2212 assert(set
->desc_surface_state
.alloc_size
);
2213 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2214 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2215 anv_descriptor_set_address(cmd_buffer
, set
));
2219 const struct anv_descriptor
*desc
=
2220 anv_descriptor_for_binding(pipe_state
, binding
);
2222 switch (desc
->type
) {
2223 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2224 /* Nothing for us to do here */
2227 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2228 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2229 struct anv_surface_state sstate
=
2230 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2231 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2232 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2233 surface_state
= sstate
.state
;
2234 assert(surface_state
.alloc_size
);
2235 if (need_client_mem_relocs
)
2236 add_surface_state_relocs(cmd_buffer
, sstate
);
2239 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2240 assert(stage
== MESA_SHADER_FRAGMENT
);
2241 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2242 /* For depth and stencil input attachments, we treat it like any
2243 * old texture that a user may have bound.
2245 struct anv_surface_state sstate
=
2246 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2247 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2248 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2249 surface_state
= sstate
.state
;
2250 assert(surface_state
.alloc_size
);
2251 if (need_client_mem_relocs
)
2252 add_surface_state_relocs(cmd_buffer
, sstate
);
2254 /* For color input attachments, we create the surface state at
2255 * vkBeginRenderPass time so that we can include aux and clear
2256 * color information.
2258 assert(binding
->input_attachment_index
< subpass
->input_count
);
2259 const unsigned subpass_att
= binding
->input_attachment_index
;
2260 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2261 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2265 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2266 struct anv_surface_state sstate
= (binding
->write_only
)
2267 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2268 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2269 surface_state
= sstate
.state
;
2270 assert(surface_state
.alloc_size
);
2271 if (need_client_mem_relocs
)
2272 add_surface_state_relocs(cmd_buffer
, sstate
);
2276 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2277 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2278 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2279 surface_state
= desc
->buffer_view
->surface_state
;
2280 assert(surface_state
.alloc_size
);
2281 if (need_client_mem_relocs
) {
2282 add_surface_reloc(cmd_buffer
, surface_state
,
2283 desc
->buffer_view
->address
);
2287 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2288 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2289 /* Compute the offset within the buffer */
2290 uint32_t dynamic_offset
=
2291 dynamic_offset_for_binding(pipe_state
, binding
);
2292 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2293 /* Clamp to the buffer size */
2294 offset
= MIN2(offset
, desc
->buffer
->size
);
2295 /* Clamp the range to the buffer size */
2296 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2298 struct anv_address address
=
2299 anv_address_add(desc
->buffer
->address
, offset
);
2302 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2303 enum isl_format format
=
2304 anv_isl_format_for_descriptor_type(desc
->type
);
2306 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2307 format
, address
, range
, 1);
2308 if (need_client_mem_relocs
)
2309 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2313 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2314 surface_state
= (binding
->write_only
)
2315 ? desc
->buffer_view
->writeonly_storage_surface_state
2316 : desc
->buffer_view
->storage_surface_state
;
2317 assert(surface_state
.alloc_size
);
2318 if (need_client_mem_relocs
) {
2319 add_surface_reloc(cmd_buffer
, surface_state
,
2320 desc
->buffer_view
->address
);
2325 assert(!"Invalid descriptor type");
2329 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2333 /* The PIPE_CONTROL command description says:
2335 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2336 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2337 * Target Cache Flush by enabling this bit. When render target flush
2338 * is set due to new association of BTI, PS Scoreboard Stall bit must
2339 * be set in this packet."
2341 * FINISHME: Currently we shuffle around the surface states in the binding
2342 * table based on if they are getting used or not. So, we've to do below
2343 * pipe control flush for every binding table upload. Make changes so
2344 * that we do it only when we modify render target surface states.
2346 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2347 pc
.RenderTargetCacheFlushEnable
= true;
2348 pc
.StallAtPixelScoreboard
= true;
2356 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2357 gl_shader_stage stage
,
2358 struct anv_state
*state
)
2360 struct anv_cmd_pipeline_state
*pipe_state
=
2361 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2362 &cmd_buffer
->state
.gfx
.base
;
2363 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2365 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2366 *state
= (struct anv_state
) { 0, };
2370 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2371 if (map
->sampler_count
== 0) {
2372 *state
= (struct anv_state
) { 0, };
2376 uint32_t size
= map
->sampler_count
* 16;
2377 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2379 if (state
->map
== NULL
)
2380 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2382 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2383 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2384 const struct anv_descriptor
*desc
=
2385 anv_descriptor_for_binding(pipe_state
, binding
);
2387 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2388 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2391 struct anv_sampler
*sampler
= desc
->sampler
;
2393 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2394 * happens to be zero.
2396 if (sampler
== NULL
)
2399 memcpy(state
->map
+ (s
* 16),
2400 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2407 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2409 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2411 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2412 pipeline
->active_stages
;
2414 VkResult result
= VK_SUCCESS
;
2415 anv_foreach_stage(s
, dirty
) {
2416 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2417 if (result
!= VK_SUCCESS
)
2419 result
= emit_binding_table(cmd_buffer
, s
,
2420 &cmd_buffer
->state
.binding_tables
[s
]);
2421 if (result
!= VK_SUCCESS
)
2425 if (result
!= VK_SUCCESS
) {
2426 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2428 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2429 if (result
!= VK_SUCCESS
)
2432 /* Re-emit state base addresses so we get the new surface state base
2433 * address before we start emitting binding tables etc.
2435 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2437 /* Re-emit all active binding tables */
2438 dirty
|= pipeline
->active_stages
;
2439 anv_foreach_stage(s
, dirty
) {
2440 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2441 if (result
!= VK_SUCCESS
) {
2442 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2445 result
= emit_binding_table(cmd_buffer
, s
,
2446 &cmd_buffer
->state
.binding_tables
[s
]);
2447 if (result
!= VK_SUCCESS
) {
2448 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2454 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2460 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2463 static const uint32_t sampler_state_opcodes
[] = {
2464 [MESA_SHADER_VERTEX
] = 43,
2465 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2466 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2467 [MESA_SHADER_GEOMETRY
] = 46,
2468 [MESA_SHADER_FRAGMENT
] = 47,
2469 [MESA_SHADER_COMPUTE
] = 0,
2472 static const uint32_t binding_table_opcodes
[] = {
2473 [MESA_SHADER_VERTEX
] = 38,
2474 [MESA_SHADER_TESS_CTRL
] = 39,
2475 [MESA_SHADER_TESS_EVAL
] = 40,
2476 [MESA_SHADER_GEOMETRY
] = 41,
2477 [MESA_SHADER_FRAGMENT
] = 42,
2478 [MESA_SHADER_COMPUTE
] = 0,
2481 anv_foreach_stage(s
, stages
) {
2482 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2483 assert(binding_table_opcodes
[s
] > 0);
2485 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2486 anv_batch_emit(&cmd_buffer
->batch
,
2487 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2488 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2489 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2493 /* Always emit binding table pointers if we're asked to, since on SKL
2494 * this is what flushes push constants. */
2495 anv_batch_emit(&cmd_buffer
->batch
,
2496 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2497 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2498 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2504 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2505 VkShaderStageFlags dirty_stages
)
2507 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2508 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2510 static const uint32_t push_constant_opcodes
[] = {
2511 [MESA_SHADER_VERTEX
] = 21,
2512 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2513 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2514 [MESA_SHADER_GEOMETRY
] = 22,
2515 [MESA_SHADER_FRAGMENT
] = 23,
2516 [MESA_SHADER_COMPUTE
] = 0,
2519 VkShaderStageFlags flushed
= 0;
2521 anv_foreach_stage(stage
, dirty_stages
) {
2522 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2523 assert(push_constant_opcodes
[stage
] > 0);
2525 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2526 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2528 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2529 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2530 const struct brw_stage_prog_data
*prog_data
=
2531 pipeline
->shaders
[stage
]->prog_data
;
2532 const struct anv_pipeline_bind_map
*bind_map
=
2533 &pipeline
->shaders
[stage
]->bind_map
;
2535 /* The Skylake PRM contains the following restriction:
2537 * "The driver must ensure The following case does not occur
2538 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2539 * buffer 3 read length equal to zero committed followed by a
2540 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2543 * To avoid this, we program the buffers in the highest slots.
2544 * This way, slot 0 is only used if slot 3 is also used.
2548 for (int i
= 3; i
>= 0; i
--) {
2549 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2550 if (range
->length
== 0)
2553 const unsigned surface
=
2554 prog_data
->binding_table
.ubo_start
+ range
->block
;
2556 assert(surface
<= bind_map
->surface_count
);
2557 const struct anv_pipeline_binding
*binding
=
2558 &bind_map
->surface_to_descriptor
[surface
];
2560 struct anv_address read_addr
;
2562 if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2563 struct anv_address constant_data
= {
2564 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2565 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2567 unsigned constant_data_size
=
2568 pipeline
->shaders
[stage
]->constant_data_size
;
2570 read_len
= MIN2(range
->length
,
2571 DIV_ROUND_UP(constant_data_size
, 32) - range
->start
);
2572 read_addr
= anv_address_add(constant_data
,
2574 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2575 /* This is a descriptor set buffer so the set index is
2576 * actually given by binding->binding. (Yes, that's
2579 struct anv_descriptor_set
*set
=
2580 gfx_state
->base
.descriptors
[binding
->binding
];
2581 struct anv_address desc_buffer_addr
=
2582 anv_descriptor_set_address(cmd_buffer
, set
);
2583 const unsigned desc_buffer_size
= set
->desc_mem
.alloc_size
;
2585 read_len
= MIN2(range
->length
,
2586 DIV_ROUND_UP(desc_buffer_size
, 32) - range
->start
);
2587 read_addr
= anv_address_add(desc_buffer_addr
,
2590 const struct anv_descriptor
*desc
=
2591 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2593 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2594 read_len
= MIN2(range
->length
,
2595 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2596 read_addr
= anv_address_add(desc
->buffer_view
->address
,
2599 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2601 uint32_t dynamic_offset
=
2602 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2603 uint32_t buf_offset
=
2604 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2605 uint32_t buf_range
=
2606 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2608 read_len
= MIN2(range
->length
,
2609 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2610 read_addr
= anv_address_add(desc
->buffer
->address
,
2611 buf_offset
+ range
->start
* 32);
2616 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2617 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2622 struct anv_state state
=
2623 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2625 if (state
.alloc_size
> 0) {
2626 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2627 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2628 .offset
= state
.offset
,
2630 c
.ConstantBody
.ReadLength
[n
] =
2631 DIV_ROUND_UP(state
.alloc_size
, 32);
2634 /* For Ivy Bridge, the push constants packets have a different
2635 * rule that would require us to iterate in the other direction
2636 * and possibly mess around with dynamic state base address.
2637 * Don't bother; just emit regular push constants at n = 0.
2639 struct anv_state state
=
2640 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2642 if (state
.alloc_size
> 0) {
2643 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2644 c
.ConstantBody
.ReadLength
[0] =
2645 DIV_ROUND_UP(state
.alloc_size
, 32);
2651 flushed
|= mesa_to_vk_shader_stage(stage
);
2654 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2658 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2660 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2663 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2664 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2665 vb_emit
|= pipeline
->vb_used
;
2667 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2669 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2671 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2674 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2675 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2677 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2678 GENX(3DSTATE_VERTEX_BUFFERS
));
2680 for_each_bit(vb
, vb_emit
) {
2681 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2682 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2684 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2685 .VertexBufferIndex
= vb
,
2687 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
2689 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2690 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2693 .AddressModifyEnable
= true,
2694 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2695 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2698 .BufferSize
= buffer
->size
- offset
2700 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2704 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2709 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2712 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
2713 /* We don't need any per-buffer dirty tracking because you're not
2714 * allowed to bind different XFB buffers while XFB is enabled.
2716 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
2717 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
2718 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
2719 sob
.SOBufferIndex
= idx
;
2721 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
2722 sob
.SOBufferEnable
= true;
2723 sob
.MOCS
= cmd_buffer
->device
->default_mocs
,
2724 sob
.StreamOffsetWriteEnable
= false;
2725 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
2727 /* Size is in DWords - 1 */
2728 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
2733 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
2735 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2739 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2740 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2742 /* The exact descriptor layout is pulled from the pipeline, so we need
2743 * to re-emit binding tables on every pipeline change.
2745 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2747 /* If the pipeline changed, we may need to re-allocate push constant
2750 cmd_buffer_alloc_push_constants(cmd_buffer
);
2754 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2755 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2756 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2758 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2759 * stall needs to be sent just prior to any 3DSTATE_VS,
2760 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2761 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2762 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2763 * PIPE_CONTROL needs to be sent before any combination of VS
2764 * associated 3DSTATE."
2766 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2767 pc
.DepthStallEnable
= true;
2768 pc
.PostSyncOperation
= WriteImmediateData
;
2770 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2775 /* Render targets live in the same binding table as fragment descriptors */
2776 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2777 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2779 /* We emit the binding tables and sampler tables first, then emit push
2780 * constants and then finally emit binding table and sampler table
2781 * pointers. It has to happen in this order, since emitting the binding
2782 * tables may change the push constants (in case of storage images). After
2783 * emitting push constants, on SKL+ we have to emit the corresponding
2784 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2787 if (cmd_buffer
->state
.descriptors_dirty
)
2788 dirty
= flush_descriptor_sets(cmd_buffer
);
2790 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2791 /* Because we're pushing UBOs, we have to push whenever either
2792 * descriptors or push constants is dirty.
2794 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2795 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2796 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2800 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2802 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2803 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2805 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2806 ANV_CMD_DIRTY_PIPELINE
)) {
2807 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2808 pipeline
->depth_clamp_enable
);
2811 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2812 ANV_CMD_DIRTY_RENDER_TARGETS
))
2813 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2815 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2817 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2821 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2822 struct anv_address addr
,
2823 uint32_t size
, uint32_t index
)
2825 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2826 GENX(3DSTATE_VERTEX_BUFFERS
));
2828 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2829 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2830 .VertexBufferIndex
= index
,
2831 .AddressModifyEnable
= true,
2833 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
),
2835 .BufferStartingAddress
= addr
,
2838 .BufferStartingAddress
= addr
,
2839 .EndAddress
= anv_address_add(addr
, size
),
2845 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2846 struct anv_address addr
)
2848 emit_vertex_bo(cmd_buffer
, addr
, 8, ANV_SVGS_VB_INDEX
);
2852 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2853 uint32_t base_vertex
, uint32_t base_instance
)
2855 struct anv_state id_state
=
2856 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2858 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2859 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2861 struct anv_address addr
= {
2862 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2863 .offset
= id_state
.offset
,
2866 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2870 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2872 struct anv_state state
=
2873 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2875 ((uint32_t *)state
.map
)[0] = draw_index
;
2877 struct anv_address addr
= {
2878 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2879 .offset
= state
.offset
,
2882 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2886 VkCommandBuffer commandBuffer
,
2887 uint32_t vertexCount
,
2888 uint32_t instanceCount
,
2889 uint32_t firstVertex
,
2890 uint32_t firstInstance
)
2892 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2893 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2894 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2896 if (anv_batch_has_error(&cmd_buffer
->batch
))
2899 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2901 if (cmd_buffer
->state
.conditional_render_enabled
)
2902 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2904 if (vs_prog_data
->uses_firstvertex
||
2905 vs_prog_data
->uses_baseinstance
)
2906 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2907 if (vs_prog_data
->uses_drawid
)
2908 emit_draw_index(cmd_buffer
, 0);
2910 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2911 * different views. We need to multiply instanceCount by the view count.
2913 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2915 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2916 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2917 prim
.VertexAccessType
= SEQUENTIAL
;
2918 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2919 prim
.VertexCountPerInstance
= vertexCount
;
2920 prim
.StartVertexLocation
= firstVertex
;
2921 prim
.InstanceCount
= instanceCount
;
2922 prim
.StartInstanceLocation
= firstInstance
;
2923 prim
.BaseVertexLocation
= 0;
2927 void genX(CmdDrawIndexed
)(
2928 VkCommandBuffer commandBuffer
,
2929 uint32_t indexCount
,
2930 uint32_t instanceCount
,
2931 uint32_t firstIndex
,
2932 int32_t vertexOffset
,
2933 uint32_t firstInstance
)
2935 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2936 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2937 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2939 if (anv_batch_has_error(&cmd_buffer
->batch
))
2942 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2944 if (cmd_buffer
->state
.conditional_render_enabled
)
2945 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2947 if (vs_prog_data
->uses_firstvertex
||
2948 vs_prog_data
->uses_baseinstance
)
2949 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2950 if (vs_prog_data
->uses_drawid
)
2951 emit_draw_index(cmd_buffer
, 0);
2953 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2954 * different views. We need to multiply instanceCount by the view count.
2956 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2958 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2959 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2960 prim
.VertexAccessType
= RANDOM
;
2961 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2962 prim
.VertexCountPerInstance
= indexCount
;
2963 prim
.StartVertexLocation
= firstIndex
;
2964 prim
.InstanceCount
= instanceCount
;
2965 prim
.StartInstanceLocation
= firstInstance
;
2966 prim
.BaseVertexLocation
= vertexOffset
;
2970 /* Auto-Draw / Indirect Registers */
2971 #define GEN7_3DPRIM_END_OFFSET 0x2420
2972 #define GEN7_3DPRIM_START_VERTEX 0x2430
2973 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2974 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2975 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2976 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2978 void genX(CmdDrawIndirectByteCountEXT
)(
2979 VkCommandBuffer commandBuffer
,
2980 uint32_t instanceCount
,
2981 uint32_t firstInstance
,
2982 VkBuffer counterBuffer
,
2983 VkDeviceSize counterBufferOffset
,
2984 uint32_t counterOffset
,
2985 uint32_t vertexStride
)
2987 #if GEN_IS_HASWELL || GEN_GEN >= 8
2988 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2989 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
2990 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2991 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2993 /* firstVertex is always zero for this draw function */
2994 const uint32_t firstVertex
= 0;
2996 if (anv_batch_has_error(&cmd_buffer
->batch
))
2999 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3001 if (vs_prog_data
->uses_firstvertex
||
3002 vs_prog_data
->uses_baseinstance
)
3003 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3004 if (vs_prog_data
->uses_drawid
)
3005 emit_draw_index(cmd_buffer
, 0);
3007 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3008 * different views. We need to multiply instanceCount by the view count.
3010 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3012 struct gen_mi_builder b
;
3013 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3014 struct gen_mi_value count
=
3015 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
3016 counterBufferOffset
));
3018 count
= gen_mi_isub(&b
, count
, gen_mi_imm(counterOffset
));
3019 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
3020 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
3022 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3023 gen_mi_imm(firstVertex
));
3024 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
3025 gen_mi_imm(instanceCount
));
3026 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3027 gen_mi_imm(firstInstance
));
3028 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3030 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3031 prim
.IndirectParameterEnable
= true;
3032 prim
.VertexAccessType
= SEQUENTIAL
;
3033 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3035 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3039 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
3040 struct anv_address addr
,
3043 struct gen_mi_builder b
;
3044 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3046 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
),
3047 gen_mi_mem32(anv_address_add(addr
, 0)));
3049 struct gen_mi_value instance_count
= gen_mi_mem32(anv_address_add(addr
, 4));
3050 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3051 if (view_count
> 1) {
3052 #if GEN_IS_HASWELL || GEN_GEN >= 8
3053 instance_count
= gen_mi_imul_imm(&b
, instance_count
, view_count
);
3055 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3056 "MI_MATH is not supported on Ivy Bridge");
3059 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
), instance_count
);
3061 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3062 gen_mi_mem32(anv_address_add(addr
, 8)));
3065 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
),
3066 gen_mi_mem32(anv_address_add(addr
, 12)));
3067 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3068 gen_mi_mem32(anv_address_add(addr
, 16)));
3070 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3071 gen_mi_mem32(anv_address_add(addr
, 12)));
3072 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3076 void genX(CmdDrawIndirect
)(
3077 VkCommandBuffer commandBuffer
,
3079 VkDeviceSize offset
,
3083 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3084 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3085 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3086 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3088 if (anv_batch_has_error(&cmd_buffer
->batch
))
3091 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3093 if (cmd_buffer
->state
.conditional_render_enabled
)
3094 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3096 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3097 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3099 if (vs_prog_data
->uses_firstvertex
||
3100 vs_prog_data
->uses_baseinstance
)
3101 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3102 if (vs_prog_data
->uses_drawid
)
3103 emit_draw_index(cmd_buffer
, i
);
3105 load_indirect_parameters(cmd_buffer
, draw
, false);
3107 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3108 prim
.IndirectParameterEnable
= true;
3109 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3110 prim
.VertexAccessType
= SEQUENTIAL
;
3111 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3118 void genX(CmdDrawIndexedIndirect
)(
3119 VkCommandBuffer commandBuffer
,
3121 VkDeviceSize offset
,
3125 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3126 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3127 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3128 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3130 if (anv_batch_has_error(&cmd_buffer
->batch
))
3133 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3135 if (cmd_buffer
->state
.conditional_render_enabled
)
3136 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3138 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3139 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3141 /* TODO: We need to stomp base vertex to 0 somehow */
3142 if (vs_prog_data
->uses_firstvertex
||
3143 vs_prog_data
->uses_baseinstance
)
3144 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3145 if (vs_prog_data
->uses_drawid
)
3146 emit_draw_index(cmd_buffer
, i
);
3148 load_indirect_parameters(cmd_buffer
, draw
, true);
3150 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3151 prim
.IndirectParameterEnable
= true;
3152 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3153 prim
.VertexAccessType
= RANDOM
;
3154 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3161 #define TMP_DRAW_COUNT_REG 0x2670 /* MI_ALU_REG14 */
3164 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3165 struct anv_address count_address
,
3166 const bool conditional_render_enabled
)
3168 struct gen_mi_builder b
;
3169 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3171 if (conditional_render_enabled
) {
3172 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3173 gen_mi_store(&b
, gen_mi_reg64(TMP_DRAW_COUNT_REG
),
3174 gen_mi_mem32(count_address
));
3177 /* Upload the current draw count from the draw parameters buffer to
3178 * MI_PREDICATE_SRC0.
3180 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
3181 gen_mi_mem32(count_address
));
3183 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
+ 4), gen_mi_imm(0));
3188 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3189 uint32_t draw_index
)
3191 struct gen_mi_builder b
;
3192 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3194 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3195 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
), gen_mi_imm(draw_index
));
3197 if (draw_index
== 0) {
3198 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3199 mip
.LoadOperation
= LOAD_LOADINV
;
3200 mip
.CombineOperation
= COMBINE_SET
;
3201 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3204 /* While draw_index < draw_count the predicate's result will be
3205 * (draw_index == draw_count) ^ TRUE = TRUE
3206 * When draw_index == draw_count the result is
3207 * (TRUE) ^ TRUE = FALSE
3208 * After this all results will be:
3209 * (FALSE) ^ FALSE = FALSE
3211 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3212 mip
.LoadOperation
= LOAD_LOAD
;
3213 mip
.CombineOperation
= COMBINE_XOR
;
3214 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3219 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3221 emit_draw_count_predicate_with_conditional_render(
3222 struct anv_cmd_buffer
*cmd_buffer
,
3223 uint32_t draw_index
)
3225 struct gen_mi_builder b
;
3226 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3228 struct gen_mi_value pred
= gen_mi_ult(&b
, gen_mi_imm(draw_index
),
3229 gen_mi_reg64(TMP_DRAW_COUNT_REG
));
3230 pred
= gen_mi_iand(&b
, pred
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
));
3233 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_RESULT
), pred
);
3235 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3236 * so we emit MI_PREDICATE to set it.
3239 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), pred
);
3240 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3242 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3243 mip
.LoadOperation
= LOAD_LOADINV
;
3244 mip
.CombineOperation
= COMBINE_SET
;
3245 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3251 void genX(CmdDrawIndirectCountKHR
)(
3252 VkCommandBuffer commandBuffer
,
3254 VkDeviceSize offset
,
3255 VkBuffer _countBuffer
,
3256 VkDeviceSize countBufferOffset
,
3257 uint32_t maxDrawCount
,
3260 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3261 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3262 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3263 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3264 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3265 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3267 if (anv_batch_has_error(&cmd_buffer
->batch
))
3270 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3272 struct anv_address count_address
=
3273 anv_address_add(count_buffer
->address
, countBufferOffset
);
3275 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3276 cmd_state
->conditional_render_enabled
);
3278 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3279 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3281 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3282 if (cmd_state
->conditional_render_enabled
) {
3283 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3285 emit_draw_count_predicate(cmd_buffer
, i
);
3288 emit_draw_count_predicate(cmd_buffer
, i
);
3291 if (vs_prog_data
->uses_firstvertex
||
3292 vs_prog_data
->uses_baseinstance
)
3293 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3294 if (vs_prog_data
->uses_drawid
)
3295 emit_draw_index(cmd_buffer
, i
);
3297 load_indirect_parameters(cmd_buffer
, draw
, false);
3299 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3300 prim
.IndirectParameterEnable
= true;
3301 prim
.PredicateEnable
= true;
3302 prim
.VertexAccessType
= SEQUENTIAL
;
3303 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3310 void genX(CmdDrawIndexedIndirectCountKHR
)(
3311 VkCommandBuffer commandBuffer
,
3313 VkDeviceSize offset
,
3314 VkBuffer _countBuffer
,
3315 VkDeviceSize countBufferOffset
,
3316 uint32_t maxDrawCount
,
3319 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3320 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3321 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3322 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3323 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3324 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3326 if (anv_batch_has_error(&cmd_buffer
->batch
))
3329 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3331 struct anv_address count_address
=
3332 anv_address_add(count_buffer
->address
, countBufferOffset
);
3334 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3335 cmd_state
->conditional_render_enabled
);
3337 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3338 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3340 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3341 if (cmd_state
->conditional_render_enabled
) {
3342 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3344 emit_draw_count_predicate(cmd_buffer
, i
);
3347 emit_draw_count_predicate(cmd_buffer
, i
);
3350 /* TODO: We need to stomp base vertex to 0 somehow */
3351 if (vs_prog_data
->uses_firstvertex
||
3352 vs_prog_data
->uses_baseinstance
)
3353 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3354 if (vs_prog_data
->uses_drawid
)
3355 emit_draw_index(cmd_buffer
, i
);
3357 load_indirect_parameters(cmd_buffer
, draw
, true);
3359 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3360 prim
.IndirectParameterEnable
= true;
3361 prim
.PredicateEnable
= true;
3362 prim
.VertexAccessType
= RANDOM
;
3363 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3370 void genX(CmdBeginTransformFeedbackEXT
)(
3371 VkCommandBuffer commandBuffer
,
3372 uint32_t firstCounterBuffer
,
3373 uint32_t counterBufferCount
,
3374 const VkBuffer
* pCounterBuffers
,
3375 const VkDeviceSize
* pCounterBufferOffsets
)
3377 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3379 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3380 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3381 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3383 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3385 * "Ssoftware must ensure that no HW stream output operations can be in
3386 * process or otherwise pending at the point that the MI_LOAD/STORE
3387 * commands are processed. This will likely require a pipeline flush."
3389 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3390 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3392 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3393 /* If we have a counter buffer, this is a resume so we need to load the
3394 * value into the streamout offset register. Otherwise, this is a begin
3395 * and we need to reset it to zero.
3397 if (pCounterBuffers
&&
3398 idx
>= firstCounterBuffer
&&
3399 idx
- firstCounterBuffer
< counterBufferCount
&&
3400 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
3401 uint32_t cb_idx
= idx
- firstCounterBuffer
;
3402 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3403 uint64_t offset
= pCounterBufferOffsets
?
3404 pCounterBufferOffsets
[cb_idx
] : 0;
3406 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3407 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3408 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3412 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
3413 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3419 cmd_buffer
->state
.xfb_enabled
= true;
3420 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3423 void genX(CmdEndTransformFeedbackEXT
)(
3424 VkCommandBuffer commandBuffer
,
3425 uint32_t firstCounterBuffer
,
3426 uint32_t counterBufferCount
,
3427 const VkBuffer
* pCounterBuffers
,
3428 const VkDeviceSize
* pCounterBufferOffsets
)
3430 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3432 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3433 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3434 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3436 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3438 * "Ssoftware must ensure that no HW stream output operations can be in
3439 * process or otherwise pending at the point that the MI_LOAD/STORE
3440 * commands are processed. This will likely require a pipeline flush."
3442 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3443 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3445 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
3446 unsigned idx
= firstCounterBuffer
+ cb_idx
;
3448 /* If we have a counter buffer, this is a resume so we need to load the
3449 * value into the streamout offset register. Otherwise, this is a begin
3450 * and we need to reset it to zero.
3452 if (pCounterBuffers
&&
3453 cb_idx
< counterBufferCount
&&
3454 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
3455 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3456 uint64_t offset
= pCounterBufferOffsets
?
3457 pCounterBufferOffsets
[cb_idx
] : 0;
3459 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
3460 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3462 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3467 cmd_buffer
->state
.xfb_enabled
= false;
3468 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3472 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
3474 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3475 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
3478 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3479 if (result
!= VK_SUCCESS
) {
3480 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3482 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
3483 if (result
!= VK_SUCCESS
)
3486 /* Re-emit state base addresses so we get the new surface state base
3487 * address before we start emitting binding tables etc.
3489 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
3491 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3492 if (result
!= VK_SUCCESS
) {
3493 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3498 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3499 if (result
!= VK_SUCCESS
) {
3500 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3504 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3505 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3506 .BindingTablePointer
= surfaces
.offset
,
3507 .SamplerStatePointer
= samplers
.offset
,
3509 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3511 struct anv_state state
=
3512 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3513 pipeline
->interface_descriptor_data
,
3514 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3517 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3518 anv_batch_emit(&cmd_buffer
->batch
,
3519 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3520 mid
.InterfaceDescriptorTotalLength
= size
;
3521 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3528 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3530 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3531 MAYBE_UNUSED VkResult result
;
3533 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3535 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3537 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3539 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3540 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3542 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3543 * the only bits that are changed are scoreboard related: Scoreboard
3544 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3545 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3548 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3549 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3551 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3554 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3555 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3556 /* FIXME: figure out descriptors for gen7 */
3557 result
= flush_compute_descriptor_set(cmd_buffer
);
3558 if (result
!= VK_SUCCESS
)
3561 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3564 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3565 struct anv_state push_state
=
3566 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3568 if (push_state
.alloc_size
) {
3569 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3570 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3571 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3575 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3578 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3580 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3586 verify_cmd_parser(const struct anv_device
*device
,
3587 int required_version
,
3588 const char *function
)
3590 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3591 return vk_errorf(device
->instance
, device
->instance
,
3592 VK_ERROR_FEATURE_NOT_PRESENT
,
3593 "cmd parser version %d is required for %s",
3594 required_version
, function
);
3603 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3604 uint32_t baseGroupX
,
3605 uint32_t baseGroupY
,
3606 uint32_t baseGroupZ
)
3608 if (anv_batch_has_error(&cmd_buffer
->batch
))
3611 struct anv_push_constants
*push
=
3612 &cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3613 if (push
->base_work_group_id
[0] != baseGroupX
||
3614 push
->base_work_group_id
[1] != baseGroupY
||
3615 push
->base_work_group_id
[2] != baseGroupZ
) {
3616 push
->base_work_group_id
[0] = baseGroupX
;
3617 push
->base_work_group_id
[1] = baseGroupY
;
3618 push
->base_work_group_id
[2] = baseGroupZ
;
3620 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3624 void genX(CmdDispatch
)(
3625 VkCommandBuffer commandBuffer
,
3630 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3633 void genX(CmdDispatchBase
)(
3634 VkCommandBuffer commandBuffer
,
3635 uint32_t baseGroupX
,
3636 uint32_t baseGroupY
,
3637 uint32_t baseGroupZ
,
3638 uint32_t groupCountX
,
3639 uint32_t groupCountY
,
3640 uint32_t groupCountZ
)
3642 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3643 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3644 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3646 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3647 baseGroupY
, baseGroupZ
);
3649 if (anv_batch_has_error(&cmd_buffer
->batch
))
3652 if (prog_data
->uses_num_work_groups
) {
3653 struct anv_state state
=
3654 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3655 uint32_t *sizes
= state
.map
;
3656 sizes
[0] = groupCountX
;
3657 sizes
[1] = groupCountY
;
3658 sizes
[2] = groupCountZ
;
3659 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3660 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3661 .offset
= state
.offset
,
3665 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3667 if (cmd_buffer
->state
.conditional_render_enabled
)
3668 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3670 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3671 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3672 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3673 ggw
.ThreadDepthCounterMaximum
= 0;
3674 ggw
.ThreadHeightCounterMaximum
= 0;
3675 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3676 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3677 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3678 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3679 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3680 ggw
.BottomExecutionMask
= 0xffffffff;
3683 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3686 #define GPGPU_DISPATCHDIMX 0x2500
3687 #define GPGPU_DISPATCHDIMY 0x2504
3688 #define GPGPU_DISPATCHDIMZ 0x2508
3690 void genX(CmdDispatchIndirect
)(
3691 VkCommandBuffer commandBuffer
,
3693 VkDeviceSize offset
)
3695 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3696 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3697 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3698 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3699 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3700 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3702 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3705 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3706 * indirect dispatch registers to be written.
3708 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3709 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3713 if (prog_data
->uses_num_work_groups
)
3714 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3716 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3718 struct gen_mi_builder b
;
3719 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3721 struct gen_mi_value size_x
= gen_mi_mem32(anv_address_add(addr
, 0));
3722 struct gen_mi_value size_y
= gen_mi_mem32(anv_address_add(addr
, 4));
3723 struct gen_mi_value size_z
= gen_mi_mem32(anv_address_add(addr
, 8));
3725 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMX
), size_x
);
3726 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMY
), size_y
);
3727 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMZ
), size_z
);
3730 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3731 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), size_x
);
3732 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3733 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3734 mip
.LoadOperation
= LOAD_LOAD
;
3735 mip
.CombineOperation
= COMBINE_SET
;
3736 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3739 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3740 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_y
);
3741 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3742 mip
.LoadOperation
= LOAD_LOAD
;
3743 mip
.CombineOperation
= COMBINE_OR
;
3744 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3747 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3748 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_z
);
3749 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3750 mip
.LoadOperation
= LOAD_LOAD
;
3751 mip
.CombineOperation
= COMBINE_OR
;
3752 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3755 /* predicate = !predicate; */
3756 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3757 mip
.LoadOperation
= LOAD_LOADINV
;
3758 mip
.CombineOperation
= COMBINE_OR
;
3759 mip
.CompareOperation
= COMPARE_FALSE
;
3763 if (cmd_buffer
->state
.conditional_render_enabled
) {
3764 /* predicate &= !(conditional_rendering_predicate == 0); */
3765 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
),
3766 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
3767 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3768 mip
.LoadOperation
= LOAD_LOADINV
;
3769 mip
.CombineOperation
= COMBINE_AND
;
3770 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3775 #else /* GEN_GEN > 7 */
3776 if (cmd_buffer
->state
.conditional_render_enabled
)
3777 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3780 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3781 ggw
.IndirectParameterEnable
= true;
3782 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
3783 cmd_buffer
->state
.conditional_render_enabled
;
3784 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3785 ggw
.ThreadDepthCounterMaximum
= 0;
3786 ggw
.ThreadHeightCounterMaximum
= 0;
3787 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3788 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3789 ggw
.BottomExecutionMask
= 0xffffffff;
3792 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3796 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3799 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3801 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3804 #if GEN_GEN >= 8 && GEN_GEN < 10
3805 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3807 * Software must clear the COLOR_CALC_STATE Valid field in
3808 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3809 * with Pipeline Select set to GPGPU.
3811 * The internal hardware docs recommend the same workaround for Gen9
3814 if (pipeline
== GPGPU
)
3815 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3818 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3819 * PIPELINE_SELECT [DevBWR+]":
3823 * Software must ensure all the write caches are flushed through a
3824 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3825 * command to invalidate read only caches prior to programming
3826 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3828 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3829 pc
.RenderTargetCacheFlushEnable
= true;
3830 pc
.DepthCacheFlushEnable
= true;
3831 pc
.DCFlushEnable
= true;
3832 pc
.PostSyncOperation
= NoWrite
;
3833 pc
.CommandStreamerStallEnable
= true;
3836 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3837 pc
.TextureCacheInvalidationEnable
= true;
3838 pc
.ConstantCacheInvalidationEnable
= true;
3839 pc
.StateCacheInvalidationEnable
= true;
3840 pc
.InstructionCacheInvalidateEnable
= true;
3841 pc
.PostSyncOperation
= NoWrite
;
3844 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3848 ps
.PipelineSelection
= pipeline
;
3852 if (devinfo
->is_geminilake
) {
3855 * "This chicken bit works around a hardware issue with barrier logic
3856 * encountered when switching between GPGPU and 3D pipelines. To
3857 * workaround the issue, this mode bit should be set after a pipeline
3861 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3863 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3864 : GLK_BARRIER_MODE_3D_HULL
,
3865 .GLKBarrierModeMask
= 1);
3866 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3870 cmd_buffer
->state
.current_pipeline
= pipeline
;
3874 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3876 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3880 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3882 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3886 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3891 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3893 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3894 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3895 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3896 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3897 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3898 * Depth Flush Bit set, followed by another pipelined depth stall
3899 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3900 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3901 * via a preceding MI_FLUSH)."
3903 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3904 pipe
.DepthStallEnable
= true;
3906 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3907 pipe
.DepthCacheFlushEnable
= true;
3909 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3910 pipe
.DepthStallEnable
= true;
3915 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3917 struct anv_device
*device
= cmd_buffer
->device
;
3918 const struct anv_image_view
*iview
=
3919 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3920 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3922 /* FIXME: Width and Height are wrong */
3924 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3926 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3927 device
->isl_dev
.ds
.size
/ 4);
3931 struct isl_depth_stencil_hiz_emit_info info
= { };
3934 info
.view
= &iview
->planes
[0].isl
;
3936 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3937 uint32_t depth_plane
=
3938 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3939 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
3941 info
.depth_surf
= &surface
->isl
;
3943 info
.depth_address
=
3944 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3945 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
3946 image
->planes
[depth_plane
].address
.bo
,
3947 image
->planes
[depth_plane
].address
.offset
+
3950 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
3953 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
3954 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
3955 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
3956 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
3959 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3960 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
3961 image
->planes
[depth_plane
].address
.bo
,
3962 image
->planes
[depth_plane
].address
.offset
+
3963 image
->planes
[depth_plane
].aux_surface
.offset
);
3965 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
3969 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3970 uint32_t stencil_plane
=
3971 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
3972 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
3974 info
.stencil_surf
= &surface
->isl
;
3976 info
.stencil_address
=
3977 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3978 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
3979 image
->planes
[stencil_plane
].address
.bo
,
3980 image
->planes
[stencil_plane
].address
.offset
+
3983 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
3986 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
3988 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
3992 * This ANDs the view mask of the current subpass with the pending clear
3993 * views in the attachment to get the mask of views active in the subpass
3994 * that still need to be cleared.
3996 static inline uint32_t
3997 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
3998 const struct anv_attachment_state
*att_state
)
4000 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
4004 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
4005 const struct anv_attachment_state
*att_state
)
4007 if (!cmd_state
->subpass
->view_mask
)
4010 uint32_t pending_clear_mask
=
4011 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4013 return pending_clear_mask
& 1;
4017 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
4020 const uint32_t last_subpass_idx
=
4021 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
4022 const struct anv_subpass
*last_subpass
=
4023 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
4024 return last_subpass
== cmd_state
->subpass
;
4028 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
4029 uint32_t subpass_id
)
4031 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4032 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
4033 cmd_state
->subpass
= subpass
;
4035 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
4037 /* Our implementation of VK_KHR_multiview uses instancing to draw the
4038 * different views. If the client asks for instancing, we need to use the
4039 * Instance Data Step Rate to ensure that we repeat the client's
4040 * per-instance data once for each view. Since this bit is in
4041 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
4045 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
4047 /* It is possible to start a render pass with an old pipeline. Because the
4048 * render pass and subpass index are both baked into the pipeline, this is
4049 * highly unlikely. In order to do so, it requires that you have a render
4050 * pass with a single subpass and that you use that render pass twice
4051 * back-to-back and use the same pipeline at the start of the second render
4052 * pass as at the end of the first. In order to avoid unpredictable issues
4053 * with this edge case, we just dirty the pipeline at the start of every
4056 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
4058 /* Accumulate any subpass flushes that need to happen before the subpass */
4059 cmd_buffer
->state
.pending_pipe_bits
|=
4060 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
4062 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4063 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4065 bool is_multiview
= subpass
->view_mask
!= 0;
4067 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4068 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4069 if (a
== VK_ATTACHMENT_UNUSED
)
4072 assert(a
< cmd_state
->pass
->attachment_count
);
4073 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4075 struct anv_image_view
*iview
= fb
->attachments
[a
];
4076 const struct anv_image
*image
= iview
->image
;
4078 /* A resolve is necessary before use as an input attachment if the clear
4079 * color or auxiliary buffer usage isn't supported by the sampler.
4081 const bool input_needs_resolve
=
4082 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
4083 att_state
->input_aux_usage
!= att_state
->aux_usage
;
4085 VkImageLayout target_layout
;
4086 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
4087 !input_needs_resolve
) {
4088 /* Layout transitions before the final only help to enable sampling
4089 * as an input attachment. If the input attachment supports sampling
4090 * using the auxiliary surface, we can skip such transitions by
4091 * making the target layout one that is CCS-aware.
4093 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
4095 target_layout
= subpass
->attachments
[i
].layout
;
4098 uint32_t base_layer
, layer_count
;
4099 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4101 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4102 iview
->planes
[0].isl
.base_level
);
4104 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4105 layer_count
= fb
->layers
;
4108 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4109 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4110 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4111 iview
->planes
[0].isl
.base_level
, 1,
4112 base_layer
, layer_count
,
4113 att_state
->current_layout
, target_layout
);
4116 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4117 transition_depth_buffer(cmd_buffer
, image
,
4118 att_state
->current_layout
, target_layout
);
4119 att_state
->aux_usage
=
4120 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
4121 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
4124 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4125 transition_stencil_buffer(cmd_buffer
, image
,
4126 iview
->planes
[0].isl
.base_level
, 1,
4127 base_layer
, layer_count
,
4128 att_state
->current_layout
, target_layout
);
4130 att_state
->current_layout
= target_layout
;
4132 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
4133 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4135 /* Multi-planar images are not supported as attachments */
4136 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4137 assert(image
->n_planes
== 1);
4139 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
4140 uint32_t clear_layer_count
= fb
->layers
;
4142 if (att_state
->fast_clear
&&
4143 do_first_layer_clear(cmd_state
, att_state
)) {
4144 /* We only support fast-clears on the first layer */
4145 assert(iview
->planes
[0].isl
.base_level
== 0);
4146 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4148 union isl_color_value clear_color
= {};
4149 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
4150 if (iview
->image
->samples
== 1) {
4151 anv_image_ccs_op(cmd_buffer
, image
,
4152 iview
->planes
[0].isl
.format
,
4153 VK_IMAGE_ASPECT_COLOR_BIT
,
4154 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4158 anv_image_mcs_op(cmd_buffer
, image
,
4159 iview
->planes
[0].isl
.format
,
4160 VK_IMAGE_ASPECT_COLOR_BIT
,
4161 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4166 clear_layer_count
--;
4168 att_state
->pending_clear_views
&= ~1;
4170 if (att_state
->clear_color_is_zero
) {
4171 /* This image has the auxiliary buffer enabled. We can mark the
4172 * subresource as not needing a resolve because the clear color
4173 * will match what's in every RENDER_SURFACE_STATE object when
4174 * it's being used for sampling.
4176 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4177 VK_IMAGE_ASPECT_COLOR_BIT
,
4178 ANV_FAST_CLEAR_DEFAULT_VALUE
);
4180 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4181 VK_IMAGE_ASPECT_COLOR_BIT
,
4182 ANV_FAST_CLEAR_ANY
);
4186 /* From the VkFramebufferCreateInfo spec:
4188 * "If the render pass uses multiview, then layers must be one and each
4189 * attachment requires a number of layers that is greater than the
4190 * maximum bit index set in the view mask in the subpasses in which it
4193 * So if multiview is active we ignore the number of layers in the
4194 * framebuffer and instead we honor the view mask from the subpass.
4197 assert(image
->n_planes
== 1);
4198 uint32_t pending_clear_mask
=
4199 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4202 for_each_bit(layer_idx
, pending_clear_mask
) {
4204 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4206 anv_image_clear_color(cmd_buffer
, image
,
4207 VK_IMAGE_ASPECT_COLOR_BIT
,
4208 att_state
->aux_usage
,
4209 iview
->planes
[0].isl
.format
,
4210 iview
->planes
[0].isl
.swizzle
,
4211 iview
->planes
[0].isl
.base_level
,
4214 vk_to_isl_color(att_state
->clear_value
.color
));
4217 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4218 } else if (clear_layer_count
> 0) {
4219 assert(image
->n_planes
== 1);
4220 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4221 att_state
->aux_usage
,
4222 iview
->planes
[0].isl
.format
,
4223 iview
->planes
[0].isl
.swizzle
,
4224 iview
->planes
[0].isl
.base_level
,
4225 base_clear_layer
, clear_layer_count
,
4227 vk_to_isl_color(att_state
->clear_value
.color
));
4229 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
4230 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4231 if (att_state
->fast_clear
&& !is_multiview
) {
4232 /* We currently only support HiZ for single-layer images */
4233 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4234 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
4235 assert(iview
->planes
[0].isl
.base_level
== 0);
4236 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4237 assert(fb
->layers
== 1);
4240 anv_image_hiz_clear(cmd_buffer
, image
,
4241 att_state
->pending_clear_aspects
,
4242 iview
->planes
[0].isl
.base_level
,
4243 iview
->planes
[0].isl
.base_array_layer
,
4244 fb
->layers
, render_area
,
4245 att_state
->clear_value
.depthStencil
.stencil
);
4246 } else if (is_multiview
) {
4247 uint32_t pending_clear_mask
=
4248 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4251 for_each_bit(layer_idx
, pending_clear_mask
) {
4253 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4255 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4256 att_state
->pending_clear_aspects
,
4257 att_state
->aux_usage
,
4258 iview
->planes
[0].isl
.base_level
,
4261 att_state
->clear_value
.depthStencil
.depth
,
4262 att_state
->clear_value
.depthStencil
.stencil
);
4265 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4267 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4268 att_state
->pending_clear_aspects
,
4269 att_state
->aux_usage
,
4270 iview
->planes
[0].isl
.base_level
,
4271 iview
->planes
[0].isl
.base_array_layer
,
4272 fb
->layers
, render_area
,
4273 att_state
->clear_value
.depthStencil
.depth
,
4274 att_state
->clear_value
.depthStencil
.stencil
);
4277 assert(att_state
->pending_clear_aspects
== 0);
4281 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4282 image
->planes
[0].aux_surface
.isl
.size_B
> 0 &&
4283 iview
->planes
[0].isl
.base_level
== 0 &&
4284 iview
->planes
[0].isl
.base_array_layer
== 0) {
4285 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
4286 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
4287 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4288 false /* copy to ss */);
4291 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
4292 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
4293 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
4294 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4295 false /* copy to ss */);
4299 if (subpass
->attachments
[i
].usage
==
4300 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
4301 /* We assume that if we're starting a subpass, we're going to do some
4302 * rendering so we may end up with compressed data.
4304 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
4305 VK_IMAGE_ASPECT_COLOR_BIT
,
4306 att_state
->aux_usage
,
4307 iview
->planes
[0].isl
.base_level
,
4308 iview
->planes
[0].isl
.base_array_layer
,
4310 } else if (subpass
->attachments
[i
].usage
==
4311 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
4312 /* We may be writing depth or stencil so we need to mark the surface.
4313 * Unfortunately, there's no way to know at this point whether the
4314 * depth or stencil tests used will actually write to the surface.
4316 * Even though stencil may be plane 1, it always shares a base_level
4319 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
4320 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4321 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4322 VK_IMAGE_ASPECT_DEPTH_BIT
,
4323 att_state
->aux_usage
,
4324 ds_view
->base_level
,
4325 ds_view
->base_array_layer
,
4328 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4329 /* Even though stencil may be plane 1, it always shares a
4330 * base_level with depth.
4332 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4333 VK_IMAGE_ASPECT_STENCIL_BIT
,
4335 ds_view
->base_level
,
4336 ds_view
->base_array_layer
,
4341 /* If multiview is enabled, then we are only done clearing when we no
4342 * longer have pending layers to clear, or when we have processed the
4343 * last subpass that uses this attachment.
4345 if (!is_multiview
||
4346 att_state
->pending_clear_views
== 0 ||
4347 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
4348 att_state
->pending_clear_aspects
= 0;
4351 att_state
->pending_load_aspects
= 0;
4354 cmd_buffer_emit_depth_stencil(cmd_buffer
);
4357 static enum blorp_filter
4358 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
4361 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
4362 return BLORP_FILTER_SAMPLE_0
;
4363 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
4364 return BLORP_FILTER_AVERAGE
;
4365 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
4366 return BLORP_FILTER_MIN_SAMPLE
;
4367 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
4368 return BLORP_FILTER_MAX_SAMPLE
;
4370 return BLORP_FILTER_NONE
;
4375 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
4377 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4378 struct anv_subpass
*subpass
= cmd_state
->subpass
;
4379 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
4380 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4382 if (subpass
->has_color_resolve
) {
4383 /* We are about to do some MSAA resolves. We need to flush so that the
4384 * result of writes to the MSAA color attachments show up in the sampler
4385 * when we blit to the single-sampled resolve target.
4387 cmd_buffer
->state
.pending_pipe_bits
|=
4388 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4389 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
4391 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
4392 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
4393 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
4395 if (dst_att
== VK_ATTACHMENT_UNUSED
)
4398 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4399 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4401 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4402 /* From the Vulkan 1.0 spec:
4404 * If the first use of an attachment in a render pass is as a
4405 * resolve attachment, then the loadOp is effectively ignored
4406 * as the resolve is guaranteed to overwrite all pixels in the
4409 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4412 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
4413 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
4415 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4417 enum isl_aux_usage src_aux_usage
=
4418 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
4419 enum isl_aux_usage dst_aux_usage
=
4420 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
4422 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
4423 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
4425 anv_image_msaa_resolve(cmd_buffer
,
4426 src_iview
->image
, src_aux_usage
,
4427 src_iview
->planes
[0].isl
.base_level
,
4428 src_iview
->planes
[0].isl
.base_array_layer
,
4429 dst_iview
->image
, dst_aux_usage
,
4430 dst_iview
->planes
[0].isl
.base_level
,
4431 dst_iview
->planes
[0].isl
.base_array_layer
,
4432 VK_IMAGE_ASPECT_COLOR_BIT
,
4433 render_area
.offset
.x
, render_area
.offset
.y
,
4434 render_area
.offset
.x
, render_area
.offset
.y
,
4435 render_area
.extent
.width
,
4436 render_area
.extent
.height
,
4437 fb
->layers
, BLORP_FILTER_NONE
);
4441 if (subpass
->ds_resolve_attachment
) {
4442 /* We are about to do some MSAA resolves. We need to flush so that the
4443 * result of writes to the MSAA depth attachments show up in the sampler
4444 * when we blit to the single-sampled resolve target.
4446 cmd_buffer
->state
.pending_pipe_bits
|=
4447 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4448 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
4450 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
4451 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
4453 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4454 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4456 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4457 /* From the Vulkan 1.0 spec:
4459 * If the first use of an attachment in a render pass is as a
4460 * resolve attachment, then the loadOp is effectively ignored
4461 * as the resolve is guaranteed to overwrite all pixels in the
4464 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4467 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
4468 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
4470 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4472 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
4473 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4475 struct anv_attachment_state
*src_state
=
4476 &cmd_state
->attachments
[src_att
];
4477 struct anv_attachment_state
*dst_state
=
4478 &cmd_state
->attachments
[dst_att
];
4480 /* MSAA resolves sample from the source attachment. Transition the
4481 * depth attachment first to get rid of any HiZ that we may not be
4484 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
4485 src_state
->current_layout
,
4486 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4487 src_state
->aux_usage
=
4488 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
4489 VK_IMAGE_ASPECT_DEPTH_BIT
,
4490 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4491 src_state
->current_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
4493 /* MSAA resolves write to the resolve attachment as if it were any
4494 * other transfer op. Transition the resolve attachment accordingly.
4496 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
4498 /* If our render area is the entire size of the image, we're going to
4499 * blow it all away so we can claim the initial layout is UNDEFINED
4500 * and we'll get a HiZ ambiguate instead of a resolve.
4502 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
4503 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
4504 render_area
.extent
.width
== dst_iview
->extent
.width
&&
4505 render_area
.extent
.height
== dst_iview
->extent
.height
)
4506 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
4508 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
4510 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4511 dst_state
->aux_usage
=
4512 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
4513 VK_IMAGE_ASPECT_DEPTH_BIT
,
4514 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4515 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
4517 enum blorp_filter filter
=
4518 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
4520 anv_image_msaa_resolve(cmd_buffer
,
4521 src_iview
->image
, src_state
->aux_usage
,
4522 src_iview
->planes
[0].isl
.base_level
,
4523 src_iview
->planes
[0].isl
.base_array_layer
,
4524 dst_iview
->image
, dst_state
->aux_usage
,
4525 dst_iview
->planes
[0].isl
.base_level
,
4526 dst_iview
->planes
[0].isl
.base_array_layer
,
4527 VK_IMAGE_ASPECT_DEPTH_BIT
,
4528 render_area
.offset
.x
, render_area
.offset
.y
,
4529 render_area
.offset
.x
, render_area
.offset
.y
,
4530 render_area
.extent
.width
,
4531 render_area
.extent
.height
,
4532 fb
->layers
, filter
);
4535 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
4536 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4538 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
4539 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
4541 enum blorp_filter filter
=
4542 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
4544 anv_image_msaa_resolve(cmd_buffer
,
4545 src_iview
->image
, src_aux_usage
,
4546 src_iview
->planes
[0].isl
.base_level
,
4547 src_iview
->planes
[0].isl
.base_array_layer
,
4548 dst_iview
->image
, dst_aux_usage
,
4549 dst_iview
->planes
[0].isl
.base_level
,
4550 dst_iview
->planes
[0].isl
.base_array_layer
,
4551 VK_IMAGE_ASPECT_STENCIL_BIT
,
4552 render_area
.offset
.x
, render_area
.offset
.y
,
4553 render_area
.offset
.x
, render_area
.offset
.y
,
4554 render_area
.extent
.width
,
4555 render_area
.extent
.height
,
4556 fb
->layers
, filter
);
4561 /* On gen7, we have to store a texturable version of the stencil buffer in
4562 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
4563 * forth at strategic points. Stencil writes are only allowed in three
4566 * - VK_IMAGE_LAYOUT_GENERAL
4567 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
4568 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
4569 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
4571 * For general, we have no nice opportunity to transition so we do the copy
4572 * to the shadow unconditionally at the end of the subpass. For transfer
4573 * destinations, we can update it as part of the transfer op. For the
4574 * other two, we delay the copy until a transition into some other layout.
4576 if (subpass
->depth_stencil_attachment
) {
4577 uint32_t a
= subpass
->depth_stencil_attachment
->attachment
;
4578 assert(a
!= VK_ATTACHMENT_UNUSED
);
4580 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4581 struct anv_image_view
*iview
= fb
->attachments
[a
];
4582 const struct anv_image
*image
= iview
->image
;
4584 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4585 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
4586 VK_IMAGE_ASPECT_STENCIL_BIT
);
4588 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
4589 att_state
->current_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
4590 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
4591 anv_image_copy_to_shadow(cmd_buffer
, image
,
4592 VK_IMAGE_ASPECT_STENCIL_BIT
,
4593 iview
->planes
[plane
].isl
.base_level
, 1,
4594 iview
->planes
[plane
].isl
.base_array_layer
,
4599 #endif /* GEN_GEN == 7 */
4601 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4602 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4603 if (a
== VK_ATTACHMENT_UNUSED
)
4606 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4609 assert(a
< cmd_state
->pass
->attachment_count
);
4610 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4611 struct anv_image_view
*iview
= fb
->attachments
[a
];
4612 const struct anv_image
*image
= iview
->image
;
4614 if ((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4615 image
->vk_format
!= iview
->vk_format
) {
4616 enum anv_fast_clear_type fast_clear_type
=
4617 anv_layout_to_fast_clear_type(&cmd_buffer
->device
->info
,
4618 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4619 att_state
->current_layout
);
4621 /* If any clear color was used, flush it down the aux surfaces. If we
4622 * don't do it now using the view's format we might use the clear
4623 * color incorrectly in the following resolves (for example with an
4624 * SRGB view & a UNORM image).
4626 if (fast_clear_type
!= ANV_FAST_CLEAR_NONE
) {
4627 anv_perf_warn(cmd_buffer
->device
->instance
, fb
,
4628 "Doing a partial resolve to get rid of clear color at the "
4629 "end of a renderpass due to an image/view format mismatch");
4631 uint32_t base_layer
, layer_count
;
4632 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4634 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4635 iview
->planes
[0].isl
.base_level
);
4637 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4638 layer_count
= fb
->layers
;
4641 for (uint32_t a
= 0; a
< layer_count
; a
++) {
4642 uint32_t array_layer
= base_layer
+ a
;
4643 if (image
->samples
== 1) {
4644 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
4645 iview
->planes
[0].isl
.format
,
4646 VK_IMAGE_ASPECT_COLOR_BIT
,
4647 iview
->planes
[0].isl
.base_level
,
4649 ISL_AUX_OP_PARTIAL_RESOLVE
,
4650 ANV_FAST_CLEAR_NONE
);
4652 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
4653 iview
->planes
[0].isl
.format
,
4654 VK_IMAGE_ASPECT_COLOR_BIT
,
4656 ISL_AUX_OP_PARTIAL_RESOLVE
,
4657 ANV_FAST_CLEAR_NONE
);
4663 /* Transition the image into the final layout for this render pass */
4664 VkImageLayout target_layout
=
4665 cmd_state
->pass
->attachments
[a
].final_layout
;
4667 uint32_t base_layer
, layer_count
;
4668 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4670 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4671 iview
->planes
[0].isl
.base_level
);
4673 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4674 layer_count
= fb
->layers
;
4677 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4678 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4679 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4680 iview
->planes
[0].isl
.base_level
, 1,
4681 base_layer
, layer_count
,
4682 att_state
->current_layout
, target_layout
);
4685 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4686 transition_depth_buffer(cmd_buffer
, image
,
4687 att_state
->current_layout
, target_layout
);
4690 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4691 transition_stencil_buffer(cmd_buffer
, image
,
4692 iview
->planes
[0].isl
.base_level
, 1,
4693 base_layer
, layer_count
,
4694 att_state
->current_layout
, target_layout
);
4698 /* Accumulate any subpass flushes that need to happen after the subpass.
4699 * Yes, they do get accumulated twice in the NextSubpass case but since
4700 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
4701 * ORing the bits in twice so it's harmless.
4703 cmd_buffer
->state
.pending_pipe_bits
|=
4704 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
4707 void genX(CmdBeginRenderPass
)(
4708 VkCommandBuffer commandBuffer
,
4709 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4710 VkSubpassContents contents
)
4712 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4713 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4714 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4716 cmd_buffer
->state
.framebuffer
= framebuffer
;
4717 cmd_buffer
->state
.pass
= pass
;
4718 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4720 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
4722 /* If we failed to setup the attachments we should not try to go further */
4723 if (result
!= VK_SUCCESS
) {
4724 assert(anv_batch_has_error(&cmd_buffer
->batch
));
4728 genX(flush_pipeline_select_3d
)(cmd_buffer
);
4730 cmd_buffer_begin_subpass(cmd_buffer
, 0);
4733 void genX(CmdBeginRenderPass2KHR
)(
4734 VkCommandBuffer commandBuffer
,
4735 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4736 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
4738 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
4739 pSubpassBeginInfo
->contents
);
4742 void genX(CmdNextSubpass
)(
4743 VkCommandBuffer commandBuffer
,
4744 VkSubpassContents contents
)
4746 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4748 if (anv_batch_has_error(&cmd_buffer
->batch
))
4751 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4753 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
4754 cmd_buffer_end_subpass(cmd_buffer
);
4755 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4758 void genX(CmdNextSubpass2KHR
)(
4759 VkCommandBuffer commandBuffer
,
4760 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
4761 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4763 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
4766 void genX(CmdEndRenderPass
)(
4767 VkCommandBuffer commandBuffer
)
4769 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4771 if (anv_batch_has_error(&cmd_buffer
->batch
))
4774 cmd_buffer_end_subpass(cmd_buffer
);
4776 cmd_buffer
->state
.hiz_enabled
= false;
4779 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
4782 /* Remove references to render pass specific state. This enables us to
4783 * detect whether or not we're in a renderpass.
4785 cmd_buffer
->state
.framebuffer
= NULL
;
4786 cmd_buffer
->state
.pass
= NULL
;
4787 cmd_buffer
->state
.subpass
= NULL
;
4790 void genX(CmdEndRenderPass2KHR
)(
4791 VkCommandBuffer commandBuffer
,
4792 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4794 genX(CmdEndRenderPass
)(commandBuffer
);
4798 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
4800 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4801 struct gen_mi_builder b
;
4802 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4804 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
4805 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
4806 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
4808 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
4809 mip
.LoadOperation
= LOAD_LOADINV
;
4810 mip
.CombineOperation
= COMBINE_SET
;
4811 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4816 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4817 void genX(CmdBeginConditionalRenderingEXT
)(
4818 VkCommandBuffer commandBuffer
,
4819 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
4821 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4822 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
4823 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4824 struct anv_address value_address
=
4825 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
4827 const bool isInverted
= pConditionalRenderingBegin
->flags
&
4828 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
4830 cmd_state
->conditional_render_enabled
= true;
4832 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4834 struct gen_mi_builder b
;
4835 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4837 /* Section 19.4 of the Vulkan 1.1.85 spec says:
4839 * If the value of the predicate in buffer memory changes
4840 * while conditional rendering is active, the rendering commands
4841 * may be discarded in an implementation-dependent way.
4842 * Some implementations may latch the value of the predicate
4843 * upon beginning conditional rendering while others
4844 * may read it before every rendering command.
4846 * So it's perfectly fine to read a value from the buffer once.
4848 struct gen_mi_value value
= gen_mi_mem32(value_address
);
4850 /* Precompute predicate result, it is necessary to support secondary
4851 * command buffers since it is unknown if conditional rendering is
4852 * inverted when populating them.
4854 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
4855 isInverted
? gen_mi_uge(&b
, gen_mi_imm(0), value
) :
4856 gen_mi_ult(&b
, gen_mi_imm(0), value
));
4859 void genX(CmdEndConditionalRenderingEXT
)(
4860 VkCommandBuffer commandBuffer
)
4862 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4863 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4865 cmd_state
->conditional_render_enabled
= false;
4869 /* Set of stage bits for which are pipelined, i.e. they get queued by the
4870 * command streamer for later execution.
4872 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
4873 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
4874 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
4875 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
4876 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
4877 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
4878 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
4879 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
4880 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
4881 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
4882 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
4883 VK_PIPELINE_STAGE_TRANSFER_BIT | \
4884 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
4885 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
4886 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
4888 void genX(CmdSetEvent
)(
4889 VkCommandBuffer commandBuffer
,
4891 VkPipelineStageFlags stageMask
)
4893 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4894 ANV_FROM_HANDLE(anv_event
, event
, _event
);
4896 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4897 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
4898 pc
.StallAtPixelScoreboard
= true;
4899 pc
.CommandStreamerStallEnable
= true;
4902 pc
.DestinationAddressType
= DAT_PPGTT
,
4903 pc
.PostSyncOperation
= WriteImmediateData
,
4904 pc
.Address
= (struct anv_address
) {
4905 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4908 pc
.ImmediateData
= VK_EVENT_SET
;
4912 void genX(CmdResetEvent
)(
4913 VkCommandBuffer commandBuffer
,
4915 VkPipelineStageFlags stageMask
)
4917 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4918 ANV_FROM_HANDLE(anv_event
, event
, _event
);
4920 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4921 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
4922 pc
.StallAtPixelScoreboard
= true;
4923 pc
.CommandStreamerStallEnable
= true;
4926 pc
.DestinationAddressType
= DAT_PPGTT
;
4927 pc
.PostSyncOperation
= WriteImmediateData
;
4928 pc
.Address
= (struct anv_address
) {
4929 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4932 pc
.ImmediateData
= VK_EVENT_RESET
;
4936 void genX(CmdWaitEvents
)(
4937 VkCommandBuffer commandBuffer
,
4938 uint32_t eventCount
,
4939 const VkEvent
* pEvents
,
4940 VkPipelineStageFlags srcStageMask
,
4941 VkPipelineStageFlags destStageMask
,
4942 uint32_t memoryBarrierCount
,
4943 const VkMemoryBarrier
* pMemoryBarriers
,
4944 uint32_t bufferMemoryBarrierCount
,
4945 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
4946 uint32_t imageMemoryBarrierCount
,
4947 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
4950 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4952 for (uint32_t i
= 0; i
< eventCount
; i
++) {
4953 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
4955 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
4956 sem
.WaitMode
= PollingMode
,
4957 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
4958 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
4959 sem
.SemaphoreAddress
= (struct anv_address
) {
4960 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4966 anv_finishme("Implement events on gen7");
4969 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
4970 false, /* byRegion */
4971 memoryBarrierCount
, pMemoryBarriers
,
4972 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
4973 imageMemoryBarrierCount
, pImageMemoryBarriers
);