2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_aux_map.h"
33 #include "common/gen_l3_config.h"
34 #include "genxml/gen_macros.h"
35 #include "genxml/genX_pack.h"
37 /* We reserve GPR 14 and 15 for conditional rendering */
38 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
39 #define __gen_get_batch_dwords anv_batch_emit_dwords
40 #define __gen_address_offset anv_address_add
41 #include "common/gen_mi_builder.h"
44 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
46 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
47 lri
.RegisterOffset
= reg
;
53 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
55 struct anv_device
*device
= cmd_buffer
->device
;
56 uint32_t mocs
= device
->isl_dev
.mocs
.internal
;
58 /* If we are emitting a new state base address we probably need to re-emit
61 cmd_buffer
->state
.descriptors_dirty
|= ~0;
63 /* Emit a render target cache flush.
65 * This isn't documented anywhere in the PRM. However, it seems to be
66 * necessary prior to changing the surface state base adress. Without
67 * this, we get GPU hangs when using multi-level command buffers which
68 * clear depth, reset state base address, and then go render stuff.
70 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
71 pc
.DCFlushEnable
= true;
72 pc
.RenderTargetCacheFlushEnable
= true;
73 pc
.CommandStreamerStallEnable
= true;
75 pc
.TileCacheFlushEnable
= true;
79 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
80 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
81 sba
.GeneralStateMOCS
= mocs
;
82 sba
.GeneralStateBaseAddressModifyEnable
= true;
84 sba
.StatelessDataPortAccessMOCS
= mocs
;
86 sba
.SurfaceStateBaseAddress
=
87 anv_cmd_buffer_surface_base_address(cmd_buffer
);
88 sba
.SurfaceStateMOCS
= mocs
;
89 sba
.SurfaceStateBaseAddressModifyEnable
= true;
91 sba
.DynamicStateBaseAddress
=
92 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
93 sba
.DynamicStateMOCS
= mocs
;
94 sba
.DynamicStateBaseAddressModifyEnable
= true;
96 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
97 sba
.IndirectObjectMOCS
= mocs
;
98 sba
.IndirectObjectBaseAddressModifyEnable
= true;
100 sba
.InstructionBaseAddress
=
101 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
102 sba
.InstructionMOCS
= mocs
;
103 sba
.InstructionBaseAddressModifyEnable
= true;
106 /* Broadwell requires that we specify a buffer size for a bunch of
107 * these fields. However, since we will be growing the BO's live, we
108 * just set them all to the maximum.
110 sba
.GeneralStateBufferSize
= 0xfffff;
111 sba
.GeneralStateBufferSizeModifyEnable
= true;
112 sba
.DynamicStateBufferSize
= 0xfffff;
113 sba
.DynamicStateBufferSizeModifyEnable
= true;
114 sba
.IndirectObjectBufferSize
= 0xfffff;
115 sba
.IndirectObjectBufferSizeModifyEnable
= true;
116 sba
.InstructionBufferSize
= 0xfffff;
117 sba
.InstructionBuffersizeModifyEnable
= true;
119 /* On gen7, we have upper bounds instead. According to the docs,
120 * setting an upper bound of zero means that no bounds checking is
121 * performed so, in theory, we should be able to leave them zero.
122 * However, border color is broken and the GPU bounds-checks anyway.
123 * To avoid this and other potential problems, we may as well set it
126 sba
.GeneralStateAccessUpperBound
=
127 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
128 sba
.GeneralStateAccessUpperBoundModifyEnable
= true;
129 sba
.DynamicStateAccessUpperBound
=
130 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
131 sba
.DynamicStateAccessUpperBoundModifyEnable
= true;
132 sba
.InstructionAccessUpperBound
=
133 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
134 sba
.InstructionAccessUpperBoundModifyEnable
= true;
137 if (cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
) {
138 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) {
139 .bo
= device
->surface_state_pool
.block_pool
.bo
,
142 sba
.BindlessSurfaceStateSize
= (1 << 20) - 1;
144 sba
.BindlessSurfaceStateBaseAddress
= ANV_NULL_ADDRESS
;
145 sba
.BindlessSurfaceStateSize
= 0;
147 sba
.BindlessSurfaceStateMOCS
= mocs
;
148 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
151 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
152 sba
.BindlessSamplerStateMOCS
= mocs
;
153 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
154 sba
.BindlessSamplerStateBufferSize
= 0;
158 /* After re-setting the surface state base address, we have to do some
159 * cache flusing so that the sampler engine will pick up the new
160 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
161 * Shared Function > 3D Sampler > State > State Caching (page 96):
163 * Coherency with system memory in the state cache, like the texture
164 * cache is handled partially by software. It is expected that the
165 * command stream or shader will issue Cache Flush operation or
166 * Cache_Flush sampler message to ensure that the L1 cache remains
167 * coherent with system memory.
171 * Whenever the value of the Dynamic_State_Base_Addr,
172 * Surface_State_Base_Addr are altered, the L1 state cache must be
173 * invalidated to ensure the new surface or sampler state is fetched
174 * from system memory.
176 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
177 * which, according the PIPE_CONTROL instruction documentation in the
180 * Setting this bit is independent of any other bit in this packet.
181 * This bit controls the invalidation of the L1 and L2 state caches
182 * at the top of the pipe i.e. at the parsing time.
184 * Unfortunately, experimentation seems to indicate that state cache
185 * invalidation through a PIPE_CONTROL does nothing whatsoever in
186 * regards to surface state and binding tables. In stead, it seems that
187 * invalidating the texture cache is what is actually needed.
189 * XXX: As far as we have been able to determine through
190 * experimentation, shows that flush the texture cache appears to be
191 * sufficient. The theory here is that all of the sampling/rendering
192 * units cache the binding table in the texture cache. However, we have
193 * yet to be able to actually confirm this.
195 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
196 pc
.TextureCacheInvalidationEnable
= true;
197 pc
.ConstantCacheInvalidationEnable
= true;
198 pc
.StateCacheInvalidationEnable
= true;
203 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
204 struct anv_state state
, struct anv_address addr
)
206 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
209 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
210 state
.offset
+ isl_dev
->ss
.addr_offset
,
211 addr
.bo
, addr
.offset
, NULL
);
212 if (result
!= VK_SUCCESS
)
213 anv_batch_set_error(&cmd_buffer
->batch
, result
);
217 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
218 struct anv_surface_state state
)
220 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
222 assert(!anv_address_is_null(state
.address
));
223 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
225 if (!anv_address_is_null(state
.aux_address
)) {
227 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
228 &cmd_buffer
->pool
->alloc
,
229 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
230 state
.aux_address
.bo
,
231 state
.aux_address
.offset
,
233 if (result
!= VK_SUCCESS
)
234 anv_batch_set_error(&cmd_buffer
->batch
, result
);
237 if (!anv_address_is_null(state
.clear_address
)) {
239 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
240 &cmd_buffer
->pool
->alloc
,
242 isl_dev
->ss
.clear_color_state_offset
,
243 state
.clear_address
.bo
,
244 state
.clear_address
.offset
,
246 if (result
!= VK_SUCCESS
)
247 anv_batch_set_error(&cmd_buffer
->batch
, result
);
252 color_attachment_compute_aux_usage(struct anv_device
* device
,
253 struct anv_cmd_state
* cmd_state
,
254 uint32_t att
, VkRect2D render_area
,
255 union isl_color_value
*fast_clear_color
)
257 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
258 struct anv_image_view
*iview
= cmd_state
->attachments
[att
].image_view
;
260 assert(iview
->n_planes
== 1);
262 if (iview
->planes
[0].isl
.base_array_layer
>=
263 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
264 iview
->planes
[0].isl
.base_level
)) {
265 /* There is no aux buffer which corresponds to the level and layer(s)
268 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
269 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
270 att_state
->fast_clear
= false;
274 att_state
->aux_usage
=
275 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
276 VK_IMAGE_ASPECT_COLOR_BIT
,
277 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
279 /* If we don't have aux, then we should have returned early in the layer
280 * check above. If we got here, we must have something.
282 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
284 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
285 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
286 att_state
->input_aux_usage
= att_state
->aux_usage
;
288 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
290 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
291 * setting is only allowed if Surface Format supported for Fast
292 * Clear. In addition, if the surface is bound to the sampling
293 * engine, Surface Format must be supported for Render Target
294 * Compression for surfaces bound to the sampling engine."
296 * In other words, we can only sample from a fast-cleared image if it
297 * also supports color compression.
299 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
) &&
300 isl_format_supports_ccs_d(&device
->info
, iview
->planes
[0].isl
.format
)) {
301 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
303 /* While fast-clear resolves and partial resolves are fairly cheap in the
304 * case where you render to most of the pixels, full resolves are not
305 * because they potentially involve reading and writing the entire
306 * framebuffer. If we can't texture with CCS_E, we should leave it off and
307 * limit ourselves to fast clears.
309 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
310 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
311 anv_perf_warn(device
->instance
, iview
->image
,
312 "Not temporarily enabling CCS_E.");
315 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
319 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
320 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
322 union isl_color_value clear_color
= {};
323 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
325 att_state
->clear_color_is_zero_one
=
326 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
327 att_state
->clear_color_is_zero
=
328 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
330 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
331 /* Start by getting the fast clear type. We use the first subpass
332 * layout here because we don't want to fast-clear if the first subpass
333 * to use the attachment can't handle fast-clears.
335 enum anv_fast_clear_type fast_clear_type
=
336 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
337 VK_IMAGE_ASPECT_COLOR_BIT
,
338 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
339 switch (fast_clear_type
) {
340 case ANV_FAST_CLEAR_NONE
:
341 att_state
->fast_clear
= false;
343 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
344 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
346 case ANV_FAST_CLEAR_ANY
:
347 att_state
->fast_clear
= true;
351 /* Potentially, we could do partial fast-clears but doing so has crazy
352 * alignment restrictions. It's easier to just restrict to full size
353 * fast clears for now.
355 if (render_area
.offset
.x
!= 0 ||
356 render_area
.offset
.y
!= 0 ||
357 render_area
.extent
.width
!= iview
->extent
.width
||
358 render_area
.extent
.height
!= iview
->extent
.height
)
359 att_state
->fast_clear
= false;
361 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
362 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
363 att_state
->fast_clear
= false;
365 /* We only allow fast clears to the first slice of an image (level 0,
366 * layer 0) and only for the entire slice. This guarantees us that, at
367 * any given time, there is only one clear color on any given image at
368 * any given time. At the time of our testing (Jan 17, 2018), there
369 * were no known applications which would benefit from fast-clearing
370 * more than just the first slice.
372 if (att_state
->fast_clear
&&
373 (iview
->planes
[0].isl
.base_level
> 0 ||
374 iview
->planes
[0].isl
.base_array_layer
> 0)) {
375 anv_perf_warn(device
->instance
, iview
->image
,
376 "Rendering with multi-lod or multi-layer framebuffer "
377 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
378 "baseArrayLayer > 0. Not fast clearing.");
379 att_state
->fast_clear
= false;
380 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
381 anv_perf_warn(device
->instance
, iview
->image
,
382 "Rendering to a multi-layer framebuffer with "
383 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
386 if (att_state
->fast_clear
)
387 *fast_clear_color
= clear_color
;
389 att_state
->fast_clear
= false;
394 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
395 struct anv_cmd_state
*cmd_state
,
396 uint32_t att
, VkRect2D render_area
)
398 struct anv_render_pass_attachment
*pass_att
=
399 &cmd_state
->pass
->attachments
[att
];
400 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
401 struct anv_image_view
*iview
= cmd_state
->attachments
[att
].image_view
;
403 /* These will be initialized after the first subpass transition. */
404 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
405 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
408 /* We don't do any HiZ or depth fast-clears on gen7 yet */
409 att_state
->fast_clear
= false;
413 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
414 /* If we're just clearing stencil, we can always HiZ clear */
415 att_state
->fast_clear
= true;
419 /* Default to false for now */
420 att_state
->fast_clear
= false;
422 /* We must have depth in order to have HiZ */
423 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
426 const enum isl_aux_usage first_subpass_aux_usage
=
427 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
428 VK_IMAGE_ASPECT_DEPTH_BIT
,
429 pass_att
->first_subpass_layout
);
430 if (!blorp_can_hiz_clear_depth(&device
->info
,
431 &iview
->image
->planes
[0].surface
.isl
,
432 first_subpass_aux_usage
,
433 iview
->planes
[0].isl
.base_level
,
434 iview
->planes
[0].isl
.base_array_layer
,
435 render_area
.offset
.x
,
436 render_area
.offset
.y
,
437 render_area
.offset
.x
+
438 render_area
.extent
.width
,
439 render_area
.offset
.y
+
440 render_area
.extent
.height
))
443 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
446 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
447 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
448 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
449 * only supports returning 0.0f. Gens prior to gen8 do not support this
455 /* If we got here, then we can fast clear */
456 att_state
->fast_clear
= true;
460 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
462 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
465 /* We only allocate input attachment states for color surfaces. Compression
466 * is not yet enabled for depth textures and stencil doesn't allow
467 * compression so we can just use the texture surface state from the view.
469 return vk_format_is_color(att
->format
);
472 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
473 * the initial layout is undefined, the HiZ buffer and depth buffer will
474 * represent the same data at the end of this operation.
477 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
478 const struct anv_image
*image
,
479 VkImageLayout initial_layout
,
480 VkImageLayout final_layout
)
482 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
483 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
484 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
485 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
486 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
487 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
489 enum isl_aux_op hiz_op
;
490 if (hiz_enabled
&& !enable_hiz
) {
491 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
492 } else if (!hiz_enabled
&& enable_hiz
) {
493 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
495 assert(hiz_enabled
== enable_hiz
);
496 /* If the same buffer will be used, no resolves are necessary. */
497 hiz_op
= ISL_AUX_OP_NONE
;
500 if (hiz_op
!= ISL_AUX_OP_NONE
)
501 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
506 vk_image_layout_stencil_write_optimal(VkImageLayout layout
)
508 return layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
509 layout
== VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
||
510 layout
== VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
;
513 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
514 * the initial layout is undefined, the HiZ buffer and depth buffer will
515 * represent the same data at the end of this operation.
518 transition_stencil_buffer(struct anv_cmd_buffer
*cmd_buffer
,
519 const struct anv_image
*image
,
520 uint32_t base_level
, uint32_t level_count
,
521 uint32_t base_layer
, uint32_t layer_count
,
522 VkImageLayout initial_layout
,
523 VkImageLayout final_layout
)
526 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
527 VK_IMAGE_ASPECT_STENCIL_BIT
);
529 /* On gen7, we have to store a texturable version of the stencil buffer in
530 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
531 * forth at strategic points. Stencil writes are only allowed in following
534 * - VK_IMAGE_LAYOUT_GENERAL
535 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
536 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
537 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
538 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
540 * For general, we have no nice opportunity to transition so we do the copy
541 * to the shadow unconditionally at the end of the subpass. For transfer
542 * destinations, we can update it as part of the transfer op. For the other
543 * layouts, we delay the copy until a transition into some other layout.
545 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
546 vk_image_layout_stencil_write_optimal(initial_layout
) &&
547 !vk_image_layout_stencil_write_optimal(final_layout
)) {
548 anv_image_copy_to_shadow(cmd_buffer
, image
,
549 VK_IMAGE_ASPECT_STENCIL_BIT
,
550 base_level
, level_count
,
551 base_layer
, layer_count
);
553 #endif /* GEN_GEN == 7 */
556 #define MI_PREDICATE_SRC0 0x2400
557 #define MI_PREDICATE_SRC1 0x2408
558 #define MI_PREDICATE_RESULT 0x2418
561 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
562 const struct anv_image
*image
,
563 VkImageAspectFlagBits aspect
,
565 uint32_t base_layer
, uint32_t layer_count
,
568 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
570 /* We only have compression tracking for CCS_E */
571 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
574 for (uint32_t a
= 0; a
< layer_count
; a
++) {
575 uint32_t layer
= base_layer
+ a
;
576 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
577 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
580 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
586 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
587 const struct anv_image
*image
,
588 VkImageAspectFlagBits aspect
,
589 enum anv_fast_clear_type fast_clear
)
591 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
592 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
594 sdi
.ImmediateData
= fast_clear
;
597 /* Whenever we have fast-clear, we consider that slice to be compressed.
598 * This makes building predicates much easier.
600 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
601 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
604 /* This is only really practical on haswell and above because it requires
605 * MI math in order to get it correct.
607 #if GEN_GEN >= 8 || GEN_IS_HASWELL
609 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
610 const struct anv_image
*image
,
611 VkImageAspectFlagBits aspect
,
612 uint32_t level
, uint32_t array_layer
,
613 enum isl_aux_op resolve_op
,
614 enum anv_fast_clear_type fast_clear_supported
)
616 struct gen_mi_builder b
;
617 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
619 const struct gen_mi_value fast_clear_type
=
620 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
623 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
624 /* In this case, we're doing a full resolve which means we want the
625 * resolve to happen if any compression (including fast-clears) is
628 * In order to simplify the logic a bit, we make the assumption that,
629 * if the first slice has been fast-cleared, it is also marked as
630 * compressed. See also set_image_fast_clear_state.
632 const struct gen_mi_value compression_state
=
633 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer
->device
,
635 level
, array_layer
));
636 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
638 gen_mi_store(&b
, compression_state
, gen_mi_imm(0));
640 if (level
== 0 && array_layer
== 0) {
641 /* If the predicate is true, we want to write 0 to the fast clear type
642 * and, if it's false, leave it alone. We can do this by writing
644 * clear_type = clear_type & ~predicate;
646 struct gen_mi_value new_fast_clear_type
=
647 gen_mi_iand(&b
, fast_clear_type
,
648 gen_mi_inot(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
)));
649 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
651 } else if (level
== 0 && array_layer
== 0) {
652 /* In this case, we are doing a partial resolve to get rid of fast-clear
653 * colors. We don't care about the compression state but we do care
654 * about how much fast clear is allowed by the final layout.
656 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
657 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
659 /* We need to compute (fast_clear_supported < image->fast_clear) */
660 struct gen_mi_value pred
=
661 gen_mi_ult(&b
, gen_mi_imm(fast_clear_supported
), fast_clear_type
);
662 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
663 gen_mi_value_ref(&b
, pred
));
665 /* If the predicate is true, we want to write 0 to the fast clear type
666 * and, if it's false, leave it alone. We can do this by writing
668 * clear_type = clear_type & ~predicate;
670 struct gen_mi_value new_fast_clear_type
=
671 gen_mi_iand(&b
, fast_clear_type
, gen_mi_inot(&b
, pred
));
672 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
674 /* In this case, we're trying to do a partial resolve on a slice that
675 * doesn't have clear color. There's nothing to do.
677 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
681 /* Set src1 to 0 and use a != condition */
682 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
684 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
685 mip
.LoadOperation
= LOAD_LOADINV
;
686 mip
.CombineOperation
= COMBINE_SET
;
687 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
690 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
694 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
695 const struct anv_image
*image
,
696 VkImageAspectFlagBits aspect
,
697 uint32_t level
, uint32_t array_layer
,
698 enum isl_aux_op resolve_op
,
699 enum anv_fast_clear_type fast_clear_supported
)
701 struct gen_mi_builder b
;
702 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
704 struct gen_mi_value fast_clear_type_mem
=
705 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
708 /* This only works for partial resolves and only when the clear color is
709 * all or nothing. On the upside, this emits less command streamer code
710 * and works on Ivybridge and Bay Trail.
712 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
713 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
715 /* We don't support fast clears on anything other than the first slice. */
716 if (level
> 0 || array_layer
> 0)
719 /* On gen8, we don't have a concept of default clear colors because we
720 * can't sample from CCS surfaces. It's enough to just load the fast clear
721 * state into the predicate register.
723 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), fast_clear_type_mem
);
724 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
725 gen_mi_store(&b
, fast_clear_type_mem
, gen_mi_imm(0));
727 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
728 mip
.LoadOperation
= LOAD_LOADINV
;
729 mip
.CombineOperation
= COMBINE_SET
;
730 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
733 #endif /* GEN_GEN <= 8 */
736 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
737 const struct anv_image
*image
,
738 enum isl_format format
,
739 VkImageAspectFlagBits aspect
,
740 uint32_t level
, uint32_t array_layer
,
741 enum isl_aux_op resolve_op
,
742 enum anv_fast_clear_type fast_clear_supported
)
744 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
747 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
748 aspect
, level
, array_layer
,
749 resolve_op
, fast_clear_supported
);
750 #else /* GEN_GEN <= 8 */
751 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
752 aspect
, level
, array_layer
,
753 resolve_op
, fast_clear_supported
);
756 /* CCS_D only supports full resolves and BLORP will assert on us if we try
757 * to do a partial resolve on a CCS_D surface.
759 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
760 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
761 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
763 anv_image_ccs_op(cmd_buffer
, image
, format
, aspect
, level
,
764 array_layer
, 1, resolve_op
, NULL
, true);
768 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
769 const struct anv_image
*image
,
770 enum isl_format format
,
771 VkImageAspectFlagBits aspect
,
772 uint32_t array_layer
,
773 enum isl_aux_op resolve_op
,
774 enum anv_fast_clear_type fast_clear_supported
)
776 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
777 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
779 #if GEN_GEN >= 8 || GEN_IS_HASWELL
780 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
781 aspect
, 0, array_layer
,
782 resolve_op
, fast_clear_supported
);
784 anv_image_mcs_op(cmd_buffer
, image
, format
, aspect
,
785 array_layer
, 1, resolve_op
, NULL
, true);
787 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
792 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
793 const struct anv_image
*image
,
794 VkImageAspectFlagBits aspect
,
795 enum isl_aux_usage aux_usage
,
798 uint32_t layer_count
)
800 /* The aspect must be exactly one of the image aspects. */
801 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
803 /* The only compression types with more than just fast-clears are MCS,
804 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
805 * track the current fast-clear and compression state. This leaves us
806 * with just MCS and CCS_E.
808 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
809 aux_usage
!= ISL_AUX_USAGE_MCS
)
812 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
813 level
, base_layer
, layer_count
, true);
817 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
818 const struct anv_image
*image
,
819 VkImageAspectFlagBits aspect
)
821 assert(cmd_buffer
&& image
);
822 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
824 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
825 ANV_FAST_CLEAR_NONE
);
827 /* Initialize the struct fields that are accessed for fast-clears so that
828 * the HW restrictions on the field values are satisfied.
830 struct anv_address addr
=
831 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
834 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
835 const unsigned num_dwords
= GEN_GEN
>= 10 ?
836 isl_dev
->ss
.clear_color_state_size
/ 4 :
837 isl_dev
->ss
.clear_value_size
/ 4;
838 for (unsigned i
= 0; i
< num_dwords
; i
++) {
839 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
841 sdi
.Address
.offset
+= i
* 4;
842 sdi
.ImmediateData
= 0;
846 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
848 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
849 /* Pre-SKL, the dword containing the clear values also contains
850 * other fields, so we need to initialize those fields to match the
851 * values that would be in a color attachment.
853 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
854 ISL_CHANNEL_SELECT_GREEN
<< 22 |
855 ISL_CHANNEL_SELECT_BLUE
<< 19 |
856 ISL_CHANNEL_SELECT_ALPHA
<< 16;
857 } else if (GEN_GEN
== 7) {
858 /* On IVB, the dword containing the clear values also contains
859 * other fields that must be zero or can be zero.
861 sdi
.ImmediateData
= 0;
867 /* Copy the fast-clear value dword(s) between a surface state object and an
868 * image's fast clear state buffer.
871 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
872 struct anv_state surface_state
,
873 const struct anv_image
*image
,
874 VkImageAspectFlagBits aspect
,
875 bool copy_from_surface_state
)
877 assert(cmd_buffer
&& image
);
878 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
880 struct anv_address ss_clear_addr
= {
881 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
882 .offset
= surface_state
.offset
+
883 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
885 const struct anv_address entry_addr
=
886 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
887 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
890 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
891 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
892 * in-flight when they are issued even if the memory touched is not
893 * currently active for rendering. The weird bit is that it is not the
894 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
895 * rendering hangs such that the next stalling command after the
896 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
898 * It is unclear exactly why this hang occurs. Both MI commands come with
899 * warnings about the 3D pipeline but that doesn't seem to fully explain
900 * it. My (Jason's) best theory is that it has something to do with the
901 * fact that we're using a GPU state register as our temporary and that
902 * something with reading/writing it is causing problems.
904 * In order to work around this issue, we emit a PIPE_CONTROL with the
905 * command streamer stall bit set.
907 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
908 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
911 struct gen_mi_builder b
;
912 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
914 if (copy_from_surface_state
) {
915 gen_mi_memcpy(&b
, entry_addr
, ss_clear_addr
, copy_size
);
917 gen_mi_memcpy(&b
, ss_clear_addr
, entry_addr
, copy_size
);
919 /* Updating a surface state object may require that the state cache be
920 * invalidated. From the SKL PRM, Shared Functions -> State -> State
923 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
924 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
925 * modified [...], the L1 state cache must be invalidated to ensure
926 * the new surface or sampler state is fetched from system memory.
928 * In testing, SKL doesn't actually seem to need this, but HSW does.
930 cmd_buffer
->state
.pending_pipe_bits
|=
931 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
936 * @brief Transitions a color buffer from one layout to another.
938 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
941 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
942 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
943 * this represents the maximum layers to transition at each
944 * specified miplevel.
947 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
948 const struct anv_image
*image
,
949 VkImageAspectFlagBits aspect
,
950 const uint32_t base_level
, uint32_t level_count
,
951 uint32_t base_layer
, uint32_t layer_count
,
952 VkImageLayout initial_layout
,
953 VkImageLayout final_layout
)
955 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
956 /* Validate the inputs. */
958 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
959 /* These values aren't supported for simplicity's sake. */
960 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
961 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
962 /* Ensure the subresource range is valid. */
963 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
964 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
965 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
966 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
967 assert(last_level_num
<= image
->levels
);
968 /* The spec disallows these final layouts. */
969 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
970 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
972 /* No work is necessary if the layout stays the same or if this subresource
973 * range lacks auxiliary data.
975 if (initial_layout
== final_layout
)
978 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
980 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
981 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
982 /* This surface is a linear compressed image with a tiled shadow surface
983 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
984 * we need to ensure the shadow copy is up-to-date.
986 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
987 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
988 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
989 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
991 anv_image_copy_to_shadow(cmd_buffer
, image
,
992 VK_IMAGE_ASPECT_COLOR_BIT
,
993 base_level
, level_count
,
994 base_layer
, layer_count
);
997 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
1000 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
1002 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
1003 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
1004 /* A subresource in the undefined layout may have been aliased and
1005 * populated with any arrangement of bits. Therefore, we must initialize
1006 * the related aux buffer and clear buffer entry with desirable values.
1007 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
1008 * images with VK_IMAGE_TILING_OPTIMAL.
1010 * Initialize the relevant clear buffer entries.
1012 if (base_level
== 0 && base_layer
== 0)
1013 init_fast_clear_color(cmd_buffer
, image
, aspect
);
1015 /* Initialize the aux buffers to enable correct rendering. In order to
1016 * ensure that things such as storage images work correctly, aux buffers
1017 * need to be initialized to valid data.
1019 * Having an aux buffer with invalid data is a problem for two reasons:
1021 * 1) Having an invalid value in the buffer can confuse the hardware.
1022 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1023 * invalid and leads to the hardware doing strange things. It
1024 * doesn't hang as far as we can tell but rendering corruption can
1027 * 2) If this transition is into the GENERAL layout and we then use the
1028 * image as a storage image, then we must have the aux buffer in the
1029 * pass-through state so that, if we then go to texture from the
1030 * image, we get the results of our storage image writes and not the
1031 * fast clear color or other random data.
1033 * For CCS both of the problems above are real demonstrable issues. In
1034 * that case, the only thing we can do is to perform an ambiguate to
1035 * transition the aux surface into the pass-through state.
1037 * For MCS, (2) is never an issue because we don't support multisampled
1038 * storage images. In theory, issue (1) is a problem with MCS but we've
1039 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1040 * theory, be interpreted as something but we don't know that all bit
1041 * patterns are actually valid. For 2x and 8x, you could easily end up
1042 * with the MCS referring to an invalid plane because not all bits of
1043 * the MCS value are actually used. Even though we've never seen issues
1044 * in the wild, it's best to play it safe and initialize the MCS. We
1045 * can use a fast-clear for MCS because we only ever touch from render
1046 * and texture (no image load store).
1048 if (image
->samples
== 1) {
1049 for (uint32_t l
= 0; l
< level_count
; l
++) {
1050 const uint32_t level
= base_level
+ l
;
1052 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1053 if (base_layer
>= aux_layers
)
1054 break; /* We will only get fewer layers as level increases */
1055 uint32_t level_layer_count
=
1056 MIN2(layer_count
, aux_layers
- base_layer
);
1058 anv_image_ccs_op(cmd_buffer
, image
,
1059 image
->planes
[plane
].surface
.isl
.format
,
1060 aspect
, level
, base_layer
, level_layer_count
,
1061 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1063 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1064 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1065 level
, base_layer
, level_layer_count
,
1070 if (image
->samples
== 4 || image
->samples
== 16) {
1071 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1072 "Doing a potentially unnecessary fast-clear to "
1073 "define an MCS buffer.");
1076 assert(base_level
== 0 && level_count
== 1);
1077 anv_image_mcs_op(cmd_buffer
, image
,
1078 image
->planes
[plane
].surface
.isl
.format
,
1079 aspect
, base_layer
, layer_count
,
1080 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1085 const enum isl_aux_usage initial_aux_usage
=
1086 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1087 const enum isl_aux_usage final_aux_usage
=
1088 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1090 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1091 * We can handle transitions between CCS_D/E to and from NONE. What we
1092 * don't yet handle is switching between CCS_E and CCS_D within a given
1093 * image. Doing so in a performant way requires more detailed aux state
1094 * tracking such as what is done in i965. For now, just assume that we
1095 * only have one type of compression.
1097 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1098 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1099 initial_aux_usage
== final_aux_usage
);
1101 /* If initial aux usage is NONE, there is nothing to resolve */
1102 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1105 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1107 /* If the initial layout supports more fast clear than the final layout
1108 * then we need at least a partial resolve.
1110 const enum anv_fast_clear_type initial_fast_clear
=
1111 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1112 const enum anv_fast_clear_type final_fast_clear
=
1113 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1114 if (final_fast_clear
< initial_fast_clear
)
1115 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1117 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1118 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1119 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1121 if (resolve_op
== ISL_AUX_OP_NONE
)
1124 /* Perform a resolve to synchronize data between the main and aux buffer.
1125 * Before we begin, we must satisfy the cache flushing requirement specified
1126 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1128 * Any transition from any value in {Clear, Render, Resolve} to a
1129 * different value in {Clear, Render, Resolve} requires end of pipe
1132 * We perform a flush of the write cache before and after the clear and
1133 * resolve operations to meet this requirement.
1135 * Unlike other drawing, fast clear operations are not properly
1136 * synchronized. The first PIPE_CONTROL here likely ensures that the
1137 * contents of the previous render or clear hit the render target before we
1138 * resolve and the second likely ensures that the resolve is complete before
1139 * we do any more rendering or clearing.
1141 cmd_buffer
->state
.pending_pipe_bits
|=
1142 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1144 for (uint32_t l
= 0; l
< level_count
; l
++) {
1145 uint32_t level
= base_level
+ l
;
1147 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1148 if (base_layer
>= aux_layers
)
1149 break; /* We will only get fewer layers as level increases */
1150 uint32_t level_layer_count
=
1151 MIN2(layer_count
, aux_layers
- base_layer
);
1153 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1154 uint32_t array_layer
= base_layer
+ a
;
1155 if (image
->samples
== 1) {
1156 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1157 image
->planes
[plane
].surface
.isl
.format
,
1158 aspect
, level
, array_layer
, resolve_op
,
1161 /* We only support fast-clear on the first layer so partial
1162 * resolves should not be used on other layers as they will use
1163 * the clear color stored in memory that is only valid for layer0.
1165 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1169 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1170 image
->planes
[plane
].surface
.isl
.format
,
1171 aspect
, array_layer
, resolve_op
,
1177 cmd_buffer
->state
.pending_pipe_bits
|=
1178 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1182 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1185 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1186 struct anv_render_pass
*pass
,
1187 const VkRenderPassBeginInfo
*begin
)
1189 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1190 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1191 struct anv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1193 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1195 if (pass
->attachment_count
> 0) {
1196 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1197 pass
->attachment_count
*
1198 sizeof(state
->attachments
[0]),
1199 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1200 if (state
->attachments
== NULL
) {
1201 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1202 return anv_batch_set_error(&cmd_buffer
->batch
,
1203 VK_ERROR_OUT_OF_HOST_MEMORY
);
1206 state
->attachments
= NULL
;
1209 /* Reserve one for the NULL state. */
1210 unsigned num_states
= 1;
1211 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1212 if (vk_format_is_color(pass
->attachments
[i
].format
))
1215 if (need_input_attachment_state(&pass
->attachments
[i
]))
1219 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1220 state
->render_pass_states
=
1221 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1222 num_states
* ss_stride
, isl_dev
->ss
.align
);
1224 struct anv_state next_state
= state
->render_pass_states
;
1225 next_state
.alloc_size
= isl_dev
->ss
.size
;
1227 state
->null_surface_state
= next_state
;
1228 next_state
.offset
+= ss_stride
;
1229 next_state
.map
+= ss_stride
;
1231 const VkRenderPassAttachmentBeginInfoKHR
*begin_attachment
=
1232 vk_find_struct_const(begin
, RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR
);
1234 if (begin
&& !begin_attachment
)
1235 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1237 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1238 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1239 state
->attachments
[i
].color
.state
= next_state
;
1240 next_state
.offset
+= ss_stride
;
1241 next_state
.map
+= ss_stride
;
1244 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1245 state
->attachments
[i
].input
.state
= next_state
;
1246 next_state
.offset
+= ss_stride
;
1247 next_state
.map
+= ss_stride
;
1250 if (begin_attachment
&& begin_attachment
->attachmentCount
!= 0) {
1251 assert(begin_attachment
->attachmentCount
== pass
->attachment_count
);
1252 ANV_FROM_HANDLE(anv_image_view
, iview
, begin_attachment
->pAttachments
[i
]);
1253 cmd_buffer
->state
.attachments
[i
].image_view
= iview
;
1254 } else if (framebuffer
&& i
< framebuffer
->attachment_count
) {
1255 cmd_buffer
->state
.attachments
[i
].image_view
= framebuffer
->attachments
[i
];
1258 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1259 state
->render_pass_states
.alloc_size
);
1262 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1263 isl_extent3d(framebuffer
->width
,
1264 framebuffer
->height
,
1265 framebuffer
->layers
));
1267 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1268 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1269 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1270 VkImageAspectFlags clear_aspects
= 0;
1271 VkImageAspectFlags load_aspects
= 0;
1273 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1274 /* color attachment */
1275 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1276 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1277 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1278 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1281 /* depthstencil attachment */
1282 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1283 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1284 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1285 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1286 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1289 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1290 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1291 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1292 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1293 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1298 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1299 state
->attachments
[i
].current_stencil_layout
= att
->stencil_initial_layout
;
1300 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1301 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1303 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1305 struct anv_image_view
*iview
= cmd_buffer
->state
.attachments
[i
].image_view
;
1306 anv_assert(iview
->vk_format
== att
->format
);
1308 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1309 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1311 union isl_color_value clear_color
= { .u32
= { 0, } };
1312 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1313 anv_assert(iview
->n_planes
== 1);
1314 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1315 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1316 state
, i
, begin
->renderArea
,
1319 anv_image_fill_surface_state(cmd_buffer
->device
,
1321 VK_IMAGE_ASPECT_COLOR_BIT
,
1322 &iview
->planes
[0].isl
,
1323 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1324 state
->attachments
[i
].aux_usage
,
1327 &state
->attachments
[i
].color
,
1330 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1332 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1337 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1338 anv_image_fill_surface_state(cmd_buffer
->device
,
1340 VK_IMAGE_ASPECT_COLOR_BIT
,
1341 &iview
->planes
[0].isl
,
1342 ISL_SURF_USAGE_TEXTURE_BIT
,
1343 state
->attachments
[i
].input_aux_usage
,
1346 &state
->attachments
[i
].input
,
1349 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1358 genX(BeginCommandBuffer
)(
1359 VkCommandBuffer commandBuffer
,
1360 const VkCommandBufferBeginInfo
* pBeginInfo
)
1362 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1364 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1365 * command buffer's state. Otherwise, we must *reset* its state. In both
1366 * cases we reset it.
1368 * From the Vulkan 1.0 spec:
1370 * If a command buffer is in the executable state and the command buffer
1371 * was allocated from a command pool with the
1372 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1373 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1374 * as if vkResetCommandBuffer had been called with
1375 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1376 * the command buffer in the recording state.
1378 anv_cmd_buffer_reset(cmd_buffer
);
1380 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1382 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1383 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1385 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1387 /* We sometimes store vertex data in the dynamic state buffer for blorp
1388 * operations and our dynamic state stream may re-use data from previous
1389 * command buffers. In order to prevent stale cache data, we flush the VF
1390 * cache. We could do this on every blorp call but that's not really
1391 * needed as all of the data will get written by the CPU prior to the GPU
1392 * executing anything. The chances are fairly high that they will use
1393 * blorp at least once per primary command buffer so it shouldn't be
1396 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1398 /* We send an "Indirect State Pointers Disable" packet at
1399 * EndCommandBuffer, so all push contant packets are ignored during a
1400 * context restore. Documentation says after that command, we need to
1401 * emit push constants again before any rendering operation. So we
1402 * flag them dirty here to make sure they get emitted.
1404 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1406 VkResult result
= VK_SUCCESS
;
1407 if (cmd_buffer
->usage_flags
&
1408 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1409 assert(pBeginInfo
->pInheritanceInfo
);
1410 cmd_buffer
->state
.pass
=
1411 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1412 cmd_buffer
->state
.subpass
=
1413 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1415 /* This is optional in the inheritance info. */
1416 cmd_buffer
->state
.framebuffer
=
1417 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1419 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1420 cmd_buffer
->state
.pass
, NULL
);
1422 /* Record that HiZ is enabled if we can. */
1423 if (cmd_buffer
->state
.framebuffer
) {
1424 const struct anv_image_view
* const iview
=
1425 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1428 VkImageLayout layout
=
1429 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1431 enum isl_aux_usage aux_usage
=
1432 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1433 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1435 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1439 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1442 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1443 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1444 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1445 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1447 /* If secondary buffer supports conditional rendering
1448 * we should emit commands as if conditional rendering is enabled.
1450 cmd_buffer
->state
.conditional_render_enabled
=
1451 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1458 /* From the PRM, Volume 2a:
1460 * "Indirect State Pointers Disable
1462 * At the completion of the post-sync operation associated with this pipe
1463 * control packet, the indirect state pointers in the hardware are
1464 * considered invalid; the indirect pointers are not saved in the context.
1465 * If any new indirect state commands are executed in the command stream
1466 * while the pipe control is pending, the new indirect state commands are
1469 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1470 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1471 * commands are only considered as Indirect State Pointers. Once ISP is
1472 * issued in a context, SW must initialize by programming push constant
1473 * commands for all the shaders (at least to zero length) before attempting
1474 * any rendering operation for the same context."
1476 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1477 * even though they point to a BO that has been already unreferenced at
1478 * the end of the previous batch buffer. This has been fine so far since
1479 * we are protected by these scratch page (every address not covered by
1480 * a BO should be pointing to the scratch page). But on CNL, it is
1481 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1484 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1485 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1486 * context restore, so the mentioned hang doesn't happen. However,
1487 * software must program push constant commands for all stages prior to
1488 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1490 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1491 * constants have been loaded into the EUs prior to disable the push constants
1492 * so that it doesn't hang a previous 3DPRIMITIVE.
1495 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1497 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1498 pc
.StallAtPixelScoreboard
= true;
1499 pc
.CommandStreamerStallEnable
= true;
1501 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1502 pc
.IndirectStatePointersDisable
= true;
1503 pc
.CommandStreamerStallEnable
= true;
1508 genX(EndCommandBuffer
)(
1509 VkCommandBuffer commandBuffer
)
1511 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1513 if (anv_batch_has_error(&cmd_buffer
->batch
))
1514 return cmd_buffer
->batch
.status
;
1516 /* We want every command buffer to start with the PMA fix in a known state,
1517 * so we disable it at the end of the command buffer.
1519 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1521 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1523 emit_isp_disable(cmd_buffer
);
1525 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1531 genX(CmdExecuteCommands
)(
1532 VkCommandBuffer commandBuffer
,
1533 uint32_t commandBufferCount
,
1534 const VkCommandBuffer
* pCmdBuffers
)
1536 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1538 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1540 if (anv_batch_has_error(&primary
->batch
))
1543 /* The secondary command buffers will assume that the PMA fix is disabled
1544 * when they begin executing. Make sure this is true.
1546 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1548 /* The secondary command buffer doesn't know which textures etc. have been
1549 * flushed prior to their execution. Apply those flushes now.
1551 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1553 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1554 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1556 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1557 assert(!anv_batch_has_error(&secondary
->batch
));
1559 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1560 if (secondary
->state
.conditional_render_enabled
) {
1561 if (!primary
->state
.conditional_render_enabled
) {
1562 /* Secondary buffer is constructed as if it will be executed
1563 * with conditional rendering, we should satisfy this dependency
1564 * regardless of conditional rendering being enabled in primary.
1566 struct gen_mi_builder b
;
1567 gen_mi_builder_init(&b
, &primary
->batch
);
1568 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
1569 gen_mi_imm(UINT64_MAX
));
1574 if (secondary
->usage_flags
&
1575 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1576 /* If we're continuing a render pass from the primary, we need to
1577 * copy the surface states for the current subpass into the storage
1578 * we allocated for them in BeginCommandBuffer.
1580 struct anv_bo
*ss_bo
=
1581 primary
->device
->surface_state_pool
.block_pool
.bo
;
1582 struct anv_state src_state
= primary
->state
.render_pass_states
;
1583 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1584 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1586 genX(cmd_buffer_so_memcpy
)(primary
,
1587 (struct anv_address
) {
1589 .offset
= dst_state
.offset
,
1591 (struct anv_address
) {
1593 .offset
= src_state
.offset
,
1595 src_state
.alloc_size
);
1598 anv_cmd_buffer_add_secondary(primary
, secondary
);
1601 /* The secondary may have selected a different pipeline (3D or compute) and
1602 * may have changed the current L3$ configuration. Reset our tracking
1603 * variables to invalid values to ensure that we re-emit these in the case
1604 * where we do any draws or compute dispatches from the primary after the
1605 * secondary has returned.
1607 primary
->state
.current_pipeline
= UINT32_MAX
;
1608 primary
->state
.current_l3_config
= NULL
;
1609 primary
->state
.current_hash_scale
= 0;
1611 /* Each of the secondary command buffers will use its own state base
1612 * address. We need to re-emit state base address for the primary after
1613 * all of the secondaries are done.
1615 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1618 genX(cmd_buffer_emit_state_base_address
)(primary
);
1621 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1622 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1623 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1626 * Program the hardware to use the specified L3 configuration.
1629 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1630 const struct gen_l3_config
*cfg
)
1633 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1636 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1637 intel_logd("L3 config transition: ");
1638 gen_dump_l3_config(cfg
, stderr
);
1641 UNUSED
const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1643 /* According to the hardware docs, the L3 partitioning can only be changed
1644 * while the pipeline is completely drained and the caches are flushed,
1645 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1647 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1648 pc
.DCFlushEnable
= true;
1649 pc
.PostSyncOperation
= NoWrite
;
1650 pc
.CommandStreamerStallEnable
= true;
1653 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1654 * invalidation of the relevant caches. Note that because RO invalidation
1655 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1656 * command is processed by the CS) we cannot combine it with the previous
1657 * stalling flush as the hardware documentation suggests, because that
1658 * would cause the CS to stall on previous rendering *after* RO
1659 * invalidation and wouldn't prevent the RO caches from being polluted by
1660 * concurrent rendering before the stall completes. This intentionally
1661 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1662 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1663 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1664 * already guarantee that there is no concurrent GPGPU kernel execution
1665 * (see SKL HSD 2132585).
1667 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1668 pc
.TextureCacheInvalidationEnable
= true;
1669 pc
.ConstantCacheInvalidationEnable
= true;
1670 pc
.InstructionCacheInvalidateEnable
= true;
1671 pc
.StateCacheInvalidationEnable
= true;
1672 pc
.PostSyncOperation
= NoWrite
;
1675 /* Now send a third stalling flush to make sure that invalidation is
1676 * complete when the L3 configuration registers are modified.
1678 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1679 pc
.DCFlushEnable
= true;
1680 pc
.PostSyncOperation
= NoWrite
;
1681 pc
.CommandStreamerStallEnable
= true;
1686 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1689 #define L3_ALLOCATION_REG GENX(L3ALLOC)
1690 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
1692 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
1693 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
1697 anv_pack_struct(&l3cr
, L3_ALLOCATION_REG
,
1699 .SLMEnable
= has_slm
,
1702 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1703 * in L3CNTLREG register. The default setting of the bit is not the
1704 * desirable behavior.
1706 .ErrorDetectionBehaviorControl
= true,
1707 .UseFullWays
= true,
1709 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1710 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1711 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1712 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1714 /* Set up the L3 partitioning. */
1715 emit_lri(&cmd_buffer
->batch
, L3_ALLOCATION_REG_num
, l3cr
);
1719 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1720 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1721 cfg
->n
[GEN_L3P_ALL
];
1722 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1723 cfg
->n
[GEN_L3P_ALL
];
1724 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1725 cfg
->n
[GEN_L3P_ALL
];
1727 assert(!cfg
->n
[GEN_L3P_ALL
]);
1729 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1730 * the matching space on the remaining banks has to be allocated to a
1731 * client (URB for all validated configurations) set to the
1732 * lower-bandwidth 2-bank address hashing mode.
1734 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1735 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1736 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1738 /* Minimum number of ways that can be allocated to the URB. */
1739 const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1740 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1742 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1743 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1744 .ConvertDC_UC
= !has_dc
,
1745 .ConvertIS_UC
= !has_is
,
1746 .ConvertC_UC
= !has_c
,
1747 .ConvertT_UC
= !has_t
);
1749 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1750 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1751 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1753 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1754 .SLMEnable
= has_slm
,
1755 .URBLowBandwidth
= urb_low_bw
,
1756 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1758 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1760 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1761 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1763 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1764 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1765 .ISLowBandwidth
= 0,
1766 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1768 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1769 .TLowBandwidth
= 0);
1771 /* Set up the L3 partitioning. */
1772 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1773 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1774 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1777 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1778 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1779 * them disabled to avoid crashing the system hard.
1781 uint32_t scratch1
, chicken3
;
1782 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1783 .L3AtomicDisable
= !has_dc
);
1784 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1785 .L3AtomicDisableMask
= true,
1786 .L3AtomicDisable
= !has_dc
);
1787 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1788 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1794 cmd_buffer
->state
.current_l3_config
= cfg
;
1798 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1800 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1802 if (cmd_buffer
->device
->instance
->physicalDevice
.always_flush_cache
)
1803 bits
|= ANV_PIPE_FLUSH_BITS
| ANV_PIPE_INVALIDATE_BITS
;
1805 /* Flushes are pipelined while invalidations are handled immediately.
1806 * Therefore, if we're flushing anything then we need to schedule a stall
1807 * before any invalidations can happen.
1809 if (bits
& ANV_PIPE_FLUSH_BITS
)
1810 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1812 /* If we're going to do an invalidate and we have a pending CS stall that
1813 * has yet to be resolved, we do the CS stall now.
1815 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1816 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1817 bits
|= ANV_PIPE_CS_STALL_BIT
;
1818 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1821 if (GEN_GEN
>= 12 &&
1822 ((bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
) ||
1823 (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
))) {
1824 /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
1827 * Unified Cache (Tile Cache Disabled):
1829 * When the Color and Depth (Z) streams are enabled to be cached in
1830 * the DC space of L2, Software must use "Render Target Cache Flush
1831 * Enable" and "Depth Cache Flush Enable" along with "Tile Cache
1832 * Flush" for getting the color and depth (Z) write data to be
1833 * globally observable. In this mode of operation it is not required
1834 * to set "CS Stall" upon setting "Tile Cache Flush" bit.
1836 bits
|= ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
1839 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1840 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1842 pipe
.TileCacheFlushEnable
= bits
& ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
1844 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1845 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1846 pipe
.RenderTargetCacheFlushEnable
=
1847 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1849 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1850 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1851 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1854 * According to the Broadwell documentation, any PIPE_CONTROL with the
1855 * "Command Streamer Stall" bit set must also have another bit set,
1856 * with five different options:
1858 * - Render Target Cache Flush
1859 * - Depth Cache Flush
1860 * - Stall at Pixel Scoreboard
1861 * - Post-Sync Operation
1865 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1866 * mesa and it seems to work fine. The choice is fairly arbitrary.
1868 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1869 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1870 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1871 pipe
.StallAtPixelScoreboard
= true;
1874 /* If a render target flush was emitted, then we can toggle off the bit
1875 * saying that render target writes are ongoing.
1877 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
1878 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
1880 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1883 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1884 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1886 * "If the VF Cache Invalidation Enable is set to a 1 in a
1887 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1888 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1889 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1892 * This appears to hang Broadwell, so we restrict it to just gen9.
1894 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1895 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1897 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1898 pipe
.StateCacheInvalidationEnable
=
1899 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1900 pipe
.ConstantCacheInvalidationEnable
=
1901 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1902 pipe
.VFCacheInvalidationEnable
=
1903 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1904 pipe
.TextureCacheInvalidationEnable
=
1905 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1906 pipe
.InstructionCacheInvalidateEnable
=
1907 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1909 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1911 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1912 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1913 * “Write Timestamp”.
1915 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1916 pipe
.PostSyncOperation
= WriteImmediateData
;
1918 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
1922 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1925 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1928 void genX(CmdPipelineBarrier
)(
1929 VkCommandBuffer commandBuffer
,
1930 VkPipelineStageFlags srcStageMask
,
1931 VkPipelineStageFlags destStageMask
,
1933 uint32_t memoryBarrierCount
,
1934 const VkMemoryBarrier
* pMemoryBarriers
,
1935 uint32_t bufferMemoryBarrierCount
,
1936 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1937 uint32_t imageMemoryBarrierCount
,
1938 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1940 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1942 /* XXX: Right now, we're really dumb and just flush whatever categories
1943 * the app asks for. One of these days we may make this a bit better
1944 * but right now that's all the hardware allows for in most areas.
1946 VkAccessFlags src_flags
= 0;
1947 VkAccessFlags dst_flags
= 0;
1949 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1950 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1951 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1954 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1955 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1956 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1959 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1960 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1961 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1962 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1963 const VkImageSubresourceRange
*range
=
1964 &pImageMemoryBarriers
[i
].subresourceRange
;
1966 uint32_t base_layer
, layer_count
;
1967 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1969 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1971 base_layer
= range
->baseArrayLayer
;
1972 layer_count
= anv_get_layerCount(image
, range
);
1975 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1976 transition_depth_buffer(cmd_buffer
, image
,
1977 pImageMemoryBarriers
[i
].oldLayout
,
1978 pImageMemoryBarriers
[i
].newLayout
);
1981 if (range
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1982 transition_stencil_buffer(cmd_buffer
, image
,
1983 range
->baseMipLevel
,
1984 anv_get_levelCount(image
, range
),
1985 base_layer
, layer_count
,
1986 pImageMemoryBarriers
[i
].oldLayout
,
1987 pImageMemoryBarriers
[i
].newLayout
);
1990 if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1991 VkImageAspectFlags color_aspects
=
1992 anv_image_expand_aspects(image
, range
->aspectMask
);
1993 uint32_t aspect_bit
;
1994 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1995 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1996 range
->baseMipLevel
,
1997 anv_get_levelCount(image
, range
),
1998 base_layer
, layer_count
,
1999 pImageMemoryBarriers
[i
].oldLayout
,
2000 pImageMemoryBarriers
[i
].newLayout
);
2005 cmd_buffer
->state
.pending_pipe_bits
|=
2006 anv_pipe_flush_bits_for_access_flags(src_flags
) |
2007 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
2011 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
2013 VkShaderStageFlags stages
=
2014 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
2016 /* In order to avoid thrash, we assume that vertex and fragment stages
2017 * always exist. In the rare case where one is missing *and* the other
2018 * uses push concstants, this may be suboptimal. However, avoiding stalls
2019 * seems more important.
2021 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
2023 if (stages
== cmd_buffer
->state
.push_constant_stages
)
2027 const unsigned push_constant_kb
= 32;
2028 #elif GEN_IS_HASWELL
2029 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
2031 const unsigned push_constant_kb
= 16;
2034 const unsigned num_stages
=
2035 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
2036 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
2038 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
2039 * units of 2KB. Incidentally, these are the same platforms that have
2040 * 32KB worth of push constant space.
2042 if (push_constant_kb
== 32)
2043 size_per_stage
&= ~1u;
2045 uint32_t kb_used
= 0;
2046 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
2047 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
2048 anv_batch_emit(&cmd_buffer
->batch
,
2049 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
2050 alloc
._3DCommandSubOpcode
= 18 + i
;
2051 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
2052 alloc
.ConstantBufferSize
= push_size
;
2054 kb_used
+= push_size
;
2057 anv_batch_emit(&cmd_buffer
->batch
,
2058 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
2059 alloc
.ConstantBufferOffset
= kb_used
;
2060 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
2063 cmd_buffer
->state
.push_constant_stages
= stages
;
2065 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
2067 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
2068 * the next 3DPRIMITIVE command after programming the
2069 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
2071 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
2072 * pipeline setup, we need to dirty push constants.
2074 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
2077 static struct anv_address
2078 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
2079 struct anv_descriptor_set
*set
)
2082 /* This is a normal descriptor set */
2083 return (struct anv_address
) {
2084 .bo
= set
->pool
->bo
,
2085 .offset
= set
->desc_mem
.offset
,
2088 /* This is a push descriptor set. We have to flag it as used on the GPU
2089 * so that the next time we push descriptors, we grab a new memory.
2091 struct anv_push_descriptor_set
*push_set
=
2092 (struct anv_push_descriptor_set
*)set
;
2093 push_set
->set_used_on_gpu
= true;
2095 return (struct anv_address
) {
2096 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2097 .offset
= set
->desc_mem
.offset
,
2103 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2104 gl_shader_stage stage
,
2105 struct anv_state
*bt_state
)
2107 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2108 struct anv_cmd_pipeline_state
*pipe_state
;
2109 struct anv_pipeline
*pipeline
;
2110 uint32_t state_offset
;
2113 case MESA_SHADER_COMPUTE
:
2114 pipe_state
= &cmd_buffer
->state
.compute
.base
;
2117 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
2120 pipeline
= pipe_state
->pipeline
;
2122 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2123 *bt_state
= (struct anv_state
) { 0, };
2127 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2128 if (map
->surface_count
== 0) {
2129 *bt_state
= (struct anv_state
) { 0, };
2133 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2136 uint32_t *bt_map
= bt_state
->map
;
2138 if (bt_state
->map
== NULL
)
2139 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2141 /* We only need to emit relocs if we're not using softpin. If we are using
2142 * softpin then we always keep all user-allocated memory objects resident.
2144 const bool need_client_mem_relocs
=
2145 !cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
;
2147 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2148 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2150 struct anv_state surface_state
;
2152 switch (binding
->set
) {
2153 case ANV_DESCRIPTOR_SET_NULL
:
2157 case ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
:
2158 /* Color attachment binding */
2159 assert(stage
== MESA_SHADER_FRAGMENT
);
2160 if (binding
->index
< subpass
->color_count
) {
2161 const unsigned att
=
2162 subpass
->color_attachments
[binding
->index
].attachment
;
2164 /* From the Vulkan 1.0.46 spec:
2166 * "If any color or depth/stencil attachments are
2167 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2170 if (att
== VK_ATTACHMENT_UNUSED
) {
2171 surface_state
= cmd_buffer
->state
.null_surface_state
;
2173 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2176 surface_state
= cmd_buffer
->state
.null_surface_state
;
2179 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2182 case ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
: {
2183 struct anv_state surface_state
=
2184 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2186 struct anv_address constant_data
= {
2187 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2188 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2190 unsigned constant_data_size
=
2191 pipeline
->shaders
[stage
]->constant_data_size
;
2193 const enum isl_format format
=
2194 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2195 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2196 surface_state
, format
,
2197 constant_data
, constant_data_size
, 1);
2199 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2200 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2204 case ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
: {
2205 /* This is always the first binding for compute shaders */
2206 assert(stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2208 struct anv_state surface_state
=
2209 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2211 const enum isl_format format
=
2212 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2213 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2215 cmd_buffer
->state
.compute
.num_workgroups
,
2217 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2218 if (need_client_mem_relocs
) {
2219 add_surface_reloc(cmd_buffer
, surface_state
,
2220 cmd_buffer
->state
.compute
.num_workgroups
);
2225 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2226 /* This is a descriptor set buffer so the set index is actually
2227 * given by binding->binding. (Yes, that's confusing.)
2229 struct anv_descriptor_set
*set
=
2230 pipe_state
->descriptors
[binding
->index
];
2231 assert(set
->desc_mem
.alloc_size
);
2232 assert(set
->desc_surface_state
.alloc_size
);
2233 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2234 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2235 anv_descriptor_set_address(cmd_buffer
, set
));
2240 assert(binding
->set
< MAX_SETS
);
2241 const struct anv_descriptor
*desc
=
2242 &pipe_state
->descriptors
[binding
->set
]->descriptors
[binding
->index
];
2244 switch (desc
->type
) {
2245 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2246 /* Nothing for us to do here */
2249 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2250 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2251 struct anv_surface_state sstate
=
2252 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2253 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2254 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2255 surface_state
= sstate
.state
;
2256 assert(surface_state
.alloc_size
);
2257 if (need_client_mem_relocs
)
2258 add_surface_state_relocs(cmd_buffer
, sstate
);
2261 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2262 assert(stage
== MESA_SHADER_FRAGMENT
);
2263 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2264 /* For depth and stencil input attachments, we treat it like any
2265 * old texture that a user may have bound.
2267 assert(desc
->image_view
->n_planes
== 1);
2268 struct anv_surface_state sstate
=
2269 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2270 desc
->image_view
->planes
[0].general_sampler_surface_state
:
2271 desc
->image_view
->planes
[0].optimal_sampler_surface_state
;
2272 surface_state
= sstate
.state
;
2273 assert(surface_state
.alloc_size
);
2274 if (need_client_mem_relocs
)
2275 add_surface_state_relocs(cmd_buffer
, sstate
);
2277 /* For color input attachments, we create the surface state at
2278 * vkBeginRenderPass time so that we can include aux and clear
2279 * color information.
2281 assert(binding
->input_attachment_index
< subpass
->input_count
);
2282 const unsigned subpass_att
= binding
->input_attachment_index
;
2283 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2284 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2288 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2289 struct anv_surface_state sstate
= (binding
->write_only
)
2290 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2291 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2292 surface_state
= sstate
.state
;
2293 assert(surface_state
.alloc_size
);
2294 if (need_client_mem_relocs
)
2295 add_surface_state_relocs(cmd_buffer
, sstate
);
2299 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2300 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2301 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2302 surface_state
= desc
->buffer_view
->surface_state
;
2303 assert(surface_state
.alloc_size
);
2304 if (need_client_mem_relocs
) {
2305 add_surface_reloc(cmd_buffer
, surface_state
,
2306 desc
->buffer_view
->address
);
2310 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2311 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2312 /* Compute the offset within the buffer */
2313 struct anv_push_constants
*push
=
2314 &cmd_buffer
->state
.push_constants
[stage
];
2316 uint32_t dynamic_offset
=
2317 push
->dynamic_offsets
[binding
->dynamic_offset_index
];
2318 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2319 /* Clamp to the buffer size */
2320 offset
= MIN2(offset
, desc
->buffer
->size
);
2321 /* Clamp the range to the buffer size */
2322 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2324 struct anv_address address
=
2325 anv_address_add(desc
->buffer
->address
, offset
);
2328 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2329 enum isl_format format
=
2330 anv_isl_format_for_descriptor_type(desc
->type
);
2332 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2333 format
, address
, range
, 1);
2334 if (need_client_mem_relocs
)
2335 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2339 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2340 surface_state
= (binding
->write_only
)
2341 ? desc
->buffer_view
->writeonly_storage_surface_state
2342 : desc
->buffer_view
->storage_surface_state
;
2343 assert(surface_state
.alloc_size
);
2344 if (need_client_mem_relocs
) {
2345 add_surface_reloc(cmd_buffer
, surface_state
,
2346 desc
->buffer_view
->address
);
2351 assert(!"Invalid descriptor type");
2354 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2364 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2365 gl_shader_stage stage
,
2366 struct anv_state
*state
)
2368 struct anv_cmd_pipeline_state
*pipe_state
=
2369 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2370 &cmd_buffer
->state
.gfx
.base
;
2371 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2373 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2374 *state
= (struct anv_state
) { 0, };
2378 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2379 if (map
->sampler_count
== 0) {
2380 *state
= (struct anv_state
) { 0, };
2384 uint32_t size
= map
->sampler_count
* 16;
2385 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2387 if (state
->map
== NULL
)
2388 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2390 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2391 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2392 const struct anv_descriptor
*desc
=
2393 &pipe_state
->descriptors
[binding
->set
]->descriptors
[binding
->index
];
2395 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2396 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2399 struct anv_sampler
*sampler
= desc
->sampler
;
2401 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2402 * happens to be zero.
2404 if (sampler
== NULL
)
2407 memcpy(state
->map
+ (s
* 16),
2408 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2415 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2417 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2419 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2420 pipeline
->active_stages
;
2422 VkResult result
= VK_SUCCESS
;
2423 anv_foreach_stage(s
, dirty
) {
2424 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2425 if (result
!= VK_SUCCESS
)
2427 result
= emit_binding_table(cmd_buffer
, s
,
2428 &cmd_buffer
->state
.binding_tables
[s
]);
2429 if (result
!= VK_SUCCESS
)
2433 if (result
!= VK_SUCCESS
) {
2434 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2436 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2437 if (result
!= VK_SUCCESS
)
2440 /* Re-emit state base addresses so we get the new surface state base
2441 * address before we start emitting binding tables etc.
2443 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2445 /* Re-emit all active binding tables */
2446 dirty
|= pipeline
->active_stages
;
2447 anv_foreach_stage(s
, dirty
) {
2448 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2449 if (result
!= VK_SUCCESS
) {
2450 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2453 result
= emit_binding_table(cmd_buffer
, s
,
2454 &cmd_buffer
->state
.binding_tables
[s
]);
2455 if (result
!= VK_SUCCESS
) {
2456 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2462 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2468 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2471 static const uint32_t sampler_state_opcodes
[] = {
2472 [MESA_SHADER_VERTEX
] = 43,
2473 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2474 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2475 [MESA_SHADER_GEOMETRY
] = 46,
2476 [MESA_SHADER_FRAGMENT
] = 47,
2477 [MESA_SHADER_COMPUTE
] = 0,
2480 static const uint32_t binding_table_opcodes
[] = {
2481 [MESA_SHADER_VERTEX
] = 38,
2482 [MESA_SHADER_TESS_CTRL
] = 39,
2483 [MESA_SHADER_TESS_EVAL
] = 40,
2484 [MESA_SHADER_GEOMETRY
] = 41,
2485 [MESA_SHADER_FRAGMENT
] = 42,
2486 [MESA_SHADER_COMPUTE
] = 0,
2489 anv_foreach_stage(s
, stages
) {
2490 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2491 assert(binding_table_opcodes
[s
] > 0);
2493 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2494 anv_batch_emit(&cmd_buffer
->batch
,
2495 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2496 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2497 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2501 /* Always emit binding table pointers if we're asked to, since on SKL
2502 * this is what flushes push constants. */
2503 anv_batch_emit(&cmd_buffer
->batch
,
2504 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2505 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2506 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2511 static struct anv_address
2512 get_push_range_address(struct anv_cmd_buffer
*cmd_buffer
,
2513 gl_shader_stage stage
,
2514 const struct anv_push_range
*range
)
2516 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2517 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2518 switch (range
->set
) {
2519 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2520 /* This is a descriptor set buffer so the set index is
2521 * actually given by binding->binding. (Yes, that's
2524 struct anv_descriptor_set
*set
=
2525 gfx_state
->base
.descriptors
[range
->index
];
2526 return anv_descriptor_set_address(cmd_buffer
, set
);
2530 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
: {
2531 struct anv_state state
=
2532 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2533 return (struct anv_address
) {
2534 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2535 .offset
= state
.offset
,
2541 assert(range
->set
< MAX_SETS
);
2542 struct anv_descriptor_set
*set
=
2543 gfx_state
->base
.descriptors
[range
->set
];
2544 const struct anv_descriptor
*desc
=
2545 &set
->descriptors
[range
->index
];
2547 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2548 return desc
->buffer_view
->address
;
2550 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2551 struct anv_push_constants
*push
=
2552 &cmd_buffer
->state
.push_constants
[stage
];
2553 uint32_t dynamic_offset
=
2554 push
->dynamic_offsets
[range
->dynamic_offset_index
];
2555 return anv_address_add(desc
->buffer
->address
,
2556 desc
->offset
+ dynamic_offset
);
2561 /* For Ivy Bridge, push constants are relative to dynamic state
2562 * base address and we only ever push actual push constants.
2564 assert(range
->length
> 0);
2565 assert(range
->set
== ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
);
2566 struct anv_state state
=
2567 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2568 return (struct anv_address
) {
2569 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2570 .offset
= state
.offset
,
2576 cmd_buffer_emit_push_constant(struct anv_cmd_buffer
*cmd_buffer
,
2577 gl_shader_stage stage
, unsigned buffer_count
)
2579 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2580 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2582 static const uint32_t push_constant_opcodes
[] = {
2583 [MESA_SHADER_VERTEX
] = 21,
2584 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2585 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2586 [MESA_SHADER_GEOMETRY
] = 22,
2587 [MESA_SHADER_FRAGMENT
] = 23,
2588 [MESA_SHADER_COMPUTE
] = 0,
2591 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2592 assert(push_constant_opcodes
[stage
] > 0);
2594 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2595 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2597 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2598 const struct anv_pipeline_bind_map
*bind_map
=
2599 &pipeline
->shaders
[stage
]->bind_map
;
2601 /* The Skylake PRM contains the following restriction:
2603 * "The driver must ensure The following case does not occur
2604 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2605 * buffer 3 read length equal to zero committed followed by a
2606 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2609 * To avoid this, we program the buffers in the highest slots.
2610 * This way, slot 0 is only used if slot 3 is also used.
2612 assert(buffer_count
<= 4);
2613 const unsigned shift
= 4 - buffer_count
;
2614 for (unsigned i
= 0; i
< buffer_count
; i
++) {
2615 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
2617 /* At this point we only have non-empty ranges */
2618 assert(range
->length
> 0);
2620 /* For Ivy Bridge, make sure we only set the first range (actual
2623 assert((GEN_GEN
>= 8 || GEN_IS_HASWELL
) || i
== 0);
2625 const struct anv_address addr
=
2626 get_push_range_address(cmd_buffer
, stage
, range
);
2627 c
.ConstantBody
.ReadLength
[i
+ shift
] = range
->length
;
2628 c
.ConstantBody
.Buffer
[i
+ shift
] =
2629 anv_address_add(addr
, range
->start
* 32);
2637 cmd_buffer_emit_push_constant_all(struct anv_cmd_buffer
*cmd_buffer
,
2638 uint32_t shader_mask
, uint32_t count
)
2641 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_ALL
), c
) {
2642 c
.ShaderUpdateEnable
= shader_mask
;
2647 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2648 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2650 static const uint32_t push_constant_opcodes
[] = {
2651 [MESA_SHADER_VERTEX
] = 21,
2652 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2653 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2654 [MESA_SHADER_GEOMETRY
] = 22,
2655 [MESA_SHADER_FRAGMENT
] = 23,
2656 [MESA_SHADER_COMPUTE
] = 0,
2659 gl_shader_stage stage
= vk_to_mesa_shader_stage(shader_mask
);
2660 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2661 assert(push_constant_opcodes
[stage
] > 0);
2663 const struct anv_pipeline_bind_map
*bind_map
=
2664 &pipeline
->shaders
[stage
]->bind_map
;
2667 const uint32_t buffers
= (1 << count
) - 1;
2668 const uint32_t num_dwords
= 2 + 2 * count
;
2670 dw
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2671 GENX(3DSTATE_CONSTANT_ALL
),
2672 .ShaderUpdateEnable
= shader_mask
,
2673 .PointerBufferMask
= buffers
);
2675 for (int i
= 0; i
< count
; i
++) {
2676 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
2677 const struct anv_address addr
=
2678 get_push_range_address(cmd_buffer
, stage
, range
);
2680 GENX(3DSTATE_CONSTANT_ALL_DATA_pack
)(
2681 &cmd_buffer
->batch
, dw
+ 2 + i
* 2,
2682 &(struct GENX(3DSTATE_CONSTANT_ALL_DATA
)) {
2683 .PointerToConstantBuffer
= anv_address_add(addr
, range
->start
* 32),
2684 .ConstantBufferReadLength
= range
->length
,
2691 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2692 VkShaderStageFlags dirty_stages
)
2694 VkShaderStageFlags flushed
= 0;
2695 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2696 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2699 uint32_t nobuffer_stages
= 0;
2702 anv_foreach_stage(stage
, dirty_stages
) {
2703 unsigned buffer_count
= 0;
2704 flushed
|= mesa_to_vk_shader_stage(stage
);
2705 uint32_t max_push_range
= 0;
2707 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2708 const struct anv_pipeline_bind_map
*bind_map
=
2709 &pipeline
->shaders
[stage
]->bind_map
;
2711 for (unsigned i
= 0; i
< 4; i
++) {
2712 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
2713 if (range
->length
> 0) {
2715 if (GEN_GEN
>= 12 && range
->length
> max_push_range
)
2716 max_push_range
= range
->length
;
2722 /* If this stage doesn't have any push constants, emit it later in a
2723 * single CONSTANT_ALL packet.
2725 if (buffer_count
== 0) {
2726 nobuffer_stages
|= 1 << stage
;
2730 /* The Constant Buffer Read Length field from 3DSTATE_CONSTANT_ALL
2731 * contains only 5 bits, so we can only use it for buffers smaller than
2734 if (max_push_range
< 32) {
2735 cmd_buffer_emit_push_constant_all(cmd_buffer
, 1 << stage
,
2741 cmd_buffer_emit_push_constant(cmd_buffer
, stage
, buffer_count
);
2745 if (nobuffer_stages
)
2746 cmd_buffer_emit_push_constant_all(cmd_buffer
, nobuffer_stages
, 0);
2749 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2754 genX(cmd_buffer_aux_map_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2756 void *aux_map_ctx
= cmd_buffer
->device
->aux_map_ctx
;
2759 uint32_t aux_map_state_num
= gen_aux_map_get_state_num(aux_map_ctx
);
2760 if (cmd_buffer
->state
.last_aux_map_state
!= aux_map_state_num
) {
2761 /* If the aux-map state number increased, then we need to rewrite the
2762 * register. Rewriting the register is used to both set the aux-map
2763 * translation table address, and also to invalidate any previously
2764 * cached translations.
2766 uint64_t base_addr
= gen_aux_map_get_base(aux_map_ctx
);
2767 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
2768 lri
.RegisterOffset
= GENX(GFX_AUX_TABLE_BASE_ADDR_num
);
2769 lri
.DataDWord
= base_addr
& 0xffffffff;
2771 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
2772 lri
.RegisterOffset
= GENX(GFX_AUX_TABLE_BASE_ADDR_num
) + 4;
2773 lri
.DataDWord
= base_addr
>> 32;
2775 cmd_buffer
->state
.last_aux_map_state
= aux_map_state_num
;
2781 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2783 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2786 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2787 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2788 vb_emit
|= pipeline
->vb_used
;
2790 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2792 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2794 genX(cmd_buffer_emit_hashing_mode
)(cmd_buffer
, UINT_MAX
, UINT_MAX
, 1);
2796 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2799 genX(cmd_buffer_aux_map_state
)(cmd_buffer
);
2803 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2804 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2806 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2807 GENX(3DSTATE_VERTEX_BUFFERS
));
2809 for_each_bit(vb
, vb_emit
) {
2810 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2811 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2813 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2814 .VertexBufferIndex
= vb
,
2816 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
2818 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2819 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2822 .AddressModifyEnable
= true,
2823 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2824 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2827 .BufferSize
= buffer
->size
- offset
2829 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2833 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2838 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2841 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
2842 /* We don't need any per-buffer dirty tracking because you're not
2843 * allowed to bind different XFB buffers while XFB is enabled.
2845 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
2846 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
2847 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
2849 sob
.SOBufferIndex
= idx
;
2851 sob
._3DCommandOpcode
= 0;
2852 sob
._3DCommandSubOpcode
= SO_BUFFER_INDEX_0_CMD
+ idx
;
2855 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
2856 sob
.SOBufferEnable
= true;
2857 sob
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
,
2858 sob
.StreamOffsetWriteEnable
= false;
2859 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
2861 /* Size is in DWords - 1 */
2862 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
2867 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
2869 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2873 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2874 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2876 /* If the pipeline changed, we may need to re-allocate push constant
2879 cmd_buffer_alloc_push_constants(cmd_buffer
);
2883 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2884 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2885 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2887 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2888 * stall needs to be sent just prior to any 3DSTATE_VS,
2889 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2890 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2891 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2892 * PIPE_CONTROL needs to be sent before any combination of VS
2893 * associated 3DSTATE."
2895 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2896 pc
.DepthStallEnable
= true;
2897 pc
.PostSyncOperation
= WriteImmediateData
;
2899 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
2904 /* Render targets live in the same binding table as fragment descriptors */
2905 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2906 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2908 /* We emit the binding tables and sampler tables first, then emit push
2909 * constants and then finally emit binding table and sampler table
2910 * pointers. It has to happen in this order, since emitting the binding
2911 * tables may change the push constants (in case of storage images). After
2912 * emitting push constants, on SKL+ we have to emit the corresponding
2913 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2916 if (cmd_buffer
->state
.descriptors_dirty
)
2917 dirty
= flush_descriptor_sets(cmd_buffer
);
2919 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2920 /* Because we're pushing UBOs, we have to push whenever either
2921 * descriptors or push constants is dirty.
2923 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2924 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2925 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2929 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2931 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2932 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2934 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2935 ANV_CMD_DIRTY_PIPELINE
)) {
2936 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2937 pipeline
->depth_clamp_enable
);
2940 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2941 ANV_CMD_DIRTY_RENDER_TARGETS
))
2942 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2944 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2946 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2950 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2951 struct anv_address addr
,
2952 uint32_t size
, uint32_t index
)
2954 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2955 GENX(3DSTATE_VERTEX_BUFFERS
));
2957 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2958 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2959 .VertexBufferIndex
= index
,
2960 .AddressModifyEnable
= true,
2962 .MOCS
= addr
.bo
? anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
) : 0,
2963 .NullVertexBuffer
= size
== 0,
2965 .BufferStartingAddress
= addr
,
2968 .BufferStartingAddress
= addr
,
2969 .EndAddress
= anv_address_add(addr
, size
),
2975 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2976 struct anv_address addr
)
2978 emit_vertex_bo(cmd_buffer
, addr
, addr
.bo
? 8 : 0, ANV_SVGS_VB_INDEX
);
2982 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2983 uint32_t base_vertex
, uint32_t base_instance
)
2985 if (base_vertex
== 0 && base_instance
== 0) {
2986 emit_base_vertex_instance_bo(cmd_buffer
, ANV_NULL_ADDRESS
);
2988 struct anv_state id_state
=
2989 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2991 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2992 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2994 struct anv_address addr
= {
2995 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2996 .offset
= id_state
.offset
,
2999 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
3004 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
3006 struct anv_state state
=
3007 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
3009 ((uint32_t *)state
.map
)[0] = draw_index
;
3011 struct anv_address addr
= {
3012 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3013 .offset
= state
.offset
,
3016 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
3020 VkCommandBuffer commandBuffer
,
3021 uint32_t vertexCount
,
3022 uint32_t instanceCount
,
3023 uint32_t firstVertex
,
3024 uint32_t firstInstance
)
3026 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3027 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3028 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3030 if (anv_batch_has_error(&cmd_buffer
->batch
))
3033 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3035 if (cmd_buffer
->state
.conditional_render_enabled
)
3036 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3038 if (vs_prog_data
->uses_firstvertex
||
3039 vs_prog_data
->uses_baseinstance
)
3040 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3041 if (vs_prog_data
->uses_drawid
)
3042 emit_draw_index(cmd_buffer
, 0);
3044 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3045 * different views. We need to multiply instanceCount by the view count.
3047 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3049 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3050 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3051 prim
.VertexAccessType
= SEQUENTIAL
;
3052 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3053 prim
.VertexCountPerInstance
= vertexCount
;
3054 prim
.StartVertexLocation
= firstVertex
;
3055 prim
.InstanceCount
= instanceCount
;
3056 prim
.StartInstanceLocation
= firstInstance
;
3057 prim
.BaseVertexLocation
= 0;
3061 void genX(CmdDrawIndexed
)(
3062 VkCommandBuffer commandBuffer
,
3063 uint32_t indexCount
,
3064 uint32_t instanceCount
,
3065 uint32_t firstIndex
,
3066 int32_t vertexOffset
,
3067 uint32_t firstInstance
)
3069 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3070 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3071 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3073 if (anv_batch_has_error(&cmd_buffer
->batch
))
3076 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3078 if (cmd_buffer
->state
.conditional_render_enabled
)
3079 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3081 if (vs_prog_data
->uses_firstvertex
||
3082 vs_prog_data
->uses_baseinstance
)
3083 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
3084 if (vs_prog_data
->uses_drawid
)
3085 emit_draw_index(cmd_buffer
, 0);
3087 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3088 * different views. We need to multiply instanceCount by the view count.
3090 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3092 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3093 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3094 prim
.VertexAccessType
= RANDOM
;
3095 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3096 prim
.VertexCountPerInstance
= indexCount
;
3097 prim
.StartVertexLocation
= firstIndex
;
3098 prim
.InstanceCount
= instanceCount
;
3099 prim
.StartInstanceLocation
= firstInstance
;
3100 prim
.BaseVertexLocation
= vertexOffset
;
3104 /* Auto-Draw / Indirect Registers */
3105 #define GEN7_3DPRIM_END_OFFSET 0x2420
3106 #define GEN7_3DPRIM_START_VERTEX 0x2430
3107 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
3108 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
3109 #define GEN7_3DPRIM_START_INSTANCE 0x243C
3110 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
3112 void genX(CmdDrawIndirectByteCountEXT
)(
3113 VkCommandBuffer commandBuffer
,
3114 uint32_t instanceCount
,
3115 uint32_t firstInstance
,
3116 VkBuffer counterBuffer
,
3117 VkDeviceSize counterBufferOffset
,
3118 uint32_t counterOffset
,
3119 uint32_t vertexStride
)
3121 #if GEN_IS_HASWELL || GEN_GEN >= 8
3122 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3123 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
3124 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3125 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3127 /* firstVertex is always zero for this draw function */
3128 const uint32_t firstVertex
= 0;
3130 if (anv_batch_has_error(&cmd_buffer
->batch
))
3133 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3135 if (vs_prog_data
->uses_firstvertex
||
3136 vs_prog_data
->uses_baseinstance
)
3137 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3138 if (vs_prog_data
->uses_drawid
)
3139 emit_draw_index(cmd_buffer
, 0);
3141 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3142 * different views. We need to multiply instanceCount by the view count.
3144 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3146 struct gen_mi_builder b
;
3147 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3148 struct gen_mi_value count
=
3149 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
3150 counterBufferOffset
));
3152 count
= gen_mi_isub(&b
, count
, gen_mi_imm(counterOffset
));
3153 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
3154 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
3156 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3157 gen_mi_imm(firstVertex
));
3158 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
3159 gen_mi_imm(instanceCount
));
3160 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3161 gen_mi_imm(firstInstance
));
3162 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3164 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3165 prim
.IndirectParameterEnable
= true;
3166 prim
.VertexAccessType
= SEQUENTIAL
;
3167 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3169 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3173 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
3174 struct anv_address addr
,
3177 struct gen_mi_builder b
;
3178 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3180 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
),
3181 gen_mi_mem32(anv_address_add(addr
, 0)));
3183 struct gen_mi_value instance_count
= gen_mi_mem32(anv_address_add(addr
, 4));
3184 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3185 if (view_count
> 1) {
3186 #if GEN_IS_HASWELL || GEN_GEN >= 8
3187 instance_count
= gen_mi_imul_imm(&b
, instance_count
, view_count
);
3189 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3190 "MI_MATH is not supported on Ivy Bridge");
3193 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
), instance_count
);
3195 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3196 gen_mi_mem32(anv_address_add(addr
, 8)));
3199 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
),
3200 gen_mi_mem32(anv_address_add(addr
, 12)));
3201 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3202 gen_mi_mem32(anv_address_add(addr
, 16)));
3204 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3205 gen_mi_mem32(anv_address_add(addr
, 12)));
3206 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3210 void genX(CmdDrawIndirect
)(
3211 VkCommandBuffer commandBuffer
,
3213 VkDeviceSize offset
,
3217 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3218 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3219 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3220 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3222 if (anv_batch_has_error(&cmd_buffer
->batch
))
3225 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3227 if (cmd_buffer
->state
.conditional_render_enabled
)
3228 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3230 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3231 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3233 if (vs_prog_data
->uses_firstvertex
||
3234 vs_prog_data
->uses_baseinstance
)
3235 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3236 if (vs_prog_data
->uses_drawid
)
3237 emit_draw_index(cmd_buffer
, i
);
3239 load_indirect_parameters(cmd_buffer
, draw
, false);
3241 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3242 prim
.IndirectParameterEnable
= true;
3243 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3244 prim
.VertexAccessType
= SEQUENTIAL
;
3245 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3252 void genX(CmdDrawIndexedIndirect
)(
3253 VkCommandBuffer commandBuffer
,
3255 VkDeviceSize offset
,
3259 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3260 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3261 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3262 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3264 if (anv_batch_has_error(&cmd_buffer
->batch
))
3267 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3269 if (cmd_buffer
->state
.conditional_render_enabled
)
3270 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3272 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3273 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3275 /* TODO: We need to stomp base vertex to 0 somehow */
3276 if (vs_prog_data
->uses_firstvertex
||
3277 vs_prog_data
->uses_baseinstance
)
3278 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3279 if (vs_prog_data
->uses_drawid
)
3280 emit_draw_index(cmd_buffer
, i
);
3282 load_indirect_parameters(cmd_buffer
, draw
, true);
3284 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3285 prim
.IndirectParameterEnable
= true;
3286 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3287 prim
.VertexAccessType
= RANDOM
;
3288 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3295 #define TMP_DRAW_COUNT_REG 0x2670 /* MI_ALU_REG14 */
3298 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3299 struct anv_address count_address
,
3300 const bool conditional_render_enabled
)
3302 struct gen_mi_builder b
;
3303 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3305 if (conditional_render_enabled
) {
3306 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3307 gen_mi_store(&b
, gen_mi_reg64(TMP_DRAW_COUNT_REG
),
3308 gen_mi_mem32(count_address
));
3311 /* Upload the current draw count from the draw parameters buffer to
3312 * MI_PREDICATE_SRC0.
3314 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
3315 gen_mi_mem32(count_address
));
3317 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
+ 4), gen_mi_imm(0));
3322 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3323 uint32_t draw_index
)
3325 struct gen_mi_builder b
;
3326 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3328 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3329 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
), gen_mi_imm(draw_index
));
3331 if (draw_index
== 0) {
3332 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3333 mip
.LoadOperation
= LOAD_LOADINV
;
3334 mip
.CombineOperation
= COMBINE_SET
;
3335 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3338 /* While draw_index < draw_count the predicate's result will be
3339 * (draw_index == draw_count) ^ TRUE = TRUE
3340 * When draw_index == draw_count the result is
3341 * (TRUE) ^ TRUE = FALSE
3342 * After this all results will be:
3343 * (FALSE) ^ FALSE = FALSE
3345 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3346 mip
.LoadOperation
= LOAD_LOAD
;
3347 mip
.CombineOperation
= COMBINE_XOR
;
3348 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3353 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3355 emit_draw_count_predicate_with_conditional_render(
3356 struct anv_cmd_buffer
*cmd_buffer
,
3357 uint32_t draw_index
)
3359 struct gen_mi_builder b
;
3360 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3362 struct gen_mi_value pred
= gen_mi_ult(&b
, gen_mi_imm(draw_index
),
3363 gen_mi_reg64(TMP_DRAW_COUNT_REG
));
3364 pred
= gen_mi_iand(&b
, pred
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
));
3367 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_RESULT
), pred
);
3369 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3370 * so we emit MI_PREDICATE to set it.
3373 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), pred
);
3374 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3376 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3377 mip
.LoadOperation
= LOAD_LOADINV
;
3378 mip
.CombineOperation
= COMBINE_SET
;
3379 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3385 void genX(CmdDrawIndirectCountKHR
)(
3386 VkCommandBuffer commandBuffer
,
3388 VkDeviceSize offset
,
3389 VkBuffer _countBuffer
,
3390 VkDeviceSize countBufferOffset
,
3391 uint32_t maxDrawCount
,
3394 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3395 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3396 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3397 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3398 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3399 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3401 if (anv_batch_has_error(&cmd_buffer
->batch
))
3404 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3406 struct anv_address count_address
=
3407 anv_address_add(count_buffer
->address
, countBufferOffset
);
3409 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3410 cmd_state
->conditional_render_enabled
);
3412 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3413 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3415 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3416 if (cmd_state
->conditional_render_enabled
) {
3417 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3419 emit_draw_count_predicate(cmd_buffer
, i
);
3422 emit_draw_count_predicate(cmd_buffer
, i
);
3425 if (vs_prog_data
->uses_firstvertex
||
3426 vs_prog_data
->uses_baseinstance
)
3427 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3428 if (vs_prog_data
->uses_drawid
)
3429 emit_draw_index(cmd_buffer
, i
);
3431 load_indirect_parameters(cmd_buffer
, draw
, false);
3433 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3434 prim
.IndirectParameterEnable
= true;
3435 prim
.PredicateEnable
= true;
3436 prim
.VertexAccessType
= SEQUENTIAL
;
3437 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3444 void genX(CmdDrawIndexedIndirectCountKHR
)(
3445 VkCommandBuffer commandBuffer
,
3447 VkDeviceSize offset
,
3448 VkBuffer _countBuffer
,
3449 VkDeviceSize countBufferOffset
,
3450 uint32_t maxDrawCount
,
3453 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3454 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3455 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3456 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3457 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3458 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3460 if (anv_batch_has_error(&cmd_buffer
->batch
))
3463 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3465 struct anv_address count_address
=
3466 anv_address_add(count_buffer
->address
, countBufferOffset
);
3468 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3469 cmd_state
->conditional_render_enabled
);
3471 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3472 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3474 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3475 if (cmd_state
->conditional_render_enabled
) {
3476 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3478 emit_draw_count_predicate(cmd_buffer
, i
);
3481 emit_draw_count_predicate(cmd_buffer
, i
);
3484 /* TODO: We need to stomp base vertex to 0 somehow */
3485 if (vs_prog_data
->uses_firstvertex
||
3486 vs_prog_data
->uses_baseinstance
)
3487 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3488 if (vs_prog_data
->uses_drawid
)
3489 emit_draw_index(cmd_buffer
, i
);
3491 load_indirect_parameters(cmd_buffer
, draw
, true);
3493 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3494 prim
.IndirectParameterEnable
= true;
3495 prim
.PredicateEnable
= true;
3496 prim
.VertexAccessType
= RANDOM
;
3497 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3504 void genX(CmdBeginTransformFeedbackEXT
)(
3505 VkCommandBuffer commandBuffer
,
3506 uint32_t firstCounterBuffer
,
3507 uint32_t counterBufferCount
,
3508 const VkBuffer
* pCounterBuffers
,
3509 const VkDeviceSize
* pCounterBufferOffsets
)
3511 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3513 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3514 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3515 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3517 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3519 * "Ssoftware must ensure that no HW stream output operations can be in
3520 * process or otherwise pending at the point that the MI_LOAD/STORE
3521 * commands are processed. This will likely require a pipeline flush."
3523 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3524 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3526 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3527 /* If we have a counter buffer, this is a resume so we need to load the
3528 * value into the streamout offset register. Otherwise, this is a begin
3529 * and we need to reset it to zero.
3531 if (pCounterBuffers
&&
3532 idx
>= firstCounterBuffer
&&
3533 idx
- firstCounterBuffer
< counterBufferCount
&&
3534 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
3535 uint32_t cb_idx
= idx
- firstCounterBuffer
;
3536 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3537 uint64_t offset
= pCounterBufferOffsets
?
3538 pCounterBufferOffsets
[cb_idx
] : 0;
3540 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3541 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3542 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3546 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
3547 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3553 cmd_buffer
->state
.xfb_enabled
= true;
3554 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3557 void genX(CmdEndTransformFeedbackEXT
)(
3558 VkCommandBuffer commandBuffer
,
3559 uint32_t firstCounterBuffer
,
3560 uint32_t counterBufferCount
,
3561 const VkBuffer
* pCounterBuffers
,
3562 const VkDeviceSize
* pCounterBufferOffsets
)
3564 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3566 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3567 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3568 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3570 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3572 * "Ssoftware must ensure that no HW stream output operations can be in
3573 * process or otherwise pending at the point that the MI_LOAD/STORE
3574 * commands are processed. This will likely require a pipeline flush."
3576 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3577 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3579 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
3580 unsigned idx
= firstCounterBuffer
+ cb_idx
;
3582 /* If we have a counter buffer, this is a resume so we need to load the
3583 * value into the streamout offset register. Otherwise, this is a begin
3584 * and we need to reset it to zero.
3586 if (pCounterBuffers
&&
3587 cb_idx
< counterBufferCount
&&
3588 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
3589 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3590 uint64_t offset
= pCounterBufferOffsets
?
3591 pCounterBufferOffsets
[cb_idx
] : 0;
3593 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
3594 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3596 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3601 cmd_buffer
->state
.xfb_enabled
= false;
3602 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3606 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
3608 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3609 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
3612 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3613 if (result
!= VK_SUCCESS
) {
3614 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3616 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
3617 if (result
!= VK_SUCCESS
)
3620 /* Re-emit state base addresses so we get the new surface state base
3621 * address before we start emitting binding tables etc.
3623 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
3625 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3626 if (result
!= VK_SUCCESS
) {
3627 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3632 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3633 if (result
!= VK_SUCCESS
) {
3634 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3638 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3639 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3640 .BindingTablePointer
= surfaces
.offset
,
3641 .SamplerStatePointer
= samplers
.offset
,
3643 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3645 struct anv_state state
=
3646 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3647 pipeline
->interface_descriptor_data
,
3648 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3651 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3652 anv_batch_emit(&cmd_buffer
->batch
,
3653 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3654 mid
.InterfaceDescriptorTotalLength
= size
;
3655 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3662 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3664 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3667 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3669 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3671 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3674 genX(cmd_buffer_aux_map_state
)(cmd_buffer
);
3677 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3678 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3680 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3681 * the only bits that are changed are scoreboard related: Scoreboard
3682 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3683 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3686 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3687 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3689 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3691 /* The workgroup size of the pipeline affects our push constant layout
3692 * so flag push constants as dirty if we change the pipeline.
3694 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3697 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3698 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3699 /* FIXME: figure out descriptors for gen7 */
3700 result
= flush_compute_descriptor_set(cmd_buffer
);
3701 if (result
!= VK_SUCCESS
)
3704 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3707 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3708 struct anv_state push_state
=
3709 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3711 if (push_state
.alloc_size
) {
3712 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3713 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3714 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3718 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3721 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3723 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3729 verify_cmd_parser(const struct anv_device
*device
,
3730 int required_version
,
3731 const char *function
)
3733 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3734 return vk_errorf(device
->instance
, device
->instance
,
3735 VK_ERROR_FEATURE_NOT_PRESENT
,
3736 "cmd parser version %d is required for %s",
3737 required_version
, function
);
3746 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3747 uint32_t baseGroupX
,
3748 uint32_t baseGroupY
,
3749 uint32_t baseGroupZ
)
3751 if (anv_batch_has_error(&cmd_buffer
->batch
))
3754 struct anv_push_constants
*push
=
3755 &cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3756 if (push
->cs
.base_work_group_id
[0] != baseGroupX
||
3757 push
->cs
.base_work_group_id
[1] != baseGroupY
||
3758 push
->cs
.base_work_group_id
[2] != baseGroupZ
) {
3759 push
->cs
.base_work_group_id
[0] = baseGroupX
;
3760 push
->cs
.base_work_group_id
[1] = baseGroupY
;
3761 push
->cs
.base_work_group_id
[2] = baseGroupZ
;
3763 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3767 void genX(CmdDispatch
)(
3768 VkCommandBuffer commandBuffer
,
3773 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3776 void genX(CmdDispatchBase
)(
3777 VkCommandBuffer commandBuffer
,
3778 uint32_t baseGroupX
,
3779 uint32_t baseGroupY
,
3780 uint32_t baseGroupZ
,
3781 uint32_t groupCountX
,
3782 uint32_t groupCountY
,
3783 uint32_t groupCountZ
)
3785 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3786 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3787 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3789 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3790 baseGroupY
, baseGroupZ
);
3792 if (anv_batch_has_error(&cmd_buffer
->batch
))
3795 if (prog_data
->uses_num_work_groups
) {
3796 struct anv_state state
=
3797 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3798 uint32_t *sizes
= state
.map
;
3799 sizes
[0] = groupCountX
;
3800 sizes
[1] = groupCountY
;
3801 sizes
[2] = groupCountZ
;
3802 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3803 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3804 .offset
= state
.offset
,
3808 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3810 if (cmd_buffer
->state
.conditional_render_enabled
)
3811 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3813 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3814 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3815 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3816 ggw
.ThreadDepthCounterMaximum
= 0;
3817 ggw
.ThreadHeightCounterMaximum
= 0;
3818 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3819 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3820 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3821 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3822 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3823 ggw
.BottomExecutionMask
= 0xffffffff;
3826 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3829 #define GPGPU_DISPATCHDIMX 0x2500
3830 #define GPGPU_DISPATCHDIMY 0x2504
3831 #define GPGPU_DISPATCHDIMZ 0x2508
3833 void genX(CmdDispatchIndirect
)(
3834 VkCommandBuffer commandBuffer
,
3836 VkDeviceSize offset
)
3838 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3839 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3840 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3841 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3842 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3843 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3845 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3848 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3849 * indirect dispatch registers to be written.
3851 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3852 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3856 if (prog_data
->uses_num_work_groups
)
3857 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3859 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3861 struct gen_mi_builder b
;
3862 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3864 struct gen_mi_value size_x
= gen_mi_mem32(anv_address_add(addr
, 0));
3865 struct gen_mi_value size_y
= gen_mi_mem32(anv_address_add(addr
, 4));
3866 struct gen_mi_value size_z
= gen_mi_mem32(anv_address_add(addr
, 8));
3868 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMX
), size_x
);
3869 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMY
), size_y
);
3870 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMZ
), size_z
);
3873 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3874 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), size_x
);
3875 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3876 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3877 mip
.LoadOperation
= LOAD_LOAD
;
3878 mip
.CombineOperation
= COMBINE_SET
;
3879 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3882 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3883 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_y
);
3884 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3885 mip
.LoadOperation
= LOAD_LOAD
;
3886 mip
.CombineOperation
= COMBINE_OR
;
3887 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3890 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3891 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_z
);
3892 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3893 mip
.LoadOperation
= LOAD_LOAD
;
3894 mip
.CombineOperation
= COMBINE_OR
;
3895 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3898 /* predicate = !predicate; */
3899 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3900 mip
.LoadOperation
= LOAD_LOADINV
;
3901 mip
.CombineOperation
= COMBINE_OR
;
3902 mip
.CompareOperation
= COMPARE_FALSE
;
3906 if (cmd_buffer
->state
.conditional_render_enabled
) {
3907 /* predicate &= !(conditional_rendering_predicate == 0); */
3908 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
),
3909 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
3910 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3911 mip
.LoadOperation
= LOAD_LOADINV
;
3912 mip
.CombineOperation
= COMBINE_AND
;
3913 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3918 #else /* GEN_GEN > 7 */
3919 if (cmd_buffer
->state
.conditional_render_enabled
)
3920 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3923 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3924 ggw
.IndirectParameterEnable
= true;
3925 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
3926 cmd_buffer
->state
.conditional_render_enabled
;
3927 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3928 ggw
.ThreadDepthCounterMaximum
= 0;
3929 ggw
.ThreadHeightCounterMaximum
= 0;
3930 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3931 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3932 ggw
.BottomExecutionMask
= 0xffffffff;
3935 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3939 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3942 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3944 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3947 #if GEN_GEN >= 8 && GEN_GEN < 10
3948 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3950 * Software must clear the COLOR_CALC_STATE Valid field in
3951 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3952 * with Pipeline Select set to GPGPU.
3954 * The internal hardware docs recommend the same workaround for Gen9
3957 if (pipeline
== GPGPU
)
3958 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3962 if (pipeline
== _3D
) {
3963 /* There is a mid-object preemption workaround which requires you to
3964 * re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D. However,
3965 * even without preemption, we have issues with geometry flickering when
3966 * GPGPU and 3D are back-to-back and this seems to fix it. We don't
3969 const uint32_t subslices
=
3970 MAX2(cmd_buffer
->device
->instance
->physicalDevice
.subslice_total
, 1);
3971 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
3972 vfe
.MaximumNumberofThreads
=
3973 devinfo
->max_cs_threads
* subslices
- 1;
3974 vfe
.NumberofURBEntries
= 2;
3975 vfe
.URBEntryAllocationSize
= 2;
3980 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3981 * PIPELINE_SELECT [DevBWR+]":
3985 * Software must ensure all the write caches are flushed through a
3986 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3987 * command to invalidate read only caches prior to programming
3988 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3990 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3991 pc
.RenderTargetCacheFlushEnable
= true;
3992 pc
.DepthCacheFlushEnable
= true;
3993 pc
.DCFlushEnable
= true;
3994 pc
.PostSyncOperation
= NoWrite
;
3995 pc
.CommandStreamerStallEnable
= true;
3997 pc
.TileCacheFlushEnable
= true;
4001 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4002 pc
.TextureCacheInvalidationEnable
= true;
4003 pc
.ConstantCacheInvalidationEnable
= true;
4004 pc
.StateCacheInvalidationEnable
= true;
4005 pc
.InstructionCacheInvalidateEnable
= true;
4006 pc
.PostSyncOperation
= NoWrite
;
4008 pc
.TileCacheFlushEnable
= true;
4012 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
4016 ps
.PipelineSelection
= pipeline
;
4020 if (devinfo
->is_geminilake
) {
4023 * "This chicken bit works around a hardware issue with barrier logic
4024 * encountered when switching between GPGPU and 3D pipelines. To
4025 * workaround the issue, this mode bit should be set after a pipeline
4029 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
4031 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
4032 : GLK_BARRIER_MODE_3D_HULL
,
4033 .GLKBarrierModeMask
= 1);
4034 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
4038 cmd_buffer
->state
.current_pipeline
= pipeline
;
4042 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
4044 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
4048 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
4050 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
4054 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
4059 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
4061 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
4062 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
4063 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
4064 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
4065 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
4066 * Depth Flush Bit set, followed by another pipelined depth stall
4067 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
4068 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
4069 * via a preceding MI_FLUSH)."
4071 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4072 pipe
.DepthStallEnable
= true;
4074 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4075 pipe
.DepthCacheFlushEnable
= true;
4077 pipe
.TileCacheFlushEnable
= true;
4080 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4081 pipe
.DepthStallEnable
= true;
4086 * Update the pixel hashing modes that determine the balancing of PS threads
4087 * across subslices and slices.
4089 * \param width Width bound of the rendering area (already scaled down if \p
4090 * scale is greater than 1).
4091 * \param height Height bound of the rendering area (already scaled down if \p
4092 * scale is greater than 1).
4093 * \param scale The number of framebuffer samples that could potentially be
4094 * affected by an individual channel of the PS thread. This is
4095 * typically one for single-sampled rendering, but for operations
4096 * like CCS resolves and fast clears a single PS invocation may
4097 * update a huge number of pixels, in which case a finer
4098 * balancing is desirable in order to maximally utilize the
4099 * bandwidth available. UINT_MAX can be used as shorthand for
4100 * "finest hashing mode available".
4103 genX(cmd_buffer_emit_hashing_mode
)(struct anv_cmd_buffer
*cmd_buffer
,
4104 unsigned width
, unsigned height
,
4108 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4109 const unsigned slice_hashing
[] = {
4110 /* Because all Gen9 platforms with more than one slice require
4111 * three-way subslice hashing, a single "normal" 16x16 slice hashing
4112 * block is guaranteed to suffer from substantial imbalance, with one
4113 * subslice receiving twice as much work as the other two in the
4116 * The performance impact of that would be particularly severe when
4117 * three-way hashing is also in use for slice balancing (which is the
4118 * case for all Gen9 GT4 platforms), because one of the slices
4119 * receives one every three 16x16 blocks in either direction, which
4120 * is roughly the periodicity of the underlying subslice imbalance
4121 * pattern ("roughly" because in reality the hardware's
4122 * implementation of three-way hashing doesn't do exact modulo 3
4123 * arithmetic, which somewhat decreases the magnitude of this effect
4124 * in practice). This leads to a systematic subslice imbalance
4125 * within that slice regardless of the size of the primitive. The
4126 * 32x32 hashing mode guarantees that the subslice imbalance within a
4127 * single slice hashing block is minimal, largely eliminating this
4131 /* Finest slice hashing mode available. */
4134 const unsigned subslice_hashing
[] = {
4135 /* 16x16 would provide a slight cache locality benefit especially
4136 * visible in the sampler L1 cache efficiency of low-bandwidth
4137 * non-LLC platforms, but it comes at the cost of greater subslice
4138 * imbalance for primitives of dimensions approximately intermediate
4139 * between 16x4 and 16x16.
4142 /* Finest subslice hashing mode available. */
4145 /* Dimensions of the smallest hashing block of a given hashing mode. If
4146 * the rendering area is smaller than this there can't possibly be any
4147 * benefit from switching to this mode, so we optimize out the
4150 const unsigned min_size
[][2] = {
4154 const unsigned idx
= scale
> 1;
4156 if (cmd_buffer
->state
.current_hash_scale
!= scale
&&
4157 (width
> min_size
[idx
][0] || height
> min_size
[idx
][1])) {
4160 anv_pack_struct(>_mode
, GENX(GT_MODE
),
4161 .SliceHashing
= (devinfo
->num_slices
> 1 ? slice_hashing
[idx
] : 0),
4162 .SliceHashingMask
= (devinfo
->num_slices
> 1 ? -1 : 0),
4163 .SubsliceHashing
= subslice_hashing
[idx
],
4164 .SubsliceHashingMask
= -1);
4166 cmd_buffer
->state
.pending_pipe_bits
|=
4167 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
4168 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4170 emit_lri(&cmd_buffer
->batch
, GENX(GT_MODE_num
), gt_mode
);
4172 cmd_buffer
->state
.current_hash_scale
= scale
;
4178 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
4180 struct anv_device
*device
= cmd_buffer
->device
;
4181 const struct anv_image_view
*iview
=
4182 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
4183 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
4185 /* FIXME: Width and Height are wrong */
4187 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
4189 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
4190 device
->isl_dev
.ds
.size
/ 4);
4194 struct isl_depth_stencil_hiz_emit_info info
= { };
4197 info
.view
= &iview
->planes
[0].isl
;
4199 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
4200 uint32_t depth_plane
=
4201 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
4202 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
4204 info
.depth_surf
= &surface
->isl
;
4206 info
.depth_address
=
4207 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4208 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
4209 image
->planes
[depth_plane
].address
.bo
,
4210 image
->planes
[depth_plane
].address
.offset
+
4213 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
4216 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
4217 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
4218 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
4219 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
4222 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4223 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
4224 image
->planes
[depth_plane
].address
.bo
,
4225 image
->planes
[depth_plane
].address
.offset
+
4226 image
->planes
[depth_plane
].aux_surface
.offset
);
4228 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
4232 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4233 uint32_t stencil_plane
=
4234 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
4235 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
4237 info
.stencil_surf
= &surface
->isl
;
4239 info
.stencil_address
=
4240 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4241 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
4242 image
->planes
[stencil_plane
].address
.bo
,
4243 image
->planes
[stencil_plane
].address
.offset
+
4246 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
4249 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
4251 if (GEN_GEN
>= 12) {
4252 /* GEN:BUG:1408224581
4254 * Workaround: Gen12LP Astep only An additional pipe control with
4255 * post-sync = store dword operation would be required.( w/a is to
4256 * have an additional pipe control after the stencil state whenever
4257 * the surface state bits of this state is changing).
4259 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4260 pc
.PostSyncOperation
= WriteImmediateData
;
4262 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
4265 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
4269 * This ANDs the view mask of the current subpass with the pending clear
4270 * views in the attachment to get the mask of views active in the subpass
4271 * that still need to be cleared.
4273 static inline uint32_t
4274 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
4275 const struct anv_attachment_state
*att_state
)
4277 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
4281 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
4282 const struct anv_attachment_state
*att_state
)
4284 if (!cmd_state
->subpass
->view_mask
)
4287 uint32_t pending_clear_mask
=
4288 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4290 return pending_clear_mask
& 1;
4294 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
4297 const uint32_t last_subpass_idx
=
4298 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
4299 const struct anv_subpass
*last_subpass
=
4300 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
4301 return last_subpass
== cmd_state
->subpass
;
4305 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
4306 uint32_t subpass_id
)
4308 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4309 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
4310 cmd_state
->subpass
= subpass
;
4312 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
4314 /* Our implementation of VK_KHR_multiview uses instancing to draw the
4315 * different views. If the client asks for instancing, we need to use the
4316 * Instance Data Step Rate to ensure that we repeat the client's
4317 * per-instance data once for each view. Since this bit is in
4318 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
4322 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
4324 /* It is possible to start a render pass with an old pipeline. Because the
4325 * render pass and subpass index are both baked into the pipeline, this is
4326 * highly unlikely. In order to do so, it requires that you have a render
4327 * pass with a single subpass and that you use that render pass twice
4328 * back-to-back and use the same pipeline at the start of the second render
4329 * pass as at the end of the first. In order to avoid unpredictable issues
4330 * with this edge case, we just dirty the pipeline at the start of every
4333 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
4335 /* Accumulate any subpass flushes that need to happen before the subpass */
4336 cmd_buffer
->state
.pending_pipe_bits
|=
4337 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
4339 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4340 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4342 bool is_multiview
= subpass
->view_mask
!= 0;
4344 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4345 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4346 if (a
== VK_ATTACHMENT_UNUSED
)
4349 assert(a
< cmd_state
->pass
->attachment_count
);
4350 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4352 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
4353 const struct anv_image
*image
= iview
->image
;
4355 /* A resolve is necessary before use as an input attachment if the clear
4356 * color or auxiliary buffer usage isn't supported by the sampler.
4358 const bool input_needs_resolve
=
4359 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
4360 att_state
->input_aux_usage
!= att_state
->aux_usage
;
4362 VkImageLayout target_layout
, target_stencil_layout
;
4363 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
4364 !input_needs_resolve
) {
4365 /* Layout transitions before the final only help to enable sampling
4366 * as an input attachment. If the input attachment supports sampling
4367 * using the auxiliary surface, we can skip such transitions by
4368 * making the target layout one that is CCS-aware.
4370 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
4372 target_layout
= subpass
->attachments
[i
].layout
;
4373 target_stencil_layout
= subpass
->attachments
[i
].stencil_layout
;
4376 uint32_t base_layer
, layer_count
;
4377 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4379 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4380 iview
->planes
[0].isl
.base_level
);
4382 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4383 layer_count
= fb
->layers
;
4386 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4387 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4388 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4389 iview
->planes
[0].isl
.base_level
, 1,
4390 base_layer
, layer_count
,
4391 att_state
->current_layout
, target_layout
);
4394 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4395 transition_depth_buffer(cmd_buffer
, image
,
4396 att_state
->current_layout
, target_layout
);
4397 att_state
->aux_usage
=
4398 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
4399 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
4402 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4403 transition_stencil_buffer(cmd_buffer
, image
,
4404 iview
->planes
[0].isl
.base_level
, 1,
4405 base_layer
, layer_count
,
4406 att_state
->current_stencil_layout
,
4407 target_stencil_layout
);
4409 att_state
->current_layout
= target_layout
;
4410 att_state
->current_stencil_layout
= target_stencil_layout
;
4412 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
4413 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4415 /* Multi-planar images are not supported as attachments */
4416 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4417 assert(image
->n_planes
== 1);
4419 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
4420 uint32_t clear_layer_count
= fb
->layers
;
4422 if (att_state
->fast_clear
&&
4423 do_first_layer_clear(cmd_state
, att_state
)) {
4424 /* We only support fast-clears on the first layer */
4425 assert(iview
->planes
[0].isl
.base_level
== 0);
4426 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4428 union isl_color_value clear_color
= {};
4429 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
4430 if (iview
->image
->samples
== 1) {
4431 anv_image_ccs_op(cmd_buffer
, image
,
4432 iview
->planes
[0].isl
.format
,
4433 VK_IMAGE_ASPECT_COLOR_BIT
,
4434 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4438 anv_image_mcs_op(cmd_buffer
, image
,
4439 iview
->planes
[0].isl
.format
,
4440 VK_IMAGE_ASPECT_COLOR_BIT
,
4441 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4446 clear_layer_count
--;
4448 att_state
->pending_clear_views
&= ~1;
4450 if (att_state
->clear_color_is_zero
) {
4451 /* This image has the auxiliary buffer enabled. We can mark the
4452 * subresource as not needing a resolve because the clear color
4453 * will match what's in every RENDER_SURFACE_STATE object when
4454 * it's being used for sampling.
4456 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4457 VK_IMAGE_ASPECT_COLOR_BIT
,
4458 ANV_FAST_CLEAR_DEFAULT_VALUE
);
4460 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4461 VK_IMAGE_ASPECT_COLOR_BIT
,
4462 ANV_FAST_CLEAR_ANY
);
4466 /* From the VkFramebufferCreateInfo spec:
4468 * "If the render pass uses multiview, then layers must be one and each
4469 * attachment requires a number of layers that is greater than the
4470 * maximum bit index set in the view mask in the subpasses in which it
4473 * So if multiview is active we ignore the number of layers in the
4474 * framebuffer and instead we honor the view mask from the subpass.
4477 assert(image
->n_planes
== 1);
4478 uint32_t pending_clear_mask
=
4479 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4482 for_each_bit(layer_idx
, pending_clear_mask
) {
4484 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4486 anv_image_clear_color(cmd_buffer
, image
,
4487 VK_IMAGE_ASPECT_COLOR_BIT
,
4488 att_state
->aux_usage
,
4489 iview
->planes
[0].isl
.format
,
4490 iview
->planes
[0].isl
.swizzle
,
4491 iview
->planes
[0].isl
.base_level
,
4494 vk_to_isl_color(att_state
->clear_value
.color
));
4497 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4498 } else if (clear_layer_count
> 0) {
4499 assert(image
->n_planes
== 1);
4500 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4501 att_state
->aux_usage
,
4502 iview
->planes
[0].isl
.format
,
4503 iview
->planes
[0].isl
.swizzle
,
4504 iview
->planes
[0].isl
.base_level
,
4505 base_clear_layer
, clear_layer_count
,
4507 vk_to_isl_color(att_state
->clear_value
.color
));
4509 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
4510 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4511 if (att_state
->fast_clear
&& !is_multiview
) {
4512 /* We currently only support HiZ for single-layer images */
4513 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4514 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
4515 assert(iview
->planes
[0].isl
.base_level
== 0);
4516 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4517 assert(fb
->layers
== 1);
4520 anv_image_hiz_clear(cmd_buffer
, image
,
4521 att_state
->pending_clear_aspects
,
4522 iview
->planes
[0].isl
.base_level
,
4523 iview
->planes
[0].isl
.base_array_layer
,
4524 fb
->layers
, render_area
,
4525 att_state
->clear_value
.depthStencil
.stencil
);
4526 } else if (is_multiview
) {
4527 uint32_t pending_clear_mask
=
4528 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4531 for_each_bit(layer_idx
, pending_clear_mask
) {
4533 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4535 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4536 att_state
->pending_clear_aspects
,
4537 att_state
->aux_usage
,
4538 iview
->planes
[0].isl
.base_level
,
4541 att_state
->clear_value
.depthStencil
.depth
,
4542 att_state
->clear_value
.depthStencil
.stencil
);
4545 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4547 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4548 att_state
->pending_clear_aspects
,
4549 att_state
->aux_usage
,
4550 iview
->planes
[0].isl
.base_level
,
4551 iview
->planes
[0].isl
.base_array_layer
,
4552 fb
->layers
, render_area
,
4553 att_state
->clear_value
.depthStencil
.depth
,
4554 att_state
->clear_value
.depthStencil
.stencil
);
4557 assert(att_state
->pending_clear_aspects
== 0);
4561 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4562 image
->planes
[0].aux_surface
.isl
.size_B
> 0 &&
4563 iview
->planes
[0].isl
.base_level
== 0 &&
4564 iview
->planes
[0].isl
.base_array_layer
== 0) {
4565 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
4566 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
4567 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4568 false /* copy to ss */);
4571 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
4572 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
4573 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
4574 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4575 false /* copy to ss */);
4579 if (subpass
->attachments
[i
].usage
==
4580 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
4581 /* We assume that if we're starting a subpass, we're going to do some
4582 * rendering so we may end up with compressed data.
4584 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
4585 VK_IMAGE_ASPECT_COLOR_BIT
,
4586 att_state
->aux_usage
,
4587 iview
->planes
[0].isl
.base_level
,
4588 iview
->planes
[0].isl
.base_array_layer
,
4590 } else if (subpass
->attachments
[i
].usage
==
4591 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
4592 /* We may be writing depth or stencil so we need to mark the surface.
4593 * Unfortunately, there's no way to know at this point whether the
4594 * depth or stencil tests used will actually write to the surface.
4596 * Even though stencil may be plane 1, it always shares a base_level
4599 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
4600 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4601 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4602 VK_IMAGE_ASPECT_DEPTH_BIT
,
4603 att_state
->aux_usage
,
4604 ds_view
->base_level
,
4605 ds_view
->base_array_layer
,
4608 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4609 /* Even though stencil may be plane 1, it always shares a
4610 * base_level with depth.
4612 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4613 VK_IMAGE_ASPECT_STENCIL_BIT
,
4615 ds_view
->base_level
,
4616 ds_view
->base_array_layer
,
4621 /* If multiview is enabled, then we are only done clearing when we no
4622 * longer have pending layers to clear, or when we have processed the
4623 * last subpass that uses this attachment.
4625 if (!is_multiview
||
4626 att_state
->pending_clear_views
== 0 ||
4627 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
4628 att_state
->pending_clear_aspects
= 0;
4631 att_state
->pending_load_aspects
= 0;
4634 cmd_buffer_emit_depth_stencil(cmd_buffer
);
4637 /* The PIPE_CONTROL command description says:
4639 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
4640 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
4641 * Target Cache Flush by enabling this bit. When render target flush
4642 * is set due to new association of BTI, PS Scoreboard Stall bit must
4643 * be set in this packet."
4645 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4646 pc
.RenderTargetCacheFlushEnable
= true;
4647 pc
.StallAtPixelScoreboard
= true;
4649 pc
.TileCacheFlushEnable
= true;
4655 static enum blorp_filter
4656 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
4659 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
4660 return BLORP_FILTER_SAMPLE_0
;
4661 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
4662 return BLORP_FILTER_AVERAGE
;
4663 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
4664 return BLORP_FILTER_MIN_SAMPLE
;
4665 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
4666 return BLORP_FILTER_MAX_SAMPLE
;
4668 return BLORP_FILTER_NONE
;
4673 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
4675 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4676 struct anv_subpass
*subpass
= cmd_state
->subpass
;
4677 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
4678 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4680 if (subpass
->has_color_resolve
) {
4681 /* We are about to do some MSAA resolves. We need to flush so that the
4682 * result of writes to the MSAA color attachments show up in the sampler
4683 * when we blit to the single-sampled resolve target.
4685 cmd_buffer
->state
.pending_pipe_bits
|=
4686 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4687 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
4689 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
4690 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
4691 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
4693 if (dst_att
== VK_ATTACHMENT_UNUSED
)
4696 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4697 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4699 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4700 /* From the Vulkan 1.0 spec:
4702 * If the first use of an attachment in a render pass is as a
4703 * resolve attachment, then the loadOp is effectively ignored
4704 * as the resolve is guaranteed to overwrite all pixels in the
4707 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4710 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
4711 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
4713 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4715 enum isl_aux_usage src_aux_usage
=
4716 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
4717 enum isl_aux_usage dst_aux_usage
=
4718 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
4720 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
4721 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
4723 anv_image_msaa_resolve(cmd_buffer
,
4724 src_iview
->image
, src_aux_usage
,
4725 src_iview
->planes
[0].isl
.base_level
,
4726 src_iview
->planes
[0].isl
.base_array_layer
,
4727 dst_iview
->image
, dst_aux_usage
,
4728 dst_iview
->planes
[0].isl
.base_level
,
4729 dst_iview
->planes
[0].isl
.base_array_layer
,
4730 VK_IMAGE_ASPECT_COLOR_BIT
,
4731 render_area
.offset
.x
, render_area
.offset
.y
,
4732 render_area
.offset
.x
, render_area
.offset
.y
,
4733 render_area
.extent
.width
,
4734 render_area
.extent
.height
,
4735 fb
->layers
, BLORP_FILTER_NONE
);
4739 if (subpass
->ds_resolve_attachment
) {
4740 /* We are about to do some MSAA resolves. We need to flush so that the
4741 * result of writes to the MSAA depth attachments show up in the sampler
4742 * when we blit to the single-sampled resolve target.
4744 cmd_buffer
->state
.pending_pipe_bits
|=
4745 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4746 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
4748 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
4749 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
4751 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4752 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4754 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4755 /* From the Vulkan 1.0 spec:
4757 * If the first use of an attachment in a render pass is as a
4758 * resolve attachment, then the loadOp is effectively ignored
4759 * as the resolve is guaranteed to overwrite all pixels in the
4762 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4765 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
4766 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
4768 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4770 struct anv_attachment_state
*src_state
=
4771 &cmd_state
->attachments
[src_att
];
4772 struct anv_attachment_state
*dst_state
=
4773 &cmd_state
->attachments
[dst_att
];
4775 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
4776 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4778 /* MSAA resolves sample from the source attachment. Transition the
4779 * depth attachment first to get rid of any HiZ that we may not be
4782 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
4783 src_state
->current_layout
,
4784 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4785 src_state
->aux_usage
=
4786 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
4787 VK_IMAGE_ASPECT_DEPTH_BIT
,
4788 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4789 src_state
->current_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
4791 /* MSAA resolves write to the resolve attachment as if it were any
4792 * other transfer op. Transition the resolve attachment accordingly.
4794 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
4796 /* If our render area is the entire size of the image, we're going to
4797 * blow it all away so we can claim the initial layout is UNDEFINED
4798 * and we'll get a HiZ ambiguate instead of a resolve.
4800 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
4801 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
4802 render_area
.extent
.width
== dst_iview
->extent
.width
&&
4803 render_area
.extent
.height
== dst_iview
->extent
.height
)
4804 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
4806 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
4808 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4809 dst_state
->aux_usage
=
4810 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
4811 VK_IMAGE_ASPECT_DEPTH_BIT
,
4812 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4813 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
4815 enum blorp_filter filter
=
4816 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
4818 anv_image_msaa_resolve(cmd_buffer
,
4819 src_iview
->image
, src_state
->aux_usage
,
4820 src_iview
->planes
[0].isl
.base_level
,
4821 src_iview
->planes
[0].isl
.base_array_layer
,
4822 dst_iview
->image
, dst_state
->aux_usage
,
4823 dst_iview
->planes
[0].isl
.base_level
,
4824 dst_iview
->planes
[0].isl
.base_array_layer
,
4825 VK_IMAGE_ASPECT_DEPTH_BIT
,
4826 render_area
.offset
.x
, render_area
.offset
.y
,
4827 render_area
.offset
.x
, render_area
.offset
.y
,
4828 render_area
.extent
.width
,
4829 render_area
.extent
.height
,
4830 fb
->layers
, filter
);
4833 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
4834 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4836 src_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
4837 dst_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
4839 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
4840 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
4842 enum blorp_filter filter
=
4843 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
4845 anv_image_msaa_resolve(cmd_buffer
,
4846 src_iview
->image
, src_aux_usage
,
4847 src_iview
->planes
[0].isl
.base_level
,
4848 src_iview
->planes
[0].isl
.base_array_layer
,
4849 dst_iview
->image
, dst_aux_usage
,
4850 dst_iview
->planes
[0].isl
.base_level
,
4851 dst_iview
->planes
[0].isl
.base_array_layer
,
4852 VK_IMAGE_ASPECT_STENCIL_BIT
,
4853 render_area
.offset
.x
, render_area
.offset
.y
,
4854 render_area
.offset
.x
, render_area
.offset
.y
,
4855 render_area
.extent
.width
,
4856 render_area
.extent
.height
,
4857 fb
->layers
, filter
);
4862 /* On gen7, we have to store a texturable version of the stencil buffer in
4863 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
4864 * forth at strategic points. Stencil writes are only allowed in following
4867 * - VK_IMAGE_LAYOUT_GENERAL
4868 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
4869 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
4870 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
4871 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
4873 * For general, we have no nice opportunity to transition so we do the copy
4874 * to the shadow unconditionally at the end of the subpass. For transfer
4875 * destinations, we can update it as part of the transfer op. For the other
4876 * layouts, we delay the copy until a transition into some other layout.
4878 if (subpass
->depth_stencil_attachment
) {
4879 uint32_t a
= subpass
->depth_stencil_attachment
->attachment
;
4880 assert(a
!= VK_ATTACHMENT_UNUSED
);
4882 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4883 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;;
4884 const struct anv_image
*image
= iview
->image
;
4886 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4887 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
4888 VK_IMAGE_ASPECT_STENCIL_BIT
);
4890 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
4891 att_state
->current_stencil_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
4892 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
4893 anv_image_copy_to_shadow(cmd_buffer
, image
,
4894 VK_IMAGE_ASPECT_STENCIL_BIT
,
4895 iview
->planes
[plane
].isl
.base_level
, 1,
4896 iview
->planes
[plane
].isl
.base_array_layer
,
4901 #endif /* GEN_GEN == 7 */
4903 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4904 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4905 if (a
== VK_ATTACHMENT_UNUSED
)
4908 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4911 assert(a
< cmd_state
->pass
->attachment_count
);
4912 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4913 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
4914 const struct anv_image
*image
= iview
->image
;
4916 if ((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4917 image
->vk_format
!= iview
->vk_format
) {
4918 enum anv_fast_clear_type fast_clear_type
=
4919 anv_layout_to_fast_clear_type(&cmd_buffer
->device
->info
,
4920 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4921 att_state
->current_layout
);
4923 /* If any clear color was used, flush it down the aux surfaces. If we
4924 * don't do it now using the view's format we might use the clear
4925 * color incorrectly in the following resolves (for example with an
4926 * SRGB view & a UNORM image).
4928 if (fast_clear_type
!= ANV_FAST_CLEAR_NONE
) {
4929 anv_perf_warn(cmd_buffer
->device
->instance
, iview
,
4930 "Doing a partial resolve to get rid of clear color at the "
4931 "end of a renderpass due to an image/view format mismatch");
4933 uint32_t base_layer
, layer_count
;
4934 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4936 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4937 iview
->planes
[0].isl
.base_level
);
4939 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4940 layer_count
= fb
->layers
;
4943 for (uint32_t a
= 0; a
< layer_count
; a
++) {
4944 uint32_t array_layer
= base_layer
+ a
;
4945 if (image
->samples
== 1) {
4946 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
4947 iview
->planes
[0].isl
.format
,
4948 VK_IMAGE_ASPECT_COLOR_BIT
,
4949 iview
->planes
[0].isl
.base_level
,
4951 ISL_AUX_OP_PARTIAL_RESOLVE
,
4952 ANV_FAST_CLEAR_NONE
);
4954 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
4955 iview
->planes
[0].isl
.format
,
4956 VK_IMAGE_ASPECT_COLOR_BIT
,
4958 ISL_AUX_OP_PARTIAL_RESOLVE
,
4959 ANV_FAST_CLEAR_NONE
);
4965 /* Transition the image into the final layout for this render pass */
4966 VkImageLayout target_layout
=
4967 cmd_state
->pass
->attachments
[a
].final_layout
;
4968 VkImageLayout target_stencil_layout
=
4969 cmd_state
->pass
->attachments
[a
].stencil_final_layout
;
4971 uint32_t base_layer
, layer_count
;
4972 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4974 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4975 iview
->planes
[0].isl
.base_level
);
4977 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4978 layer_count
= fb
->layers
;
4981 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4982 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4983 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4984 iview
->planes
[0].isl
.base_level
, 1,
4985 base_layer
, layer_count
,
4986 att_state
->current_layout
, target_layout
);
4989 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4990 transition_depth_buffer(cmd_buffer
, image
,
4991 att_state
->current_layout
, target_layout
);
4994 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4995 transition_stencil_buffer(cmd_buffer
, image
,
4996 iview
->planes
[0].isl
.base_level
, 1,
4997 base_layer
, layer_count
,
4998 att_state
->current_stencil_layout
,
4999 target_stencil_layout
);
5003 /* Accumulate any subpass flushes that need to happen after the subpass.
5004 * Yes, they do get accumulated twice in the NextSubpass case but since
5005 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
5006 * ORing the bits in twice so it's harmless.
5008 cmd_buffer
->state
.pending_pipe_bits
|=
5009 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
5012 void genX(CmdBeginRenderPass
)(
5013 VkCommandBuffer commandBuffer
,
5014 const VkRenderPassBeginInfo
* pRenderPassBegin
,
5015 VkSubpassContents contents
)
5017 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5018 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
5019 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
5021 cmd_buffer
->state
.framebuffer
= framebuffer
;
5022 cmd_buffer
->state
.pass
= pass
;
5023 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
5025 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
5027 /* If we failed to setup the attachments we should not try to go further */
5028 if (result
!= VK_SUCCESS
) {
5029 assert(anv_batch_has_error(&cmd_buffer
->batch
));
5033 genX(flush_pipeline_select_3d
)(cmd_buffer
);
5035 cmd_buffer_begin_subpass(cmd_buffer
, 0);
5038 void genX(CmdBeginRenderPass2KHR
)(
5039 VkCommandBuffer commandBuffer
,
5040 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
5041 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
5043 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
5044 pSubpassBeginInfo
->contents
);
5047 void genX(CmdNextSubpass
)(
5048 VkCommandBuffer commandBuffer
,
5049 VkSubpassContents contents
)
5051 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5053 if (anv_batch_has_error(&cmd_buffer
->batch
))
5056 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
5058 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
5059 cmd_buffer_end_subpass(cmd_buffer
);
5060 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
5063 void genX(CmdNextSubpass2KHR
)(
5064 VkCommandBuffer commandBuffer
,
5065 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
5066 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5068 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
5071 void genX(CmdEndRenderPass
)(
5072 VkCommandBuffer commandBuffer
)
5074 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5076 if (anv_batch_has_error(&cmd_buffer
->batch
))
5079 cmd_buffer_end_subpass(cmd_buffer
);
5081 cmd_buffer
->state
.hiz_enabled
= false;
5084 anv_dump_add_attachments(cmd_buffer
);
5087 /* Remove references to render pass specific state. This enables us to
5088 * detect whether or not we're in a renderpass.
5090 cmd_buffer
->state
.framebuffer
= NULL
;
5091 cmd_buffer
->state
.pass
= NULL
;
5092 cmd_buffer
->state
.subpass
= NULL
;
5095 void genX(CmdEndRenderPass2KHR
)(
5096 VkCommandBuffer commandBuffer
,
5097 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5099 genX(CmdEndRenderPass
)(commandBuffer
);
5103 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
5105 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5106 struct gen_mi_builder b
;
5107 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5109 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
5110 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
5111 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
5113 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
5114 mip
.LoadOperation
= LOAD_LOADINV
;
5115 mip
.CombineOperation
= COMBINE_SET
;
5116 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
5121 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5122 void genX(CmdBeginConditionalRenderingEXT
)(
5123 VkCommandBuffer commandBuffer
,
5124 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5126 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5127 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5128 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5129 struct anv_address value_address
=
5130 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
5132 const bool isInverted
= pConditionalRenderingBegin
->flags
&
5133 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
5135 cmd_state
->conditional_render_enabled
= true;
5137 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5139 struct gen_mi_builder b
;
5140 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5142 /* Section 19.4 of the Vulkan 1.1.85 spec says:
5144 * If the value of the predicate in buffer memory changes
5145 * while conditional rendering is active, the rendering commands
5146 * may be discarded in an implementation-dependent way.
5147 * Some implementations may latch the value of the predicate
5148 * upon beginning conditional rendering while others
5149 * may read it before every rendering command.
5151 * So it's perfectly fine to read a value from the buffer once.
5153 struct gen_mi_value value
= gen_mi_mem32(value_address
);
5155 /* Precompute predicate result, it is necessary to support secondary
5156 * command buffers since it is unknown if conditional rendering is
5157 * inverted when populating them.
5159 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
5160 isInverted
? gen_mi_uge(&b
, gen_mi_imm(0), value
) :
5161 gen_mi_ult(&b
, gen_mi_imm(0), value
));
5164 void genX(CmdEndConditionalRenderingEXT
)(
5165 VkCommandBuffer commandBuffer
)
5167 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5168 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5170 cmd_state
->conditional_render_enabled
= false;
5174 /* Set of stage bits for which are pipelined, i.e. they get queued by the
5175 * command streamer for later execution.
5177 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
5178 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
5179 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
5180 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
5181 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
5182 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
5183 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
5184 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
5185 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
5186 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
5187 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
5188 VK_PIPELINE_STAGE_TRANSFER_BIT | \
5189 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
5190 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
5191 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
5193 void genX(CmdSetEvent
)(
5194 VkCommandBuffer commandBuffer
,
5196 VkPipelineStageFlags stageMask
)
5198 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5199 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5201 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5202 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5203 pc
.StallAtPixelScoreboard
= true;
5204 pc
.CommandStreamerStallEnable
= true;
5207 pc
.DestinationAddressType
= DAT_PPGTT
,
5208 pc
.PostSyncOperation
= WriteImmediateData
,
5209 pc
.Address
= (struct anv_address
) {
5210 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5213 pc
.ImmediateData
= VK_EVENT_SET
;
5217 void genX(CmdResetEvent
)(
5218 VkCommandBuffer commandBuffer
,
5220 VkPipelineStageFlags stageMask
)
5222 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5223 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5225 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5226 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5227 pc
.StallAtPixelScoreboard
= true;
5228 pc
.CommandStreamerStallEnable
= true;
5231 pc
.DestinationAddressType
= DAT_PPGTT
;
5232 pc
.PostSyncOperation
= WriteImmediateData
;
5233 pc
.Address
= (struct anv_address
) {
5234 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5237 pc
.ImmediateData
= VK_EVENT_RESET
;
5241 void genX(CmdWaitEvents
)(
5242 VkCommandBuffer commandBuffer
,
5243 uint32_t eventCount
,
5244 const VkEvent
* pEvents
,
5245 VkPipelineStageFlags srcStageMask
,
5246 VkPipelineStageFlags destStageMask
,
5247 uint32_t memoryBarrierCount
,
5248 const VkMemoryBarrier
* pMemoryBarriers
,
5249 uint32_t bufferMemoryBarrierCount
,
5250 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5251 uint32_t imageMemoryBarrierCount
,
5252 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5255 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5257 for (uint32_t i
= 0; i
< eventCount
; i
++) {
5258 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
5260 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
5261 sem
.WaitMode
= PollingMode
,
5262 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
5263 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
5264 sem
.SemaphoreAddress
= (struct anv_address
) {
5265 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5271 anv_finishme("Implement events on gen7");
5274 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
5275 false, /* byRegion */
5276 memoryBarrierCount
, pMemoryBarriers
,
5277 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5278 imageMemoryBarrierCount
, pImageMemoryBarriers
);
5281 VkResult
genX(CmdSetPerformanceOverrideINTEL
)(
5282 VkCommandBuffer commandBuffer
,
5283 const VkPerformanceOverrideInfoINTEL
* pOverrideInfo
)
5285 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5287 switch (pOverrideInfo
->type
) {
5288 case VK_PERFORMANCE_OVERRIDE_TYPE_NULL_HARDWARE_INTEL
: {
5292 anv_pack_struct(&dw
, GENX(CS_DEBUG_MODE2
),
5293 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
5294 .MediaInstructionDisable
= pOverrideInfo
->enable
,
5295 ._3DRenderingInstructionDisableMask
= true,
5296 .MediaInstructionDisableMask
= true);
5297 emit_lri(&cmd_buffer
->batch
, GENX(CS_DEBUG_MODE2_num
), dw
);
5299 anv_pack_struct(&dw
, GENX(INSTPM
),
5300 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
5301 .MediaInstructionDisable
= pOverrideInfo
->enable
,
5302 ._3DRenderingInstructionDisableMask
= true,
5303 .MediaInstructionDisableMask
= true);
5304 emit_lri(&cmd_buffer
->batch
, GENX(INSTPM_num
), dw
);
5309 case VK_PERFORMANCE_OVERRIDE_TYPE_FLUSH_GPU_CACHES_INTEL
:
5310 if (pOverrideInfo
->enable
) {
5311 /* FLUSH ALL THE THINGS! As requested by the MDAPI team. */
5312 cmd_buffer
->state
.pending_pipe_bits
|=
5313 ANV_PIPE_FLUSH_BITS
|
5314 ANV_PIPE_INVALIDATE_BITS
;
5315 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5320 unreachable("Invalid override");
5326 VkResult
genX(CmdSetPerformanceStreamMarkerINTEL
)(
5327 VkCommandBuffer commandBuffer
,
5328 const VkPerformanceStreamMarkerInfoINTEL
* pMarkerInfo
)
5330 /* TODO: Waiting on the register to write, might depend on generation. */